JP2007140192A - Active matrix type liquid crystal display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent enlargement of a frame, in an active matrix type liquid crystal display device of an auxiliary capacity line inversion system. <P>SOLUTION: The liquid crystal display device is provided with a display area 10 composed of a plurality of pixels GS11 to GS14 arranged on a glass substrate 100 in a matrix form; a horizontal drive circuit 30 for outputting a video signal to drain lines 20-1 to 20-4, connected in common to the drains of switching TFTs 11 in respective pixels arrayed in a column direction; a vertical drive circuit 50 for outputting a gate signal to gate lines 40-1, 40-2 connected in common to the gates of the switching TFTs of respective pixels arrayed in the row direction; and an auxiliary capacity line inversion drive circuit 70 for driving first and second auxiliary capacity lines 61-1, 62-1 so that the phases of the potential of the first and second auxiliary capacity lines 61-1, 62-1 are mutually reversed. The vertical drive circuit 50 and the auxiliary capacity lines inversion drive circuit 70 are respectively arranged sandwiching both sides of a display area 10 in-between the display area 10. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to an active matrix type liquid crystal display device, and more particularly to an active matrix type liquid crystal display device having an auxiliary capacitor line inversion drive function.

  Conventionally, in an active matrix liquid crystal display device that supplies a video signal to a pixel electrode of each pixel through a switching element such as a thin film transistor (TFT), an alternating current is applied to a counter electrode and an auxiliary capacitor facing the pixel electrode. The liquid crystal is prevented from deteriorating by performing counter electrode AC line inversion driving for applying a potential.

  However, in the counter AC inversion driving that inverts the polarity of the video signal applied to each drain line every horizontal period, the polarity of the potential of the counter electrode and the auxiliary capacitance line is inverted every horizontal period. The capacitive load in the auxiliary capacity line and the power consumption due to these were large.

  Therefore, in order to realize low power consumption, the potential difference between the positive and negative polarity of the video signal is reduced by inverting the polarity of the potential of the auxiliary capacitance line at a constant cycle while keeping the potential of the counter electrode constant. A driving method for reducing the power consumption of the horizontal driving circuit (hereinafter referred to as “auxiliary capacitor line inversion driving method”, abbreviated as “SC inversion driving method”) is disclosed in Patent Document 1.

Further, in order to prevent capacitive coupling and image unevenness caused by such SC inversion driving, voltages having different polarities are applied to pixel electrodes adjacent in the gate line direction, as shown in FIG. Japanese Patent Application Laid-Open No. 2004-228561 discloses a dot inversion driving method in which a voltage having a reverse polarity is applied to all pixels adjacent in the vertical and horizontal directions.
JP-A-12-81606 JP 2003-150127 A

  However, in the above SC inversion driving method, since it is necessary to provide an SC inversion driving circuit, there is a problem that the circuit area is increased and the frame of the panel is increased.

  An active matrix type liquid crystal display device according to the present invention is sealed between a display region composed of a plurality of pixels arranged in a matrix, a pixel electrode arranged for each of the plurality of pixels, and the pixel electrode and a counter electrode. A liquid crystal; a switching element connected to each of the pixel electrodes and switching in accordance with a gate signal; a vertical driving circuit for outputting the gate signal based on a vertical clock; and a first driving circuit disposed corresponding to a pixel in each row. An auxiliary capacitance line inversion driving circuit for performing inversion driving so that the potentials of the first and second auxiliary capacitance lines and the first and second auxiliary capacitance lines are in opposite phases with each other in a predetermined cycle; and the first auxiliary capacitance A first auxiliary capacitor connected between the line and the pixel electrode, a second auxiliary capacitor connected between the second auxiliary capacitor line and the pixel electrode, and a switch for each pixel. A horizontal driving circuit for supplying a desired video signal through the scanning element, and the vertical driving circuit and the auxiliary capacitance line inversion driving circuit are respectively disposed on both sides of the display area with the display area interposed therebetween. It is characterized by.

  According to the present invention, in the active matrix type liquid crystal display device of the auxiliary capacitance line inversion method, the vertical driving circuit and the auxiliary capacitance are not arranged side by side on one side of the display area. Since the line inversion driving circuit is arranged on both sides of the display area with the display area in between, it is possible to arrange the circuits on the substrate in a well-balanced manner to prevent the frame from becoming large.

  Next, an active matrix liquid crystal display device according to an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a circuit diagram of the active matrix type liquid crystal display device.

  This active matrix type liquid crystal display device includes a display region 10 composed of a plurality of pixels GS11, GS12,... Arranged in a matrix on a glass substrate 100, and a drain of the switching TFT 11 of each pixel arranged in the column direction. Are connected in common to drain lines 20-1, 20-2,..., A horizontal drive circuit 30 for outputting a video signal, and gate lines connected in common to the gates of the switching TFTs 11 of the pixels arranged in the row direction. 40, 40-2,..., And a first auxiliary capacitance line 61-1 and a second auxiliary capacitance line extending in the row direction corresponding to the pixels of each row. An auxiliary capacitance line inversion drive circuit 70 (hereinafter abbreviated as “SC inversion drive circuit”) that drives the potentials 62-1 to be in opposite phases to each other; 20-1 and 20-2, and a precharge circuit 80 for supplying a precharge signal to ....

  A feature of the present invention is that the vertical drive circuit 50 and the auxiliary capacitance line inversion drive circuit 70 are respectively arranged on both sides of the display area 10 with the display area 10 interposed therebetween. Further, the vertical drive circuit 50 and the auxiliary capacitance line inversion drive circuit 70 can be arranged in a balanced manner to prevent the frame from becoming large.

  Hereinafter, the configuration of each circuit will be described in detail. First, in the display area 10, the first row is arranged in the order of red, green, and blue, such as a red pixel GS11, a green pixel GS12, a blue pixel GS13, and a red pixel GS14. The array is repeated in the row direction. Similarly, in the second row, red pixel GS21, green pixel GS22, blue pixel GS23, and red pixel GS24 are arranged in the order of red, green, and blue, and this array is arranged in the row direction. Has been repeated.

  In one pixel, for example, the pixel GS11, the gate line 40-1 is sealed between the switching TFT 11 connected to the gate, the pixel electrode 12 connected to the source of the switching TFT 11, and the pixel electrode 12 and the counter electrode 13. A first auxiliary capacitor 15 connected between the liquid crystal 14 and the pixel electrode 12 and the first auxiliary capacitor line 61-1 is provided. The same applies to the pixel GS12 adjacent to the pixel GS11, but the second auxiliary capacitor 16 is provided between the pixel electrode 12 and the second auxiliary capacitor line 62-1.

  For the pixel GS13 adjacent to the pixel GS12, the first auxiliary capacitor 15 is provided between the pixel electrode 12 and the first auxiliary capacitor line 61-1. That is, in order to enable dot inversion driving, the auxiliary capacitance in each pixel is alternately connected to the first auxiliary capacitance line 61-1 and the second auxiliary capacitance line 62-1.

  The horizontal drive circuit 30 outputs signal signals S1, S2,... That output video signals input from the outside, and drains 20-1, 20 the video signals from these signal lines S1, S2,. A first video switch 31, a second video switch 32, and a third video switch 33 for selectively outputting to -2,.

  For example, when the red video signal enable signal RENB becomes high level, the first video switch 31 is turned on, and the red video signal is output to the drain line 20-1 from the signal lines S1, S2,. Is done. Next, when the green video signal enable signal GENB becomes high, the second video switch 32 is turned on, and the green video signal is output to the drain line 20-2 from the signal lines S1, S2,. Is done. Next, when the blue video signal enable signal BENB becomes high level, the third video switch 33 is turned on, and in synchronization therewith, the blue video signal is sent from the signal lines S1, S2,... To the drain line 20-3. Is output.

  Here, the horizontal drive circuit 30 supplies a video signal to each pixel in the display area selected from the display area 10 composed of a plurality of pixels in response to the SC inversion drive display area control signal ENBSC. Here, in the display of the active matrix liquid crystal display device, only the normal display (FIG. 2A) for displaying the entire display area 10 as shown in FIG. 2 and the partial display area 10P only. There is a partial display (FIG. 2 (b)) for performing display, but the SC inversion drive display area control signal is a control signal for designating a display area for SC inversion drive. It is a signal supplied from the figure. That is, the period when the SC inversion drive display area control signal ENBSC is at the low level corresponds to the partial display area, and the period when the SC inversion drive display area control signal ENBSC is at the high level corresponds to the background display area.

  The vertical drive circuit 50 is a circuit that sequentially outputs gate signals GL1, GL2,... To the gate lines 40-1, 40-2,. The vertical drive circuit 50 includes a shift register including a plurality of shift register units S / R1, S / R2, S / R3,... Connected in series. This shift register sequentially shifts the vertical start signal STV input to the first shift register unit S / R1 in the first stage based on the vertical clocks CKV1 and CKV2 (CKV2 is an inverted clock of CKV1). The first AND circuit 51 is provided with the output of the first shift register unit S / R1, the output of the second shift register unit S / R2, and the output enable signal ENB. The first gate signal GL1 is output from the first to the gate line 40-1 in the first row.

  The second AND circuit 52 is provided with the output of the second shift register unit S / R2, the output of the third shift register unit S / R3, and the output enable signal ENB. The second gate signal GL2 is output to the gate line 40-2 in the second row. The output enable signal ENB is a clock that falls to a low level every half cycle of the vertical clock CKV1, and prevents the gate signals output to adjacent gate lines, for example, GL1 and GL2, from overlapping with each other. This is a signal for eliminating the problem.

  The SC inversion drive circuit 70 includes SC inversion control units 71, 72,... Provided corresponding to the respective rows, and the SC inversion control units 71, 72,. And inversion control signals SC1, SC2,... For inverting the potentials of the second auxiliary capacitance lines (61-1, 62-1), (61-2, 62-2),. To do. These inversion control signals SC1, SC2,... Control the switching of the switches SW1, SW2,.

  The SC inversion control unit 71 corresponding to the first row is an SC inversion reference signal CKVSC that repeats inversion in one frame cycle, an SC inversion drive display area control signal ENBSC, and a gate signal corresponding to the second row. Based on the gate signal GL2, the inversion control signal SC1 is output. The inversion control signal SC1 repeats inversion in one frame period in synchronization with the rising edge of the second gate signal GL2. The SC inversion control unit 72 corresponding to the second row is an SC inversion reference signal CKVSC that repeats inversion in one frame period, an SC inversion drive display area control signal ENBSC, and a gate signal corresponding to the third row. The inverted control signal SC2 is output based on the third gate signal GL3. The inversion control signal SC2 repeats inversion in one frame period in synchronization with the rising edge of the third gate signal GL3. The SC inversion control units corresponding to the other rows have the same configuration.

  For example, when the inversion control signal SC1 changes to a high level, the potential of the first auxiliary capacitance line 61-1 is changed to a low level (VSCL) by the switch SW1, and the potential of the second auxiliary capacitance line 62-1 is high. When the level shifts to the level (VSCH) and the inversion control signal SC1 changes to the low level, the potential of the first auxiliary capacitance line 61-1 is inverted to the high level (VSCH) by the switch SW1, and the second auxiliary capacitance is reversed. The potential of the line 62-1 is inverted to the low level (VSCL).

  In response to the SC inversion drive display area control signal ENBSC, the inversion drive of the SC inversion drive circuit 70 is performed only for the partial display area selected from the display area 10 and the inversion drive is performed for the background display area. By stopping, power consumption can be reduced. That is, the inversion drive of the SC inversion drive circuit 70 is performed only for the partial display area where the SC inversion drive display area control signal ENBSC is at the low level. Then, the inversion driving of the SC inversion driving circuit 70 is stopped for the background display area where the SC inversion driving display area control signal ENBSC is at a high level. When the inversion drive of the SC inversion drive circuit 70 is stopped, the inversion control signal corresponding to the background display area is fixed at a constant level, whereby the first auxiliary capacitance lines 61-1 and 62 corresponding to the background display area are fixed. ..,... And the second auxiliary capacitance lines 62-1, 62-2,... Are kept at a constant potential of low level or high level.

  The precharge circuit 80 outputs precharge signals DSD to the drain lines 20-1, 20-2, 20-3,... According to the precharge control signal DSG. , 81-3,. These precharge switches 81-1, 81-2, 81-3,... Are turned on before the video signal from the horizontal drive circuit 30 is written to the pixels. Then, the drain lines 20-1, 20-2, 20-3,... Are set to the level of the precharge signal DSD. The precharge signal DSD is used as a background display signal, and this signal is written to each pixel in the background display area through the switching TFT 11.

  Next, the operation of the active matrix liquid crystal display device configured as described above will be described in detail. First, the operation when SC inversion driving is performed will be described. Such an operation involving SC inversion driving is performed when the normal display is performed on the entire display area 10 as shown in FIG. 2 (FIG. 2A) and only when the partial display area 10P is displayed. Is performed (FIG. 2B).

  FIG. 3 is a timing chart of the horizontal scanning system, and is a diagram for explaining writing of a precharge signal and a video signal to a pixel. 4 and 5 are timing charts of the vertical scanning system. More specifically, FIG. 4 is a timing chart of input signals to the vertical drive circuit 50 and the SC inversion drive circuit 70, and FIG. 5 is a timing diagram of internal signals of the inverting drive circuit 70. FIG.

  When the gate signal GL1 rises to a high level, the switching TFT 11 of each pixel in the first row is turned on, the precharge control signal DSG is pulsed in response to the horizontal synchronization signal Hsync, and the precharge signal DSD is output to the drain line 20-1. , 20-2, 20-3,... Thereafter, when the red video signal enable signal RENB is pulsed, the first video switch 31 is turned on, and the red video signal is output from the signal lines S1, S2,. The data is written into the corresponding red pixel GS11 through the TFT 11.

  Thereafter, when the green video signal enable signal GENB is pulsed, the second video switch 32 is turned on, and the green video signal is output from the signal lines S1, S2,. The data is written into the corresponding green pixel GS12 through the TFT 11.

  Thereafter, when the blue video signal enable signal BENB is output in pulses, the third video switch 33 is turned on, and a blue video signal is output from the signal lines S1, S2,. Data is written into the corresponding blue pixel GS13 through the TFT 11.

  Then, when the gate signal GL1 falls and the gate signal GL2 corresponding to the next line rises, the inversion control signal SC1 from the SC inversion control unit 71 rises to a high level. The potential of the auxiliary capacitance line 61-1 changes to the low level (VSCL), and the potential of the second auxiliary capacitance line 62-1 changes to the high level (VSCH). As a result, as shown in FIG. 6, the potential of the pixel electrode 12 of the pixel GS11 changes in the negative direction due to the capacitive coupling of the first auxiliary capacitor 15, and the potential of the adjacent pixel GS12 changes to that of the second auxiliary capacitor 16. It changes in the positive polarity direction due to capacitive coupling. Here, in the dot inversion driving, the polarities of the video signals supplied from the horizontal driving circuit 30 to the adjacent pixels GS11 and GS12 are reversed.

  The above-described operation relates to the first line, but the same applies to the second line. However, as shown in FIG. 1, the connection between the first auxiliary capacitance line 61-2 and the second auxiliary capacitance line 62-2 and the auxiliary capacitance in each pixel is the reverse of the first row. The odd lines have the same connection as the first row, and the even lines have the same connection as the second row.

  According to such SC inversion driving, the potential difference between the positive and negative polarity of the video signal can be reduced and the power consumption of the horizontal drive circuit can be reduced. However, the SC inversion driving itself involves power consumption. Is. Therefore, at the time of partial display, further reduction in power consumption is realized by stopping SC inversion driving for the background display region 10B. The stop of such SC reversal operation will be described with reference to FIG.

  In the present embodiment, the first 80 horizontal periods in one frame period, that is, the display area corresponding to the first to 80th lines is set as the partial display area 10P, and the display area corresponding to the remaining 239 lines is displayed in the background. The area 10B is set. For the partial display area 10P, the SC inversion drive display area control signal ENBSC is set to a low level and the above-described SC inversion drive is performed. However, for the background display area 10B, the SC inversion drive display area control signal ENBSC is high. The SC inversion control units 71, 72,... Of the SC inversion drive circuit 70 corresponding to the background display area 10B are all stopped.

  At this time, a background display signal may be supplied from the horizontal drive circuit 30 to each pixel in the background display region 10B, but the precharge control signal DSG is fixed at a high level and the precharge signal DSD is used as the background display signal. It is preferable to supply. As a result, the operation of the horizontal drive circuit 30 can be stopped, and the power consumption can be further reduced. The background display signal is a signal having a low voltage of about 1 V with respect to the constant potential of the counter electrode 13, and is a white display in a normally white liquid crystal display device and a black display in a normally black liquid crystal display device. It is.

  The frequencies of the vertical clocks CKV1 and CKV2 for the background display area 10B are preferably higher than the frequencies of the vertical clocks CKV1 and CKV2 for the partial display area 10P. This is because the background display area 10B continues to write the same color signal as described above, so that it is not necessary to consider the rise time of the video signal and the like unlike the partial display area 10P, and high-speed signal writing is possible. As a result, when the frame rate is the same as the conventional one, the video signal writing operation in the partial display area 10P can be performed at a low speed by the amount that the display operation in the background display area 10B is performed at a high speed.

  In addition, for the background display area 10B, the output enable signal ENB input to the vertical drive circuit 50 can be fixed at a high level to further reduce power consumption. Since the background color display area 10B continues to write the same color signal as described above, it is not necessary to consider the mutual interference between the gate signals (for example, GL1 and GL2) output to the adjacent gate lines and the video signal output to the drain line. . Therefore, the output enable signal ENB can be fixed at a certain level, and the power consumption can be further reduced.

1 is a circuit diagram of an active matrix liquid crystal display device according to an embodiment of the present invention. It is a figure which shows the display mode in the active matrix type liquid crystal display device concerning embodiment of this invention. FIG. 3 is a timing diagram of a horizontal scanning system in the active matrix liquid crystal display device according to the embodiment of the present invention. FIG. 6 is a timing diagram of input signals to the vertical drive circuit 50 and the SC inversion drive circuit in the active matrix liquid crystal display device according to the embodiment of the present invention. FIG. 4 is a timing diagram of internal signals of a vertical drive circuit 50 and an SC inversion drive circuit in an active matrix liquid crystal display device according to an embodiment of the present invention. It is a figure explaining the change of the pixel electric potential by SC inversion drive in the active matrix type liquid crystal display device concerning the embodiment of the present invention. FIG. 6 is a timing chart for explaining the operation of the active matrix liquid crystal display device according to the embodiment of the present invention. It is a figure explaining the dot inversion drive of an active matrix type liquid crystal display device.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Display area 11 Switching TFT 12 Pixel electrode 13 Counter electrode 14 Liquid crystal 15 1st auxiliary capacity 16 2nd auxiliary capacity 20-1, 20-2, 20-3 Drain line 30 Horizontal drive circuit 31 1st video switch 32 Second video switch 33 Third video switch
40-1, 40-2 Gate line
50 vertical drive circuit 51 first AND circuit 52 second AND circuit
61-1 first auxiliary capacitance line 61-2 second auxiliary capacitance line
70 SC inversion drive circuit 71, 72 SC inversion control unit 80 Precharge circuit 81-1, 81-2, 81-3 Precharge switch S / R1, S / R2, S / R3 Shift register unit

Claims (3)

A display area composed of a plurality of pixels arranged in a matrix;
A pixel electrode disposed for each of the plurality of pixels;
Liquid crystal sealed between the pixel electrode and the counter electrode;
A switching element connected to each of the pixel electrodes and switching according to a gate signal;
A vertical driving circuit for outputting the gate signal based on a vertical clock;
First and second auxiliary capacitance lines arranged corresponding to the pixels of each row;
An auxiliary capacitance line inversion driving circuit that performs inversion driving so that the potentials of the first and second auxiliary capacitance lines are in opposite phases with each other at a predetermined period;
A first auxiliary capacitor connected between the first auxiliary capacitor line and the pixel electrode;
A second auxiliary capacitor connected between the second auxiliary capacitor line and the pixel electrode;
A horizontal driving circuit that supplies a desired video signal to each pixel through the switching element, and the vertical driving circuit and the auxiliary capacitance line inversion driving circuit are respectively provided on both sides of the display area with the display area interposed therebetween. An active matrix liquid crystal display device characterized by being arranged. The auxiliary capacitance line inversion driving circuit is provided corresponding to each row, and is based on an inversion reference signal that repeats inversion in one frame cycle and a gate signal corresponding to the next row, and in synchronization with the rising edge of the gate signal for one frame cycle. And an auxiliary capacitor line inversion drive unit that outputs an inversion control signal that repeats inversion in response to the inversion control signal, and a switch that switches a potential of the first and second auxiliary capacitance lines in accordance with the inversion control signal. 2. An active matrix liquid crystal display device according to 1. 3. The active matrix liquid crystal display device according to claim 1, wherein the horizontal driving circuit supplies video signals having different polarities to pixels adjacent in the row direction.

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