CN109061972A - Display panel - Google Patents
Display panel Download PDFInfo
- Publication number
- CN109061972A CN109061972A CN201811054895.1A CN201811054895A CN109061972A CN 109061972 A CN109061972 A CN 109061972A CN 201811054895 A CN201811054895 A CN 201811054895A CN 109061972 A CN109061972 A CN 109061972A
- Authority
- CN
- China
- Prior art keywords
- display area
- metal layer
- scan line
- sub
- line
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000002184 metal Substances 0.000 claims abstract description 92
- 229910052751 metal Inorganic materials 0.000 claims abstract description 92
- 239000010409 thin film Substances 0.000 claims description 32
- 239000010408 film Substances 0.000 claims description 23
- 239000000758 substrate Substances 0.000 claims description 23
- 230000007704 transition Effects 0.000 claims description 7
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims 1
- 239000010931 gold Substances 0.000 claims 1
- 229910052737 gold Inorganic materials 0.000 claims 1
- 230000003071 parasitic effect Effects 0.000 abstract description 9
- 238000010586 diagram Methods 0.000 description 16
- 238000009413 insulation Methods 0.000 description 16
- 239000004065 semiconductor Substances 0.000 description 7
- 230000000694 effects Effects 0.000 description 5
- 230000005684 electric field Effects 0.000 description 4
- 238000000034 method Methods 0.000 description 4
- 238000001514 detection method Methods 0.000 description 3
- 238000012546 transfer Methods 0.000 description 3
- 230000002159 abnormal effect Effects 0.000 description 2
- 230000000052 comparative effect Effects 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 238000006073 displacement reaction Methods 0.000 description 2
- 238000003487 electrochemical reaction Methods 0.000 description 2
- 238000007689 inspection Methods 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 239000004973 liquid crystal related substance Substances 0.000 description 2
- 230000002441 reversible effect Effects 0.000 description 2
- 230000001960 triggered effect Effects 0.000 description 2
- 238000004804 winding Methods 0.000 description 2
- 241000208340 Araliaceae Species 0.000 description 1
- 235000005035 Panax pseudoginseng ssp. pseudoginseng Nutrition 0.000 description 1
- 235000003140 Panax quinquefolius Nutrition 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000004744 fabric Substances 0.000 description 1
- 235000008434 ginseng Nutrition 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
Classifications
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/13624—Active matrix addressed cells having more than one switching element per pixel
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
Landscapes
- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Mathematical Physics (AREA)
- Crystallography & Structural Chemistry (AREA)
- Chemical & Material Sciences (AREA)
- Optics & Photonics (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Computer Hardware Design (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
- Liquid Crystal (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Abstract
The invention describes a display panel, which comprises a display area and a non-display area surrounding the display area, a plurality of scanning lines and a plurality of data lines, a demultiplexing unit comprising a plurality of switching elements, wherein each switching element comprises a control end, an input end and an output end, the control ends of the switching elements of each demultiplexing unit are respectively connected to different timing control lines, the timing control lines are arranged in the non-display area, the scanning lines comprise first scanning lines, the first scanning lines comprise a first part and a second part, the first part is overlapped with the timing control lines, and the first part and the second part are positioned on different film layers. According to the display panel, the overlapping area of the scanning lines and the time sequence control lines adopts the metal film layer different from the scanning lines in the display area, so that the distance between the scanning lines and the time sequence control lines in the overlapping area can be increased, the parasitic capacitance between the time sequence control lines and the scanning lines is reduced, and the power consumption of the time sequence control lines is reduced.
Description
Technical field
The present invention relates to display fields, more particularly to a kind of display panel.
Background technique
With the development of science and technology, the purposes of the display device with display panel is more and more extensive, so that people couple
The requirement of display panel is more and more diversified, is no longer only satisfied with the performance of the routine such as large scale, fine definition of display panel
Index also has more diversified requirement to the shape of display panel, therefore special-shaped display panel occurs.
The appearance of special-shaped display panel breaches the limitation of display panel single rectangular structure, not only makes display effect
It is more diversified, and make the application approach of display panel also more and more extensive, it has been successfully applied to such as wrist-watch, glasses
Or in the wearable Electronic Design of Intelligent bracelet etc.Compared to convention display, the main distinction of special-shaped display screen is
Non-rectangle special shape is presented in its display area, and in general, circuit trace and circuit module in display screen are all rule
Structure then, therefore, when it is applied to special-shaped display screen, especially at the edge of abnormity display, such as curved edge, due to side
The particularity of edge structure can make frame region be difficult to be routed if electrode module, circuit trace quote conventional design, or
Unreasonable structure after person's wiring causes the deterioration of display result or appearance to be unable to satisfy customer demand.
Summary of the invention
In view of this, the present invention provides a kind of display panel.
The present invention provides a kind of display panels, comprising:
Array substrate, the array substrate include display area and non-display area, and the non-display area is around described
Display area setting；
Plural scan line and plural data line, the plural number scan line and the plural data line intersection are set
It sets；In the display area, two adjacent scan lines and adjacent two data lines intersect one sub- picture of restriction
Plain region；
De-multiplexing circuitry is arranged in the non-display area；The de-multiplexing circuitry includes multiple demultiplexing units, each
The demultiplexing unit includes multiple switch element；Each switch element includes control terminal, input terminal and output end；Each
The control terminal of the multiple switch element of demultiplexing unit is respectively connected to different timing control lines, each demultiplexing
The input terminal of the multiple switch element of unit is connected to identical signal input bus, the institute of each demultiplexing unit
The output end for stating multiple switch element is respectively connected to the different data lines；
The timing control line is arranged in the non-display area；
The plural number scan line includes the first scan line, and first scan line includes first part and second part,
The first part and the timing control line are overlapping, and the first part is located at different film layers from the second part.
Compared with prior art, the present invention at least has the advantages that one of prominent as follows:
Display panel provided in an embodiment of the present invention in plural scan line, in the overlapping region with timing control line, is adopted
With the metallic diaphragm for being different from scan line in display area, overlapping region scan line is capable of increasing at a distance from timing control line,
Reduce the parasitic capacitance between timing control line and scan line, reduces the power consumption of timing control line, and then reduce display panel
Power consumption, while cabling arrangement is improved, improve display effect.
Detailed description of the invention
Fig. 1 is the overlooking structure diagram of display panel provided in an embodiment of the present invention；
Fig. 2 is the amplifying circuit schematic illustration in the region S in Fig. 1；
Fig. 3 is the overlooking structure diagram in the region S in Fig. 1 of a reference examples of the invention；
Fig. 4 is the schematic cross-sectional view in Fig. 3 along AA '；
Fig. 5 is the schematic cross-sectional view in Fig. 3 along BB '；
Fig. 6 is the schematic cross-sectional view in Fig. 3 along CC '；
Fig. 7 is the overlooking structure diagram in the region S in Fig. 1 of one embodiment of the invention；
Fig. 8 is the schematic cross-sectional view in Fig. 7 along AA '；
Fig. 9 is the schematic cross-sectional view in Fig. 7 along BB '；
Figure 10 is the schematic cross-sectional view in Fig. 7 along CC '；
Figure 11 is the overlooking structure diagram in the region S in Fig. 1 of another embodiment of the present invention；
Figure 12 is the schematic cross-sectional view in Figure 11 along DD '；
Figure 13 is the schematic cross-sectional view in Figure 11 along EE '；
Figure 14 is the schematic cross-sectional view in Figure 11 along CC '；
Figure 15 is the overlooking structure diagram of the second part of the active layer and the first scan line of de-multiplexing circuitry in Figure 11.
Specific embodiment
To make the above purposes, features and advantages of the invention more obvious and understandable, below in conjunction with attached drawing and implementation
The present invention will be further described for example.
It should be noted that elaborating detail in the following description to fully understand the present invention.But this hair
Bright to be different from other way described herein with a variety of and be implemented, those skilled in the art can be without prejudice in the present invention
Similar popularization is done in the case where culvert.Therefore the present invention is not limited by following public specific embodiment.
Fig. 1 to Fig. 2 is please referred to, Fig. 1 is the overlooking structure diagram of display panel provided in an embodiment of the present invention, and Fig. 2 is
The amplifying circuit schematic illustration in the region S in Fig. 1.
In conjunction with referring to figs. 1 to Fig. 2, in a reference examples of the embodiment of the present invention, display panel includes array substrate, should
Array substrate includes display area A1 and non-display area A2, and non-display area A2 is arranged around display area A1.Specifically,
In one embodiment of the invention, display area A1 includes curved edge, with reference to Fig. 1, one embodiment of the present of invention
In, display area A1 is round viewing area.
Multi-strip scanning line G (G1, G2 ... Gn) and multiple data lines D (D1, D2 ..., D are provided in array substrate
(3m-1), D (3m)), m and n are the positive integer greater than 1, multi-strip scanning line G and multiple data lines D from non-display area to
Non-display area extends, and multi-strip scanning line and multiple data lines are arranged in a crossed manner.In display area A1, two adjacent scan line G
Intersect with two adjacent data lines and limits a subpixel area P.Also, in the A1 of display area, scan line G is along first party
To extension, data line D extends in a second direction, wherein first direction and second direction are mutually perpendicular to.With reference to Fig. 1 and Fig. 2, originally
In inventive embodiments, first direction is the horizontal direction of diagram, and second direction is the vertical direction of diagram.
In each subpixel area P, it is provided with display thin film transistor (TFT) T and pixel electrode E1, the display film crystal
The grid of pipe T is electrically connected with corresponding scan line G, and the source electrode of display thin film transistor (TFT) T is electrically connected with corresponding data line D, is shown
Show that the drain electrode of thin film transistor (TFT) T is electrically connected with pixel electrode E1, the signal when showing that thin film transistor (TFT) T is opened, on data line D
By showing that thin film transistor (TFT) T is transmitted to pixel electrode E1.Driving liquid can be formed between pixel electrode E1 and public electrode E2
The electric field of brilliant molecule rotation, to be shown.
It further include the de-multiplexing circuitry that non-display area A2 is set in embodiment provided by the invention
(demultiplexer, DEMUX) is decomposed into multiple data letters for inputting a signal into the data resultant signal transmitted on bus DB
Number, and be transmitted separately on corresponding multiple data lines D.In one embodiment of the invention, each de-multiplexing circuitry includes
Multiple demultiplexing units, each demultiplexing unit show four demultiplexing units, often with reference to Fig. 2 including three switch elements
A demultiplexing unit includes three switch element M.Each switch element includes control terminal, input terminal and output end.Each demultiplex
Different timing control lines is respectively connected to the control terminal of the multiple switch element of unit.In the present embodiment, in array substrate
It is provided with three timing control lines, including the first timing control line CK1, the second timing control line CK2 and third timing control line
The control terminal branch of CK3, three switch elements of each demultiplexing unit are connected to different timing control lines.Three timing controls
Line processed sequentially inputs timing control signal respectively, which is square-wave signal, in synchronization, three timing control
Only have on a timing control line on line and transmit square-wave signal, three timing control lines successively transmit, to control same demultiplexing
Three switch elements in unit are successively opened.The input terminal of three switch elements of each demultiplexing unit is connected to identical
Signal input bus.With reference to Fig. 2, four bars input bus DB1 ... ... DBm are shown, wherein m is the positive integer greater than 1,
The corresponding demultiplexing unit of every bars input bus.The output end branch of three switch elements of each demultiplexing unit connects
It is connected to different data lines, with this, is successively opened by three switch elements of demultiplexing unit, bus can be input a signal into
On data-signal, be successively transferred on different data lines.In the present embodiment, number corresponding with signal input bus DB1
It is D1, D5 and D3 according to line, data line corresponding with signal input bus DB2 is D4, D2 and D6, and adjacent two bars input is total
The corresponding data line of line can be arranged in a crossed manner, this is because when display panel is shown, in order to avoid flashing is asked
Topic, can set the signal on two adjacent data lines to the signal of reverse phase, if a bars input bus corresponding three
There are the signal of opposite in phase in data line, then the letter that signal input bus needs input phase opposite at the time of corresponding
Number, it will cause power consumption rising, and after data line and corresponding signal input bus arranged in a crossed manner, same signal input bus pair
The data line answered, transmission signal phase be all it is identical, in signal input process, without additionally carrying out the phase of signal
Adjustment, saving power consumption, and adjacent signal input bus, the signal inversion of input, it can achieve number adjacent on viewing area
According to line signal polarity reverse effect.In the present embodiment, the switch element M in de-multiplexing circuitry can be thin film transistor (TFT), i.e.,
The control terminal of switch element M can be grid, and input terminal can be source electrode, and output end is drain electrode.It should be noted that this implementation
It is to be illustrated so that a demultiplexing unit includes three switch elements as an example, in the other embodiment of the present invention in example
In, each demultiplexing unit can also include the switch element of other numbers, for example, 4,6 or 8, it can be according to tool
The resolution ratio and resolution and border width demand of body are specifically designed, in demultiplexing unit the quantity of switch element with
The quantity of timing control line is corresponding.
In the present embodiment, three timing control lines, i.e. the first timing control line CK1, the second timing control line CK2, third
Timing control line CK3 is respectively positioned on non-display area.
In traditional rectangular display panel, since display area is rectangle, so surrounding the non-display area of display area
Domain is also rectangle, therefore, some driving circuits, such as area of grid circuit, the elements such as timing control line, non-display area can
To be arranged along the direction that data line extends.And in one embodiment of the invention, with reference to Fig. 1 and Fig. 2, due to display area A1
For circle, therefore, in non-display area, the elements such as gate driving circuit, timing control line need to surround display area A1 setting,
That is, it is not to extend arrangement along single direction.With reference to Fig. 2, signal input bus DB and timing control line CK include
The line segment extended along first direction and in a second direction.Scanning signal on scan line G is provided by gate driving circuit, and grid drives
Dynamic circuit includes multiple vertical transfer registers (vertical shift register, VSR), each vertical transfer register
Correspondence is connected with a grid, with reference to Fig. 2, shows a vertical transfer register VSR (n) and the scanning that is electrically connected
Line Gn, wherein n is the positive integer greater than 1.In traditional rectangular display, scan drive circuit, i.e., multiple vertical movements are posted
Storage is usually located at non-display area identical with data line extending direction, and de-multiplexing circuitry is located at and scan line extending direction
Identical non-display area, i.e. scan drive circuit are located at different non-display areas from de-multiplexing circuitry, member between the two
There is no overlapping or intersections for part and signal wire.And in the present embodiment, it is circular at this since display area is circle
The corresponding non-display area of arc area not only needs that gate driving circuit is arranged, but also needs that de-multiplexing circuitry is arranged, and causes cloth
Line is difficult.
In the present embodiment, in multi-strip scanning line, including the first scan line, first scan line include first part and
Two parts, the first part of first scan line and timing control line are overlapping, and the first part and second part are located at not
Same film layer.Subsection setup is carried out by the scan line that will be overlapped with timing control line, increases scan line and timing control line is handed over
The distance in folded region, and then reduce the parasitic capacitance of overlapping region, the power consumption of timing control line is reduced, and then reduce display panel
Power consumption, while improve cabling arrangement, improve display effect.
It is illustrated below by specific reference examples and embodiment.
With reference to Fig. 3-Fig. 6 and Fig. 7-Figure 10.Fig. 3 is the vertical view knot in the region S in Fig. 1 of a reference examples of the invention
Structure schematic diagram, Fig. 4 are the schematic cross-sectional view in Fig. 3 along AA ', and Fig. 5 is the schematic cross-sectional view in Fig. 3 along BB ', Fig. 6
For the schematic cross-sectional view in Fig. 3 along CC '.Fig. 7 is the overlooking structure diagram in the region S in Fig. 1 of the embodiment of the present invention,
Fig. 8 is the schematic cross-sectional view in Fig. 7 along AA ', and Fig. 9 is the schematic cross-sectional view in Fig. 7 along BB ', and Figure 10 is edge in Fig. 7
The schematic cross-sectional view of CC '.In order to become apparent from the opposite position for showing scan line and de-multiplexing circuitry and timing control line
Relationship is set, the structures such as gate driving circuit are omitted in the overlooking structure diagram of reference examples and embodiment of the invention.
With reference to Fig. 3-Fig. 6, in reference examples of the invention, array substrate includes substrate 100, and is provided in array substrate
One metal layer 101 is provided with the first insulating layer 102 on the first metal layer 101, is provided with semiconductor on the first insulating layer 102
Layer, is provided with second metal layer 103 on semiconductor layer and the first insulating layer 102, is provided with second in second metal layer 103
Insulating layer 104, and the third insulating layer 106 in second insulating layer 104, and on third insulating layer 106
Four insulating layers 108.In reference examples of the invention, third insulating layer 106 is organic film, the first insulating layer 102, second insulating layer
104 and the 4th insulation 108 be inorganic film, the thickness of third insulating layer 106 is greater than 5 times of other each thickness of insulating layer
More than, planarization can be played the role of.In the two sides of the 4th insulating layer 108, it is respectively arranged with pixel electrode E1 and common electrical
Pole E2 is with pixel electrode upper in this reference examples, what public electrode was illustrated for lower, in other of the invention
In embodiment, it is also possible to pixel electrode under, public electrode is upper.
In reference examples of the invention, it is located at the first metal layer 101 in display area A1, scan line G, and in viewing area
The grid T1 of domain A1, display thin film transistor (TFT) T also are located at the first metal layer 101.In non-display area A2, de-multiplexing circuitry it is each
The grid M1 of the switch element M (i.e. thin film transistor (TFT)) of a demultiplexing unit is located at the first metal layer 101, also, by non-display
The scan line G that region A2 extends to display area A1 also is located at the first metal layer.The active layer of the switch element M of demultiplexing unit
The active layer T4 of M4 and display thin film transistor (TFT) is respectively positioned on semiconductor layer.In display area A1, data line D and display film are brilliant
The source electrode T2 and drain electrode T3 of body pipe T is located at second metal layer.And in non-display area, each demultiplexing unit of de-multiplexing circuitry
Switch element M source electrode M2 and drain electrode M3 also be located at second metal layer 103.And signal input bus DB and timing control line
CK also is located at second metal layer 103, and the grid M1 and timing control line CK of switch element M is electrically connected by via hole.Switch element M
Source electrode M2 and signal input bus DB pass through be located at the first metal layer bridge realize electrical connection.
Further, in comparative example of the invention, public electrode E2 can also include multiple sub- public electrodes, multiple
The sub- mutually indepedent insulation set of public electrode, every sub- public electrode can be electrically connected with a touching signals cabling.In conjunction with ginseng
It examines Fig. 1 and Fig. 3, in Fig. 1, shows multiple mutually independent sub- public electrodes, every sub- public electrode and three sub-pixels pair
It should be arranged, in actual products, every sub- public electrode can also be correspondingly arranged with more sub-pixels.Every sub- public electrode
It is connected to driving chip by touching signals cabling L, driving chip controls each sub- public electrode and inputs common electrical in the display stage
Pressure forms electric field between pixel electrode E1, and in the touch-control stage, touch control detection letter is inputted simultaneously to each sub- public electrode
Number, by detecting feedback signal, it can detecte touch location.In order to clearly show that the relationship of public electrode Yu touching signals line L,
Three touching signals cablings are illustrated only in Fig. 1.In order to cooperate circular display area, at least partly touching signals cabling is being shown
Region A1 includes the line segment extended in a first direction and the line segment extended in a second direction.In this reference examples, it is additionally provided with
Three metal layers, the touching signals cabling are located at third metal layer.
In conjunction with reference Fig. 3 and Fig. 4, in this reference examples, it is located at the first metal layer in non-display area A2, scan line G
101, timing control line CK are located at second metal layer 103, and in its overlapping region, scan line G and timing control line CK are across first
The insulation of insulating layer 102 intersects, and since the first insulating layer 102 is inorganic insulation layer, thicknesses of layers is relatively thin, therefore, in scan line G and
The overlapping region of timing control line CK, can have biggish parasitic capacitance, increase the load of timing control line CK, increase function
Consumption.
With reference to Fig. 7-Figure 10, in the embodiment of the present invention, array substrate includes substrate 100, is provided in array substrate
The first metal layer 101 is provided with the first insulating layer 102 on the first metal layer 101, is provided on the first insulating layer 102 and partly leads
Body layer is provided with second metal layer 103 on the first insulating layer of semiconductor level 102, and is provided in second metal layer 103
Two insulating layers 104, and the third insulating layer 106 in second insulating layer 104, and on third insulating layer 106
4th insulating layer 108.In the embodiment of the present invention, third insulating layer 106 is organic film, the insulation of the first insulating layer 102, second
Layer 104 and the 4th insulation 108 are inorganic film, and the thickness of third insulating layer 106 is greater than the 5 of other each thickness of insulating layer
Times or more, planarization can be played the role of.In the two sides of the 4th insulating layer 108, it is respectively arranged with pixel electrode E1 and public
Electrode E2 is with pixel electrode upper in the present embodiment, what public electrode was illustrated for lower, in its of the invention
In his embodiment, it is also possible to pixel electrode under, public electrode is upper.
In the present embodiment, in multi-strip scanning line, first scan line is included at least, the present embodiment is with scan line Gn
It is illustrated for first scan line, the first scan line Gn includes first part Ga and second part Gb, wherein first part Ga
It is overlapping with timing control line CK, and first part Ga and second part Gb is located at different film layers.
In an embodiment of the present invention, in display area A1, the part that the first scan line is located at the region is second part
Gb, second part Gb are located at the first metal layer 101, and in display area A1, show the also position the grid T1 of thin film transistor (TFT) T
In the first metal layer 101.In non-display area A2, (i.e. film is brilliant by the switch element M of each demultiplexing unit of de-multiplexing circuitry
Body pipe M) grid M1 be located at the first metal layer 101, also, both included first in non-display area A2, the first scan line Gn
Divide Ga, also includes second part Gb, wherein first part Ga mutually overlaps mutually with sequential control circuit CK.Demultiplexing unit is opened
The active layer T4 of the active layer M4 and display thin film transistor (TFT) that close element M are respectively positioned on semiconductor layer.In display area A1, data line
The source electrode T2 and drain electrode T3 of D and display thin film transistor (TFT) T is located at second metal layer.And in non-display area, de-multiplexing circuitry
Each demultiplexing unit switch element M source electrode M2 and drain electrode M3 also be located at second metal layer 103.And signal input is total
Line DB and timing control line CK also is located at second metal layer 103, and the grid M1 and timing control line CK of switch element M passes through via hole
Electrical connection.The source electrode M2 and signal input bus DB of switch element M realizes electrical connection by being located at the bridge of the first metal layer.
Further, in the present embodiment, public electrode E2 can also include multiple sub- public electrodes, and multiple son is public
The mutually indepedent insulation set of electrode can be each electrically connected from public electrode with a touching signals cabling.In conjunction with reference Fig. 1 and
In Fig. 7, Fig. 1, multiple mutually independent sub- public electrodes are shown, every sub- public electrode is correspondingly arranged with three sub-pixels,
In actual products, every sub- public electrode can also be correspondingly arranged with more sub-pixels.Every sub- public electrode passes through touching
Control signal lead L is connected to driving chip, and driving chip controls each sub- public electrode and inputs common voltage in the display stage, with picture
Electric field is formed between plain electrode E1, and in the touch-control stage, touch control detection signal is inputted simultaneously to each sub- public electrode, passes through inspection
Feedback signal is surveyed, can detecte touch location.In order to clearly show that the relationship of public electrode Yu touching signals line L, only show in Fig. 1
Three touching signals cablings are gone out.In order to cooperate circular display area, at least partly touching signals cabling is in display area A1 packet
Include the line segment extended in a first direction and the line segment extended in a second direction.In the present embodiment, it is additionally provided with third metal layer,
The touching signals cabling is located at third metal layer.Also, in the present embodiment, the first part Ga of the first scan line G (n) is located at the
Three metal layers.
In the present embodiment, second metal layer between the first metal layer and third metal layer, and the first metal layer and
It is provided with second insulating layer between second metal layer, third insulating layer is provided between second metal layer and third metal layer.Its
Middle third insulating layer is organic film, thickness namely third metal layer and second metal layer of the thickness greater than second insulating layer
Between insulating layer thickness, greater than the thickness of insulating layer between second metal layer and the first metal layer.
It include being located at third in non-display area A2, the first scan line Gn in the present embodiment in conjunction with reference Fig. 7 and Fig. 8
The first part Gb of metal layer, timing control line CK are located at second metal layer 103, in its overlapping region, the first scan line Gn's
First part and timing control line CK intersect across second insulating layer 104 and the insulation of third insulating layer 106.Due to third insulating layer
106 be organic insulator, and thicknesses of layers is thicker, the thickness of the inorganic insulation layer commonly greater than 5 times, therefore, scan line and when
The overlapping region of sequence control line CK, scan line and timing control line compare comparative example in the direction row perpendicular to substrate 100, distance
It greatly improves, parasitic capacitance very little, reduces the power consumption of timing control line, and then reduce the power consumption of display panel, improve simultaneously
Cabling arrangement, improves display effect.
Further, the first part Ga and second part Gb of the first scan line can be by through the first insulation, the
The via hole of two insulating layers and third insulating layer realizes electrical connection.Also, the of the first scan line is formed using third metal layer
A part can be arranged with touching signals line same layer, increase metallic diaphragm without additional, do not increase technique.
Further, the embodiment of the present invention, can also include the second scan line, and the second scan line is entirely located in first
Metal layer.Circle in this present embodiment is shown for it, referring to FIG. 1, driving chip is located at the circle display panel
The lower section of diagram, therefore, de-multiplexing circuitry can be provided only on the side semicircle for being provided with driving chip of round display panel
Non-display area, and the non-display area of the other side semicircle opposite with de-multiplexing circuitry is provided with is not provided with demultiplexing
Circuit, so without considering the overlapping problem of scan line Yu timing control line, therefore, in the one side edge, scan line can be with
It is only located at the first metal layer.
The present embodiment is only illustrated by taking circular display area as an example, in other embodiments of the invention, can also be wrapped
The display area for including other shapes can make scan line when the corresponding timing control line of de-multiplexing circuitry and overlapping scan line
Part including being located at different film layers, to realize the reduction of parasitic capacitance.
In general, in de-multiplexing circuitry switch element M driving capability, be far longer than in the sub-pixel of display area and show film
The driving capability of transistor T, therefore, the active layer size of switch element, is far longer than display area A1's in de-multiplexing circuitry
The size of the active layer of display thin film transistor (TFT) T in sub-pixel.With reference to Fig. 7, in the present embodiment, the switch of de-multiplexing circuitry
Element M namely thin film transistor (TFT) are less than its width in a second direction along the width of first direction, and first of the first scan line
Point Ga is in de-multiplexing circuitry region, between two adjacent thin film transistor (TFT)s, and and thin film transistor (TFT) perpendicular to battle array
No overlap on the direction of column substrate.It is provided in this way, the first scan line is in de-multiplexing circuitry region, with de-multiplexing circuitry without friendship
It is folded, the parasitic capacitance of vertical direction will not be generated, further reduced power consumption.
Please further refer to Fig. 2 and Fig. 7, in the present embodiment, transition region A3 can further include, transition region A3
Between display area A1 and non-display area A2.More specifically, transitional region A3 is located at display area A1 and non-display
Between the de-multiplexing circuitry of region A2.In transitional region A3, it is provided with multiple individual redundant sub-pixel DP.Individual redundant sub-pixel DP's sets
It sets, the display boundary that can mitigate display area A1 is abnormal.Individual redundant sub-pixel DP can be identical with sub-pixel P-structure, that is, is arranged
There are display thin film transistor (TFT) and pixel electrode, pixel electrode can also be not provided with, setting is not provided with display thin film transistor (TFT) and picture
Plain electrode, this is not limited by the present invention.The first part of first scan line and the connection via hole H1 of second part can be located at
In individual redundant sub-pixel DP, via hole is arranged in individual redundant sub-pixel, it will not be to the winding displacement knot of display area or non-display area
Structure brings any influence, without carrying out special designing.The first part of first scan line and the via hole of second part, with viewing area
Distance of the domain on the direction along scan line namely on first direction, greater than the width of two sub-pixels.By via hole and viewing area
The boundary in domain maintains a certain distance, and after can preventing subsequent liquid crystal from injecting, connects in the different metal layer of via area
Raw electrochemical reaction is triggered, the display of display area is influenced.
It is the overlooking structure diagram in the region S in Fig. 1 of another embodiment of the present invention with reference to Figure 11-Figure 15, Figure 11,
Figure 12 is the schematic cross-sectional view in Figure 11 along DD ', and Figure 13 is the schematic cross-sectional view in Figure 11 along EE ', and Figure 14 is figure
Along the schematic cross-sectional view of CC ' in 11, Figure 15 is first of the active layer of de-multiplexing circuitry and the first scan line in Figure 11
The overlooking structure diagram divided.In order to become apparent from the relative position for showing scan line and de-multiplexing circuitry and timing control line
The structures such as gate driving circuit are omitted in the overlooking structure diagram of reference examples and embodiment of the invention in relationship.
With reference to Figure 11-Figure 14, in the embodiment of the present invention, array substrate includes substrate 100, is provided in array substrate
The first metal layer 101 is provided with the first insulating layer 102 on the first metal layer 101, is provided on the first insulating layer 102 and partly leads
Body layer is provided with second metal layer 103 on the first insulating layer of semiconductor level 102, and is provided in second metal layer 103
Two insulating layers 104, and the third insulating layer 106 in second insulating layer 104, and on third insulating layer 106
4th insulating layer 108.In the embodiment of the present invention, third insulating layer 106 is organic film, the insulation of the first insulating layer 102, second
Layer 104 and the 4th insulation 108 are inorganic film, and the thickness of third insulating layer 106 is greater than the 5 of other each thickness of insulating layer
Times or more, planarization can be played the role of.In the two sides of the 4th insulating layer 108, it is respectively arranged with pixel electrode E1 and public
Electrode E2 is with pixel electrode upper in the present embodiment, what public electrode was illustrated for lower, in its of the invention
In his embodiment, it is also possible to pixel electrode under, public electrode is upper.
In the present embodiment, in multi-strip scanning line, first scan line is included at least, the present embodiment is with scan line Gn
It is illustrated for first scan line, the first scan line Gn includes first part Ga and second part Gb, wherein first part Ga
It is overlapping with timing control line CK, and first part Ga and second part Gb is located at different film layers.
In an embodiment of the present invention, in display area A1, the part that the first scan line is located at the region is second part
Gb, second part Gb are located at the first metal layer 101, and in display area A1, show the also position the grid T1 of thin film transistor (TFT) T
In the first metal layer 101.In non-display area A2, (i.e. film is brilliant by the switch element M of each demultiplexing unit of de-multiplexing circuitry
Body pipe) grid M1 be located at the first metal layer 101, also, in non-display area A2, the first scan line Gn both includes first part
Ga also includes second part Gb, wherein first part Ga mutually overlaps mutually with sequential control circuit CK.The switch of demultiplexing unit
The active layer M4 of element M and the active layer T4 of display thin film transistor (TFT) are respectively positioned on semiconductor layer.In display area A1, data line D
And the source electrode T2 and drain electrode T3 of display thin film transistor (TFT) T are located at second metal layer.And in non-display area, de-multiplexing circuitry it is each
The source electrode M2 and drain electrode M3 of the switch element M of a demultiplexing unit also is located at second metal layer 103.And signal input bus DB
It also is located at second metal layer 103 with timing control line CK, the grid M1 and timing control line CK of switch element M is electrically connected by via hole
It connects.The source electrode M2 and signal input bus DB of switch element M realizes electrical connection by being located at the bridge of the first metal layer.
Further, in the present embodiment, public electrode E2 can also include multiple sub- public electrodes, and multiple son is public
The mutually indepedent insulation set of electrode, every sub- public electrode can be electrically connected with a touching signals cabling.In conjunction with reference Fig. 1 and
In Fig. 7, Fig. 1, multiple mutually independent sub- public electrodes are shown, every sub- public electrode is correspondingly arranged with three sub-pixels,
In actual products, every sub- public electrode can also be correspondingly arranged with more sub-pixels.Every sub- public electrode passes through touching
Control signal lead L is connected to driving chip, and driving chip controls each sub- public electrode and inputs common voltage in the display stage, with picture
Electric field is formed between plain electrode E1, and in the touch-control stage, touch control detection signal is inputted simultaneously to each sub- public electrode, passes through inspection
Feedback signal is surveyed, can detecte touch location.In order to clearly show that the relationship of public electrode Yu touching signals line L, only show in Fig. 1
Three touching signals cablings are gone out.In order to cooperate circular display area, at least partly touching signals cabling is in display area A1 packet
Include the line segment extended in a first direction and the line segment extended in a second direction.In the present embodiment, it is additionally provided with third metal layer,
The touching signals cabling is located at third metal layer.Also, in the present embodiment, the first part Ga of the first scan line Gn is located at third
Metal layer.
In the present embodiment, second metal layer between the first metal layer and third metal layer, and the first metal layer and
It is provided with second insulating layer between second metal layer, third insulating layer is provided between second metal layer and third metal layer.Its
Middle third insulating layer is organic film, thickness namely third metal layer and second metal layer of the thickness greater than second insulating layer
Between insulating layer thickness, greater than the thickness of insulating layer between second metal layer and the first metal layer.
In conjunction with reference Figure 11 and Figure 12, in the present embodiment, in non-display area A2, the first scan line Gn includes being located at the
The first part Ga of three metal layers, timing control line CK are located at second metal layer 103, in its overlapping region, the first scan line Gn
First part and timing control line CK across second insulating layer 104 and third insulating layer 106 insulation intersect.Since third insulate
Layer 106 is organic insulator, and thicknesses of layers is thicker, the thickness of the inorganic insulation layer commonly greater than 5 times, therefore, in scan line and
The overlapping region of timing control line CK, scan line and timing control line are in the direction row perpendicular to substrate 100, and distance is compared to comparison
Example greatly improves, parasitic capacitance very little, reduces the power consumption of timing control line, and then reduce the power consumption of display panel, improves simultaneously
Cabling arrangement, improves display effect.
Further, the first part Ga and second part Gb of the first scan line can be by through the first insulation, the
The via hole of two insulating layers and third insulating layer realizes electrical connection.Also, the of the first scan line is formed using third metal layer
Two parts can be arranged with touching signals line same layer, increase metallic diaphragm without additional, do not increase technique.
Further, the embodiment of the present invention, can also include the second scan line, and the second scan line is entirely located in first
Metal layer.Circle in this present embodiment is shown for it, referring to FIG. 1, driving chip is located at the circle display panel
The lower section of diagram, therefore, de-multiplexing circuitry can be provided only on the side semicircle for being provided with driving chip of round display panel
Non-display area, and the non-display area of the other side semicircle opposite with de-multiplexing circuitry is provided with is not provided with demultiplexing
Circuit, so without considering the overlapping problem of scan line Yu timing control line, therefore, in the one side edge, scan line can be with
It is only located at the first metal layer.
The present embodiment is only illustrated by taking circular display area as an example, in other embodiments of the invention, can also be wrapped
The display area for including other shapes can make scan line when the corresponding timing control line of de-multiplexing circuitry and overlapping scan line
Part including being located at different film layers, to realize the reduction of parasitic capacitance.
In general, in de-multiplexing circuitry switch element M driving capability, be far longer than in the sub-pixel of display area and show film
The driving capability of transistor T, therefore, the active layer size of switch element, is far longer than display area A1's in de-multiplexing circuitry
The size of the active layer of display thin film transistor (TFT) T in sub-pixel.With reference to Figure 11 and Figure 15, in the present embodiment, electricity consumption is demultiplexed
The switch element M on road, is formed in parallel by multiple thin film transistor (TFT)s, specifically, the switch element in de-multiplexing circuitry is to have film
Transistor, which includes active layer M4, and the active layer includes multiple sub- active layers arranged in a second direction.The
The first part Ga of scan line is in de-multiplexing circuitry region, between two adjacent sub- active layers, and it is brilliant with film
The active layer of body pipe no overlap on the direction perpendicular to array substrate.It is provided in this way, the first scan line is in de-multiplexing circuitry
Region, the active layer no overlap with de-multiplexing circuitry will not generate shadow to the switching characteristic of the thin film transistor (TFT) of de-multiplexing circuitry
It rings.
Please further refer to Fig. 2 and Figure 11, in the present embodiment, transition region A3 can further include, the transition region
A3 is between display area A1 and non-display area A2.More specifically, transitional region A3 is located at display area A1 and non-aobvious
Between the de-multiplexing circuitry for showing region A2.In transitional region A3, it is provided with multiple individual redundant sub-pixel DP.Individual redundant sub-pixel DP's
Setting, the display boundary that can mitigate display area A1 are abnormal.Individual redundant sub-pixel DP can be identical with sub-pixel P-structure, that is, sets
Be equipped with display thin film transistor (TFT) and pixel electrode, can also be not provided with pixel electrode, setting be not provided with display thin film transistor (TFT) and
Pixel electrode, this is not limited by the present invention.The first part of first scan line and the connection via hole H1 of second part can positions
In in individual redundant sub-pixel DP, via hole is arranged in individual redundant sub-pixel, it will not be to the winding displacement of display area or non-display area
Structure brings any influence, without carrying out special designing.The first part of first scan line and the via hole of second part, with display
Distance of the region on the direction along scan line namely on first direction, greater than the width of two sub-pixels.By via hole and display
The boundary in region maintains a certain distance, and after can preventing subsequent liquid crystal from injecting, is electrically connected in the different metal layer of via area
Raw electrochemical reaction is triggered, the display of display area is influenced.
The above content is a further detailed description of the present invention in conjunction with specific preferred embodiments, and it cannot be said that
Specific implementation of the invention is only limited to these instructions.For those of ordinary skill in the art to which the present invention belongs, exist
Under the premise of not departing from present inventive concept, a number of simple deductions or replacements can also be made, all shall be regarded as belonging to of the invention
Protection scope.
Claims (10)
1. a kind of display panel, comprising:
Array substrate, the array substrate include display area and non-display area, and the non-display area surrounds the display
Region setting；
Plural scan line and plural data line, the plural number scan line and the plural data line are arranged in a crossed manner；?
The display area, two adjacent scan lines and adjacent two data lines, which intersect, limits a sub-pixel area
Domain；
De-multiplexing circuitry is arranged in the non-display area；The de-multiplexing circuitry includes multiple demultiplexing units, each described
Demultiplexing unit includes multiple switch element；Each switch element includes control terminal, input terminal and output end；Each demultiplex
Different timing control lines, each demultiplexing unit are respectively connected to the control terminal of the multiple switch element of unit
The input terminal of the multiple switch element be connected to identical signal input bus, each demultiplexing unit it is described more
The output end of a switch element is respectively connected to the different data lines；
The timing control line is arranged in the non-display area；
The plural number scan line includes the first scan line, and first scan line includes first part and second part, described
First part and the timing control line are overlapping, and the first part is located at different film layers from the second part.
2. display panel according to claim 1, which is characterized in that further include:
The first metal layer, second metal layer and third metal layer；
The second part of first scan line is located at the first metal layer, and the data line bit is in second metal
Layer, the first part of first scan line are located at the third metal layer.
3. display panel according to claim 2, which is characterized in that further include:
Public electrode, the public electrode include multiple sub- public electrodes, and the multiple sub- public electrode insulate independently of each other to be set
It sets；Each sub- public electrode is electrically connected with a touching signals cabling, and the touching signals cabling is located at the third gold
Belong to layer.
4. display panel according to claim 2, which is characterized in that
The second metal layer between the first metal layer and the third metal layer, and the third metal layer with
The thickness of insulating layer between the second metal layer, greater than insulating layer between the second metal layer and the first metal layer
Thickness.
5. display panel according to claim 1, which is characterized in that
The display area includes curved edge, and in the display area, the scan line is extended in a first direction, the data
Line extends in a second direction, and the first direction is vertical with the second direction.
6. display panel according to claim 5, which is characterized in that
The switch element is thin film transistor (TFT), and the thin film transistor (TFT) is less than along the width of the first direction along described second
The width in direction, the first part of first scan line are set between two adjacent thin film transistor (TFT)s, and with institute
State thin film transistor (TFT) no overlap in the direction perpendicular to the array substrate.
7. display panel according to claim 5, which is characterized in that
The switch element be thin film transistor (TFT), the thin film transistor (TFT) be include active layer, the active layer includes multiple edges
The sub- active layer of the second direction arrangement, it is active that the first part of first scan line is set to the son of adjacent two
Layer between, and with the sub- active layer in the direction perpendicular to the array substrate no overlap.
8. display panel according to claim 1, which is characterized in that
The first part of first scan line is connected with the second part by via hole.
9. display panel according to claim 8, which is characterized in that further include:
Transition region, between the display area and the non-display area, the transition region is provided with more the transition region
A individual redundant sub-pixel, the via hole are located at the individual redundant sub-pixel.
10. display panel according to claim 8, which is characterized in that the via hole is swept with the display area along described
Retouch the width that the distance on the direction of line is greater than two sub-pixels.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811054895.1A CN109061972B (en) | 2018-09-11 | 2018-09-11 | Display panel |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811054895.1A CN109061972B (en) | 2018-09-11 | 2018-09-11 | Display panel |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN109061972A true CN109061972A (en) | 2018-12-21 |
| CN109061972B CN109061972B (en) | 2021-06-08 |
Family
ID=64761228
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201811054895.1A Active CN109061972B (en) | 2018-09-11 | 2018-09-11 | Display panel |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN109061972B (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111240059A (en) * | 2020-02-28 | 2020-06-05 | 厦门天马微电子有限公司 | Display panel and display device |
| WO2021253345A1 (en) * | 2020-06-18 | 2021-12-23 | 京东方科技集团股份有限公司 | Display panel and manufacturing method therefor, and display device |
| CN114270431A (en) * | 2020-06-04 | 2022-04-01 | 京东方科技集团股份有限公司 | Display substrate, manufacturing method and display device |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007140192A (en) * | 2005-11-18 | 2007-06-07 | Epson Imaging Devices Corp | Active matrix type liquid crystal display device |
| CN102254529A (en) * | 2011-05-23 | 2011-11-23 | 友达光电股份有限公司 | Liquid crystal display and method for charging and discharging pixels of liquid crystal display |
| CN107976849A (en) * | 2017-12-29 | 2018-05-01 | 深圳市华星光电技术有限公司 | Array base palte and preparation method thereof |
-
2018
- 2018-09-11 CN CN201811054895.1A patent/CN109061972B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007140192A (en) * | 2005-11-18 | 2007-06-07 | Epson Imaging Devices Corp | Active matrix type liquid crystal display device |
| CN102254529A (en) * | 2011-05-23 | 2011-11-23 | 友达光电股份有限公司 | Liquid crystal display and method for charging and discharging pixels of liquid crystal display |
| CN107976849A (en) * | 2017-12-29 | 2018-05-01 | 深圳市华星光电技术有限公司 | Array base palte and preparation method thereof |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111240059A (en) * | 2020-02-28 | 2020-06-05 | 厦门天马微电子有限公司 | Display panel and display device |
| CN114270431A (en) * | 2020-06-04 | 2022-04-01 | 京东方科技集团股份有限公司 | Display substrate, manufacturing method and display device |
| CN114270431B (en) * | 2020-06-04 | 2023-06-02 | 京东方科技集团股份有限公司 | Display substrate, manufacturing method and display device |
| WO2021253345A1 (en) * | 2020-06-18 | 2021-12-23 | 京东方科技集团股份有限公司 | Display panel and manufacturing method therefor, and display device |
| US11581391B2 (en) | 2020-06-18 | 2023-02-14 | Boe Technology Group Co., Ltd. | Display panel and manufacturing method thereof, and display device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN109061972B (en) | 2021-06-08 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN207380420U (en) | A kind of array substrate and display device | |
| CN106325608B (en) | Touch display panel and touch display device | |
| JP6161782B2 (en) | Capacitive in-cell touch panel and display device | |
| KR101835044B1 (en) | Display apparatus | |
| CN106873226A (en) | A kind of touch-control display panel | |
| CN102902119B (en) | Liquid crystal display panel | |
| CN106652927A (en) | Array substrate | |
| CN107807756A (en) | Array substrate, touch display panel and touch display device | |
| CN107132685A (en) | A kind of display base plate, display panel and display device | |
| US9971212B2 (en) | Array substrate, liquid crystal display panel, and liquid crystal display | |
| WO2021016745A1 (en) | Display substrate, display device, and manufacturing method and driving method for display substrate | |
| CN109061972A (en) | Display panel | |
| CN110471551A (en) | The production method of touch control display and touch control display | |
| CN106873225A (en) | Array base palte, display panel, display device and array base palte driving method | |
| CN110320714A (en) | Liquid crystal display | |
| CN108957889A (en) | Display panel and display device | |
| CN111708237B (en) | Array substrate, display panel and display device | |
| CN101738807B (en) | Thin film transistor array substrate and liquid crystal display device thereof | |
| TWI729735B (en) | Display device | |
| CN117539085A (en) | Array substrate, manufacturing method and embedded touch display panel | |
| WO2021227122A1 (en) | Array substrate and display panel | |
| TW202109493A (en) | Dsiplay panel | |
| CN113406832B (en) | TFT array substrate and driving method thereof | |
| CN108594552B (en) | Display substrate, display panel, display device and driving method thereof | |
| KR20200042047A (en) | Liquid crystal display device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |