JP2009069563A - Liquid crystal display device and driving method for it - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a liquid crystal display device adopting a storage capacitor line driving system, achieving low power consumption for partial display in simple circuit configuration, and preventing the occurrence of display failure when refresh operation for a non-display area is intermittently performed. <P>SOLUTION: When the transition from the whole screen display to the partial display occurs according to a partial display command, refresh operation is performed in two consecutive frames after transition. After that, some frames for non-refresh are connected. Thus, display failure in the first frame after the transition to the partial display can be canceled by refresh operation for the next frame to prevent display failure. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

    The present invention relates to a storage capacitor line driving type liquid crystal display device and a driving method thereof.

  Conventionally, a storage capacitor line driving method is known as a driving method of a liquid crystal display device. In this method, a storage capacitor is provided between the storage capacitor line and the pixel electrode, and after writing a display signal to the pixel electrode, the potential of the storage capacitor line is changed to change the potential of the pixel electrode in the positive or negative direction. Change. As a result, the dynamic range of the display signal can be reduced, so that driving with low power consumption is possible. A liquid crystal display device using this storage capacitor line driving method is described in Patent Document 1.

  In addition, a partial display method is known as a display method of a liquid crystal display device. In this method, a part of the pixel area is a display area where an image is displayed, and the remaining area is a non-display area (a white or black display area) where no image is displayed.

In a storage capacitor line driving liquid crystal display device, when partial display is performed, power consumption can be reduced by stopping driving of a storage capacitor line in a non-display region. This type of liquid crystal display device is described in Patent Document 2.
JP 2002-196358 A JP 2007-140192 A

  However, when driving the storage capacitor line is stopped, if the polarity signal for determining the polarity of the potential of the storage capacitor line is stopped by taking over the polarity of the previous frame, changing the display area results in a complicated operation. There is a problem that the circuit configuration becomes complicated.

  Therefore, in order to simplify the circuit configuration, a method of fixing the polarity signal at the L level or the H level in the non-display area can be considered. By the way, in the non-display area, it is necessary to perform a refresh operation in which a non-display signal is periodically written to the pixel electrode of the corresponding pixel, but in order to further reduce power consumption, it is not performed for all frames. Intermittent refresh (also called thinning refresh) is performed intermittently for some frames.

  However, in the non-display area, when the polarity signal is fixed to the L level or the H level, the intermittent refresh described above causes a display defect.

  The liquid crystal display device of the present invention displays a pixel region composed of a plurality of pixels, a plurality of storage capacitor lines, a storage capacitor connected between the pixel electrode of the pixel and the storage capacitor line, and an image in the pixel region. In the display area, a polarity signal that repeats inversion between the first level and the second level is generated every frame, and in the non-display area where no image is displayed, the polarity signal is set to the first level or A polarity signal generation circuit that is fixed at the second level, a first switching element that switches the potential of the storage capacitor line in accordance with the polarity signal generated by the polarity signal generation circuit, and a display area is changed to a non-display area In this case, a refresh operation for writing a signal corresponding to non-display to the pixel electrode of the pixel corresponding to the non-display area is performed continuously for two or more frames, and refresh is performed in the subsequent frames. Characterized in that it comprises a control circuit for controlling to stop the operation.

  The liquid crystal display device driving method according to the present invention includes a pixel region including a plurality of pixels, a plurality of storage capacitor lines, a storage capacitor connected between the pixel electrode of the pixel and the storage capacitor line, In the display area where the image in the pixel area is displayed, a polarity signal that repeats inversion between the first level and the second level is generated every frame, and in the non-display area where the image is not displayed, the polarity is displayed. A polarity signal generation circuit that fixes the signal to the first level or the second level, and a first switching element that switches the potential of the storage capacitor line in accordance with the polarity signal generated by the polarity signal generation circuit. In the driving method of the liquid crystal display device provided, a refresh operation for writing a signal corresponding to non-display to the pixel electrode of the pixel corresponding to the non-display area when the display area is changed to the non-display area is performed. With intermittently performed for the frame, two frames or more continuously and performs the refresh operation.

  According to the present invention, low power consumption of partial display can be realized with a simple circuit configuration in a storage capacitor line driving type liquid crystal display device. In addition, when the refresh operation of the non-display area is intermittently performed, it is possible to prevent display defects.

  A liquid crystal display device according to an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram of a liquid crystal display device. This liquid crystal display device employs a storage capacitor line driving system and can perform partial display.

  A plurality of pixels are arranged in a matrix to form a pixel region. In FIG. 1, nine pixels of 3 rows × 3 columns are shown for simplicity. Each pixel is arranged corresponding to each intersection of the gate lines GL1 to GL3 and the source lines SL1 to SL3, and includes a pixel transistor 10 made of an N-channel thin film transistor, a pixel electrode 11 connected to the drain of the pixel transistor 10, A liquid crystal 12 is provided between the pixel electrode 11 and the common electrode CE. A common potential VCOM is supplied to the common electrode CE.

  A first storage capacitor line SC1 is provided corresponding to the pixels in the first row, and a storage capacitor 13 is provided between the pixel electrode 11 and the first storage capacitor line SC1. A second storage capacitor line SC2 is provided corresponding to the pixels in the second row, and a storage capacitor 13 is provided between the pixel electrode 11 and the second storage capacitor line SC2. A third storage capacitor line SC3 is provided corresponding to the pixels in the third row, and a storage capacitor 13 is provided between the pixel electrode 11 and the third storage capacitor line SC3.

  The source of the pixel transistor 10 of each pixel in the first column is connected to the first source line SL1, and the source of the pixel transistor 10 of each pixel in the second column is connected to the second source line SL2. The source of the pixel transistor 10 of each pixel in the third column is connected to the third source line SL3.

  The gate of the pixel transistor 10 of each pixel in the first row is connected to the first gate line GL1, and the gate of the pixel transistor 10 of each pixel in the second row is connected to the second gate line GL2. The gate of the pixel transistor 10 of each pixel in the third row is connected to the third gate line GL3.

  In addition, a source line driving circuit 20 is provided for supplying a source signal Sig (display signal) to the first to third source lines SL1 to SL3. The polarity of the source signal Sig is inverted with respect to the reference potential at a constant cycle (for example, one horizontal cycle). Further, a DSG control circuit 21 that supplies the common potential VCOM to the first to third source lines SL1 to SL3 according to the control signal DSG is provided.

  Further, a gate line driving circuit 22 for supplying a gate signal to the first to third gate lines GL1 to GL3 is provided. Further, a storage capacitor line driving circuit 23 for driving the first to third storage capacitor lines SC1 to SC3 is provided. A polarity signal generation circuit 24 that generates a polarity signal POL that determines the polarity of the potential of the first to third storage capacitor lines SC1 to SC3 is provided. The storage capacitor line drive circuit 23 drives the potentials of the first to third storage capacitor lines SC1 to SC3 to the low potential VCOML or the high potential VCOMH based on the polarity signal POL output from the polarity signal generation circuit 24.

[Configuration of Retention Capacitor Line Drive Circuit and Polarity Signal Generation Circuit]
FIG. 2 is a diagram showing the configuration of the storage capacitor line drive circuit 23 and the polarity signal generation circuit 24. First, the configuration of the polarity signal generation circuit 24 will be described. The polarity signal generation circuit 24 includes a frame inversion signal generation circuit 241 and a memory 242. The frame inversion signal generation circuit 241 is a circuit that generates a frame inversion signal that repeats inversion between the H level and the L level for each frame. In the memory 242, data representing a distinction between a display area where an image is displayed and a non-display area where an image is not displayed is stored corresponding to each line (each row). The data is “1” in the display area and “0” in the non-display area. The memory 242 can be formed of, for example, a shift register, and holds and shifts data in synchronization with a clock HCLK that is a pulse signal having a period of one horizontal period (1H period).

  The frame inversion signal generated by the frame inversion signal generation circuit 241 and the data read from the memory 242 in synchronization with the clock HCLK are input to the 2-input AND circuit 243. When the data read from the memory 242 represents the display area, that is, when the data is “1”, the AND circuit 243 outputs the frame inversion signal as it is as the polarity signal POL. The output of the AND circuit 243 is fixed to “0” when the data read from the memory 242 represents a non-display area, that is, when the data is “0”. That is, in this case, the AND circuit 243 outputs the polarity signal POL fixed to “0” (= L level).

  Thus, in the display area, the polarity signal POL is inverted every frame. In addition, when shifting from a full screen display that displays an image in the entire pixel area to a partial display (or when changing the display area in the partial display), the polarity of the polarity signal POL is changed in the non-display area. It is possible to fix. In addition, since the polarity signal generation circuit 24 can be configured by only the frame inversion signal generation circuit 241 (which can be formed by an inversion circuit), the memory 242, and the AND circuit 243, the circuit configuration is simple.

  The Vreset signal is a signal synchronized with the vertical synchronization signal, and resets the read counters of the first memory and the second memory.

  Next, the configuration of the storage capacitor line driving circuit 23 will be described. The polarity signal POL output from the polarity signal generation circuit 24 is supplied to the first to third latch circuits LCH1 to LCH3 provided corresponding to the first to third storage capacitor lines SC1 to SC3, respectively. ~ Latched based on the third timing clocks TCLK1 to TCLK3. The first to third latch circuits LCH1 to LCH3 output and hold the latched polarity signal POL as the first to third latch signals POL1 to POL3. The first to third timing clocks TCLK1 to TCLK3 are generated by the timing control circuit 231 based on the gate signals G1 to G3 and the timing control signal TCLK.

  The inverted polarity signal POL is latched in the second latch circuit LCH2 corresponding to the even lines. This is because the potentials of the storage capacitor lines corresponding to the odd lines (first line, third line,...) And even lines (second line, fourth line,. This is to make it possible. For example, the potentials of the first storage capacitor line SC1 and the second storage capacitor line SC2 are opposite in polarity.

  The first to third latch signals POL1 to POL3 are used as signals for controlling the switching of the first to third switches SW1 to SW3 in the subsequent stage. For example, when the first latch signal POL1 is at the H level, the low potential VCOML is applied to the first storage capacitor line SC1, and when the first latch signal POL1 is at the L level, the first storage capacitor line SC1. Is applied with a high potential VCOMH.

  That is, the potentials of the first to third storage capacitor lines SC1 to SC2 are determined by the rising timing of the first to third timing clocks TCLK1 to TCLK3. In such a storage capacitor line driving system, such timing is generally after the gate signals G1 to G3 fall.

[Configuration of Source Line Driver Circuit and DSG Control Circuit]
FIG. 3 shows a configuration of the source line driver circuit 20 and the DSG control circuit 21 around the pixel region. FIG. 3 shows only the configuration related to the pixel corresponding to the first column of the pixel area. The output terminal of the source driver 14 is connected to one end of the first source line SL1 through the horizontal switch SWH. The horizontal switch SWH switches according to the horizontal scanning signal. When the horizontal switch SWH is turned on, the source signal Sig (display signal) is supplied from the source driver 14 to the first source line SL1. The output terminal of the common electrode driver 15 is connected to the other end of the first source line SL1 through the switch SWS. The switch SWS switches according to the DSG signal. The output terminal of the common electrode driver 15 is connected to the common electrode CE, and the common potential VCOM is supplied to the common electrode CE.

  Therefore, when the switch SWS is turned on, the first source line SL1 and the common electrode CE are short-circuited, and the common potential VCOM is also supplied to the first source line SL1.

Next, an example of the operation of the liquid crystal display device will be described with reference to the timing chart of FIG. This description is based on the circuit of FIG. In the figure, 1), 2) and 3) represent line numbers, ON represents a display area, and OFF represents a non-display area.
Initially, full screen display is performed. Since the memory 242 stores data = “1” corresponding to the first to third lines, the output of the memory 242 maintains “1”. Therefore, the polarity signal POL repeats inversion between the first level and the second level for each frame.

  Based on the first to third timing clocks TCLK1 to TCLK3 generated in time series, the polarity signal POL is latched by the first to third latch circuits LCH1 to LCH3 one after another and inverted every frame. Repeated first to third latch signals POL1 to POL3 are generated. Therefore, the potentials of the first to third storage capacitor lines SC1 to SC3 are repeatedly inverted in synchronization with the first to third latch signals POL1 to POL3, and the storage capacitor line drive is performed. That is, after writing a display signal to the pixel electrode, the potential of the corresponding storage capacitor line is changed, and the potential of the pixel electrode 11 is changed in the positive or negative direction. As a result, the dynamic range of the display signal can be reduced, so that driving with low power consumption is possible.

  Next, a transition is made from full screen display to partial display. Now, it is assumed that the contents of the memory 242 are changed so that the first line corresponds to the display area and the second and third lines correspond to the non-display area. Then, for the first line, the polarity signal POL repeats inversion between the H level and the L level. Since the second and third lines are non-display areas, the polarity signal POL is fixed at the L level. As a result, the driving of the second and third storage capacitor lines SC2 and SC3 is stopped.

  In the non-display area, the pixel is not displayed by writing the common potential VCOM (non-display signal) to the pixel electrode of the corresponding pixel. This will be described with reference to FIG. In the non-display region, the switch SWS is turned on in response to the DSG signal, the first source line SL1 and the common electrode CE are short-circuited, and the common potential VCOM is also supplied to the first source line SL1. When the pixel transistor 10 is turned on according to the gate signal G1, the common potential VCOM is applied to the pixel electrode 11. As a result, the voltage applied to the liquid crystal 12 becomes about 0 V, so that a non-display state (for example, black display in a normally black liquid crystal display device) is obtained.

  Thus, in the non-display area, a refresh operation for periodically writing the non-display signal to the pixel electrode of the corresponding pixel is performed. Then, in order to reduce power consumption, this refresh operation is not performed for all frames, but intermittent refresh is performed in which only some frames are intermittently performed.

  However, as shown in FIG. 4, since the third latch signal POL3 changes from the H level to the L level for the third line after the transition to the partial display, the storage capacitor line is driven and is common to the pixel electrodes. After the potential VCOM (non-display signal) is written, the third storage capacitor line SC3 changes. Then, since the voltage applied to the liquid crystal 12 changes from 0V, display failure occurs when intermittent refresh is performed.

  Subsequently, the display area is changed in the partial display. Here, it is assumed that the contents of the memory 242 are changed so that the first and second lines correspond to the non-display area and the third line corresponds to the display area. Then, since the first and second lines are non-display areas, the polarity signal POL is fixed at the L level. That is, the driving of the first and second storage capacitor lines SC1 and SC2 is stopped. On the other hand, since the third line has been changed to the display area, the polarity signal POL is inverted.

  As described above, in the case of performing partial display, in the non-display area, the polarity of the polarity signal POL is fixed and the driving of the storage capacitor line can be stopped. When such intermittent refresh is performed, a display defect occurs.

  Therefore, in the present invention, when transitioning from full-screen display to partial display (or when changing the display area in partial display), on the premise of intermittent refreshing, two or more frames continuously, A refresh operation for writing the common potential VCOM (non-display signal) to the pixels corresponding to the non-display area is performed. Thereby, the display defect of the first frame can be canceled and the display defect can be prevented.

This point will be described in more detail with reference to the timing diagrams of FIGS.
As shown in FIG. 5, when a transition is made from a partial display command full screen display to a partial display, a refresh operation is performed in one frame after the transition, and thereafter, a frame in which no refresh operation is performed and several non-refresh frames continue. . That is, intermittent refresh.

  Then, when the polarity signal POL is not inverted (L level is maintained in the case of FIG. 5), the display defect does not occur. However, when the polarity signal POL is inverted (in the case of FIG. 5, the level changes from H level to L level), a display defect occurs due to the above reason.

  Therefore, as shown in FIG. 6, when a transition is made from full screen display to partial display based on a partial display command, a refresh operation is performed in two consecutive frames after the transition. After that, several non-refresh frames follow. Thereby, the display defect of the first frame after shifting to the partial display can be canceled by the refresh operation of the next frame to prevent the display defect.

  The same applies to the case where the display area is changed in the partial display based on the display area change command as shown in FIG. That is, the refresh operation is performed in two consecutive frames after changing the display area of the partial display. After that, several non-refresh frames follow. Thereby, the display defect of the first frame after changing the display area can be canceled by the refresh operation of the next frame to prevent the display defect.

It is a figure which shows the structure of the liquid crystal display device by embodiment of this invention. It is a figure which shows the structure of the storage capacity line drive circuit and polarity signal generation circuit in the liquid crystal display device by embodiment of this invention. It is a figure which shows the structure of the source line drive circuit and DSG control circuit in the liquid crystal display device by embodiment of this invention. It is a timing diagram explaining operation | movement of the liquid crystal display device by a comparative example and embodiment of this invention. It is a timing diagram explaining operation | movement of the liquid crystal display device by a comparative example. FIG. 5 is a timing diagram illustrating an operation of the liquid crystal display device according to the embodiment of the present invention. FIG. 5 is a timing diagram illustrating an operation of the liquid crystal display device according to the embodiment of the present invention.

Explanation of symbols

10 pixel transistor 11 pixel electrode 12 liquid crystal 13 holding capacitor 14 source driver 15 common electrode driver 20 source line driving circuit 21 DSG control circuit 22 gate line driving circuit 23 holding capacitor line driving circuit 24 polarity signal generating circuit 231 timing control circuit LCH1 to LCH3 1st-3rd latch circuit SW1-SW3 1st-3rd switch 241 Frame inversion signal generation circuit 242 Memory 243 AND circuit

Claims (6)

A pixel region composed of a plurality of pixels;
A plurality of storage capacitor lines;
A storage capacitor connected between a pixel electrode of the pixel and the storage capacitor line;
In the display area where the image in the pixel area is displayed, a polarity signal that repeats inversion between the first level and the second level is generated for each frame, and in the non-display area where the image is not displayed, A polarity signal generating circuit for fixing the polarity signal to the first level or the second level;
A first switching element that switches the potential of the storage capacitor line according to the polarity signal generated by the polarity signal generation circuit;
When the display area is changed to the non-display area, a refresh operation for writing a signal corresponding to non-display to the pixel electrode of the pixel corresponding to the non-display area is intermittently performed for a part of the frames and two or more frames are continuously performed. And a control circuit for performing control so as to perform a refresh operation. The polarity signal generation circuit generates a frame inversion signal generation circuit that generates a frame inversion signal that repeats inversion between a first level and a second level for each frame;
A memory storing data representing a distinction between a display area in which an image in the pixel area is displayed and a non-display area in which no image is displayed;
When the data output from the memory represents a display area, the frame inversion signal is output as the polarity signal, and when the data output from the memory represents a non-display area, a first level or The liquid crystal display device according to claim 1, further comprising: a logic circuit that outputs the polarity signal fixed at a second level. 3. The liquid crystal display device according to claim 2, wherein the logic circuit is an AND circuit to which the data output from the memory and the frame inversion signal generated by the frame inversion signal generation circuit are applied. A latch circuit that latches the polarity signal generated by the polarity signal generation circuit based on a timing signal; and the first switching element includes a latch circuit configured to store the storage capacitor line in accordance with the polarity signal latched by the latch circuit. The liquid crystal display device according to claim 1, wherein the potential is switched. A common electrode to which a common potential is applied;
A liquid crystal disposed between the pixel electrode and the common electrode;
5. The liquid crystal according to claim 1, further comprising: a second switching element that applies the common potential to the pixel electrode of a pixel corresponding to a non-display area. Display device. A pixel region composed of a plurality of pixels;
A plurality of storage capacitor lines;
A storage capacitor connected between a pixel electrode of the pixel and the storage capacitor line;
In the display area where the image in the pixel area is displayed, a polarity signal that repeats inversion between the first level and the second level is generated for each frame, and in the non-display area where the image is not displayed, The polarity signal generating circuit for fixing the polarity signal at a first level or a second level;
In a driving method of a liquid crystal display device comprising: a first switching element that switches a potential of the storage capacitor line according to a polarity signal generated by the polarity signal generation circuit;
When the display area is changed to the non-display area, a refresh operation for writing a signal corresponding to non-display to the pixel electrode of the pixel corresponding to the non-display area is intermittently performed for a part of the frames and two or more frames are continuously performed. And performing a refresh operation.

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