JP2006171041A - Display apparatus, and driving circuit/driving method for same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent degradation of display quality due to lack of charging time for a pixel capacitance with a simple structure in an active matrix type display apparatus. <P>SOLUTION: In the active matrix type liquid crystal display apparatus in which a plurality of data lines and a plurality of gate lines are arranged in a lattice form, a pulse width modulation (PWM) circuit included in a gate driver generates a gate signal OG(j) by PWM controlling a predetermined period of an output pulse signal from a shift register, based on an ouput control signal OE for PWM control having a predetermined duty ratio, which is output from a display control circuit. The gate signal OG(j) is the signal which becomes active (H level) in each frame period for selecting a corresponding gate line and the gate signal OG(j) reaches H level early for preliminarily charging the gate line by PWM controlling just before the active period. Therefore, enough charging time for the pixel capacitance can be assured. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to an active matrix display device, and more specifically, a plurality of pixel forming portions arranged in a matrix in such a display device or scanning signal lines for selecting these pixel forming portions. The present invention relates to a driving circuit and a driving method for preliminarily charging the scanning signal line or the pixel formation portion by applying a predetermined voltage to the pixel.

  In general, an active matrix liquid crystal display device includes a display unit including two substrates that sandwich a liquid crystal layer, and one of the two substrates has a plurality of data lines as video signal lines. And a plurality of gate lines as scanning signal lines are arranged in a lattice pattern, and a plurality of pixel forming portions are provided which are arranged in a matrix corresponding to the intersections of the plurality of data lines and the gate lines. An active matrix liquid crystal display device includes a data driver for driving data lines of the display unit, a gate driver for driving gate lines of the display unit, and a display control circuit for controlling the data driver and the gate driver. have.

  FIG. 11 is a block diagram showing a configuration of a main part of a conventional active matrix liquid crystal display device together with an equivalent circuit of the display unit. The display unit 603 in this liquid crystal display device has a plurality (m) of gate lines GL1 corresponding to horizontal scanning lines in an image represented by image data received by a display control circuit (not shown) from an external signal source or the like. GLm, a plurality (n) of data lines (also referred to as “source bus lines”) SL1 to SLn intersecting with each of the gate lines GL1 to GLm, the gate lines GL1 to GLm, and the data lines SL1 to SL1 A plurality of (m × n) pixel forming portions provided corresponding to the intersections with SLn.

  These pixel formation portions are arranged in a matrix to form a pixel array, and each pixel formation portion is connected to a gate line GLj that passes through a corresponding intersection and a data line SLk that passes through the intersection. A TFT (Thin Film Transistor) which is a switching element to which a source terminal is connected, a pixel electrode connected to the drain terminal of the TFT, and a counter electrode provided in common to the plurality of pixel forming portions. It consists of a common electrode Ec and a liquid crystal layer provided in common to the plurality of pixel formation portions and sandwiched between the pixel electrode and the common electrode Ec. A pixel capacitor Cp is constituted by a capacitor formed by the pixel electrode and the common electrode Ec.

  The display control circuit receives a digital video signal indicating image data from an external signal source or the like, and displays a data driver start pulse signal SSP as a signal for causing the display unit 603 to display an image represented by the digital video signal, and data A driver clock signal SCK, a digital image signal DA, a gate driver start pulse signal GSP, and a gate driver clock signal GCK are generated.

  The data driver 601 receives the data driver start pulse signal SSP, the data driver clock signal SCK, and the digital image signal DA from the display control circuit, and based on these signals, each horizontal image of the image represented by the digital image signal DA. Analog voltages corresponding to pixel values in the scanning lines are sequentially generated as data signals S (1) to S (n), and these data signals S (1) to S (n) are generated on the data lines SL1 to SLn in the display portion 603. Respectively.

  The gate driver 602 receives the gate driver start pulse signal GSP and the gate driver clock signal GCK from the display control circuit and, based on these signals, displays each frame period (for displaying an image represented by the digital image signal DA). In each vertical scanning period), the gate lines GL1 to GLm in the display portion 603 are sequentially selected by one horizontal scanning period, and an active gate signal (voltage for turning on the TFT 10) is applied to the selected gate line.

  As described above, the data signals S (1) to S (n) are respectively applied from the data driver 601 to the data lines SL1 to SLn, and the gate signals G (1) to SGL (n) are applied to the gate lines GL1 to GLm. By applying G (m), a voltage corresponding to the value of the corresponding pixel in the image represented by the digital image signal DA is applied to and held in each pixel capacitor Cp in the display unit 603 via the TFT 10. . As a result, a voltage corresponding to the potential difference between each pixel electrode and the common electrode Ec is applied to the liquid crystal layer according to the digital image signal DA. The display unit 603 displays an image represented by the digital image signal DA, that is, an image represented by a digital video signal received from an external signal source or the like, by controlling the light transmittance of the liquid crystal layer by the applied voltage.

  Incidentally, in recent years, the display portion of the liquid crystal display device as described above has been increased in size. Accordingly, the number of gate lines has increased, and the number of TFTs connected to one gate line has increased. Resistance and capacitance are increasing. When the resistance and capacitance of the gate line increase in this way, the waveform of the gate signal applied to the gate line on the terminal side of the gate line may become large. This rounding of the waveform, specifically, the rounding of the waveform at the rise of the gate signal, reduces the charging time for the pixel capacitance by the data signal. As a result of this decrease, when the charging time for the pixel capacitor is less than the required time, the display image quality may be deteriorated due to insufficient charging time for the pixel capacitor.

  In contrast, a stepwise driving method in which the gate signal is temporarily increased to an intermediate potential that does not lead to writing to the pixel capacitor, and then increased to the writing potential (threshold voltage at which the TFT is turned on) to the pixel capacitor. (Hereinafter referred to as “stepped gate drive system”) has been proposed (see, for example, Patent Document 1). In this driving method, since the potential of the gate signal is once raised to an intermediate potential and then further increased from the intermediate potential, the gate signal can be reduced, and as a result, the charge time to the pixel capacitor can be reduced. It is possible to prevent the display image quality from being deteriorated due to the shortage.

  In general, the polarity of the voltage applied to the liquid crystal layer is generally inverted every frame period. This is because it is necessary to perform AC driving in order to prevent deterioration of the liquid crystal. In order to further improve display quality, in recent years, line inversion in which a voltage having a different polarity is applied every horizontal period and dot inversion in which a voltage having a different polarity is applied every dot (each pixel in the horizontal scanning direction) have been performed. Often adopted. In these cases, each pixel capacitor Cp is charged to a reverse polarity during one horizontal scanning period (from a charged state to a negative polarity, or from a negatively charged state to a positive polarity. Charging of the pixel capacitor is necessary. On the other hand, with the recent increase in the size of the display unit, the delay of the data signal has increased, and the definition of the image to be displayed has been increased. For this reason, the time available for charging the pixel capacity has been shortened. As a result, the display image quality may be deteriorated due to a shortage of charging time for the pixel capacitance by the data signal.

  On the other hand, by selecting each gate line twice in each frame period, preliminary charging is performed in a period before the original period in which each pixel capacity is to be charged, thereby charging the pixel capacity. A driving method (hereinafter referred to as “double gate driving method”) that can be sufficiently performed has been proposed (see, for example, Patent Document 2). In this manner, the pixel capacitor is charged during the original selection period of the gate line (hereinafter referred to as “main charge”), and the pixel capacitor is preliminarily charged during the period prior to the original selection period (hereinafter referred to as “preliminary charge”). 11) is adopted in the liquid crystal display device of FIG. 11, the data signal S (k) and the gate signal G (j) have waveforms as shown in FIG. j ≦ m, 1 ≦ k ≦ n).

  Since this liquid crystal display device employs a line inversion driving method, the polarity of the data signal S (k) is inverted every one frame period (vertical scanning period) Tv as shown in FIG. At the same time, the polarity is inverted every horizontal scanning period Th. In each frame period, the gate signal G (j) is supplied to the pixel capacitor Cp (hereinafter, “pixel capacitor Cp (j, k)” corresponding to the intersection (j, k) between the data line SLk and the gate line GLj. )), And becomes active twice (a gate signal), a period T1 during which preliminary charging is performed and a period T2 during which main charging is performed for the pixel capacitance Cp (j, k). G (j) assumes a high level (H level) when active, and so on).

In the case of this double gate driving method, as shown in FIG. 12B, the pixel capacitance Cp (j, k) is in the period T1 in which the polarity of the data signal S (k) is the same as the polarity in the main charging period T2. Is preliminarily charged, and the main charge is performed on the pixel capacitor Cp (j, k) in the subsequent period T2. As a result, the charging period for each pixel capacitor Cp in the display unit 603 is substantially extended, and sufficient charging is possible. Therefore, it is possible to prevent display image quality from being deteriorated due to insufficient charging time for the pixel capacitor.
JP 2002-99256 A JP 2001-249643 A JP 2003-15608 A

  However, when the stepped gate driving method is employed in the active matrix liquid crystal display device as described above, an intermediate potential for raising the potential of the gate signal must be given to the gate driver 602. The structure of a circuit (typically, a power supply circuit) that generates a large potential becomes complicated and expensive. When the intermediate potential is changed according to the characteristics of the liquid crystal panel, the configuration is further complicated.

  In addition, when the double gate driving method is employed in the active matrix liquid crystal display device as described above, the TFT is completely turned on during the precharge period. As a result, the original image is displayed during the precharge period. An image signal different from the signal may be completely written. For example, the image signal charged to the pixel capacitor Cp (j, k) in the period T2 shown in FIG. 12B is the original image signal, and the pixel capacitor Cp (j, k) in the period T1. Unlike the original image signal, the image signal to be charged is an image signal to be charged to the pixel capacitor Cp (j−2, k). Therefore, an image signal different from the original image signal may be completely written in each pixel capacity, which may cause a display defect.

  Therefore, the present invention provides a circuit that generates an intermediate potential (typically, even if it is configured to raise the potential of the gate signal to an intermediate potential, which corresponds to the case where the stepped gate driving method is employed. Without complicating the configuration of the power supply circuit), and preparatory charging is performed in a period before the original period in which each pixel capacitor corresponding to the case where the above-described double gate driving method is employed should be charged. Provided is an active matrix display device capable of preventing deterioration in display image quality due to lack of charging time for a pixel capacity, etc., and a driving circuit and a driving method thereof, even if the configuration is performed. For the purpose.

The first invention provides a plurality of video signal lines for respectively transmitting a plurality of video signals representing images to be displayed, a plurality of scanning signal lines intersecting with the plurality of video signal lines, and the plurality of video signals. A scanning line driving circuit for driving the scanning signal lines in an active matrix display device comprising a plurality of pixel forming portions arranged in a matrix corresponding to intersections of lines and the plurality of scanning signal lines, respectively. ,
The plurality of scanning signal lines are selectively driven so that the scanning signal line is selected during a main charging period set in advance for each scanning signal line, and a spare set immediately before the main charging period is set. During the charging period, a predetermined potential for driving is intermittently applied to the scanning signal line to be selected during the main charging period.

According to a second invention, in the first invention,
A pulse having a width equal to the sum of the preliminary charging period and the main charging period is sequentially applied from the input terminal to the output terminal based on a clock signal in which a pulse having a width corresponding to the preliminary charging period repeatedly appears in a predetermined cycle. A shift register having a number of stages corresponding to the number of the scanning signal lines to be shifted;
Based on the output signal of each stage of the shift register, the predetermined potential is intermittently applied to each scanning signal line during the preliminary charging period set for the scanning signal line, and each scanning signal line is applied to the scanning signal line. And a selection circuit for outputting a signal for selection during the main charging period set for each scanning signal line.

According to a third invention, in the first or second invention,
The attribute of the signal to be applied to the scanning signal line in order to intermittently apply the predetermined potential during the preliminary charging period may affect the signal transmission characteristics of the scanning signal line including the temperature of the display device. It is set according to one or more of the parameters.

  A fourth invention is an active matrix display device comprising the scanning signal line drive circuit according to any one of the first to third inventions.

According to a fifth aspect of the present invention, a plurality of video signal lines for respectively transmitting a plurality of video signals representing an image to be displayed, a plurality of scanning signal lines intersecting with the plurality of video signal lines, and the plurality of video signals A scanning line driving circuit for driving the scanning signal lines in an active matrix display device comprising a plurality of pixel forming portions arranged in a matrix corresponding to intersections of lines and the plurality of scanning signal lines, respectively. ,
The plurality of scanning signal lines are selectively driven so that the scanning signal line is selected during a main charging period set in advance for each scanning signal line, and a spare set before the main charging period is set. During the charging period, the scanning signal line to be selected is intermittently selected by intermittently applying a predetermined potential for driving to the scanning signal line to be selected during the main charging period. And

According to a sixth invention, in the fifth invention,
Based on a predetermined clock signal, a pulse having a width equal to the length of the preliminary charging period and a pulse having a width equal to the length of the main charging period are sequentially shifted from the input end to the output end. A shift register with a number of stages according to the number,
Based on the output signal from each stage included in the first group selected every other set, the predetermined number adjacent to each stage among the stages of the shift register, to each scanning signal line corresponding to the first group On the other hand, the predetermined potential is intermittently applied during the preliminary charging period set for the scanning signal line, and each scanning signal line corresponding to the first group is set for the main charging for the scanning signal line. A first selection circuit that outputs a signal for selection in a period, and an output signal from each stage included in a second group other than the first group among the stages of the shift register; The predetermined potential is intermittently applied to each corresponding scanning signal line during the preliminary charging period set for the scanning signal line, and each scanning signal line corresponding to the second group is assigned to the scanning signal line. Selected during the regular charging period And a second selection circuit that outputs a signal for performing the operation.

A seventh invention is the fifth or sixth invention, wherein
The pixel attribute to be applied to the scanning signal line in order to intermittently apply the predetermined potential during the preliminary charging period includes the temperature of the display device and display data of an image represented by the image signal. It is characterized in that it is set according to one or more parameters that can affect the voltage to be applied to the forming part.

  An eighth invention is an active matrix display device comprising the scanning signal line drive circuit according to any one of the fifth to seventh inventions.

According to a ninth aspect of the present invention, a plurality of video signal lines for respectively transmitting a plurality of video signals representing an image to be displayed, a plurality of scanning signal lines intersecting with the plurality of video signal lines, and the plurality of video signals A scanning signal line driving method in an active matrix display device comprising a plurality of pixel forming portions arranged in a matrix corresponding to intersections of a line and the plurality of scanning signal lines, respectively,
The plurality of scanning signal lines are selectively driven so that the scanning signal line is selected during a main charging period set in advance for each scanning signal line, and a spare set immediately before the main charging period is set. During the charging period, a predetermined potential for driving is intermittently applied to the scanning signal line to be selected during the main charging period.

According to a tenth aspect of the present invention, a plurality of video signal lines for respectively transmitting a plurality of video signals representing images to be displayed, a plurality of scanning signal lines intersecting with the plurality of video signal lines, and the plurality of video signals A scanning signal line driving method in an active matrix display device comprising a plurality of pixel forming portions arranged in a matrix corresponding to intersections of a line and the plurality of scanning signal lines, respectively,
The plurality of scanning signal lines are selectively driven so that the scanning signal line is selected during a main charging period set in advance for each scanning signal line, and a spare set before the main charging period is set. During the charging period, the scanning signal line to be selected is intermittently selected by intermittently applying a predetermined potential for driving to the scanning signal line to be selected during the main charging period. And

  According to the first aspect of the present invention, the scanning signal line driving circuit immediately before the main charging period can be used without using the intermediate potential generated by the power supply circuit as in the conventional configuration employing the stepped gate driving system. A predetermined potential for driving is intermittently applied during the pre-charging period set to. As a result, since the potential of the scanning signal line rises earlier than before from the start of the main charging period, the display quality of the display due to, for example, insufficient charging time to the pixel capacitance is reduced without causing a display failure with a simple configuration. A decrease can be prevented.

  According to the second invention, the shift register outputs a pulse having a width equal to the sum of the precharge period and the main charge period, and the selection circuit intermittently applies a predetermined potential during the precharge period. As a result, one shift register can effectively use a period in which the scanning signal line is not driven conventionally.

  According to the third aspect of the invention, the attribute of the signal to be applied to the scanning signal line in order to intermittently apply the predetermined potential during the preliminary charging period (for example, the duty ratio or period of the pulse as the signal) Since it is set according to one or more of the parameters that can affect the signal transmission characteristics of the scanning signal line, including the temperature of the display device, for example, even if the device environment changes, the display can be performed with a simple configuration. For example, it is possible to prevent the display image quality from being deteriorated due to, for example, insufficient charging time for the pixel capacity.

  According to the fourth aspect of the present invention, an active matrix liquid crystal display device having the same effects as the first aspect of the invention can be provided.

  According to the fifth aspect of the present invention, during the preliminary charging period set before the main charging period, the predetermined potential for driving is intermittently applied to the scanning signal line to be selected during the main charging period. The scanning signal line to be selected is intermittently selected. Thus, for example, unlike the conventional double gate driving method, a video signal different from the original video signal is not completely written in the pixel formation portion in the precharge period, and on the other hand, scanning in the precharge period is performed. Due to the intermittent and short-term charging based on the intermittent selection of the signal line, the charging time for the pixel capacitance by the selection pulse can be shortened. Therefore, it is possible to prevent deterioration in display image quality due to shortage of charging time for the pixel capacitance without causing a display failure with a simple configuration.

  According to the sixth aspect of the invention, the shift register outputs a pulse having a width equal to the length of the precharge period and a pulse having a width equal to the length of the main charge period, and the first and second selection circuits provide the precharge period. A predetermined potential is applied intermittently during the charging period. As a result, one shift register can effectively use a period in which the scanning signal line is not driven conventionally. In the sixth aspect of the invention, typically, in the liquid crystal display device, when the AC driving is performed by the line inversion driving method or the dot inversion driving method, the preliminary charging is performed so that the video signal having the same polarity as the main charging period is given. The predetermined potential may be intermittently applied during the period.

  According to the seventh aspect of the invention, the attribute of the signal to be applied to the scanning signal line in order to intermittently apply the predetermined potential during the preliminary charging period (for example, the duty ratio or period of the pulse as the signal) Since it is set according to one or more parameters that include the temperature of the display device and the display data of the image represented by the image signal, and can affect the voltage to be applied to the pixel formation unit, for example, Even when the device environment or the like is changed, the display quality can be prevented from being deteriorated due to insufficient charging time or the like to the pixel capacity without causing a display failure with a simple configuration.

  According to the eighth aspect of the invention, an active matrix liquid crystal display device having the same effect as that of the fifth aspect of the invention can be provided.

  According to the ninth aspect, it is possible to provide a scanning signal line driving method in an active matrix type liquid crystal display device having the same effects as the first aspect.

  According to the tenth aspect of the present invention, it is possible to provide a scanning signal line driving method in an active matrix liquid crystal display device having the same effects as the fifth aspect of the invention.

Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.
<1. First Embodiment>
<1.1 Overall configuration and operation>
First, the overall configuration and operation of the liquid crystal display device according to the first embodiment of the present invention will be described. The liquid crystal display device of this embodiment has a configuration in which the potential of the gate signal is raised to a pseudo or substantially intermediate potential, which corresponds to the case where the conventional stepped gate drive system is adopted.

  FIG. 1 is a block diagram showing the configuration of the liquid crystal display device according to this embodiment together with an equivalent circuit of the display unit. This liquid crystal display device is similar to the conventional active matrix liquid crystal display device shown in FIG. 11, and includes a data driver 101 as a video signal line driving circuit, a gate driver 102 as a scanning signal line driving circuit, and an active matrix type. A display unit 103 and a display control circuit 200 for controlling the data driver 101 and the gate driver 102 are provided. The liquid crystal display device further includes a temperature sensor 300 for measuring the temperature of the liquid crystal panel.

  The display unit 103 in this embodiment has the same configuration as the display unit 603 shown in FIG. That is, the display unit 103 includes gate lines GL1 to GLm as a plurality (m lines) of scanning signal lines and a plurality (n lines) of video signal lines that intersect with each of the gate lines GL1 to GLm. It includes data lines SL1 to SLn and a plurality (m × n) of pixel forming portions provided corresponding to the intersections of the gate lines GL1 to GLm and the data lines SL1 to SLn.

  These pixel formation portions are arranged in a matrix to form a pixel array, and each pixel formation portion is connected to a gate line GLj that passes through a corresponding intersection and a data line SLk that passes through the intersection. The TFT 10 that is a switching element to which the source terminal is connected, the pixel electrode that is connected to the drain terminal of the TFT 10, the common electrode Ec that is the common electrode provided in the plurality of pixel formation portions, and the plurality And a liquid crystal layer sandwiched between the pixel electrode and the common electrode Ec. If necessary, an auxiliary capacitor is provided in parallel with the capacitor formed by the pixel electrode and the common electrode Ec. Is added. A pixel capacitor Cp is configured by a capacitor formed by the pixel electrode and the common electrode Ec (a capacitor obtained by adding an auxiliary capacitor to the capacitor if an auxiliary capacitor is added). The driving method and driving circuit of the present invention for the display unit 103 of the present embodiment having such a configuration will be described below.

  In this embodiment, image data (in a narrow sense) representing an image to be displayed on the liquid crystal panel and data (for example, data indicating the frequency of the display clock) (hereinafter referred to as “display control data”) for determining the timing of the display operation, etc. The data is sent to the display control circuit 200 from a CPU or the like in an external computer (hereinafter, these data Dv sent from the outside are referred to as “broadly defined image data”). That is, an external CPU or the like writes image data and display control data (in a narrow sense) constituting image data Dv in a broad sense to a display memory and a register described later in the display control circuit 200, respectively.

  The display control circuit 200 receives the image data Dv and a signal Tp indicating the temperature of the liquid crystal panel measured by the temperature sensor 300, and displays an image represented by the image data Dv based on the signals Dv and Tp. As signals to be displayed on 103, a data driver start pulse signal SSP, a data driver clock signal SCK, a digital image signal DA (an image signal Dv) representing an image to be displayed, and a gate driver signal A start pulse signal GSP, a gate driver clock signal GCK, and an output control signal OE for controlling the potential of the gate signal output from the gate driver 102 (in the vicinity of the rising time) are generated and output.

  More specifically, the image data Dv is output from the display control circuit 200 as the digital image signal DA after timing adjustment or the like is performed in the internal memory as necessary, and corresponds to each pixel of the image represented by the digital image signal DA. A data driver clock signal SCK is generated as a signal composed of a pulse, and a data driver start pulse signal SSP is generated as a signal that is high (H level) for a predetermined period every one horizontal scanning period, and one frame period (1 A gate driver start pulse signal GSP is generated as a signal which is H level for a predetermined period every vertical scanning period), a gate driver clock signal GCK including a predetermined pulse is generated repeatedly, a temperature signal Tp and a digital image Gate signal output from the gate driver 102 based on the signal DA Generating an output control signal OE for controlling so as to suppress the potential of the vicinity of the rise time as described below.

  Of the signals generated in the display control circuit 200 as described above, the digital image signal DA, the data driver start pulse signal SSP, and the clock signal SCK are input to the data driver 101 and the gate driver start pulse. The signal GSP, the clock signal GCK, and the output control signal OE are input to the gate driver 102.

  Based on the digital image signal DA, the data driver start pulse signal SSP, and the clock signal SCK, the data driver 101 uses the data signal S as an analog voltage corresponding to the pixel value in each horizontal scanning line of the image represented by the digital image signal DA. (1) to S (n) are sequentially generated for each horizontal scanning period, and these data signals S (1) to S (n) are applied to the data lines SL1 to SLn, respectively. In the data driver 101 in the present embodiment, the polarity of the voltage applied to the liquid crystal layer is inverted every frame period, and is also inverted every horizontal scanning line in each frame. A driving method in which S (n) is output, that is, a line inversion driving method is adopted. From the viewpoint of improving display quality, in addition to this, the liquid crystal layer is also applied to each data line (every vertical line). It is preferable to employ a driving method that reverses the polarity of the applied voltage, that is, a dot inversion driving method. That is, the data driver 101 preferably outputs the data signals S (1) to S (n) so that the polarity of the voltage applied to the data lines SL1 to SLn is inverted for each data line.

  The gate driver 102 receives the gate driver start pulse signal GSP, the gate driver clock signal GCK, and the output control signal OE from the display control circuit 200, and based on these signals GSP, GCK, OE, the digital image signal DA In each frame period (each vertical scanning period), the gate lines GL1 to GLm are sequentially selected, and an active gate signal (voltage for turning on the TFT 10) is applied to the selected gate lines. The gate driver 102 in the present embodiment operates so that each of the gate lines GL1 to GLm is selected once in each frame period. In the display unit 103, when each of the gate lines GL1 to GLm is selected in each frame period, each TFT 10 whose gate terminal is connected to the selected gate line GLj is turned on in each selection period. Thus, a voltage corresponding to the value of the corresponding pixel in the image represented by the digital image signal DA is held in the pixel capacitor Cp connected to the drain terminal of each TFT 10.

  In the display unit 103, the data signals S (1) to S (n) are applied to the data lines SL1 to SLn, respectively, and the gate signal G ( 1) to G (m) are respectively applied. As a result, the voltage corresponding to the value of the corresponding pixel in the image represented by the digital image signal DA is given to the pixel capacitance Cp of each pixel formation unit in the display unit 103 by the data signals S (1) to S (n). A voltage corresponding to the potential difference between the pixel electrode and the common electrode Ec is applied to the liquid crystal layer according to the digital image signal DA. That is, the voltage held in each pixel capacitor Cp becomes the voltage applied to the corresponding liquid crystal portion.

  The display unit 103 displays the image represented by the digital image signal DA, that is, the image represented by the digital video signal received from an external signal source, by controlling the light transmittance of the liquid crystal layer by the applied voltage. The detailed configuration of the display control circuit for controlling the display in this way will be described below.

<1.2 Display control circuit>
FIG. 2 is a block diagram showing a configuration of the display control circuit 200 in the liquid crystal display device. The display control circuit 200 includes an input control circuit 20, a display memory 21, a register 22, a timing generation circuit 23, a memory control circuit 24, an OE generation circuit 25, and a duty ratio determination circuit 26. .

  A signal indicating image data Dv in a broad sense received by the display control circuit 200 from an external CPU or the like (hereinafter, this signal is also expressed by “Dv”) is input to the input control circuit 20. The input control circuit 20 distributes the broad image data Dv into the image data Da and the display control data Dc based on the address signal included in the broad image data Dv. Then, a signal representing the image data Da (hereinafter, these signals are also denoted by “Da”) is supplied to the display memory 21 together with an address signal ADw for writing to the display memory 21 based on the address signal. Then, the image data Da is written into the display memory 21 and the display control data Dc is written into the register 22. The display control data Dc includes timing information that specifies the frequency of the clock signal including the source clock signal SCK and the horizontal scanning period and the vertical scanning period for displaying the image represented by the image data Dv.

  A timing generation circuit (hereinafter abbreviated as “TG”) 23 generates a source clock signal SCK and a source start pulse signal SSP based on the display control data Dc held in the register 22. The TG 23 generates a timing signal for operating the display memory 21 and the memory control circuit 24 in synchronization with the source clock signal SCK. Further, the TG 23 generates a timing signal for operating the OE generation circuit 25 and the duty ratio determination circuit 26 in synchronization with the gate driver clock signal GCK.

  The memory control circuit 24 receives an address signal ADr for reading out data representing an image to be displayed on the liquid crystal panel from the image data Da input from the outside and stored in the display memory 21 via the input control circuit 20, and a display. A signal for controlling the operation of the memory 21 is generated. These address signal ADr and control signal are supplied to the display memory 21, whereby data representing an image to be displayed on the liquid crystal panel is read from the display memory 21 as a digital image signal DA and output from the display control circuit 200. The The digital image signal DA is supplied to the video signal line driving circuit 300 as described above.

  The OE generation circuit 25 generates and outputs an output control signal OE based on a duty ratio Dr given from a later-described duty ratio determination circuit 26 and a timing signal given from the TG 23 corresponding to the gate driver clock signal GCK. This output control signal OE becomes active (H level) during a period when the gate driver clock signal GCK is at L level, and at a ratio corresponding to the duty ratio during a period when the gate driver clock signal GCK is at H level. Alternately active (H level) or inactive (L level). The number of times that the output control signal OE is alternately switched between active (H level) and inactive (L level) during the period when the gate driver clock signal GCK is at H level is set to an appropriate value in advance. As described above, the output control signal OE is alternately switched to active (H level) or inactive (L level) at a rate corresponding to the duty ratio, so that a so-called pulse width modulation (PWM) is applied to the gate signal. ) Control is performed. With this PWM control, the (average) potential of the gate signal for preliminarily charging the gate line can be easily set to a desired potential without changing the configuration of the power supply circuit. A specific configuration for realizing this PWM control will be described later.

  The duty ratio determining circuit 26 is based on a signal Tp indicating the temperature given from the temperature sensor 300 (hereinafter, the temperature indicated by this signal is also expressed by the symbol “Tp”), and the duty ratio Dr of the output control signal OE. And is supplied to the OE generation circuit 25. Here, the duty ratio Dr corresponds to the PWM control period in the period in which the PWM control is performed (here, the period in which the gate driver clock signal GCK is at the H level) (hereinafter referred to as “PWM control period”). This is the ratio of the entire period during which the output control signal OE is active. The PWM control period substantially corresponds to a preliminary charging period when the conventional stepped gate driving method is employed, and is set immediately before the period for selecting each scanning signal line.

  The duty ratio determination circuit 26 determines the duty ratio Dr by referring to a correspondence table in which the correspondence relationship between the temperature Tp and the duty ratio Dr is determined in advance. This correspondence table is determined so that the duty ratio Dr increases as the temperature Tp increases, and the duty ratio Dr decreases as the temperature Tp decreases. This is because, as the temperature Tp of the liquid crystal panel becomes higher, the rounding of the waveform of the gate signal flowing through the gate line becomes larger (that is, the time until reaching the threshold voltage of the TFT becomes longer). This is because the potential needs to be increased. Here, as the duty ratio Dr increases, the potential of the gate signal OG (j) output from the gate driver 102 in the PWM control period increases. For example, when the duty ratio Dr is 100%, the gate signal OG (j) in the PWM control period has an H level potential, and when the duty ratio Dr is 0%, the gate signal OG (j) in the PWM control period is It becomes an L level potential. However, as will be described later, when the potential of the gate signal OG (j) reaches the threshold voltage Vgon of the TFT 10 during the PWM control period, a problem may occur in the display. Therefore, the duty ratio Dr and the pulse period (in the PWM control period) The attributes of the pulse including the number of pulses are preferably set to a value at which the potential of the gate signal OG (j) does not reach the threshold voltage Vgon. A specific configuration for generating the gate signal OG (j) and the waveform of the signal will be described in detail below with reference to the drawings.

<1.3 Operation and configuration example of gate driver>
FIG. 3 is a block diagram schematically showing a configuration example of the gate driver 102 in the present embodiment. FIG. 4 is a signal waveform diagram for explaining the operation of the gate driver 102. The gate driver 102 shown in FIG. 3 includes an m-stage shift register 1021 and a PWM circuit 1022 composed of m AND circuits. The gate driver clock signal GCK and the gate driver start pulse signal GSP are supplied to the shift register 1021, and the pulse signal from the shift register 1021 and the output control signal OE are supplied to the PWM circuit 1022. Each signal output from the PWM circuit 1022 is given to an output circuit (not shown) such as a buffer circuit, and gate signals OG (1) to OG (m) to be applied to the gate lines GL1 to GLm, respectively. Output from the circuit.

  The shift register 1021 is based on the gate driver clock signal GCK and the start pulse signal GSP as shown in FIG. 4A, from the rising edge of the gate driver clock signal GCK to the next rising edge (that is, the length of one horizontal scanning period). ) Are sequentially shifted from the input end to the output end. A pulse signal SH (j) as shown in FIG. 4C is output from the j-th stage in the shift register 1021 (j = 1, 2,..., M). Similarly, a pulse signal SH (j + 1) as shown in FIG. 4D is output from the j + 1 stage in the shift register 1021.

  The PWM circuit 1022 includes first to m-th AND circuits, and the j-th AND circuit receives the j-th output signal SH (j) of the shift register 1021. Further, the first to mth AND circuits are supplied with an output control signal OE as shown in FIG. 4B, which is a control signal for performing PWM control. Even if the output signal SH (j) at the jth stage of the shift register 1021 is at the H level by the AND operation by the jth AND circuit, if the output control signal OE is at the L level, the jth AND circuit An L level signal is output. As described above, the output signal SH (j) of the j-th stage of the shift register 1021 given to the j-th AND circuit by the output control signal OE is a predetermined number of times according to the duty ratio Dr within the PWM control period. Are alternately set to H level or L level. The output signal SH (j) at the j-th stage of the shift register 1021 set to H level or L level within the PWM control period according to the duty ratio Dr by the jth AND circuit passes through an output circuit (not shown). , And output from the gate driver 102 as the gate signal OG (j). This gate signal OG (j) is applied to one end of the gate line GLj.

  As described above, the OE generation circuit 25 (and the duty ratio determination circuit 26) and the PWM circuit 1022 alternately set the gate at the H level or the L level alternately a predetermined number of times in accordance with the duty ratio Dr within the PWM control period. Since signals are obtained, these circuits function as a selection circuit that intermittently applies an H level potential during the PWM control period and outputs a signal for selecting each scanning signal line.

  Here, since the gate line GLj has a predetermined resistance and capacitance, the waveform becomes large at the other end (on the opposite side) of the gate line GLj (that is, the time until the threshold voltage of the TFT is reached becomes longer). ). FIG. 4E shows the waveform of the gate signal OGp (j) at the other end. Also, the (j + 1) -th output signal SH (j + 1) of the shift register 1021 set to the H level or the L level within the PWM control period according to the duty ratio Dr by the j + 1-th AND circuit is the gate signal OG (j + 1). ) Is output from the gate driver 102. Similarly, the gate signal OG (j + 1) has a larger waveform as shown in FIG. 4F with respect to the gate signal OGp (j + 1) at the other end of the gate line GL (j + 1). However, since the rounding of the waveform, that is, the time taken to reach the threshold voltage of the TFT from the rise time is sufficiently shorter than in the case of the conventional configuration, the display image quality is deteriorated due to insufficient charging time for the pixel capacity. Can be prevented. Hereinafter, description will be given with reference to the drawings.

  FIG. 5A is a diagram showing a waveform of the gate signal G (j) at the other end (on the side opposite to one end connected to the gate driver) of the gate line GLj in the conventional configuration shown in FIG. FIG. 5B is a diagram schematically showing a part of the waveform of the gate signal OG (j) at the other end of the gate line GLj in the present embodiment. In the figure, Vgh represents an H level potential, Vgl represents an L level potential, Vm represents a potential reached at the end of the PWM control period (for example, an average potential during the PWM control period), and Vgon represents a TFT threshold value. The voltage is shown. Further, the dotted signal waveform shown in FIG. 5B is a signal waveform of the conventional configuration shown in FIG. 5A superimposed for comparison.

  Referring to FIG. 5B, when the gate signal OG (j) at the other end of the gate line GLj in this embodiment reaches the threshold voltage Vgon, the gate signal G (j) at the other end in the conventional configuration. It can be seen that the time tm is earlier than the time point when the voltage reaches the threshold voltage Vgon. It is a result of the PWM control that the threshold voltage is reached early. That is, when the source signal S (k) shown in FIG. 4G starts to be applied to the pixel capacitor to be applied, the potential of the gate signal OG (j) has reached the potential Vm higher than the potential Vgl. . Therefore, compared to the conventional configuration, in this embodiment, it is possible to take a longer charging time for the pixel capacitance, and thus it is possible to prevent display image quality from being deteriorated.

  Note that the output control signal OE shown in FIG. 4B is maintained at the L level in the first half of the period corresponding to the H level period of the gate driver clock signal GCK. This is because the gate signal to be deactivated just before a certain gate signal is activated, for example, the gate signal OGp (j) to be deactivated just before the gate signal OGp (j + 1) is activated. This is to prevent the active state. Further, it is preferable that each gate signal including the gate signals OGp (j) and OGp (j + 1) shown in FIGS. 4E and 4F does not reach the threshold voltage Vgon in the PWM control period. Even if the threshold voltage Vgon is reached during or momentarily, only a different image signal to be charged to the other pixel capacitance is instantaneously charged with respect to the corresponding pixel capacitance, causing a display inconvenience. There is nothing.

<1.4 Effects of First Embodiment>
As described above, the active matrix type liquid crystal display device (the gate driver 102 in the present embodiment) uses an intermediate potential generated by the power supply circuit as in the conventional configuration adopting the stepped gate drive system. Rather, based on the output control signal OE generated by the OE generation circuit 25, the AND circuit in the PWM circuit 1022 alternately outputs the gate signal to be output by a predetermined number of times according to a predetermined duty ratio in the PWM control period. Set to level or L level. As a result, as shown in FIG. 5B, the gate signal in the present embodiment reaches the threshold voltage Vgon earlier than the time when the gate signal in the conventional configuration reaches the threshold voltage Vgon. Without occurring, it is possible to prevent deterioration in display image quality due to insufficient charging time for the pixel capacitance.

  Further, the duty ratio determination circuit 26 of the present embodiment changes the duty ratio to an appropriate value based on the temperature Tp given from the temperature sensor 300. As a result, even if the waveform rounding of the gate signal flowing through the gate line increases due to an increase in the temperature Tp of the liquid crystal panel (that is, the time until the threshold voltage of the TFT is reached), the PWM of the gate signal It is possible to increase the potential (increase the absolute value) during the control period. As a result, even when the device environment (here, temperature) changes, the display quality can be prevented from being deteriorated due to a shortage of charging time for the pixel capacity without causing a display failure with a simple configuration. .

<2. Second Embodiment>
<2.1 Overall configuration and operation>
Next, the configuration and operation of the liquid crystal display device according to the second embodiment of the present invention will be described. The liquid crystal display device of the present embodiment is configured to perform preliminary charging in a period before the original period in which each pixel capacitor is charged, which corresponds to the case where the conventional double gate driving method is adopted.

  The overall configuration of the present liquid crystal display device is substantially the same as the configuration of the liquid crystal display device according to the first embodiment shown in FIG. Is omitted. The liquid crystal display device according to this embodiment differs from the display device according to the first embodiment in the configuration and operation of a part of the display control circuit 200 and the gate driver 102. Hereinafter, this different configuration and operation will be described.

<2.2 Display control circuit>
FIG. 6 is a block diagram showing a configuration of the display control circuit 200 in the liquid crystal display device. Since this display control circuit 200 has substantially the same configuration as that of the display control circuit 200 in the first embodiment shown in FIG. 2, the same reference numerals are given and description thereof is omitted. The display control circuit 200 in this embodiment is different from the display control circuit 200 in the first embodiment in the configuration and operation of the OE generation circuit 25 and the duty ratio determination circuit 26.

  Similarly to the duty ratio determination circuit 26 in the first embodiment, the duty ratio determination circuit 26 in the present embodiment receives a signal Tp indicating the temperature given from the temperature sensor 300 and also outputs a digital image signal output from the display memory 21. Receive DA.

  The duty ratio determining circuit 26 includes a temperature Tp, an average value Vpm of a voltage applied immediately before (to a frame cycle) for each pixel formation unit connected to the gate line to which the gate signal is applied, and a duty ratio Dr. The duty ratio Dr is determined by referring to a correspondence table in which the correspondence relationship is predetermined.

  First, in the relationship between the temperature Tp and the duty ratio Dr, this correspondence table is determined such that the duty ratio Dr increases as the temperature Tp increases, and the duty ratio Dr decreases as the temperature Tp decreases. This is because, as the temperature Tp of the liquid crystal panel becomes higher, the rounding of the waveform of the gate signal flowing through the gate line becomes larger (that is, the time until reaching the threshold voltage of the TFT becomes longer). This is because it is necessary to sufficiently charge the pixel formation portion by lengthening the period in which the potential of the gate signal exceeds the threshold voltage Vgon in the PWM control period. In the first embodiment, the pulse attributes including the duty ratio Dr and the pulse period (number of pulses in the PWM control period) are set to values at which the potential of the gate signal OG (j) does not reach the threshold voltage Vgon. However, in the present embodiment, it is preferable that the potential of the gate signal OG (j) is determined to reach the threshold voltage Vgon only during a predetermined period of the PWM control period.

  Further, in the relationship between the average value Vpm, which is the average value of the holding voltage corresponding to the value of the corresponding pixel in the image represented by the digital image signal DA given immediately before (the frame cycle), and the duty ratio Dr, this correspondence table. Is determined such that the duty ratio Dr decreases as the average value Vpm (absolute value thereof) increases, and the duty ratio Dr increases as the average value Vpm (absolute value thereof) decreases. This is because if the average value Vpm (absolute value thereof) is large, the necessity of lengthening the time for precharging the pixel forming portion is reduced, so that the gate is set in the PWM control period, which will be described later, corresponding to the period during which precharging is performed. This is because it is preferable to shorten the period during which the signal potential exceeds the threshold voltage Vgon.

  The correspondence table may be a table in which only the correspondence between the temperature Tp and the duty ratio Dr is determined in advance, or only the relationship between the average value Vpm and the duty ratio Dr is determined in advance. Also good. Further, instead of the average value Vpm, the voltage applied immediately before, such as the integral value of the voltage applied immediately before (the frame cycle) or the number of times the maximum voltage was applied to each pixel formation unit connected to the gate line, is changed to the average value Vpm. Related parameters may be used.

  Based on the duty ratio Dr determined by the duty ratio determination circuit 26 and the timing signal (given from the TG 23) corresponding to the gate driver clock signal GCK as described above, the OE generation circuit 25 Output control signals OE1 and OE2 are generated and output. The first and second output control signals OE1 and OE2 are supplied with the duty ratio in a predetermined period (that is, two horizontal scanning periods) from the trailing edge of the gate driver clock signal GCK to the trailing edge. It becomes active (H level) or inactive (L level) alternately at a rate according to. That is, this period is a PWM control period. The PWM control periods of the first and second output control signals OE1 and OE2 are set so as not to overlap each other. Details will be described later.

<2.3 Operation and configuration example of gate driver>
FIG. 7 is a block diagram schematically showing a configuration example of the gate driver 102 in the present embodiment. FIG. 8 is a conceptual diagram for explaining a driving method of the liquid crystal display device according to the present embodiment. FIG. 9 is a signal waveform diagram for explaining the operation of the gate driver 102 in the present embodiment.

  In addition, each rectangle which consists of the row | line | column shown in FIG. 8 has shown the pixel matrix, The symbol "+" or "-" attached | subjected to this pixel matrix is based on the voltage applied to a pixel liquid crystal, ie, the common electrode Ec. The polarity of the voltage of the pixel electrode Ep is indicated, and an arrow drawn along each rectangle indicating the pixel matrix indicates the scanning direction (in the ascending order of row numbers). As described above, in the present embodiment, the one-dot inversion driving method, which is a driving method that inverts the positive / negative polarity of the voltage applied to the pixel liquid crystal for each pixel and for each frame, is employed.

  The gate driver 102 in the present embodiment includes an m-stage shift register 2021, and a first PWM circuit 2022 and a second PWM circuit 2023 each composed of m / 2 AND circuits. Then, the gate driver clock signal GCK and the gate driver start pulse signal GSP are supplied to the shift register 2021, half of the pulse signal from the shift register 2021 to be described later and the first output control signal OE1 are the first PWM circuit 2022. The second half of the pulse signal from the shift register 2021 and the second output control signal OE2 are supplied to the second PWM circuit 2023. The signals output from the first and second PWM circuits 2022 and 2023 are given to an output circuit (not shown) such as a buffer circuit, and gate signals OG (1) to be applied to the gate lines GL1 to GLm, respectively. -OG (m) is output from the output circuit.

  The shift register 2021 has substantially the same configuration as that of the shift register 2021 in the first embodiment although the width and number of pulses to be output are different, and has two (H level) shown in FIG. Based on the start pulse signal GSP including the pulse and the gate driver clock signal GCK as shown in FIG. 9B, the two pulses having the same width from the falling edge to the rising edge of the gate driver clock signal GCK are input from the input terminal. Shift sequentially to the output end. Then, pulse signals SH (1) to SH (3) as shown in FIGS. 9E to 9G are output from the first stage to the third stage in the shift register 2021. In this way, each pulse signal shifted in the same manner up to the m-th stage in the shift register 2021 is output.

  The first PWM circuit 2022 is composed of m / 2 AND circuits. The first AND circuit receives the output signal SH (1) of the first stage of the shift register 2021 and the second AND circuit. The second stage output signal SH (2) of the shift register 2021 is input. The third AND circuit receives the fifth stage output signal SH (5) of the shift register 2021, and the fourth AND circuit receives the sixth stage output signal SH (2) of the shift register 2021. Is entered.

  The second PWM circuit 2023 is composed of m / 2 AND circuits, and the first AND circuit receives the output signal SH (3) of the third stage of the shift register 2021, and the second AND circuit. The output signal SH (4) of the fourth stage of the shift register 2021 is input to the circuit. The third AND circuit receives the seventh stage output signal SH (7) of the shift register 2021, and the fourth AND circuit receives the eighth stage output signal SH (8) of the shift register 2021. Is entered.

  In this way, the first and second PWM circuits 2022 and 2023 are alternately input for each set, with two signals output from two adjacent stages of the shift register 2021 as one set. Further, each AND circuit included in the first PWM circuit 2022 is given a corresponding first output control signal OE1 shown in FIG. 9C, and each AND circuit included in the second PWM circuit 2023 is supplied to each AND circuit. Is supplied with the second output control signal OE2 shown in FIG. 9D, and each AND circuit outputs the first output control signal OE1 or the second output control signal OE2 and the corresponding shift register 2021. AND operation is performed on the pulse signal output from the stage.

  Here, the PWM control period included in the first and second output control signals OE1 and OE2 is the earlier of the two (H level) pulses included in the pulse signal output from each stage of the shift register 2021. Only the pulse (hereinafter referred to as “preliminary pulse”) (left side in the figure) is set to be PWM-controlled. For example, in the PWM control period included in the first output control signal OE1 shown in FIG. 9C, the preliminary pulses of the pulse signals SH (1) and SH (2) shown in FIGS. The PWM control period included in the second output control signal OE2 shown in FIG. 9D includes the pulse signal SH (3) shown in FIG. 9G and the pulse signal SH (not shown). (4) is set to a period including both preliminary pulses.

  The PWM control period included in the first output control signal OE1 shown in FIG. 9C is the later of the two pulses included in the pulse signal SH (3) shown in FIG. The first output control signal OE1 is given to the second PWM circuit 2023 that controls the pulse signal SH (3). Therefore, the pulse signal SH (3) is not affected. Similarly, the PWM control period included in the second output control signal OE2 shown in FIG. 9D is a selection pulse of the pulse signals SH (1) and SH (2) shown in FIGS. The second output control signal OE2 is not given to the first PWM circuit 2022 that controls the pulse signals SH (1) and SH (2). The pulse signals SH (1) and SH (2) are not affected.

  Thus, as a result of the AND operation by the AND circuits included in the first and second PWM circuits 2022 and 2023, the shift register in which the preliminary pulse is set to the H level or the L level within the PWM control period according to the duty ratio Dr. Pulse output signals SH (1) to SH (m) from the first stage to the m-th stage of 1021 are output from the gate driver 102 as gate signals OG (1) to OG (m) through an output circuit (not shown). The These gate signals OG (1) to OG (m) are applied to one end of the gate lines GL1 to GLm. As described above, the waveform of the gate signal is smoothed at the other end. For example, the gate signals OGp (1) to OGp (3) at the other end are shown in FIGS. 9 (h) to (j). The waveform is as shown.

  Here, when a waveform of a portion corresponding to the preliminary pulse of the gate signals OGp (1) to OGp (3) shown in FIGS. 9 (h) to (j) is seen, a signal component that partially reaches the threshold voltage Vgon. It can be seen that is included. In this way, during the period in which the potential of the gate signal has reached the threshold voltage Vgon, the corresponding pixel formation portion is charged. Therefore, in this respect, the charging in the period in which the preliminary charging in the conventional double gate driving method is performed The same effect is produced. However, the preliminary charging period by the preliminary pulse in the present embodiment is different from the period in which the preliminary charging in the double gate driving method is performed, and is the same as the main charging period in the selection period (in this embodiment, the charging period by the selection pulse). Charging is not performed, but only intermittent and short-term charging is performed. Therefore, unlike the conventional double gate drive method, an image signal different from the original image signal is not completely written in each pixel capacity.

  As described above, the OE generation circuit 25 (and the duty ratio determination circuit 26) and the first and second PWM circuits 2022 and 2023 respond to the duty ratio Dr within the preliminary charging period (PWM control period) by the preliminary pulse. Thus, the gate signal alternately set to the H level or the L level is obtained a predetermined number of times, so that these circuits intermittently apply the H level potential during the preliminary charging period and during the charging period by the selection pulse. It functions as a selection circuit that outputs a signal for selecting each scanning signal line.

  Note that two (H level) pulses respectively included in the gate driver start pulse GSP and the pulse signal output from each stage of the shift register 2021 are substantially spaced apart by one horizontal scanning period. This is because the one-dot inversion driving method is adopted in the present embodiment as shown in FIG. For example, the pixels included in the row corresponding to GL1 shown in FIG. 8 and the row corresponding to GL2 adjacent thereto have opposite polarities in the same row, and correspond to GL3 which is one row apart from the row corresponding to GL1. The pixels included in each row have the same polarity in the same row. Therefore, if the preliminary pulse and the selection pulse are set to be adjacent to each other, it is not preferable because the preliminary pulse is charged with a potential opposite to the polarity of the potential to be charged to each pixel capacitor by the selection pulse. Therefore, as described above, an interval of approximately one horizontal scanning period is provided between the preliminary pulse and the selection pulse. This is the same even when the 1-line inversion driving method is adopted.

<2.4 Effects of Second Embodiment>
As described above, in the active matrix liquid crystal display device of the present embodiment, the precharge period by the preparatory pulse is different from the period in which the precharge in the double gate driving method is performed, and charging in the selection period (this embodiment In this case, the same charging as in the selection pulse is not performed, but only intermittent and short-term charging is performed. Therefore, unlike the conventional double gate driving method, the TFT is not completely turned on, so that an image signal different from the original image signal is completely written during the preliminary charging period. On the other hand, due to intermittent and short-term charging by the signal component exceeding the threshold voltage Vgon included in such a preliminary pulse, the charging time to the pixel capacitor by the selection pulse can be shortened. Therefore, it is possible to prevent display image quality from being deteriorated due to insufficient charging time for the pixel capacitance without causing a display failure with a simple configuration.

  In addition, the duty ratio determination circuit 26 according to the present embodiment is configured to detect the corresponding pixel in the image represented by the digital image signal DA given immediately before (the frame period) outputted from the display memory 21 and the temperature Tp given from the temperature sensor 300. The duty ratio is changed to an appropriate value based on the average value Vpm of the holding voltage corresponding to the value. As a result, even when the device environment (here, temperature) and other factors (here, the above average value) change, the display time of the pixel capacitance can be reduced with a simple configuration without causing display defects. It is possible to prevent deterioration in display image quality due to lack.

<3. Modified example of each embodiment>
In the first embodiment, the PWM control period included in the output control signal OE coincides with the period in which the gate driver clock signal GCK is at the H level. This makes it possible to effectively use a period in which the gate signal is conventionally inactive in one horizontal scanning period. If a period longer than this is set as the PWM control period, the output pulse signal from the shift register 1021 corresponding to the adjacent gate signal is simultaneously output (overlapped) in part or all of the PWM control period. become. It is difficult to simultaneously output two pulse signals having such overlapping periods with one shift register. Therefore, a gate driver including two shift registers is provided instead of the gate driver 102 in the first embodiment, and two adjacent gate signals are generated independently (alternately) based on the pulse signals of these two shift registers. It may be configured to.

  FIG. 10 is a block diagram schematically showing the configuration of the gate driver in the modification of the first embodiment having such two shift registers. This gate driver includes first and second shift registers 3021 and 3022 that output m-stage half-pulse signals, respectively, and a first PWM circuit 3023 and a second second circuit each including m / 2 AND circuits. And a PWM circuit 2024. Here, for example, the display control circuit 200 repeatedly includes pulses of two horizontal scanning periods (H level), and the first and second gate driver clock signals whose rising points of the pulses are shifted by one horizontal scanning period. GCK1 and GCK2 are generated. The first gate driver start pulse signal GSP 1 is supplied to the first shift register 3021, and the second gate driver start pulse signal GSP 2 is supplied to the second shift register 3022. Further, the pulse signal from the first shift register 3021 and the first output control signal OE1 for performing PWM control are supplied to the first PWM circuit 3023, and the pulse signal from the second shift register 3022 and PWM control are performed. The second output control signal OE2 for performing the above is given to the second PWM circuit 3024. The signals output from the first and second PWM circuits 3023 and 3024 are given to an output circuit (not shown) such as a buffer circuit, and gate signals OG (1) to be applied to the gate lines GL1 to GLm, respectively. -OG (m) is output from the output circuit.

  Here, the PWM control period included in the first and second output control signals OE1 and OE2 is a desired portion of the pulse signal output from each stage of the first and second shift registers 3021 and 3022 (typically Is set to PWM control the first half). Then, the PWM control period is not limited to the H level period of the gate driver clock signal as in the first embodiment, and can be set, for example, during one horizontal scanning period here. Therefore, even when the resistance and capacitance of the gate line are relatively large, charging can take a sufficient amount of time, so that the waveform is rounded (that is, the time until the threshold voltage of the TFT is reached) is ensured. Can be suppressed. As a result, it is possible to prevent deterioration in display image quality due to insufficient charging time for the pixel capacity.

  In the second embodiment, the one-dot inversion driving method is adopted, but the positive / negative polarity of the voltage applied to the pixel liquid crystal is inverted for each pixel in one row, and the n rows are alternately inverted as one set, Furthermore, a 1 × n dot inversion driving method, which is a driving method for inverting every frame, may be employed. In this case, the OE generation circuit included in the display control circuit 200 repeatedly includes the PWM control period having the length of two horizontal periods generated in the second embodiment with two horizontal periods (FIG. 9C). , (D), instead of the first and second output control signals OE1 and OE2, the first and second PWM control periods having a length of 2n horizontal periods are intermittently included in a 2n horizontal period. Output control signals OE1 and OE2 are generated. In addition, the shift register 1021 generates a pulse signal with an interval of approximately (2n−1) horizontal scanning periods between the preliminary pulse and the selection pulse, and the first and second PWM included in the gate driver 102. The circuits 2022 and 2023 are configured so that 2n signals output from adjacent 2n stages of the shift register 2021 are set as one set and are alternately input for each set. The configuration of this modification can also be applied to an n-line inversion driving type liquid crystal display device that inverts the polarity of the voltage applied to the liquid crystal layer for every n horizontal scanning lines, for example.

  In the second embodiment, when double gate driving is performed in which each of the gate lines GL1 to GLm is selected twice in each frame period, charging by the preliminary pulse is performed only once in each frame period. However, the present invention can also be applied to a configuration in which charging by the preliminary pulse is performed twice or more in each frame period. However, it is assumed that the polarity of the data signal S (k) in each preliminary charging period is the same as the polarity of the data signal S (k) in the main charging period corresponding to the preliminary charging.

  In the first and second embodiments, the output control signal generated by the OE generation circuit 25 and the output pulse from each stage of the shift register are ANDed by each AND circuit in the PWM circuit included in the gate driver 102. The potential applied to the corresponding gate line can be switched to the H level or the L level by the calculation, but any gate signal to be output may be set to the H level intermittently during the PWM control period. Therefore, instead of each AND circuit, an arithmetic circuit other than the AND circuit may be used. Further, any configuration that does not require the generation of a voltage signal having an intermediate potential in the power supply circuit or the like may be used. Therefore, instead of each AND circuit in the OWM circuit, for example, based on the output control signal, the shift register An analog switch that connects or disconnects each stage and the corresponding scanning signal line may be used.

  In the first and second embodiments, the duty ratio determining circuit 26 generates a correspondence table between the temperature Tp and the duty ratio Dr or a correspondence table between the temperature Tp and the average value Vpm of the given voltage and the duty ratio Dr. Although used, in place of these correspondence tables, a table indicating a unique correspondence between these parameters, such as a predetermined condition determination formula or mathematical formula, may be used. In addition, since the temperature of the apparatus is a parameter that greatly affects the signal transmission characteristics of the scanning signal lines and the charging characteristics of the pixel formation portion, it is suitable as a parameter used in these correspondence tables. One or more parameters that affect the signal transmission characteristics of the scanning signal lines, the charging characteristics of the pixel formation portion, and the like, for example, together with the temperature Tp parameter or instead of the temperature Tp parameter. May be used.

  The output control signal or gate signal in the first and second embodiments includes pulses of the same width equally within the PWM control period based on the duty ratio Dr determined by the duty ratio determination circuit 26, but is not necessarily equal. There is no need to include a pulse having a randomly determined width or a wide pulse for applying a high potential so that the potential is quickly raised in the first half of the PWM control period, and a low potential in the second half of the PWM control period. Narrow width pulses may be included to provide Further, it is sufficient that the gate line can be charged in a state where the gate line is not completely selected during the PWM control period of the output control signal or the gate signal in the first and second embodiments. Therefore, these signals in the PWM control period may be intermittent signals that are not related to PWM control without being subjected to PWM control, for example, signals other than rectangular waves such as a triangular wave.

  The display devices according to the first and second embodiments use liquid crystal for the pixel formation portion. However, if the display device is an active matrix display device having a gate line, an electro-optic element other than liquid crystal, for example, An active matrix display device using an organic EL (EelectroLuminescence) element, an LED (light emitting diode), or the like may be used. With this configuration, there is no problem that the charging time to the pixel capacity is insufficient, but it is conceivable that the time for selecting the pixel forming portion is insufficient, so that the display image quality is not deteriorated due to the insufficient selection time. be able to.

It is a block diagram which shows the structure of the liquid crystal display device which concerns on the 1st Embodiment of this invention with the equivalent circuit of the display part. It is a block diagram which shows the structure of the display control circuit in the said embodiment. It is a block diagram which shows simply the structural example of the gate driver in the said embodiment. It is a signal waveform diagram for demonstrating operation | movement of the gate driver in the said embodiment. It is a figure which shows the waveform of the gate signal in the other end on the opposite side to the one connected to the gate driver in the said embodiment with the conventional signal waveform. It is a block diagram which shows the structure of the display control circuit in the 2nd Embodiment of this invention. It is a block diagram which shows simply the structural example of the gate driver in the said embodiment. It is a conceptual diagram for demonstrating the drive method of the liquid crystal display device which concerns on the said embodiment. It is a signal waveform diagram for demonstrating operation | movement of the gate driver in the said embodiment. It is a block diagram which shows simply the structure of the gate driver in the modification of the said 1st Embodiment. 2 is a block diagram showing a configuration of a main part in a conventional active matrix liquid crystal display device together with an equivalent circuit of a display unit. It is a signal waveform diagram for demonstrating operation | movement when the double gate drive system is employ | adopted in the conventional active matrix type liquid crystal display device.

Explanation of symbols

10 ... Thin film transistor (TFT)
25 ... OE generation circuit 26 ... Duty ratio determination circuit 101 ... Data driver (video signal line drive circuit)
102: Gate driver (scanning signal line driving circuit)
DESCRIPTION OF SYMBOLS 103 ... Display part 200 ... Display control circuit 300 ... Temperature sensor 1021, 2021, 3021, 3022 ... Shift register 1022, 2022, 2023, 3023, 3024 ... PWM circuit Cp ... Pixel capacity Ec ... Common electrode GL1-GLm ... Gate line ( Scanning signal line)
OG (1) to OG (m) ... gate signal (scanning signal)
SH (1) to SH (m) ... output signals from the shift register SL1 to SLn ... data lines (video signal lines)
S (1) to S (n) ... Data signal (video signal)
DA ... Digital image signal OE ... Output control signal Dr ... Duty ratio Tp ... Temperature signal GSP ... Start pulse for gate driver GCK ... Clock signal for gate driver SSP ... Start pulse for data driver SCK ... Clock signal for data driver SSP ... Data driver For start pulse

Claims (10)

A plurality of video signal lines for respectively transmitting a plurality of video signals representing an image to be displayed, a plurality of scanning signal lines intersecting with the plurality of video signal lines, the plurality of video signal lines and the plurality of scannings A scanning line driving circuit for driving the scanning signal lines in an active matrix display device comprising a plurality of pixel formation portions arranged in a matrix corresponding to the intersections with the signal lines,
The plurality of scanning signal lines are selectively driven so that the scanning signal line is selected during a main charging period set in advance for each scanning signal line, and a spare set immediately before the main charging period is set. A scanning signal line driving circuit, wherein a predetermined potential for driving is intermittently applied to a scanning signal line to be selected during the main charging period during the charging period. A pulse having a width equal to the sum of the preliminary charging period and the main charging period is sequentially applied from the input terminal to the output terminal based on a clock signal in which a pulse having a width corresponding to the preliminary charging period repeatedly appears in a predetermined cycle. A shift register having a number of stages corresponding to the number of the scanning signal lines to be shifted;
Based on the output signal of each stage of the shift register, the predetermined potential is intermittently applied to each scanning signal line during the preliminary charging period set for the scanning signal line, and each scanning signal line is applied to the scanning signal line. The scanning signal line drive circuit according to claim 1, further comprising: a selection circuit that outputs a signal for selection during the main charging period set for the scanning signal line.   The attribute of the signal to be applied to the scanning signal line in order to intermittently apply the predetermined potential during the preliminary charging period may affect the signal transmission characteristics of the scanning signal line including the temperature of the display device. 3. The scanning signal line drive circuit according to claim 1, wherein the scanning signal line drive circuit is set according to one or more parameters.   An active matrix display device comprising the scanning signal line driving circuit according to claim 1. A plurality of video signal lines for respectively transmitting a plurality of video signals representing an image to be displayed, a plurality of scanning signal lines intersecting with the plurality of video signal lines, the plurality of video signal lines and the plurality of scannings A scanning line driving circuit for driving the scanning signal lines in an active matrix display device comprising a plurality of pixel formation portions arranged in a matrix corresponding to the intersections with the signal lines,
The plurality of scanning signal lines are selectively driven so that the scanning signal line is selected during a main charging period set in advance for each scanning signal line, and a spare set before the main charging period is set. During the charging period, the scanning signal line to be selected is intermittently selected by intermittently applying a predetermined potential for driving to the scanning signal line to be selected during the main charging period. A scanning signal line driving circuit. Based on a predetermined clock signal, a pulse having a width equal to the length of the preliminary charging period and a pulse having a width equal to the length of the main charging period are sequentially shifted from the input end to the output end. A shift register with a number of stages according to the number,
Based on the output signal from each stage included in the first group selected every other set, the predetermined number adjacent to each stage among the stages of the shift register, to each scanning signal line corresponding to the first group On the other hand, the predetermined potential is intermittently applied during the preliminary charging period set for the scanning signal line, and each scanning signal line corresponding to the first group is set for the main charging for the scanning signal line. A first selection circuit that outputs a signal for selection in a period, and an output signal from each stage included in a second group other than the first group among the stages of the shift register; The predetermined potential is intermittently applied to each corresponding scanning signal line during the preliminary charging period set for the scanning signal line, and each scanning signal line corresponding to the second group is assigned to the scanning signal line. Selected during the regular charging period The scanning signal line drive circuit according to claim 5, further comprising: a second selection circuit that outputs a signal for performing the operation.   The pixel attribute to be applied to the scanning signal line in order to intermittently apply the predetermined potential during the preliminary charging period includes the temperature of the display device and display data of an image represented by the image signal. 7. The scanning signal line driving circuit according to claim 5, wherein the scanning signal line driving circuit is set in accordance with one or more parameters that can affect a voltage to be applied to the forming unit.   An active matrix display device comprising the scanning signal line drive circuit according to claim 5. A plurality of video signal lines for respectively transmitting a plurality of video signals representing an image to be displayed, a plurality of scanning signal lines intersecting with the plurality of video signal lines, the plurality of video signal lines and the plurality of scannings A method of driving the scanning signal lines in an active matrix display device comprising a plurality of pixel forming portions arranged in a matrix corresponding to the intersections with the signal lines,
The plurality of scanning signal lines are selectively driven so that the scanning signal line is selected during a main charging period set in advance for each scanning signal line, and a spare set immediately before the main charging period is set. A driving method characterized by intermittently applying a predetermined potential for driving to a scanning signal line to be selected during the main charging period during the charging period. A plurality of video signal lines for respectively transmitting a plurality of video signals representing an image to be displayed, a plurality of scanning signal lines intersecting with the plurality of video signal lines, the plurality of video signal lines and the plurality of scannings A method of driving the scanning signal lines in an active matrix display device comprising a plurality of pixel forming portions arranged in a matrix corresponding to the intersections with the signal lines,
The plurality of scanning signal lines are selectively driven so that the scanning signal line is selected during a main charging period set in advance for each scanning signal line, and a spare set before the main charging period is set. During the charging period, the scanning signal line to be selected is intermittently selected by intermittently applying a predetermined potential for driving to the scanning signal line to be selected during the main charging period. And a driving method.

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