JP2005128153A - Liquid crystal display apparatus and driving circuit and method of the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To fully charge each pixel capacitance with a data signal even if a chargeable period of each pixel capacitance becomes short or a rise time and likewise at the time of polar change of the data signal increases, in an active matrix type liquid crystal display apparatus. <P>SOLUTION: In the active matrix type liquid crystal display apparatus in which a plurality of data lines and a plurality of gate lines are arranged in a grid pattern and line inversion driving is performed, a gate signal OG(j) for performing gate two pulse driving is formed by a gate driver. The gate signal OG(j) is the signal which becomes active (H level) twice at each frame period for selecting a corresponding gate line and in the gate signal OG(j), without shortening preliminary charging period T1 which is a first active period, only a starting time of a main charge period T2 which is a second active period is delayed by a predetermined period Δd2 with respect to a data signal S(k), in order to avoid discharging of the pixel capacitance immediately after starting the main charge. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to an active matrix liquid crystal display device, and more specifically, in order to display an image on a plurality of pixel formation portions arranged in a matrix in such a liquid crystal display device, The present invention relates to a driving circuit and a driving method for preliminarily charging a pixel capacitor before charging the pixel capacitor to a voltage corresponding to a pixel value of the image.

  In general, an active matrix liquid crystal display device includes a display unit including two substrates that sandwich a liquid crystal layer, and one of the two substrates has a plurality of data lines as video signal lines. And a plurality of gate lines as scanning signal lines are arranged in a lattice pattern, and a plurality of pixel forming portions are provided which are arranged in a matrix corresponding to the intersections of the plurality of data lines and the gate lines. An active matrix liquid crystal display device includes a data driver for driving data lines of the display unit, a gate driver for driving gate lines of the display unit, and a display control circuit for controlling the data driver and the gate driver. have.

  FIG. 9 is a block diagram showing a configuration of a main part of a conventional active matrix liquid crystal display device together with an equivalent circuit of the display unit. The display unit 603 in this liquid crystal display device has a plurality (m) of gate lines GL1 corresponding to horizontal scanning lines in an image represented by image data received by a display control circuit (not shown) from an external signal source or the like. GLm, a plurality (n) of data lines (also referred to as “source bus lines”) SL1 to SLn intersecting with each of the gate lines GL1 to GLm, the gate lines GL1 to GLm, and the data lines SL1 to SL1 A plurality of (m × n) pixel forming portions provided corresponding to the intersections with SLn. These pixel formation portions are arranged in a matrix to form a pixel array, and each pixel formation portion is connected to a gate line GLj that passes through a corresponding intersection and a data line SLk that passes through the intersection. A TFT (Thin Film Transistor) which is a switching element to which a source terminal is connected, a pixel electrode connected to the drain terminal of the TFT, and a counter electrode provided in common to the plurality of pixel forming portions. It consists of a common electrode Ec and a liquid crystal layer provided in common to the plurality of pixel formation portions and sandwiched between the pixel electrode and the common electrode Ec. A pixel capacitor Cp is constituted by a capacitor formed by the pixel electrode and the common electrode Ec.

  The display control circuit receives a digital video signal indicating image data from an external signal source or the like, and displays a data driver start pulse signal SSP as a signal for causing the display unit 603 to display an image represented by the digital video signal, and data A driver clock signal SCK, a digital image signal DA, a gate driver start pulse signal GSP, and a gate driver clock signal GCK are generated. The data driver 601 receives the data driver start pulse signal SSP, the data driver clock signal SCK, and the digital image signal DA from the display control circuit, and based on these signals, each horizontal image of the image represented by the digital image signal DA. Analog voltages corresponding to pixel values in the scanning lines are sequentially generated as data signals S (1) to S (n), and these data signals S (1) to S (n) are generated in the data line SL1 to SLn in the display unit 603. Respectively. The gate driver 602 receives the gate driver start pulse signal GSP and the gate driver clock signal GCK from the display control circuit and, based on these signals, displays each frame period (for displaying an image represented by the digital image signal DA). In each vertical scanning period), the gate lines GL1 to GLm in the display portion 603 are sequentially selected by one horizontal scanning period, and an active gate signal (voltage for turning on the TFT 10) is applied to the selected gate line.

  As described above, the data signals S (1) to S (n) are respectively applied from the data driver 601 to the data lines SL to SLn, and the gate signals G (1) to G (1) to the gate lines GL1 to GLm. By applying G (m), a voltage corresponding to the value of the corresponding pixel in the image represented by the digital image signal DA is applied to and held in each pixel capacitor Cp in the display unit 603 via the TFT 10. . As a result, a voltage corresponding to the potential difference between each pixel electrode and the common electrode Ec is applied to the liquid crystal layer according to the digital image signal DA. The display unit 603 displays an image represented by the digital image signal DA, that is, an image represented by a digital video signal received from an external signal source or the like, by controlling the light transmittance of the liquid crystal layer by the applied voltage.

  By the way, in the liquid crystal display device, in general, the polarity of the voltage applied to the liquid crystal layer is inverted every frame period. This is because it is necessary to perform AC driving in order to prevent deterioration of the liquid crystal. In order to further improve display quality, there are currently line inversion that applies a voltage with a different polarity for each horizontal period and dot inversion that applies a voltage with a different polarity for each dot (each pixel in the horizontal scanning direction). It has been adopted. In these cases, each pixel capacitor Cp is charged to a reverse polarity during one horizontal scanning period (from a charged state to a negative polarity, or from a negatively charged state to a positive polarity. Charging) is required. On the other hand, along with the recent increase in the size of the display unit, the delay of the data signal is increased, and the time available for charging the pixel capacity is shortened as the image to be displayed becomes higher in definition. As a result, it is difficult to sufficiently charge the pixel capacitor with the data signal.

  On the other hand, by selecting each gate line twice in each frame period, preliminary charging is performed in a period before the original period in which each pixel capacity is to be charged, thereby charging the pixel capacity. A driving method (hereinafter referred to as “gate two-pulse driving method”) that can be sufficiently performed has been proposed (see, for example, Patent Document 1). In this manner, the pixel capacitor is charged during the original selection period of the gate line (hereinafter referred to as “main charge”), and the pixel capacitor is preliminarily charged during the period prior to the original selection period (hereinafter referred to as “preliminary charge”). 9) is employed in the liquid crystal display device of FIG. 9, the data signal S (k), the gate signal G (j), the applied voltage VL (j, k) to the pixel liquid crystal, Has a waveform as shown in FIG. 10 (1 ≦ j ≦ m, 1 ≦ k ≦ n). This is because the original applied voltage Vα to the pixel liquid crystal is charged to Vβ by preliminary charging, and then the applied voltage VL (j, k) to the pixel liquid crystal is the original applied voltage in the main charging. It shows that Vα has been reached (Vα> Vβ). Note that “pixel liquid crystal” refers to a portion constituting one pixel formation portion in the liquid crystal layer 603 in the display portion (the same applies hereinafter).

  In this liquid crystal display device, since the line inversion driving method is adopted, the polarity of the data signal S (k) is inverted every one frame period (vertical scanning period) Tv as shown in FIG. At the same time, the polarity is inverted every horizontal scanning period Th. In each frame period, the gate signal G (j) is supplied to the pixel capacitor Cp (hereinafter referred to as “pixel capacitor Cp (j, k)” corresponding to the intersection (j, k) between the data line SLk and the gate line GLj. )), And becomes active twice (a gate signal), a period T1 during which preliminary charging is performed and a period T2 during which main charging is performed for the pixel capacitance Cp (j, k). G (j) assumes a high level (H level) when active, and so on.)

  In the case of the gate two-pulse drive method, as shown in FIGS. 10B and 10C, the pixel capacitance Cp (j , K) is preliminarily charged, and the main charge is performed on the pixel capacitor Cp (j, k) in the subsequent period T2. Thereby, the charging period for each pixel capacitor Cp in the display unit 603 is substantially extended, and sufficient charging is possible.

However, in practice, the waveform of the data signal S (k) is not an ideal rectangular wave due to the influence of the wiring resistance and wiring capacitance in the data line SLk, the on-resistance of the transistor in the output portion of the data driver 601, and the like. As shown in (a), the waveform becomes dull (here, the potential of the common electrode Ec is fixed to V _CM ). That is, the rise time at the time of polarity switching in the data signal S (k) is considerably longer than the rise time of the gate signal G (j). As a result, as shown in FIGS. 11B and 11C, when the charge accumulated in the pixel capacitor Cp (j, k) by the preliminary charging in the period T1 starts the main charging in the subsequent period T2. Some discharge is performed, and in the period T2, the pixel capacitor Cp (j, k) is charged after the discharge. Due to such discharge immediately after the start of the main charge, the pixel capacitance Cp (j, k) is not actually charged to the target potential Vs (k), and is determined by the potential difference between the pixel electrode and the common electrode Ec. The applied voltage VL (j, k) to the pixel liquid crystal may not reach the original applied voltage (voltage value corresponding to the desired pixel value) Vα = Vs (k) −V _CM . On the other hand, the rise time when the polarity of the data signal S (k) is switched increases because the wiring resistance and the like increase with the increase in size and definition of the liquid crystal panel as the display unit 603. Further, as the liquid crystal panel becomes higher in definition, the horizontal scanning period is shortened, so that a period in which the pixel capacitor Cp can be used for one charge (hereinafter referred to as “chargeable period”) is also shortened. Therefore, as the liquid crystal panel is increased in size and definition, insufficient charge for the pixel capacitance Cp (j, k) has become a problem.

On the other hand, as shown in FIG. 12, by delaying the timing of starting the main charging with respect to the pixel capacitor Cp, the active charge is prevented from being discharged in the pixel capacitor Cp immediately after the start of the main charging. A driving method of a matrix type liquid crystal display device has been proposed (see, for example, Patent Document 2). According to this, as shown in FIG. 12C, the pixel capacitance Cp (j, k) should be targeted by avoiding the discharge of the pixel capacitance Cp (j, k) immediately after the start of the main charging. It becomes possible to charge almost completely up to the potential Vs (k). Since the gate signal G (j) is normally generated by a shift register that operates based on one system of clock signals, the start timing of the main charging is delayed by Δd as shown in FIG. The start timing of the preliminary charging is also delayed by the same amount Δd.
JP 60-134293 A Japanese Patent Laid-Open No. 10-232651

The increase in size and definition of the display unit in the active matrix liquid crystal display device as described above is still in progress, and therefore the horizontal scanning period Th for determining the chargeable period of each pixel capacitor Cp is shortened. As the wiring resistance of the data line SLk increases, the rise time and the fall time at the time of polarity switching in the data signal S (k) tend to increase. Therefore, for example, even if the driving method disclosed in Patent Document 2 is adopted, as shown in FIG. 13C, the pixel capacitance Cp is not charged to the target potential Vs (k), that is, the pixel liquid crystal is not charged. The applied voltage VL (j, k) may not reach the original applied voltage Vα = Vs (k) −V _CM .

  The present invention has been made to solve such a problem, and the chargeable period of each pixel capacitor is shortened by increasing the size or the definition of the display unit, or the rise time when switching the polarity of the data signal Another object of the present invention is to provide an active matrix liquid crystal display device capable of sufficiently charging each pixel capacitor with a data signal even when the fall time is increased, and a driving circuit and a driving method thereof.

The first invention provides a plurality of video signal lines for respectively transmitting a plurality of video signals representing images to be displayed, a plurality of scanning signal lines intersecting with the plurality of video signal lines, and the plurality of video signals. A drive circuit of an active matrix liquid crystal display device comprising a plurality of pixel forming portions arranged in a matrix corresponding to intersections of lines and the plurality of scanning signal lines, respectively.
The plurality of scanning signal lines are selected so that the scanning signal line is selected during a pre-charging period preset for each scanning signal line and a main charging period set in advance as a period after the pre-charging period. A scanning signal line driving circuit for driving automatically,
The plurality of video signals are inverted in polarity every predetermined period so that the polarities of the voltages applied to the video signal lines are the same during the preliminary charging period and the main charging period. A video signal line driving circuit for applying to each video signal line,
The scanning signal line driving circuit starts selecting a scanning signal line to be selected in the main charging period while suppressing a decrease in the preliminary charging period when the polarity of the video signal is switched at the start of the main charging period. The time point is delayed by a predetermined time from the start point of the polarity switching.

According to a second invention, in the first invention,
When the polarity of the video signal is switched at the start of the preliminary charging period, the scanning signal line driving circuit is substantially referred to as the start point of polarity switching when the scanning signal line to be selected in the preliminary charging period is selected. It is characterized by matching.

According to a third invention, in the first invention,
The scanning signal line driving circuit includes:
The scanning in which a pulse having a width equal to the length of the precharge period is sequentially shifted from the input end to the output end based on a first clock signal in which a pulse having a width corresponding to the precharge period repeatedly appears in a predetermined cycle. A first shift register having a number of stages corresponding to the number of signal lines;
The main charging is based on a second clock signal corresponding to each pulse of the first clock signal, the start of which is a pulse delayed by a predetermined time from the start of the corresponding pulse in the first clock signal. A second shift register having a number of stages corresponding to the number of scanning signal lines, which shifts a pulse having a width equal to the length of the period from the input end to the output end;
Based on the output signal of each stage of the first shift register, each scanning signal line is selected only during the preliminary charging period set for the scanning signal line, and the output signal of each stage of the second shift register And an output circuit for outputting a signal for selecting each scanning signal line only during the main charging period set for the scanning signal line.

A fourth invention is an active matrix liquid crystal display device,
A drive circuit according to any one of the first to third inventions is provided.

According to a fifth aspect of the present invention, a plurality of video signal lines for respectively transmitting a plurality of video signals representing an image to be displayed, a plurality of scanning signal lines intersecting with the plurality of video signal lines, and the plurality of video signals A driving method of an active matrix liquid crystal display device including a plurality of pixel forming portions arranged in a matrix corresponding to intersections of lines and the plurality of scanning signal lines, respectively,
The plurality of scanning signal lines are selected so that the scanning signal line is selected during a pre-charging period preset for each scanning signal line and a main charging period set in advance as a period after the pre-charging period. Scanning signal line driving step for driving automatically,
The plurality of video signals are inverted in polarity every predetermined period so that the polarities of the voltages applied to the video signal lines are the same during the preliminary charging period and the main charging period. A video signal line driving step for applying each to the video signal line,
When the polarity of the video signal is switched at the start of the main charging period, the selection start point of the scanning signal line to be selected in the main charging period is the start point of the polarity switching while suppressing a decrease in the preliminary charging period. It is characterized by being delayed by a predetermined time.

According to a sixth invention, in the fifth invention,
When the polarity of the video signal is switched at the start of the precharge period, the selection start time of the scanning signal line to be selected in the precharge period is substantially the same as the start time of the polarity switching. To do.

  According to the first aspect of the invention, when the polarity of the video signal is switched at the start of the main charging period, the selection start point of the scanning signal line to be selected in the main charging period is suppressed while the decrease in the preliminary charging period is suppressed. Is delayed by a predetermined time from the start of the polarity switching. For this reason, the discharge generated in the pixel formation portion (pixel capacity) immediately after the start of the main charging due to an increase in the rise time and fall time of the video signal in the video signal line without reducing the period for the preliminary charge as much as possible. Can be avoided. As a result, even if the chargeable period of each pixel capacity is shortened or the rise time when switching the polarity of the video signal is increased due to the enlargement or high definition of the display unit of the active matrix liquid crystal display device, Each pixel capacity can be sufficiently charged by the video signal.

  According to the second aspect, when the polarity of the video signal is switched at the start of the precharge period, the selection start time of the scanning signal line to be selected in the precharge period is substantially equal to the start time of the polarity switching. Therefore, the preliminary charging period is not narrowed with a delay at the start of selection of the scanning signal line to be selected in the main charging period. Therefore, the precharge period can be maintained long while avoiding the discharge that occurs in the pixel formation portion immediately after the start of the main charge. As a result, even if the chargeable period of each pixel capacity is shortened or the rise time when switching the polarity of the video signal is increased due to the enlargement or high definition of the display unit of the active matrix liquid crystal display device, Each pixel capacity can be sufficiently charged by the video signal.

  According to the third aspect of the present invention, during the precharge period set for each scanning signal line based on the output signals of the respective stages of the first and second shift registers operating with the first and second clock signals, respectively. In addition, by generating a signal for selecting the scanning signal line during the main charging period, it is possible to maintain a long preliminary charging period while avoiding a discharge that occurs in the pixel formation portion immediately after the start of the main charging.

  According to the fourth aspect of the present invention, an active matrix liquid crystal display device having the same effects as the first aspect of the invention can be provided.

  According to the fifth aspect, it is possible to provide a driving method of an active matrix type liquid crystal display device that has the same effect as the first aspect.

  According to the sixth aspect, it is possible to provide a method for driving an active matrix liquid crystal display device that exhibits the same effect as the second aspect.

Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.
<1. Overall configuration and operation>
First, the overall configuration and operation of a liquid crystal display device according to an embodiment of the present invention will be described. FIG. 1 is a block diagram showing the configuration of the liquid crystal display device according to this embodiment together with an equivalent circuit of the display unit. This liquid crystal display device is similar to the conventional active matrix liquid crystal display device shown in FIG. 9, and includes a data driver 101 as a video signal line driving circuit, a gate driver 102 as a scanning signal line driving circuit, and an active matrix type. A display unit 103 and a display control circuit 200 for controlling the data driver 101 and the gate driver 102 are provided.

  The display unit 103 in this embodiment has the same configuration as the display unit 603 shown in FIG. That is, the display unit 103 includes gate lines GL1 to GLm as a plurality (m lines) of scanning signal lines and a plurality (n lines) of video signal lines that intersect with each of the gate lines GL1 to GLm. It includes data lines SL1 to SLn and a plurality (m × n) of pixel forming portions provided corresponding to the intersections of the gate lines GL1 to GLm and the data lines SL1 to SLn. These pixel formation portions are arranged in a matrix to form a pixel array, and each pixel formation portion is connected to a gate line GLj that passes through a corresponding intersection and a data line SLk that passes through the intersection. The TFT 10 that is a switching element to which the source terminal is connected, the pixel electrode that is connected to the drain terminal of the TFT 10, the common electrode Ec that is the common electrode provided in the plurality of pixel formation portions, and the plurality And a liquid crystal layer sandwiched between the pixel electrode and the common electrode Ec. If necessary, an auxiliary capacitor is provided in parallel with the capacitor formed by the pixel electrode and the common electrode Ec. Is added. A pixel capacitance Cp is constituted by a capacitance formed by the pixel electrode and the common electrode Ec (a capacitance obtained by adding an auxiliary capacitance to the auxiliary capacitance if added).

An example of the driving method and driving circuit of the present invention for the display unit 103 in the present embodiment will be described below.
The display control circuit 200 receives, from an external signal source or the like, a digital video signal Dv representing an image to be displayed, a horizontal synchronization signal HSY and a vertical synchronization signal VSY corresponding to the digital video signal Dv, a display operation mode, and the like. A data driver start pulse signal is received as a signal for displaying an image represented by the digital video signal Dv on the display unit 103 based on the control signal Dc for controlling and the signals Dv, HSY, VSY, Dc. SSP, data driver clock signal SCK, digital image signal DA representing the image to be displayed (signal corresponding to video signal Dv), gate driver start pulse signal GSP, and two systems of gate driver clock signal GCK1 , GCK2 and a mode for controlling the operation mode of the gate driver 102 And it generates and outputs a control signal GMODE. More specifically, the video signal Dv is output from the display control circuit 200 as the digital image signal DA after timing adjustment or the like is performed in the internal memory as necessary, and corresponds to each pixel of the image represented by the digital image signal DA. A data driver clock signal SCK is generated as a signal composed of pulses, and a data driver start pulse signal SSP is generated as a signal that becomes a high level (H level) for a predetermined period every horizontal scanning period based on the horizontal synchronization signal HSY. The gate driver start pulse signal GSP is generated as a signal that is H level for a predetermined period every frame period (one vertical scanning period) based on the vertical synchronization signal VSY, and is used as the gate driver clock signal based on the horizontal synchronization signal HSY. Generating first and second clock signals GCK1, GCK2, Generating a mode control signal GMODE for controlling the operating mode of the gate driver 102 on the basis of the control signal Dc. As will be described later, both the first and second clock signals GCK1 and GCK2 are pulse signals having a repetition period of one horizontal scanning period, but the period of the H level of the second clock signal GCK1 in each horizontal scanning period. Is set shorter than the H level period of the first clock signal GCK1 (see FIGS. 2A and 2B described later).

  Of the signals generated in the display control circuit 200 as described above, the digital image signal DA, the data driver start pulse signal SSP, and the clock signal SCK are input to the data driver 101 and the gate driver start pulse. The signal GSP, the clock signals GCK1 and GCK2, and the mode control signal GMODE are input to the gate driver 102.

  Based on the digital image signal DA, the data driver start pulse signal SSP, and the clock signal SCK, the data driver 101 uses the data signal S as an analog voltage corresponding to the pixel value in each horizontal scanning line of the image represented by the digital image signal DA. (1) to S (n) are sequentially generated for each horizontal scanning period, and these data signals S (1) to S (n) are applied to the data lines SL1 to SLn, respectively. The data driver 101 according to the present embodiment uses the data signals S (1) to S1 so that the polarity of the voltage applied to the liquid crystal layer is inverted every frame period and also every horizontal scanning line in each frame. A driving method in which S (n) is output, that is, a line inversion driving method is adopted. From the viewpoint of improving display quality, in addition to this, the liquid crystal layer is also applied to each data line (every vertical line). It is preferable to employ a driving method that reverses the polarity of the applied voltage, that is, a dot inversion driving method. That is, the data driver 101 preferably outputs the data signals S (1) to S (n) so that the polarity of the voltage applied to the data lines SL1 to SLn is inverted for each data line. However, instead of this, the data signals S (1) to S (n) may be output so that the voltages applied to the data lines SL1 to SLn have the same polarity.

  The gate driver 102 receives the gate driver start pulse signal GSP, the first and second clock signals GCK1 and GCK2 for the gate driver, and the mode control signal GMODE from the display control circuit 200, and these signals GSP, GCK1, Based on GCK2 and GMODE, in each frame period (each vertical scanning period) of the digital image signal DA, the gate lines GL1 to GLm are sequentially selected, and an active gate signal (voltage for turning on the TFT 10) is selected to the selected gate line. Apply. In the gate driver 102 in the present embodiment, the gate lines GL1 to GLm are each selected once in each frame period. A gate two-pulse drive mode, which is an operation mode selected twice each, and when the mode control signal GMODE is at a low level (L level), the gate operates in the one-pulse drive mode. Level), it operates in the gate 2 pulse drive mode. When the gate driver 102 operates in the gate two-pulse drive mode, each of the gate lines GL1 to GLm is selected twice in each frame period in the display unit 103, and the selected gate is selected in each selection period. Each TFT (hereinafter referred to as “selection TFT”) 10 whose gate terminal is connected to the line GLj is turned on. As a result, the pixel capacitor Cp connected to the drain terminal of each selection TFT 10 is precharged in the first selection period of the two selection periods in each frame period, and the main capacitor is selected in the second selection period. Charging is performed. Details of such gate two-pulse driving in this embodiment will be described later.

  In the display unit 103, the data signals S (1) to S (n) are applied to the data lines SL to SLn, respectively, and the gate signal G ( 1) to G (m) are respectively applied. As a result, the voltage corresponding to the value of the corresponding pixel in the image represented by the digital image signal DA is precharged by the data signals S (1) to S (n) to the pixel capacitance Cp of each pixel forming unit in the display unit 103. A voltage corresponding to the potential difference between the pixel electrode and the common electrode Ec is applied to the liquid crystal layer according to the digital image signal DA. That is, the voltage held in each pixel capacitor Cp is the voltage applied to the pixel liquid crystal corresponding to the voltage. The display unit 603 displays an image represented by the digital image signal DA, that is, an image represented by a digital video signal received from an external signal source or the like, by controlling the light transmittance of the liquid crystal layer by the applied voltage.

<2. Gate Driver Operation and Configuration Example>
FIG. 2 is a signal waveform diagram for explaining the operation of the gate driver 102 in the gate 1 pulse drive mode in the present embodiment. As described above, the display control circuit 200 generates the first and second clock signals GCK1 and GCK2 which are two systems of clock signals having the horizontal scanning period Th as a repetitive cycle, and FIGS. As shown in FIG. 6, the H level period of the second clock signal GCK1 is set shorter than the H level period of the first clock signal GCK1 in each horizontal scanning period Th. The first and second clock signals GCK1 and GCK2 are input to the gate driver 102. As shown in FIG. 2E, the mode control signal GMODE is set to the L level to set the gate 1 pulse driving mode. In such a case, only the first clock signal GCK1 is used. In this case, the gate driver 102 sequentially selects the gate lines GL1 to GLm based on the start pulse signal GSP and the first clock signal GCK1 so that each of the gate lines GL1 to GLm is selected once in one frame period. Gate signals OG (1) to OG (m) for selection are generated. That is, in the gate signals OG (1) to OG (m) applied to the gate lines GL1 to GLm, the j-th gate signal G (j) is as shown in FIG. It becomes active (H level) during the period when the first clock signal GCK1 is at H level in the jth horizontal scanning period (j = 1, 2,..., m).

  FIG. 3 is a signal waveform diagram for explaining the operation of the gate driver 102 in the gate two-pulse drive mode in this embodiment. As shown in FIG. 3E, when the mode control signal GMODE is set to the H level and the gate two-pulse drive mode is set, both the first and second clock signals GCK1 and GCK2 are used. In this case, the gate driver 102 selects the gate line GL1 to GLm so that each of the gate lines GL1 to GLm is selected twice in one frame period based on the start pulse signal GSP and the first and second clock signals GCK1 and GCK2. Gate signals OG (1) to OG (m) for sequentially selecting GL1 to GLm are generated. That is, as shown in FIG. 3C, the j-th gate signal G (j) has a period T1 in which the first clock signal GCK1 is at the H level in the j-th horizontal scanning period in each frame period, and It becomes active (H level) during a period T2 in which the second clock signal GCK2 is at H level during the j + 2 horizontal scanning period in each frame period. The polarity of the data signal S (k) is the same during these periods T1 and T2. Thereby, in the display unit 103, preliminary charging is performed in the period T1, and main charging is performed in the period T2 (j = 1, 2,..., M). As shown in FIGS. 3A and 3B, the H level period of the second clock signal GCK2 is set shorter than the H level period of the first clock signal GCK1 in each horizontal scanning period Th. The rising edge of the waveform in the first clock signal GCK1 is at the same time as the start time of the horizontal scanning period, but the rising edge of the waveform in the second clock signal GCK2 is slightly delayed from the start time of the horizontal scanning period. Therefore, the preliminary charging period T1 is longer than the main charging period T2, and the starting time of the main charging is slightly delayed from the starting time of the horizontal scanning period. As will be described later, this makes it possible to charge each pixel capacitor Cp in the display unit 103 more sufficiently than in the past in accordance with the data signals S (1) to S (n).

  FIG. 4 is a block diagram showing a configuration example for realizing the gate driver 102 as described above. The gate driver 102 of this configuration example includes an m-stage first shift register 11, an m + 2 stage second shift register 12, m OR gates 15, and a selection circuit 16 including m change-over switches. ing. The first clock signal GCK 1 is input to the first shift register 11, the second clock signal GCK 2 is input to the second shift register 12, and the gate driver start pulse signal GSP is supplied to the first and second shift registers 11 and 12. The mode control signal GMODE is input to both, and is input to the selection circuit 16. The m OR gates 15 and the selection circuit 16 constitute an output circuit of the gate driver 102, and gate signals OG (1) to OG (m) to be applied to the gate lines GL1 to GLm, respectively, are output from the output circuit. The

  The first shift register 11 inputs a pulse having a width equal to the pulse width (the length of the H level period in one horizontal scanning period) in the first clock signal GCK1 based on the first clock signal GCK1 and the start pulse signal GSP. The second shift register 12 shifts the pulse width in the second clock signal GCK2 (the length of the H level period in one horizontal scanning period) based on the second clock signal GCK2 and the start pulse signal GSP. Are sequentially shifted from the input end to the output end. From the j-th stage in the first shift register 11, a signal G1 (j) as shown in FIG. 5C, that is, a period during which the first clock signal GCK1 is at the H level within each horizontal scanning period Th is pulse width. The j-th output signal G1 (j) is input to the jth OR gate 15 (j = 1, 2,..., M). For the second shift register 12, the first and second stage output signals are not used, and the third and subsequent stage output signals are used. From the j + 2 stage in the second shift register 12, the signal G2 (j) as shown in FIG. 5D, that is, the period during which the second clock signal GCK2 is at the H level within each horizontal scanning period Th is pulse width. The j + 2 stage output signal G2 (j) is input to the jth OR gate 15 (j = 1, 2,..., M). Therefore, the j-th OR gate 15 is a signal of a logical sum of the j-th output signal G1 (j) of the first shift register 11 and the j + 2-th output signal G2 (j) of the second shift register 12 ( (Hereinafter referred to as “jth logical sum signal”). The selection circuit 16 includes first to mth changeover switches, and the jth output signal G1 (j) of the first shift register 11 and the jth logical sum signal are input to the jth changeover switch. The The jth changeover switch allows the output signal G1 (j) at the jth stage of the first shift register 11 when the mode control signal GMODE is L level, and the jth logic when the mode control signal GMODE is H level. The sum signal is selected, and the signal selected by the j-th change-over switch is output from the gate driver 102 as the gate signal OG (j). Therefore, when the mode control signal GMODE is at the L level, the gate signal OG (j) having a waveform as shown in FIG. 2C is output, and when the mode control signal GMODE is at the H level, the signal is shown in FIG. A gate signal OG (j) having such a waveform is output. The gate signal OG (j) shown in FIG. 5C is the same as the gate signal OG (j) shown in FIG.

<3. Action and Effect>
Hereinafter, the operation and effect of this embodiment will be described with reference to the signal waveform diagram shown in FIG. For convenience of explanation in this embodiment, although the potential of the common electrode Ec is assumed to be fixed to the V _CM, when not employing the dot inversion driving method, i.e. the data signals S (1) to S in (n) In the case where the polarities coincide with each other, the common electrode Ec may be configured to be AC driven in order to suppress the amplitude of the data signals S (1) to S (n) (the same applies to modified examples described later).

In this embodiment, since the line inversion driving method is adopted, the waveform of the data signal S (k) in the data line SLk of the display unit 103 is as shown in FIG. It is inverted every scanning period (k = 1, 2,..., N). On the other hand, the waveform of the gate signal OG (j) in the gate line GLj of the display portion 103 is as shown in FIG. 6B, and there are few restrictions on the layout of the gate line GLj and the capacity to be connected. The rise time of the signal OG (j) is much shorter than that of the data signal S (k). In the gate signal OG (j), the precharging period T1 is longer than the main charging period T2, and the main charging start time (starting time of the period T2) is the start time of the horizontal scanning period, that is, data. It is delayed by Δd2 from the start point of polarity switching of the signal S (k) (in the example of FIG. 6, the rising start point of the data signal S (k)). In this way, by delaying only the start time of the main charge without delaying the start time of the precharge, the discharge at the pixel capacitor Cp immediately after the start of the main charge (without shortening the period for the precharge) ( FIG. 11C is avoided. Therefore, according to the present embodiment, the chargeable period of each pixel capacitor is shortened by increasing the size or definition of the display unit 103, or the rise time or fall time when switching the polarity of the data signal is increased. However, each of the pixel capacitors Cp is sufficiently charged according to the data signal S (k) in the preliminary charging period T1 and the main charging period T2 as described above, and the applied voltage VL (j, k) to the pixel liquid crystal. ) Can reach the original applied voltage Vα = Vs (k) −V _CM .

<4. Modification>
In the embodiment described above, two systems of gate driver clock signals GCK1 and GCK2 are generated in the display control circuit 200. Instead of this, the display control circuit 200 uses one system as a gate driver clock signal as in the prior art. Only the clock signal GCK of the two systems is generated, and the clock signals GCK1 and GCK2 of the two systems are converted from the clock signal GCK of one system by processing such as delaying the phase of the clock signal GCK using an external capacitor and resistor, for example. The configuration may be such that the gate driver 102 generates it.

  In the above embodiment, in the gate two-pulse drive mode, as shown in FIG. 6, the start time of the preliminary charging (start time of the period T1) is the data signal S (k ) Coincides with the rising start point (generally, the start point of polarity switching), but is not limited to the configuration in which both start points coincide with each other, as shown in FIG. The period T1 is set to be longer than the period T2 of the main charging, and the start time of the preliminary charging is a predetermined time from the start time of the rise of the data signal S (k) that is the start time of the corresponding horizontal scanning period Th. You may make it delay only (DELTA) d1. In this case, as shown in FIG. 7B, the delay time Δd1 of the preliminary charging is shorter than the delay time Δd2 of the main charging start, and the specific values of Δd1 and Δd2 It is determined in consideration of the value of the horizontal scanning period Th, the rise time of the data signal S (k), etc. so as to be sufficiently performed.

  Furthermore, in the above embodiment, a one-line inversion driving method is employed in which the polarity of the voltage applied to the liquid crystal layer is inverted for each horizontal scanning line in each frame (see FIG. 6A). Is not limited to a one-line inversion driving type liquid crystal display device, but is also applied to, for example, a two-line inversion driving type liquid crystal display device that inverts the polarity of the voltage applied to the liquid crystal layer every two horizontal scanning lines. Applicable. In the case of the two-line inversion driving method, the waveform of the data signal S (k) is as shown in FIG. 8A. Therefore, for example, the gate signals OG (j) and OG as shown in FIGS. (j + 1) may be generated. That is, in the case of the two-line inversion driving method, the voltages VL (j, k) and VL (j + 1, k) applied to the pixel liquid crystal corresponding to the adjacent gate lines GLj and GLj + 1 have the same polarity, but the adjacent As shown in FIG. 8B, the gate signal OG (j similar to the gate signal OG (j) in the above embodiment is applied to the first gate line (gate line GLj selected earlier) among the gate lines. ) Is applied. On the other hand, the pixel capacitance Cp corresponding to the second gate line (the later selected gate line) GLj + 1 of the adjacent gate lines is discharged immediately after the start of the main charge, unlike the above embodiment. Therefore, there is no need to delay the starting time of the main charging. Therefore, a gate signal OG (j + 1) as shown in FIG. 8D is applied to the gate line GLj + 1. However, in order to avoid complication of the configuration of the data driver, the gate line GLj + 1 is also applied to the gate signal OG () in which only the start time of the main charging is delayed by a predetermined time Δd2 as shown in FIG. j + 1) (not shown) may be applied.

  Furthermore, in the above-described embodiment, when gate two-pulse driving is performed in which each of the gate lines GL1 to GLm is selected twice in each frame period, the preliminary charging is performed only once in each frame period. In addition, the present invention can be applied to a configuration in which the preliminary charging is performed twice or more in each frame period. However, it is assumed that the polarity of the data signal S (k) in each preliminary charging period is the same as the polarity of the data signal S (k) in the main charging period corresponding to the preliminary charging. In this case, for example, in each frame period, without delaying the start time of the first preliminary charge, by appropriately delaying the start time of the second and subsequent preliminary charges and the main charge, The pixel capacitor Cp can be sufficiently charged by the data signal S (k) while avoiding the discharge of the pixel capacitor Cp immediately after the start of the main charging.

It is a block diagram which shows the structure of the liquid crystal display device which concerns on one Embodiment of this invention with the equivalent circuit of the display part. It is a signal waveform diagram for demonstrating operation | movement in the gate 1 pulse drive mode of the gate driver in the said embodiment. It is a signal waveform diagram for demonstrating operation | movement in the gate 2 pulse drive mode of the gate driver in the said embodiment. It is a block diagram which shows one structural example of the gate driver in the said embodiment. It is a signal waveform diagram for demonstrating operation | movement of the gate driver of the said one structural example. It is a signal waveform diagram for demonstrating the effect | action and effect in the said embodiment. It is a signal waveform diagram for demonstrating one modification of the said embodiment. It is a signal waveform diagram for demonstrating the other modification of the said embodiment. 2 is a block diagram showing a configuration of a main part in a conventional active matrix liquid crystal display device together with an equivalent circuit of a display unit. It is a signal waveform diagram for demonstrating operation | movement when the gate 2 pulse drive system is employ | adopted in the conventional active matrix type liquid crystal display device. It is a signal waveform diagram for demonstrating a problem when the gate 2 pulse drive system is employ | adopted in the conventional active matrix type liquid crystal display device. It is a signal waveform diagram for demonstrating operation | movement of the conventional active matrix type liquid crystal display device improved in order to solve the said problem. It is a signal waveform diagram for demonstrating the problem in the said improved conventional active matrix type liquid crystal display device.

Explanation of symbols

10 ... Thin film transistor (TFT)
DESCRIPTION OF SYMBOLS 11 ... 1st shift register 12 ... 2nd shift register 15 ... OR gate 16 ... Selection circuit 101 ... Data driver (video signal line drive circuit)
102: Gate driver (scanning signal line driving circuit)
DESCRIPTION OF SYMBOLS 103 ... Display part 200 ... Display control circuit Cp ... Pixel capacity Ec ... Common electrode GL1-GLm ... Gate line (scanning signal line)
OG (1) to OG (m) ... Gate signal (scanning signal)
SL1 to SLn: Data line (video signal line)
S (1) to S (n) ... Data signal (video signal)
DA ... Digital image signal GSP ... Gate driver start pulse GCK1 ... Gate driver first clock signal GCK2 ... Gate driver second clock signal GMODE ... Mode control signal SSP ... Data driver start pulse SCK ... Data driver clock signal SSP ... Start pulse for data driver

Claims (6)

A plurality of video signal lines for respectively transmitting a plurality of video signals representing an image to be displayed, a plurality of scanning signal lines intersecting with the plurality of video signal lines, the plurality of video signal lines and the plurality of scannings A drive circuit for an active matrix liquid crystal display device comprising a plurality of pixel formation portions arranged in a matrix corresponding to the intersections with signal lines,
The plurality of scanning signal lines are selected so that the scanning signal line is selected during a pre-charging period preset for each scanning signal line and a main charging period set in advance as a period after the pre-charging period. A scanning signal line driving circuit for driving automatically,
The plurality of video signals are inverted in polarity every predetermined period so that the polarities of the voltages applied to the video signal lines are the same during the preliminary charging period and the main charging period. A video signal line driving circuit for applying to each video signal line,
The scanning signal line driving circuit starts selecting a scanning signal line to be selected in the main charging period while suppressing a decrease in the preliminary charging period when the polarity of the video signal is switched at the start of the main charging period. A drive circuit characterized in that the time point is delayed by a predetermined time from the start point of the polarity switching.   When the polarity of the video signal is switched at the start of the preliminary charging period, the scanning signal line driving circuit is substantially referred to as the start point of polarity switching when the scanning signal line to be selected in the preliminary charging period is selected. The drive circuit according to claim 1, wherein the drive circuits are matched. The scanning signal line driving circuit includes:
The scanning in which a pulse having a width equal to the length of the precharge period is sequentially shifted from the input end to the output end based on a first clock signal in which a pulse having a width corresponding to the precharge period repeatedly appears in a predetermined cycle. A first shift register having a number of stages corresponding to the number of signal lines;
The main charging is based on a second clock signal corresponding to each pulse of the first clock signal, the start of which is a pulse delayed by a predetermined time from the start of the corresponding pulse in the first clock signal. A second shift register having a number of stages corresponding to the number of scanning signal lines, which sequentially shifts pulses having a width equal to the length of the period from the input end to the output end;
Based on the output signal of each stage of the first shift register, each scanning signal line is selected only during the preliminary charging period set for the scanning signal line, and the output signal of each stage of the second shift register 2. The drive circuit according to claim 1, further comprising: an output circuit that outputs a signal for selecting each scanning signal line for the main charging period set for the scanning signal line based on the first scanning period.   An active matrix liquid crystal display device comprising the drive circuit according to claim 1. A plurality of video signal lines for respectively transmitting a plurality of video signals representing an image to be displayed, a plurality of scanning signal lines intersecting with the plurality of video signal lines, the plurality of video signal lines and the plurality of scannings A driving method of an active matrix liquid crystal display device comprising a plurality of pixel formation portions arranged in a matrix corresponding to the intersections with signal lines,
The plurality of scanning signal lines are selected so that the scanning signal line is selected during a pre-charging period preset for each scanning signal line and a main charging period set in advance as a period after the pre-charging period. Scanning signal line driving step for driving automatically,
The plurality of video signals are inverted in polarity every predetermined period so that the polarities of the voltages applied to the video signal lines are the same during the preliminary charging period and the main charging period. A video signal line driving step for applying each to the video signal line,
When the polarity of the video signal is switched at the start of the main charging period, the selection start point of the scanning signal line to be selected in the main charging period is the start point of the polarity switching while suppressing a decrease in the preliminary charging period. A driving method characterized by being delayed by a predetermined time. When the polarity of the video signal is switched at the start of the precharge period, the selection start time of the scanning signal line to be selected in the precharge period is substantially the same as the start time of the polarity switching. The driving method according to claim 5.

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