JPH1165536A - Image display device, image display method and electronic equipment using the same, and projection type display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce image unevennesses and ghosts even while developing an image signal in (n) phases. SOLUTION: Pixel data are developed in (n) phases and (n) pieces of sample- and-hold switches are connected in parallel to be made sample-and-holding switch blocks corresponding to them and ons/offs of the sample-and-hold switch blocks are controlled by logics between output signals of respective enable circuits and output signals of an X-shift register 104. In respective sampling periods of respective pixel data, pixel data sampled in previous sampling periods in respective phase developing signal lines which corresponds to pixels are supplied at the starting time of a normal pixel sampling period. Moreover, in the normal pixel data sample-and-holding period, corresponding sample-and- holding blocks are made to be in off states. Sampling periods of the pixel data are adjusted by a dot clock signal and they are set overall in 13-16 cycles and their duty factors are set to be roughly equal to or smaller than 66.7%.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image display device, an image display method, and an electronic device using the same, and more particularly, to a high-definition image display device that performs phase expansion driving.

[0002]

2. Description of the Related Art For example, in an active matrix type liquid crystal display device, a plurality of TFTs connected to one scanning signal line are provided.
The operation of writing data in the liquid crystal cell of each pixel via a switching element (pixel switch) such as a (thin film transistor) is performed by dot-sequential driving and line-sequential driving.

Further, in order to eliminate display unevenness due to bias of the voltage applied to the liquid crystal and to prevent deterioration of the liquid crystal due to a DC current applied to the liquid crystal, a polarity inversion drive for inverting the polarity of the voltage applied to the liquid crystal at a predetermined timing is known. Is being done.

[0004] The polarity inversion drive is a drive in which voltages of different polarities (positive or negative) are applied to one end of a liquid crystal cell with reference to a potential applied to the other end. In this specification, “polarity” means the polarity of the potential at the other end of the liquid crystal cell with reference to the potential at one end of the liquid crystal cell. To drive the polarity inversion, in an active matrix type using a TFT, the potential applied to a common electrode opposed to a pixel electrode across a liquid crystal is changed, or the voltage amplitude of a pixel signal applied to the pixel electrode is intermediate. The potential level of the pixel signal is changed based on the potential.

Here, in the polarity inversion, a so-called line inversion method in which the polarity is inverted every time a scanning signal line is selected is known.

FIG. 13 is a schematic diagram for explaining the polarity inversion driving method. A conventional active matrix type liquid crystal display device employs a dot-sequential drive and line-sequential drive system, and a system in which data signal lines are precharged in a blanking period immediately before.

In FIG. 13, "+",
“−” Indicates the polarity of driving and precharging, and in line-sequential driving, voltages with different polarities are applied to pixels connected to adjacent scanning signal lines. Also, all the pixels have TFTs as shown in the figure.
And a liquid crystal cell.

In the scanning signal line inversion driving method, voltages having different polarities are applied to pixels connected to adjacent scanning signal lines. For example, in the scanning signal lines H1 and H2 commonly connected to the data signal line S1, the scanning signal line H1
Is applied with a voltage on the positive polarity side, and a voltage on the negative polarity side is applied to the scanning signal line H2.

In this case, even when, for example, the same black is sequentially written on two pixels connected to the same data signal line and to different scanning signal lines on the display, the two pixels are connected by the polarity inversion driving method. The signal levels of the black display data are different. At this time, since the data signal line itself has a parasitic capacitance, the potential of the data signal line is
It takes time to perform normal serial data transfer to change from the black level potential on the positive polarity side to the black level potential on the negative polarity side.

By the way, in order to respond to the recent demand for multimedia display devices, for example, when a natural image such as a video signal is displayed on a personal computer (PC) or an engineering workstation (EWS). For example, it is desired to cope with multi-gradation such as 256 gradations.

In order to realize the multi-gray scale using a conventional digital driving IC and a digital image signal, the number of input signals is required to be increased by the number of bits. For example, in the case of color display of 256 gradations, the number of input signals is 3 (R, G, B) × 8 bits = 24.

For this reason, as shown in FIG. 13, an image signal is expanded into, for example, six phases, and the time of data per pixel is calculated as follows.
A technique has been proposed in which the length of the signal is longer than that in the case of serial input and the frequency of the signal supplied to the data signal line is lowered. (Japanese Patent Application No. 7-245416).

By this phase expansion, for example, even if the frequency characteristics of a TFT as a sample-and-hold switch are not sufficient, the sampling period is set only for a stable data area in the phase-expanded pixel data, so that the previous sampling can be performed. Only pixel data having a stable potential can be sent to the data signal line without being affected by the pixel data in the period.

However, in the image display device,
While the need for high-speed driving has arisen due to the increase in the number of pixels, the sampling period for pixel data has become longer, which is a new problem.

[0015]

SUMMARY OF THE INVENTION It is an object of the present invention to provide an image display which can reduce or prevent image unevenness and ghost while developing an image signal into n phases (n is an integer of 2 or more) using a driving IC. An object of the present invention is to provide an apparatus, an image display method, and an electronic apparatus including the same.

[0016]

An image display device according to claim 1, wherein the plurality of data signal lines and the plurality of scanning signal lines intersecting with the plurality of data signal lines include the plurality of data signal lines and the plurality of scanning signal lines. An image display unit in which display elements connected to signal lines are arranged in a matrix, a scanning signal selection unit that supplies a scanning signal for sequentially selecting the scanning signal lines to the scanning signal lines, and the image display unit An image signal as serial data of an image to be displayed is sampled and held by inputting a sampling period signal set based on a reference clock, and the serial data is expanded for each fixed pixel, and A plurality of pixel data whose data time has been converted to an integer multiple of n (n ≧ 2) of the reference clock; A plurality of sampling means connected to each other, sampling the plurality of pixel data over a sampling period, and supplying the plurality of pixel data to the corresponding data signal lines; and a plurality of sampling means which are generated before a sample hold period of the plurality of pixel data. The generation is terminated before the end of each sample hold period, and
A sampling period signal generating unit that supplies a plurality of sampling period signals each having a sampling period longer than n times the reference clock to the sampling unit, and the sampling period signal generating unit includes each of the sampling periods. Data signal line driving means for supplying a signal during a period to select each of the plurality of data signal lines.

Therefore, according to the image display device of the present invention, a plurality of pixel data whose data time per pixel is converted to N times the reference clock are output in parallel, and n times the reference clock is output. By sampling in a longer sampling period, each pixel data can be reliably written to the designated pixel, and line unevenness and ghost can be prevented for each writing block.

According to the image display device of the second aspect, in addition to the features of the first aspect, the sampling means includes a plurality of sample and hold switch blocks formed by a plurality of switching elements. Each of the sample-and-hold switch blocks simultaneously samples the plurality of pixel data output in parallel over a common sampling period.

Therefore, according to the image display device of the second aspect, block transfer of pixel data can be performed for each of the sample and hold switch blocks.

According to a third aspect of the present invention, in addition to the features of the second aspect, the image display section is a liquid crystal display section formed on a substrate, and the plurality of switching elements are arranged on the substrate. It is composed of a plurality of TFTs formed above,
The sampling period signal from the sampling period signal generating means is supplied to the gate of each of the TFTs for each of the sample and hold switch blocks, and pixel data is supplied to the source of each of the TFTs. It is characterized by having.

Therefore, according to the image display device of the third aspect, even if the switching characteristics of the switching element are not good, a sufficient sampling period of the pixel data is provided, so that the pixel data is transferred to the pixel. Writing can be performed reliably.

According to a fourth aspect of the present invention, in addition to the features of the second or third aspect, at the start of the sampling period, dummy pixel data is supplied to the sample and hold switch block. And

Therefore, according to the image display device of the present invention, pixel data which is not regular pixel data supplied to the sample and hold switch block is used as dummy pixel data and corresponds to each of the sample and hold switch blocks. By using the voltage for the initial voltage supply during sampling, it is possible to cover the shortcomings of the switching characteristics of the TFTs forming the sample-and-hold switch block, and during the period until normal pixel data is supplied, The potential of the data signal line corresponding to the sample hold switch block can be increased by the potential of the dummy pixel data.

According to a fifth aspect of the present invention, in addition to the features of the third aspect, the sampling signal generating means includes:
The first / second sampling period signals are respectively supplied to the adjacent first / second sample / hold switch blocks, and the supply of the first sampling period signals to the first sample / hold switch block is started. Later, during the sampling period of the corresponding first pixel data, the supply of the second sampling period signal to the second sample and hold switch block is started.

Therefore, according to the image display device of the present invention, while the first pixel data is supplied to the adjacent sample-and-hold switch blocks, the sampling corresponding to the second sample-and-hold switch is performed. By turning on the second sample-hold switch block at an early stage, it is possible to cover the shortcomings of the switching characteristics of the TFT forming the sample-hold switch block.

According to a sixth aspect of the present invention, in addition to the feature of the fifth aspect, the second sample-and-hold switch block samples the first pixel data at the start of the sampling period. The first pixel data is supplied to the data signal line as a precharge voltage.

Therefore, according to the image display device of the sixth aspect, the voltage of the first pixel data supplied to the adjacent sample and hold switch blocks is
By using the precharge voltage for the initial voltage supply in the sampling corresponding to the second sample and hold switch, it is possible to cover the shortcomings of the switching characteristics of the TFT forming the sample and hold switch block. Become.

According to a seventh aspect of the present invention, in addition to the features described in any one of the third to sixth aspects, the image display device further includes a plurality of enable circuits and first / second enable signal lines.
The plurality of enable circuits are formed between the plurality of sampling units provided in correspondence with the plurality of sample-and-hold switch blocks and the data signal line driving unit. The input line of the located enable circuit is connected to the first enable signal line, and the input line of the even-numbered enable circuit is connected to the second enable signal line. And

Therefore, according to the image display device of the present invention, the supply of the voltage to the plurality of sample-and-hold switch blocks can be controlled by the enable circuit, so that the generation / non-generation of the sampling period signal is controlled. can do.

According to an eighth aspect of the present invention, in addition to the features of the seventh aspect, the plurality of enable circuits are provided corresponding to the plurality of sample-and-hold switch blocks and the plurality of enable circuits. The output signal of each of the enable circuits is supplied to each of the sample and hold switch blocks as a sampling period signal.

Therefore, according to the image display device of the present invention, it is possible to control each of the sample-and-hold switch blocks by the output signals of the plurality of enable circuits.

According to a ninth aspect of the present invention, in addition to the feature of the eighth aspect, each of the plurality of enable circuits is supplied with a first or second enable signal to one input terminal. The other input terminal has an AND circuit to which an output signal from the data signal line driving circuit is supplied.

Therefore, according to the image display device of the ninth aspect, the outputs of the plurality of enable circuits, that is, the ON time of the sample and hold switch block by the supply of the sampling period signal, are set based on the reference clock. be able to.

According to a tenth aspect of the present invention, in addition to the feature of the ninth aspect, the duty of each of the first and second enable signals is 50% or more.

Therefore, according to the image display device of the tenth aspect, the adjacent sample hold switch blocks are turned on by alternately using the first enable signal and the second enable signal. State.

The image display device according to claim 11 is the image display device according to claim 10
The reference clock is a dot clock signal, and the reference clock is a variable which changes at least one of a duty and a phase of the first / second enable signal in units of the dot clock signal. It is characterized by further comprising means.

Therefore, according to the image display device of the eleventh aspect, with reference to the dot clock signal,
It is possible to arbitrarily change at least one of the duty and phase of the first / second enable signal by adjustment at the shipping stage or adjustment by a user.

According to a twelfth aspect of the present invention, there is provided the image display device according to the eleventh aspect.
In addition to the features described in the above, the data signal line driving means,
It is characterized by comprising a plurality of shift registers provided respectively corresponding to the plurality of sample hold switch blocks and the plurality of enable circuits.

Therefore, according to the image display device of the twelfth aspect, it is possible to operate the sample and hold switch block, the enable circuit, and the shift register as a set, respectively, and to easily perform the block transfer of the pixel data. be able to.

According to a thirteenth aspect of the present invention, there is provided the image display device according to the twelfth aspect.
In addition to the features described in the above, the data signal line driving means,
An input signal having a pulse width of 2N (N is a natural number) times one cycle of the reference clock is sequentially shifted and transmitted by N times one cycle of the reference clock, and is transmitted.

Therefore, according to the image display device of the present invention, the high-frequency reference clock can be used as a reference clock for transferring data in the image display device.

According to a fourteenth aspect of the present invention, there is provided the image display device according to the thirteenth aspect.
In addition to the above-mentioned features, in the phase expansion means, the time of data per pixel of the image signal as the serial data is converted to 12 times the reference clock.

Therefore, according to the image display device of the fourteenth aspect, in the image display device having a large number of pixels, not only can the operation be performed at high speed, but also ghost can be prevented.

According to a fifteenth aspect of the present invention, there is provided an image display apparatus according to the fourteenth aspect.
And the duty of the sampling period signal is set to approximately 66.7% or less.

Therefore, according to the image display device of the present invention, it is possible to operate at high speed in an image display device having a large number of pixels without affecting the potential level of the writing pixel. In addition, it is possible to prevent line unevenness and ghost.

According to another aspect of the present invention, there is provided an image display method comprising: a plurality of data signal lines; a plurality of scanning signal lines intersecting the plurality of data signal lines; and a display connected to the plurality of data signal lines and the scanning signal lines. In an image display method for driving an element, an image signal as serial data of an image to be displayed on the image display unit is developed for each fixed pixel based on a dot clock signal, and the time of data per pixel is reduced. Outputting in parallel a plurality of pixel data each having a data length converted to n (n ≧ 2) times one cycle of the dot clock signal; and providing a sample and hold switch activation signal to a sample and hold period of the pixel data. Generating the plurality of pixel data in a sampling period longer than n times one cycle of the dot clock signal. Sampling, and, while sequentially selecting the scanning signal line, supplying the sampled pixel data to the display element connected to the selected scanning signal line via the data signal line. Ending the generation of the sample and hold switch activation signal before the end of the sample and hold period of the captured pixel data.

Therefore, according to the image display method of the present invention, since a plurality of pixel data can be written at a time, the sampling period can be lengthened, and each pixel data can be reliably stored in the designated pixel. And ghosts can be prevented.

According to a seventeenth aspect of the present invention, there is provided an image display method according to the sixteenth aspect.
In addition to the characteristic points described above, the sampling period is adjustable with reference to the dot clock signal.

Therefore, according to the image display method of the present invention, based on the dot clock signal,
It is possible to arbitrarily change at least one of the duty and phase of the first / second enable signal by adjustment at the shipping stage or adjustment by a user.

The image display method according to claim 18 is a method according to claim 17.
, The sampling period is adjusted so that the duty of the sampling period signal is 50% or more.

Therefore, according to the image display method of the eighteenth aspect, it is possible to set the sampling period to such an extent that the pixel data can be sufficiently sampled.

The electronic device according to claim 19 is the electronic device according to claims 1 to 1
An image display device according to any one of Claims 1 to 5, a clock generation circuit that supplies the reference clock to the image display device,
A power supply circuit that supplies power to the image display unit and the clock generation circuit.

Therefore, according to the electronic device of the nineteenth aspect, the present invention can be applied to an electronic device having a high-definition image display device, and can realize an electronic device free from line unevenness and ghost.

According to a twentieth aspect of the present invention, there is provided a projection type display device.
16. An image display device according to any one of claims 15 to 15, further comprising: a projection lens for enlarging and projecting an image on the image display unit.

Therefore, according to the projection type display device of the twentieth aspect, a projection type display device which can be applied to a projection type display device having a high-definition image display device and has no line unevenness or ghost is realized. can do.

[0056]

BEST MODE FOR CARRYING OUT THE INVENTION

<Principle of the Invention> Prior to the present invention, an image display method studied by the present inventors will be described in detail with reference to FIG.

As shown in FIG. 14, as described above, the data length (data time per pixel) of each phase expansion signal which is expanded in six phases and output in parallel, that is, the phase expansion signal line VID1 to VID6
The upper potential has a length of six periods of the reference clock.

When these phase expansion signals are sampled by a sample and hold switch formed by a TFT or the like, for example, sampling period signals S / H (n), S / H (n + 6), and S / H (n) input to the gate of the TFT. S / H
At first, an attempt was made to set the (n + 12) sampling period to the length of four periods of the reference clock as shown in FIG. Here, the dot clock signal CLK is used as the reference clock.

Although the circuit is not specifically shown, according to this image display method, a plurality of pixel data (phase development signals) having a data length of six periods of the dot clock signal CLK after phase development and polarity reversal are provided. Are supplied to the source sides of a plurality of TFTs constituting the sample hold switch. On the other hand, the sampling period signal S / H (n) is input to the gates of the plurality of TFTs forming the plurality of sample-and-hold switches, and the data length of the phase expansion signal is equal to the dot clock signal CLK. In contrast to six periods, the sampling period signal S / H
(N) shows the first and sixth pulses of the dot clock signal CLK, each of which is removed by one cycle.
The period is set to the sampling period.

That is, the gate of each TFT constituting each of the sample-and-hold switches is turned on after the phase development signal is stabilized, and the voltage level of the phase development signal, that is, the pixel data changes. Before this, the gate of the TFT is turned off.
As described above, for example, in an image display device having about VGA pixels, by setting a sampling period for sampling only a data region with a stable potential with respect to the data length in the phase expansion signal,
Only stable write data, unaffected by the pixel data in the holding state during the previous sampling period, could be transmitted to the data signal line.

However, as described above, the image display device has been used in various ways, for example, in a liquid crystal monitor, a notebook personal computer (PC), and a consumer device. Therefore, development from the viewpoint of higher definition and enhanced portability has been promoted. For example,
For high definition, VGA (640 × 480 pixels) to XGA (1024 × 768 pixels) and XGA to SXG
A (1280 x 1024 pixels), from SXGA to UXGA
(1600 × 1200 pixels), the development of image display devices having a large number of pixels is progressing.

With the increase in the number of pixels in such an image display device, the size of the liquid crystal panel has been increasing, and the image unevenness in the image display device has been conspicuous. Improve uniformity,
The above-mentioned image non-uniformity is dealt with by a method of reducing non-uniformity in luminance and non-uniformity in color.

As described above, in the image display device, a plurality of data signal lines are simultaneously selected and driven.
Since the phase expansion method is adopted, it is advantageous in that the response speed is high and the moving image is excellent, but the dot clock signal has a high frequency with the increase in the number of pixels. There is a pressing need to solve the problems of responding to tone adjustment and reducing ghosts.

As shown schematically in FIG. 15, this ghost is generated when an arrow 1 is displayed on the screen 2, for example.
A ghost 3 indicated by a broken line occurs at a stage subsequent to the scanning direction of the arrow 1.

For the reasons described above, the inventor of the present application has examined ways to cope with an increase in the number of pixels of the image display device. That is, the number of scanning signal lines and the number of data signal lines also increase with an increase in the number of pixels. In particular, in order to cope with an increase in the number of pixels in the horizontal direction, the number of unit shift registers included in the X shift register and its increase In consideration of the shift speed, in order to improve the responsiveness of the sample-and-hold switch while preventing the unit shift register from increasing significantly, the inventor of the present application examined 12-phase expansion of image data.

In this case, the data signal lines are shifted by 12 lines, and each pixel data is simultaneously transferred to each pixel connected to the same scanning signal line and connected to 12 adjacent data signal lines. In writing, block transfer at the time of writing each pixel data to each pixel is required. Then, by the block transfer of the pixel data, the breaks and boundaries of each pixel by 12 data signal lines can be visually checked. For example, at the boundaries between the blocks, so-called gradations, thin lines, etc. It was confirmed that line unevenness appeared to exist.

The cause of the line unevenness is considered as follows. That is, in a plurality of data signal lines that do not exist at the boundary between the blocks, the data write operation is performed simultaneously on each of the adjacent data signal lines. On the other hand, in the data signal line existing at the boundary between the blocks, the write timing of the data to the adjacent data signal line is different. It is considered that it is.

That is, in the pixel at the boundary between the transfer blocks, for example, in the positive drive, the voltage to write black is a halfway voltage due to the capacitive coupling, resulting in a gray pattern. As a result, the above-mentioned problem has occurred.

First Embodiment (Schematic Configuration of Device) FIG. 2 shows an outline of a driving IC of a liquid crystal display device according to a first embodiment. As shown in the figure, this driving IC mainly includes a serial / parallel conversion circuit 32, a polarity inversion circuit 34, a digital / analog conversion circuit 35, an address set controller 37, and a timing generator 20. Although not described, the driving IC includes not only the above-mentioned respective circuits and external signal input terminals, but also digital / analog power terminals AVDD, DVDD, and GND. .

The function of each circuit will be described below with reference to FIG.

The address set controller 37 comprises:
Microcomputer interface terminal ADDSET, MCCO
A circuit for fetching an instruction from an external microcomputer via NT, decoding the instruction, and setting activation of the timing generator 20.

The timing generator 20 is activated by receiving a signal output from the address set controller 37, and outputs a horizontal scanning signal HSYNC via a horizontal scanning signal input terminal and a vertical scanning signal HSYNC via a vertical scanning signal input terminal. The scanning signal VSYNC is taken in the dot clock signal CLK via the clock input terminal.
By the way, in the present embodiment, the dot clock signal CLK is used as the reference clock.

The timing generator 20
Includes a variable circuit for varying the duty and phase, sets the duty and timing of each signal based on the various signals, and sets a shift register start signal D
X, a clock signal CLX, and first / second enable signals ENB1 and ENB2 are generated and supplied to a serial / parallel conversion circuit 37, a polarity inversion circuit 34, and a digital / analog conversion circuit 35 to generate an image signal, a phase development signal, and a polarity. The timing at which pixel data, which is an inverted phase expansion signal, is taken into each of the circuits is defined. Then, the driving I / O is output via each of the signal output terminals.
Each of the signals generated at C is output to a liquid crystal panel block formed on a liquid crystal substrate.

The serial / parallel conversion circuit 32 is activated based on the first timing signal generated by the timing generator 20, and converts the image signal VD into
The image signal is input through the input terminal for the image signal, and the image signal V
D is, for example, a circuit that expands to 12 phases.

The polarity inversion circuit 34 is activated based on the second timing signal generated by the timing generator 20, and converts the 12-phase expanded signal generated by the serial / parallel conversion circuit 32. This is a circuit that generates pixel data by taking in and converting it to a positive or negative voltage in accordance with the polarity of each pixel. The operation of the serial-parallel conversion circuit 32 and the polarity inversion circuit 34 will be described later in detail with reference to FIG.

The digital-to-analog conversion circuit 35 includes:
The third signal generated by the timing generator 20
The digital pixel data which is started based on the timing signal of (1) and is subjected to voltage conversion by the polarity inverting circuit 34 so as to match the polarity of each pixel, and is generated in 12-phase development, is converted into analog pixel data. This is a circuit for conversion.
The output signals from the digital-to-analog conversion circuit are output from the driving IC to the liquid crystal panel block via output terminals AOUT1 to AOUT12.

Next, the overall configuration of the liquid crystal display device according to the first embodiment will be described.

FIG. 1 shows an overall outline of the liquid crystal display device according to the first embodiment. The overall schematic diagram of the liquid crystal display device of FIG. 1 also includes the timing generator 20, the serial / parallel conversion circuit 32, and the polarity inversion circuit 34 shown in FIG. Are omitted for simplicity, and the address set controller 37 is similarly omitted.

As shown in FIG. 1, this liquid crystal display device
This is a small liquid crystal display device used as a light valve of an electronic device such as a liquid crystal projector.
0, a timing generator 20, and a data processing block 30.

The description of the timing generator 20 is omitted because it has been described above. However, the data processing circuit block 30 includes the serial-parallel conversion circuit 32 described above,
The polarity inversion circuit 34 is included. Here, in the present embodiment, description will be made assuming that the data processing circuit 30 expands the image signal VD into 12 phases.

The serial / parallel conversion circuit 32 includes:
As described above, the digital image signal VD is input, and the image signal VD is expanded into 12 phases to generate and output a 12-phase developed signal. When the liquid crystal panel 100 in the liquid crystal panel block 10 is a color liquid crystal panel having three primary color filters, three image signals of R, G, and B are input to the serial / parallel conversion circuit 32. From these three image signals VD, for example, 1
A phase expansion signal for two pixels can be generated. This one
The two-phase expansion method will be described later.

The polarity inversion circuit 34 amplifies the phase expansion signals corresponding to the 12 pixels on the 12 data signal lines to a voltage necessary for driving the liquid crystal panel block, as described above. Polarity inversion. Note that the positions of the polarity inversion circuit 34 and the serial / parallel conversion circuit 32 shown in FIGS. 1 and 2 can be reversed, and after the polarity of the image signal VD is inverted by the polarity inversion circuit 34, the serial Parallel conversion circuit 32
It is also possible to develop phases.

Data processing circuit block 3 of this embodiment
Since the output line of 0 carries out the 12-phase expansion, as shown in FIG.
1 to VID12.

The liquid crystal panel block 10 includes the liquid crystal panel 1
00, the scanning side drive circuit 102, and the X shift register 1
04 and the enable circuit 105 are provided on the same circuit board.

On the liquid crystal panel 100, for example, a plurality of scanning signal lines 110 extending in the row direction of FIG.
For example, a plurality of data signal lines 1 extending along the column direction
12 are formed. In the present embodiment, X
Since it is intended for an image display device having a large number of pixels, such as a GA, the total number of scanning signal lines 110 is 768,
The description is made on the assumption that the total number of data signal lines 112 is 1024.

As shown in FIG. 13, near the intersection of the scanning signal line 110 and the data signal line 112, as a switching element, for example, a TFT 1
14 and the liquid crystal cell 116 are connected in series to form a display element, which forms a pixel. Here, a plurality of the data signal lines 112 are provided, and some of them include several dummy data signal lines.

In the present embodiment, the switching element is, for example, a three-terminal switching element, and is constituted by, for example, a TFT. Not limited to this, two-terminal type switching element such as MIM (metal-insulating layer-metal)
An element, a MIS (metal-insulating layer-semiconductor layer) element, or the like can be used.

Note that the liquid crystal panel 100 of the present embodiment
The present invention is not limited to an active matrix type liquid crystal display panel using two-terminal or three-terminal type switching elements, but may be other various liquid crystal panels such as a simple matrix type liquid crystal display panel.

The scanning side driving circuit 102 is, for example, 769
A scanning signal in which a selection period for sequentially selecting one scanning signal line 110 from among the scanning signal lines 110a, 110b,... Is output.

The X shift register 104 uses the timing generator 20 to output the dot clock signal CLK
The clock signal CLX and the shift register start signal DX formed with four periods as one period and a duty of 50% are taken in. A circuit for generating sampling period signals PS10 and PS870 for setting a sampling period for each data transfer block, that is, for each sampling period of the twelve data signal lines 112, via a plurality of enable circuits 105 described later. It is. The X shift register 104 includes a plurality of enable circuits 10 described later.
5, unit shift registers (not shown) provided corresponding to the output signals P1 to P1 of the unit shift registers.
P87 is input to each of the enable circuits provided corresponding to the unit shift register.

The X shift register 104
12 phase expansion signal lines VID1 to VID12, which are output lines of the data processing circuit block 30, and the liquid crystal panel 1
00, the data signal lines 112a, 112b,.
.. The sampling period signals PS10 to P for driving the liquid crystal panel 100 in a dot-sequential manner with respect to each of the plurality of sample-and-hold switches 106 disposed between.
A reference signal for generating S870 is generated and output.

A plurality of sample hold switches 106 are provided corresponding to the data signal lines 112, and are formed by switching elements such as TFTs, for example. In order to perform the 12-phase expansion, the gates of the 12 sample-and-hold switches are connected in common (FIG. 3), and the sample-and-hold switch blocks SHW1 to SHW87 are configured by being controlled by the sampling period signal. ing. In other words, for example, the present embodiment is directed to XGA, so that 1024 data signal lines 112
In order to perform phase expansion driving, 87 sample-and-hold switch blocks SHW1, SHW2,..., SHW8
7 are provided. Further, in each of the sample-and-hold switches 106, each source side is connected to the first to twelfth phase expansion signal lines VID1 to VID12, respectively.
, And each drain side is connected to a data signal line.

The enable circuit 105 is provided corresponding to the plurality of sample-and-hold switch blocks SHW1 to SHW87, and controls the sampling switch 106 for sampling the pixel data of the 12-phase expanded to each pixel. Is a circuit for generating a sampling period signal, that is, setting a sampling period. Therefore, for example, in the XGA as in the present embodiment, 1024 data signal lines 112 are connected to one.
In order to perform two-phase expansion driving, the same number as the sample-and-hold switch blocks SHW1 to SHW87, that is, 8
Seven enable circuits EN1, EN2,..., EN
87 are provided respectively.

The input line of the enable circuit 105 is connected to one of the output line from the X shift register 104 and one of the first and second enable signal lines 11 and 12, and One of the first and second enable signals ENB1 and ENB2 transmitted by the enable signal lines 11 and 12 is input. The output of the sampling period signal from each of the enable circuits 105 controls the voltage applied to each gate of the sample and hold switch 106 to control the on / off of the sample and hold switch.

That is, in the enable circuit 105, as shown in FIG. 1, the odd-numbered enable circuits EN1, EN3,.
And enable circuits EN2 and EN provided in even-numbered
, ENn,..., EN86 (n = even number), the first / second enable signal line 1
1 and 12 are different.

That is, in the odd-numbered enable circuits EN1,..., EN87, the input side is connected to the first enable signal line 11.
Therefore, the output signals P1, P3,..., P87 of the unit shift registers in the X shift register 104 and the first enable signal ENB1 are input to the odd-numbered enable circuits. .

The input side of the even-numbered enable circuits EN2,..., ENn,..., EN87 is connected to the second enable signal line 12. Therefore, the output signals P2,..., Pn, of the unit shift registers in the X shift register 104 are provided to the even-numbered enable circuits.
, P86 and the second enable signal ENB2
Is entered.

Next, a method of controlling the sample and hold switch block by the enable circuit 105 will be described in detail. In the present embodiment, 87 enable circuits 105 are provided as described above, and the sample hold switches are turned on for each sample hold switch block, and block transfer of pixel data to each pixel is performed. Is what you do.

FIG. 3 shows the structure of the sample hold switch 106.
And a circuit configuration of the enable circuit 105. still,
FIG. 3 shows only the first enable circuit EN1 and the first sample and hold switch block SHW1 as an example. As described above, the sample and hold switch blocks SHW1 to SHW87 have the same circuit configuration and the same phase development. The connection with the signal lines VID1 to VID12 is made.

First, the first sample and hold switch block SHW1 shown in FIG. 3 will be described.

The first sample hold switch block SHW1 is composed of twelve sample hold switches Q1 to Q12 formed by TFTs, and the gates of the sample hold switches Q1 to Q12 are commonly connected. .

The first sampling period signal PS10, which is the output signal of the first enable circuit EN1, is supplied to the gates of the sample-and-hold switches Q1 to Q12 which are connected in common. ON / OFF of the switches Q1 to Q12 is controlled. Further, the first sample and hold switch Q1
Has a first phase expansion signal line VID1 on the source side, a second phase expansion signal line VID2 on the source side of the second sample hold Q2, and a source side of the third sample hold switch Q3. The third phase expansion signal line VID3 is connected, and the fourth to first
The phase expansion signal lines VID4 to VID12 are connected to the sample hold switches Q4 to Q12, respectively.

Therefore, by turning on each sample hold switch Q1 to Q12 forming the first sample hold switch block SHW1,
Pixel data corresponding to each pixel is simultaneously written to the data signal lines 110a to 110l.

Next, the first enable circuit EN1 shown in FIG. 3 will be described.

The enable circuits EN1 to EN87 are
Each of the odd number of inverters is constituted by a NAND circuit connected to the output stage. That is, for example, as shown in FIG. 3, the first enable circuit EN1 is configured by a first NAND circuit NAND1 in which a first inverter circuit INV1 is connected to an output stage.
Here, FIG. 3 shows an example in which one inverter circuit is provided. However, the present invention is not limited to this, and an odd number of inverter circuits may be provided in consideration of signal propagation speed and delay. It is possible. In addition, any circuit that performs the same logic output can be used without limitation, and when the sample-and-hold switch 106 is formed of a p-type transistor, an even number of inverter circuits are provided. You can do it.

Then, the first NAND circuit NAND1
A first enable signal line 11 for transmitting the first enable signal ENB1 and a second enable signal line 12 for transmitting the second enable signal ENB2 are formed between the first enable signal ENB1 and the X shift register 104. Have been.

As described above, one input node of the plurality of NAND circuits NAND1 to NAND87 is connected to the output line of the X shift register 104, and the other input node is connected to the first / second enable signal. It is fixed to one of the lines 11 and 12.
That is, in the first enable circuit of FIG. 3, the input line of the odd-numbered first enable circuit EN1 is connected to the first enable signal line 11, and one of the first enable circuits EN1 Are supplied with a first enable signal ENB1.

(Regarding Operation of Twelve-Phase Expansion) Next, FIG.
With reference to FIG. 4 and FIG. 4, the operation of the serial-parallel conversion circuit 32 in the data processing circuit block 30 for n-phase expansion, for example, 12-phase expansion will be described.

The digital image signal VD input to the data processing circuit block 30 is a digital signal in which data corresponding to each pixel of the liquid crystal panel 100 is serially arranged.

The serial / parallel conversion circuit 32 for performing the 12-phase expansion expands the image signal VD into a phase expansion signal having a data length which is 12 times as long as one cycle of the reference clock, for example, the dot clock signal CLK. In the phase development signal lines VID1 to VID12, they are converted into parallel pixel data. For example, in the first phase development signal output to the first phase development signal line VID1, the data of the thirteenth and twenty-fifth pixels has a data length that is 12 times as long as one cycle of the dot clock signal CLK. Expanded to pixel data. Similarly, data of 12 pixels ahead is sequentially expanded to the data length.

Similarly, the second phase expansion signal output to the second phase expansion signal line VID2 is the second, 14th, 26th
Data such as pixel data is expanded into pixel data having the above data length and output. In the present embodiment, in this developing operation, the digital-to-analog conversion circuit 35 shown in FIG. 2 is used to finally convert the pixel data into analog pixel data.

In the first embodiment, the first to twelfth pixel data output from the data processing circuit 30 to the first to twelfth phase development signal lines VID1 to VID12 are shown in FIG. Output in parallel as

(Regarding Configuration of Data Sampling) Next, details of the operations of the sample hold switch 106, the enable circuit 105, and the X shift register 104, which are characteristic configurations of the present embodiment, will be described with reference to the circuit diagrams of FIGS. This will be described with reference to the timing charts of FIGS.

As described above, X shift register 104 includes a unit shift register provided corresponding to enable circuits EN1 to EN87. That is,
In the XGA, 87 unit shift registers are provided, adjacent unit shift registers are connected to each other, and transmission and reception of a clock signal CLX are performed for each unit shift register. That is, the unit shift register is a circuit including a latch circuit, and a driving IC is provided at the end unit shift register at which shifting is started.
The clock signal CLX and the shift register start signal DX supplied from are supplied.

The shift register start signal DX is a signal for instructing the start of the X shift register 104, and the clock signal CLX has a duty of 50% and divides 24 periods of the dot clock signal CLK by one.
This is a clock signal having a period. Also, the unit shift register counts time by latching the clock signal CLX for one cycle, during which a unit continuously generates a high-level signal and outputs the signal to the corresponding enable circuit 105. It is.

That is, for example, when shifting from right to left in the X shift register 104 of FIG. 1, the first unit shift register is supplied with the shift register start signal DX and the first unit shift register is supplied with the first register. The unit shift register is activated and takes in the clock signal CLX. Then, the clock signal CLX is latched for one cycle by the first shift register to count time, and a high-level output signal P1 is generated.
The high-level output signal P1 is continuously supplied to the first enable circuit EN1.

After the count of the clock signal CLX is completed, the second unit shift register at the next stage is activated. Similarly, the clock signal CLX is latched by the second unit shift register, the time for one cycle is similarly counted, and a high-level output signal P2 is generated. Is continuously supplied with a high-level signal P2.

Similarly, the latch of the clock signal CLX and the latch and count of the clock signal CLX for one cycle are repeated until the clock signal CLX is transmitted to the 87th unit shift register.
Each time the high-level output signals P1 to P87 are sequentially shifted from the X shift register 104 from the unit enable circuit EN1 to the 87th unit enable circuit EN87.

The enable circuits EN1 to EN1
Reference numeral 87 denotes the X shift register 10 at regular intervals.
4, the high-level output signals P1 to P8
7 and the first or second enable signal ENB1, ENB
B2, the high-level sampling period signal PS
10 to PS870, and supplies these signals to the sample and hold switch blocks SHW1 to SHW87, respectively.

That is, for example, using the first enable circuit EN1 shown in FIG. 3 as an example, a high-level output signal P1 is input from the X shift register 104 to the first enable circuit EN1. At the same time, a first enable signal ENB1 is supplied to the first enable circuit EN1. That is, when the output signal P1 and the first enable signal ENB1 which are both at the high level are input to the first NAND circuit NAND1, the first NAND circuit NAND1 becomes
A low level signal is formed.

After that, the first inverter circuit IN of the next stage
V1 receives this low-level signal, and outputs a high-level first sampling period signal PS10 as an output of the first enable circuit EN1, which is supplied to the first sample-and-hold switch block SHW1.

Therefore, a high-level first sampling period signal PS10 is supplied to each gate of the sample and hold switches Q1 to Q12 constituting the first sample and hold switch block SHW1. Therefore, the sample hold switches Q1 to Q12
Are turned on all at once, and the source side phase expansion signal line V in the sample hold switches Q1 to Q12 is turned on.
ID1 to VID12 are electrically connected to the data signal lines 112a to 112l on the drain side.

As a result, pixel data is collectively written to each pixel via the sampling and holding switches Q1 to Q12 and the data signal lines 112a to 112l.

(Setting of Data Sampling Period) Hereinafter, a method of setting a sample and hold period of pixel data in the above-described liquid crystal display device of the present invention will be described.

The sampling period signals PS10 to PS supplied to the gates of the sample and hold switches SHW1 to SHW87 are used for the sample and hold period.
870 is set by the supply time.

That is, the driving IC generates the clock signal CLX, the X shift register start signal DX, and the like on the basis of the reference clock. Therefore, the generation and generation of this sampling period signal on the basis of the frequency of the dot clock signal CLK are performed. The sampling period can be set. In addition, this setting can be set by an inspection process before shipping the image display device or by the user.

For example, in the first sample hold switch block SHW1, as shown in FIG. 4, each pixel data having a data length of 12 periods of the dot clock signal CLK is supplied to each source line of the sample hold switches Q1 to Q12. Supplied to

On the other hand, the gates of the sample-and-hold switches Q1 to Q12 forming the first sample-and-hold switch block SHW1 are connected to the first NAND circuit NAND1 and the first inverter circuit INV1 as described above.
The first sampling period signal PS10 formed by
Is entered. This first sampling period signal P
In S10, while the data length of the phase-expanded pixel data is 12 periods of the dot clock signal CLK, for example, three periods are added before that and one period is removed after that. The sampling period is set to 14 cycles. Here, although not particularly described, the sampling periods in the first to 87th sampling period signals are all the same.

FIG. 5 is a schematic diagram for describing the writing of pixel data for each sample-and-hold switch block. The writing of pixel data will be described with reference to the timing chart of FIG. Here, as an example, the first sample hold switch block SHW
1 on the data signal line SA1 connected to the pixel A11
The case where pixel data is written to the pixel B11 on the data signal line SB1 connected to the second sample-and-hold switch block SHW2 during the holding of the pixel data in. The pixel A11 and the pixel B11 are connected to a common scanning signal line H1.

In the image display device, pixel data is written for all pixels connected to the same scanning signal line during the same horizontal scanning period. However, in the image display device of this embodiment, 12-phase development is performed. Therefore, block writing is performed for each of the sample and hold switches.

Before writing pixel data to the pixel B11, the first sample and hold switch block S
The pixel data AD is supplied to the pixel A11 on the data signal line SA1 via the HW1.

Then, as shown in FIG. 4, during the period in which the first sampling period signal PS10 for turning on the first sample hold switch block SHW1 is supplied, the second sampling period signal PS2 is turned on.
0 is the second sample-and-hold switch block SH
W2. That is, the data signal line SA11 connected to the pixel A11 is connected to the first phase expansion signal line VID1 via the first sample hold switch block SHW1, and similarly, the data signal line connected to the pixel B11 is connected. The line SB11 is also connected to the first phase expansion signal line VID1 via the second sample hold switch block SHW2.

Therefore, during the three-dot clock CLK period before the phase-expanded pixel data BD to be written to the pixel B11 is supplied, each source line of each sample-and-hold switch constituting the second sample-and-hold switch block SHW2 is used. Is supplied with the pixel data AD corresponding to the pixel A11, similarly to the source lines of the sample hold switches constituting the first sample hold switch SHW1.

Therefore, a high-level second sampling period signal PS20 is supplied to each gate of each sample-hold switch constituting the second sample-hold switch block SHW2, and the second sample-hold switch block SHW2 is turned on. By being turned on, secondly, the pixel data AD corresponding to the pixel A11 passes through the sample-and-hold switch block SHW2 to the pixel B1 via the data signal line SB1.
1 is supplied.

For example, the pixel A1 located at the intersection of the scanning signal line H1 and the data signal line SA1
1, when the positive drive black is displayed (11 V), the first sample hold switch SHW
Assume that the second sample-and-hold switch block SHW2 is turned on as described above in a state where the sample and hold of the pixel is being performed at 1.

As a result, the write data (11 V) to the pixel A11 is transferred to the data signal line SB via the second sample hold switch SHW2.
1 to the pixel B11 connected to the scanning signal line H1 and the data signal line SB1,
The charge of the liquid crystal cell in the pixel B11 is started. This allows the dot clock signal C
During three periods of LK, the potential on the data signal line SB1 is charged toward the black display voltage on the positive polarity side.
In other words, at this time, the data signal line is precharged before writing the normal pixel data.

After the period of the three periods of the dot clock signal CLK, the supply of the normal pixel data BD to the data signal line SB1 and the pixel B11 is started, whereby the second sample-and-hold switch block is started. The phase-developed pixel data BD supplied to the source of SHW2 is supplied. This pixel data is stored in the pixel A1.
The pixel data BD has the same polarity as the pixel data AD, and a black display voltage (11 V) or a white display voltage (9 V) is supplied as the pixel data BD, and one of these voltages is written to the pixel B11. It is.

That is, since it takes time to raise the potential on the data signal line SB1, the pixel data already appearing on the phase development signal line and being supplied to the adjacent sample and hold switch block is replaced with the dummy pixel data. By supplying only during the very first period of the sampling period, the sampling period in the image display device can be set longer, so that accurate sampling of pixel data can be performed.

In this embodiment, only the pixel A11 connected to the data signal line SA1 and the pixel B11 connected to the data signal line SB1 have been described as an example. As long as the sample-and-hold switches are connected to the same sample-and-hold switch block, the ON timings of the twelve sample-and-hold switches Q1 to Q12 are substantially the same. Therefore, each of the 12 samples connected to the same first / second sample / hold switch block SHW1 and SHW2
For each of the data signal lines, writing of pixel data to each of the pixels connected thereto is simultaneously performed for each sample and hold switch block.

Further, for each pixel on the data signal line connected to the same phase expansion signal line, the pixel data in the previous sampling period on the phase expansion signal line is replaced with the dummy pixel in the current pixel data writing. By taking in the data, the sampling period of each pixel data can be lengthened.

Therefore, although the description is omitted, at the same time, for example, in the beginning of the sampling period of the pixel data to the pixel B12, the pixel data corresponding to the pixel A12 is used as the dummy pixel data, and the pixel data to the pixel B112 is used. Initially to the data sampling period, the pixel A112
Can be used as dummy pixel data.

Incidentally, in the image display device of the present invention, the first sample and hold switch block SH
The switching from the ON state to the OFF state of W1 is performed during the sample and hold period of the pixel data to each data signal line 112 connected to the second sample and hold switch block.

That is, since the sampling operation of the pixel data has been completed before the next sample hold switch block is turned on and during the sampling and holding period of the normal pixel data, the next sampling data is not affected. It becomes possible. In other words, before affecting the next pixel data, the phase expansion signal line VID
TFTs constituting the sample and hold switch 106 before the pixel data on 1 to VID 12 change.
Is to be turned off.

Therefore, by setting such a sampling period, even if the sample hold switch 10
When the TFT 6 is formed of a TFT, even if the switching speed of the TFT is limited, the liquid crystal display has
A liquid crystal display without ghost and shadowing can be performed without affecting adjacent pixel data, in other words.

The aforementioned X shift register 104 shifts from the left to the right (the 87th unit shift register → the first unit shift register) or shifts from the right to the left (the first unit shift register). Any of the shift methods can be adopted for the 87th unit shift register). Hereinafter, a method of setting the sampling period of the pixel data of the image display device of the present invention in each case will be described with reference to FIGS.

FIG. 6 shows a case where the shift direction of the X shift register is set from the left to the right (the 87th unit shift register → the first unit shift register), and is input to each sample hold switch. 3 shows a relationship among a sampling period signal, a clock signal, and an X shift register output signal.

When the shift register start signal DX is supplied to the X shift register 104, the X shift register 104 is started, and the leftmost 87th unit shift register in the X shift register 104 captures the clock signal CLX. , One of the clock signals CLX
During the period, the output signal P87 is generated and supplied to the 87th enable circuit EN87.

As described above, the 87th enable circuit EN87 is supplied with the first enable signal E having a 58.3% duty through the first enable signal line 11.
NB1 is supplied. As described above, since the 87th NAND circuit NAND87 is provided at the input stage of the 87th enable circuit EN87, both the first enable signal ENB1 and the output signal P87 are at a high level. As a result, a high-level 87th sampling period signal PS870 is generated via the 87th inverter circuit INV87 provided at the output stage of the 87th enable circuit EN87.

After counting one cycle of the clock signal CLX, the unit shift register is shifted rightward in the X shift register 104, so that the clock signal CLX is shifted by the 86th unit shift register.
Is held for one cycle, and during one cycle of the clock signal CLX, the output signal P87 is generated and supplied to the 87th enable circuit EN87. 86th enable circuit EN8
6 through a second enable signal line 12, a second enable signal ENB2 having a duty of 58.3%.
Is supplied. As described above, the input stage of the 86th enable circuit EN86 is connected to the 86th NAND circuit NAN.
Since the D86 is provided, both the second enable signal ENB2 and the output signal P86 are set to a high level, so that the 86th enable circuit EN8 is provided.
86th inverter circuit INV provided in the 6th output stage
A high-level 86th sampling period signal PS860 is generated via 86.

Similarly, the X shift register 104
, The output signals are generated from P86 to P1 while shifting sequentially from one unit register at the next stage of the unit shift register to the unit shift register at the rightmost stage for each cycle of the clock signal CLX, and the corresponding enable circuit The signals are sequentially supplied to EN86 to EN1.

At this time, sampling period signals PS870 to PS10 are generated in the same manner as in the operation of the 87th / 86th enable circuit described above, and are sequentially generated for each cycle of clock signal CLX. As a result, the sample hold switch block SHW8
, SHW86,..., SHW1, high-level signals are sequentially supplied to the gates of the sample-and-hold switches with a one-cycle delay, and the pixel data are sequentially transferred in blocks, and the pixel data to each pixel are sequentially transmitted. Is written.

FIG. 7 shows an input to each sample and hold switch when the shift direction of the X shift register 104 is set from right to left (first unit shift register → 87th unit shift register). The relationship between the sampling period signal, the clock signal, and the output signal of the X shift register is shown.

The shift register start signal DX is supplied to the X shift register 104 to start the X shift register 104, and the rightmost first unit shift register in the X shift register 104 captures the clock signal CLX. , Generates the output signal P1 during one cycle of the clock signal CLX, and continuously supplies the output signal P1 to the first enable circuit EN1.

As described above, the first enable circuit E
N1 via the first enable signal line 11
First enable signal ENB having a duty of 58.3%
1 is supplied. As described above, the first NAND circuit NAND1 is connected to the input stage of the first enable circuit EN1.
Is provided, the first enable signal EN
When both B1 and the output signal P1 are set to the high level, the first sampling of the high level is performed via the first inverter circuit INV1 provided at the output stage of the first first enable circuit EN1. A period signal PS10 is generated.

After counting for one cycle of the clock signal CLX, the unit shift register is shifted leftward in the X shift register 104,
The clock signal CLX is output from the second unit shift register.
Is held for one cycle, and the output signal P2 is generated for one cycle of the clock signal CLX.
Supply to N2. The first enable circuit EN2 is supplied with a second enable signal ENB2 having a duty of 58.3% via the second enable signal line 12. As described above, the second enable circuit EN2
Is provided with a second NAND circuit NAND2, so that both the second enable signal ENB2 and the output signal P2 are set to a high level, whereby the second second enable circuit A high-level second sampling period signal PS20 is generated via a second inverter circuit INV2 provided at the output stage of EN2.

Similarly, the X shift register 104
, The output signals are generated from P3 to P87 while shifting sequentially from one unit register at the next stage of the unit shift register to the leftmost unit shift register at each cycle of the clock signal CLX, and the corresponding enable circuit is generated. EN3 to EN87 are sequentially supplied.

At this time, sampling period signals PS30 to PS870 are generated in the same manner as the operation of the first / second enable circuits described above, and are sequentially generated for each cycle of clock signal CLX. As a result, the sample and hold switch blocks SHW1, SW
A high-level signal is sequentially supplied to each gate of the sample-and-hold switches constituting the HW2,..., SHW87 with a delay of one cycle, and pixel data is sequentially transferred in blocks, and writing of each pixel data to each pixel is performed. Done.

The image display device according to the present embodiment has been described above. In the image display device according to the present embodiment, the sampling period during which the sample hold switch is turned on is set to 14 periods of the dot clock signal. However, it can be set to any of 13 to 16 periods. In this case, the first / second enable signal EN
The duty of both B1 and ENB2 is increased from 54.2% to 6
6.7% (corresponding to 13 to 16 periods of the dot clock signal).

In the present embodiment, the twelve phase development signal lines VID1 to VID in the image display device are used.
The delay of the phase expansion signal due to the wiring resistance and parasitic capacitance of D2, and the first / second enable signal lines 11,
Twelve wiring resistances and parasitic capacitances, characteristics and parasitic capacitances of the first to 87th enable circuits EN1 to EN87, and characteristics of the sample and hold switch blocks SHW1 to SHW87 and sample and hold switch blocks SHW1 to SHW87 are formed. The description has been given ignoring the delay of the on / off timing of the sample hold switches Q1 to Q12. However, in an actual image display device, such a delay of the phase expansion signal and a delay of the ON / OFF timing of the sample / hold switches Q1 to Q12 always occur, which may cause a ghost.

[0160] In this case, the first
By adjusting the on / off timing of the sample / hold switches Q1 to Q12 with respect to the phase of the second enable signals ENB1 and ENB2, and consequently, the occurrence of a ghost can be prevented.

Although the phase expansion has been described as the 12-phase expansion, the invention is not limited to this, and the n-phase expansion (n ≧ 2) can be performed according to the characteristics of each image display device. Further, in the present embodiment, the sampling period signal is formed before the last three dot clocks of the previous sampling period, and the sampling period signal is generated one cycle before one dot clock at which pixel data sampling ends. Although the supply is stopped, the present invention is not limited to this, and various methods can be adopted. That is, in the previous sampling period (on the scanning signal line n), the supply of the sampling period signal is started at such a point that the writing of the pixel data in the current sampling period (on the scanning signal line n + 1) is not affected, The supply of the sampling period signal may be stopped at a time when the writing of the pixel data is not affected in the next sampling period (on the scanning signal line n + 2).

In this embodiment, the explanation has been given on the assumption that the TFT constituting the sample hold switch is an n-type transistor.
Can be formed by a p-type transistor. In this case, when the sample-hold switch is turned on, a low-level voltage is applied, and the configuration of an enable circuit can be easily realized.

<Embodiment 2> An electronic apparatus using the image display device of Embodiment 1 described above includes a display information output source 1000, a display information processing circuit 1002 shown in FIG.
Display driving circuit 1004, display panel 1 such as a liquid crystal panel
006, clock generation circuit 1008 and power supply circuit 10
10. The display information output source 1000
A clock generation circuit 10 including a memory such as a ROM and a RAM, a tuning circuit for tuning and outputting a television signal, and the like, and corresponding to the timing generator 20 described above.
Based on the clock from 08, display information such as a video signal is output. The display information processing circuit 1002 corresponds to the data processing circuit block 30 of each of the above embodiments,
The display information is processed and output based on the clock from the clock generation circuit 1008. This display information processing circuit 10
02 can include a gamma correction circuit, a clamp circuit, and the like in addition to the above-described amplification / polarity inversion circuit, phase expansion circuit, rotation circuit, and the like. The drive circuit 1004 includes the above-described scan-side drive circuit 102, X shift register 104 and precharge drive circuit 160, or X shift register 104, and drives the liquid crystal panel 1006 for display. The power supply circuit 1010 supplies power to each of the above-described circuits.

As the electronic apparatus having such a configuration, a liquid crystal projector shown in FIG. 9, a personal computer (PC) and an engineering workstation (EWS) compatible with multimedia shown in FIG. 10, a pager shown in FIG. , A word processor, a television, a viewfinder type or a monitor direct-view type video tape recorder, an electronic organizer, an electronic desk calculator, a car navigation device, a POS terminal, and a device having a touch panel.

The liquid crystal projector shown in FIG. 9 is a projection type projector using a transmission type liquid crystal panel as a light valve, and uses, for example, a three-plate prism type optical system. 9, in a projector 1100, a projection light emitted from a lamp unit 1102 of a white light source is provided inside a light guide 1104 by a plurality of mirrors 1106.
And three active matrix type liquid crystal panels 11 which are divided into three primary colors of R, G, and B by two dichroic mirrors 1108 and display images of respective colors.
Light modulated by 10R, 1110G, and 1110B is incident on dichroic prism 1112 from three directions. In the dichroic prism 1112, the red R and blue B lights are bent by 90 °, and the green G light goes straight, so that the images of the respective colors are combined, and a color image is projected on a screen or the like through the projection lens 1114.

The personal computer 12 shown in FIG.
00 is a main body 1204 having a keyboard 1202
And a liquid crystal display screen 1206.

A pager 1300 shown in FIG. 11 includes a liquid crystal display substrate 1304, a light guide 1306 provided with a backlight 1306a, a circuit board 1308, and first and second shield plates 1310, 13 in a metal frame 1302.
12, two elastic conductors 1314 and 1316, and a film carrier tape 1318. The two elastic conductors 1314 and 1316 and the film carrier tape 1318 are connected to the liquid crystal display substrate 1304 and the circuit board 130.
8 is connected.

Here, the liquid crystal display substrate 1304 is one in which liquid crystal is sealed between two transparent substrates 1304a and 1304b, thereby constituting at least a liquid crystal display panel. The drive circuit 100 shown in FIG.
4, or in addition to this, the display information processing circuit 1002 can be formed. Circuits not mounted on the liquid crystal display substrate 1304 are external circuits of the liquid crystal display substrate.

FIG. 11 shows the configuration of the pager, so a circuit board 1308 is required. However, when a liquid crystal display device is used as one component for an electronic device, and a display driving circuit or the like is mounted on a transparent substrate, the minimum unit of the liquid crystal display device is a liquid crystal display substrate 130.
4. Alternatively, a structure in which the liquid crystal display substrate 1304 is fixed to a metal frame 1302 serving as a housing can be used as a liquid crystal display device, which is a component for electronic devices. Further, a liquid crystal display device can be configured by incorporating a light guide 1306 provided with a backlight 1306a. Instead of these, as shown in FIG. 12, two transparent substrates 1 constituting a liquid crystal display substrate 1304 are formed.
TCP (Tape Carrier Pack) in which an IC chip 1324 is mounted on a polyimide tape 1322 on which a metal conductive film is formed on one of 304a and 1304b.
age) 1320, and can be used as a liquid crystal display device, which is a component for electronic equipment.

The present invention is not limited to the above embodiment, and various modifications can be made within the scope of the present invention. For example, the present invention is not limited to being applied to the driving of the above-described various liquid crystal panels, but is also applicable to an image display device using an electroluminescence, a plasma display device, a CRT, or the like. Further, the data length of the phase expansion number signal and the length of the sampling period corresponding thereto, or the set position and length of the precharge period, can be variously modified other than the above embodiment.

[0171]

[Brief description of the drawings]

FIG. 1 is a schematic diagram of an active matrix liquid crystal display device to which the present invention is applied.

FIG. 2 is an overall schematic diagram of a liquid crystal drive circuit to which the present invention is applied.

FIG. 3 is a schematic diagram of an enable circuit and a sample and hold switch block according to the present invention.

FIG. 4 is a characteristic diagram illustrating a relationship between a data length of a 12-phase expanded signal and a sampling period according to the first embodiment of the present invention.

FIG. 5 is a schematic diagram for explaining sampling of pixel data in the image display device according to the first embodiment of the present invention.

FIG. 6 is a timing chart showing a relationship between a sampling period in which a clock signal is shifted leftward and an enable signal in the X shift register according to the first embodiment of the present invention.

FIG. 7 is a timing chart illustrating a relationship between a sampling period in which a clock signal is shifted rightward and an enable signal in the X shift register according to the first embodiment of the present invention.

FIG. 8 is a block diagram of an electronic device to which the present invention is applied.

FIG. 9 is a schematic diagram of a projector to which the present invention is applied.

FIG. 10 is an external view of a personal computer to which the present invention is applied.

FIG. 11 is an exploded perspective view of a pager to which the present invention is applied.

FIG. 12 is a schematic perspective view showing an example of a liquid crystal display device provided with an external circuit to which the present invention is applied.

FIG. 13 is a diagram illustrating polarity inversion driving in a liquid crystal display device.

FIG. 14 is a characteristic diagram showing a relationship between a data length of a conventional six-phase expanded signal and a sampling period.

FIG. 15 is a schematic explanatory diagram for explaining generation of a ghost when an image is displayed using a conventional phase expansion signal.

[Explanation of symbols]

 Reference Signs List 10 liquid crystal panel block 11 first enable signal line 12 second enable signal line 20 timing generator 30 data processing block 32 serial / parallel conversion circuit 34 polarity inversion circuit 35 digital / analog conversion circuit 36 sample / hold circuit 37 address set controller 100 image display Unit (Liquid Crystal Panel) 102 Scanning Drive Circuit 104 X Shift Register 105 Enable Circuit 106 Sample Hold Switch 110 Scan Signal Line 112 Data Signal Line 114 Switching Element 116 Liquid Crystal Cell INV Inverter Circuit NAND NAND Circuit SHW Sample Hold Switch Block EN Enable Circuit

Claims (20)

[Claims] A plurality of data signal lines, a plurality of scanning signal lines intersecting with the plurality of data signal lines, and display elements connected to the plurality of data signal lines and the scanning signal lines are arranged in a matrix. An image display unit comprising: a scanning signal for sequentially selecting the scanning signal line; a scanning signal selecting unit that supplies the scanning signal line; and an image signal as serial data of an image to be displayed on the image display unit. Sampling and holding by the input of the sampling period signal set based on the reference clock,
A phase developing means for developing the serial data for each fixed pixel and outputting in parallel a plurality of pixel data obtained by converting the time of data per pixel to n (n ≧ 2) times the reference clock; A plurality of sampling means respectively connected to each of the data signal lines, sampling the plurality of pixel data over a sampling period, and supplying the plurality of pixel data to the corresponding data signal lines; and a sample of the plurality of pixel data. A plurality of sampling period signals generated before a hold period, the generation of which is completed before the end of each sample hold period, and having a sampling period longer than n times the reference clock, A sampling period signal generating unit to be supplied to each of the sampling units; The generation means, and supplies a signal to the period including each of the sampling period, the image display apparatus, wherein the plurality of data signal lines are provided and the data signal line drive circuit for selecting each of the. 2. The device according to claim 1, wherein the sampling means includes a plurality of sample and hold switch blocks formed by a plurality of switching elements, and each of the sample and hold switch blocks is output in parallel. An image display device, wherein a plurality of pixel data are sampled simultaneously over a common sampling period. 3. The image display unit according to claim 2, wherein the image display unit is a liquid crystal display unit formed on a substrate, and the plurality of switching elements include a plurality of TFTs formed on the substrate. The sampling period signal from the sampling period signal generating means is supplied to the gate of each of the TFTs for each of the sample and hold switch blocks, and pixel data is supplied to the source of each of the TFTs. An image display device comprising: 4. The image display device according to claim 2, wherein dummy pixel data is supplied to the sample and hold switch block at the start of the sampling period. 5. The method according to claim 3, wherein the sampling signal generation unit supplies the first and second sampling period signals to adjacent first and second sample and hold switch blocks, respectively, After the supply of the first sampling period signal to the hold switch block is started, and during the sampling period of the corresponding first pixel data, the second sample / hold switch block is supplied to the second sample / hold switch block.
An image display device, wherein supply of a sampling period signal is started. 6. The second sample and hold switch block according to claim 5, wherein the first pixel data is sampled as a precharge voltage by sampling the first pixel data at the start of the sampling period. An image display device supplied to a data signal line. 7. The plurality of enable circuits according to claim 3, further comprising: a plurality of enable circuits; and a first / second enable signal line, wherein the plurality of enable circuits correspond to the plurality of sample-and-hold switch blocks. The input line of the odd-numbered enable circuit is formed between the plurality of sampling units provided as the above and the data signal line driving unit, and the input line of the odd-numbered enable circuit is the first enable signal line. And an input line of an even-numbered enable circuit is connected to the second enable signal line. 8. The plurality of enable circuits according to claim 7, wherein the plurality of enable circuits are provided corresponding to the plurality of sample and hold switch blocks, and an output signal of each of the enable circuits is used as a sampling period signal as each of the sample and hold switch blocks. An image display device supplied to a hold switch block. 9. The plurality of enable circuits according to claim 8, wherein one of the input terminals is supplied with a first or second enable signal, and the other input terminal is connected to the data signal line driving circuit. An image display device comprising an AND circuit to which an output signal from a circuit is supplied. 10. The image display device according to claim 9, wherein the first and second enable signals have a duty of 50% or more, respectively. 11. The reference clock according to claim 10, wherein the reference clock is a dot clock signal, and at least one of a duty and a phase of the first / second enable signal is changed in units of the dot clock signal. An image display device, further comprising a variable means for causing the image display device to change the image. 12. The data signal line driving means according to claim 11, wherein said data signal line driving means is constituted by a plurality of shift registers provided respectively corresponding to said plurality of sample and hold switch blocks and a plurality of enable circuits. Image display device. 13. The data signal line driving unit according to claim 12, wherein the data signal line driving means converts an input signal having a pulse width of 2N (N is a natural number) times one cycle of the reference clock to N times one cycle of the reference clock. An image display device, which sequentially shifts and transmits the images one by one. 14. The phase expansion means according to claim 13, wherein the time of data per pixel as the serial data is one of the reference clocks.
An image display device characterized in that the image is doubled. 15. The method according to claim 14, wherein the duty of the sampling period signal is approximately 66.
An image display device characterized by being set to 7% or less. 16. An image display method for driving a plurality of data signal lines, a plurality of scanning signal lines intersecting with the plurality of data signal lines, and a display element connected to the plurality of data signal lines and the scanning signal lines. In the above, an image signal as serial data of an image to be displayed on the image display unit is developed for each fixed pixel based on a dot clock signal, and the time of data per pixel is one cycle of the dot clock signal. Outputting a plurality of pixel data each having a data length converted to n (n ≧ 2) times in parallel, generating a sample and hold switch activation signal before a sample and hold period of the pixel data, The plurality of pixel data is divided into one of the dot clock signals.
Sampling each in a sampling period longer than n times the period, and sequentially selecting the scanning signal lines, and applying the sampled pixel data to the display element connected to the selected scanning signal lines. Supplying the image data via the data signal line; and terminating the generation of the sample and hold switch activation signal before the end of the sample and hold period of the captured pixel data. Method. 17. The image display method according to claim 16, wherein the sampling period is adjustable with reference to the dot clock signal. 18. The image display method according to claim 17, wherein the sampling period is adjusted so that a duty of the sampling period signal is 50% or more. 19. The image display device according to claim 1, a clock generation circuit that supplies the reference clock to the image display device, and power supply to the image display unit and the clock generation circuit. And a power supply circuit. 20. A projection display device, comprising: the image display device according to claim 1; and a projection lens for enlarging and projecting an image on the image display unit.