JP2004139092A - Data transmission method and signal line drive circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To alleviate the defect that the states of the potential of signal lines vary between the boundaries and peripheries of blocks when the signal lines on the boundary lines of the blocks receive rocking of the potential in transmitting data for each of the blocks. <P>SOLUTION: Each of signal lines enters a rehearsal polarity inversion period before a normal polarity inversion period and is subjected to polarity inversion in advance. The signal lines on the boundary lines of the blocks are subjected to thrust up of the potential by the rehearsal polarity inversion and the potential once rocks but when the normal polarity inversion period comes around thereafter, the correct potential is applied and the rocking is restored. <P>COPYRIGHT: (C)2004,JPO

Description

The present invention relates to a data transmission method for performing data transmission using a matrix substrate such as an active matrix substrate provided in a liquid crystal display device and the like, and a signal line driving circuit.

デ ー タ Various data transmission devices for exchanging data between elements such as a display unit and a light receiving unit provided with signal lines and scanning lines in a matrix and other elements have been used.

For example, an active matrix substrate used for a display device such as a liquid crystal display device has a signal line for supplying a display signal to a pixel and a scanning line for driving a switching element provided for each pixel. External drive circuits (signal line drive circuits, scan line drive circuits) are mounted to drive these.

At that time, an external drive circuit was previously mounted so as to have the same number of output terminals as the number of signal lines and scanning lines in order to drive them. However, in order to reduce the number of external circuits and the cost for mounting, a method of reducing the number of ICs to half or one-third, branching the ICs, and selecting and supplying signals by signal line switching elements. Was thought. Specifically, for example, as disclosed in Patent Document 1, a scanning signal is applied to each block such that a scanning line is divided into blocks, and one vertical period is time-divided so that a scanning signal is sequentially applied to each block. Block is changed over time.
JP-A-8-234237

In the above-described conventional structure, an error occurs in data to be transmitted because a potential is written in a state where a signal line on a boundary line is fluctuated by a parasitic capacitance between the signal line and an adjacent signal line. There is a problem.

For example, in the case of a display device, there is a problem that a signal line and a pixel corresponding to a boundary of a block are rocked when a block is switched due to a parasitic capacitance between the signal line and the pixel electrode, and the boundary is visually recognized. This principle will be described with reference to a timing chart shown in FIG. 26 and FIG. 1 which is a configuration diagram of the present invention. Actually, many signal lines and corresponding members are provided in addition to those shown in the figure, but are simplified here for convenience of explanation. Here, an example in which a signal having the maximum amplitude is supplied from the output lines s _{1 to} s ₄ corresponding to the output terminals of the signal line driving circuit 1 in order to display the entire screen in black will be described.

One block (referred to as a first block) is configured by the signal lines f ′, f, a, and b. Another block (referred to as a second block) is configured by the signal lines c, d, e, and e ′. While in the scan line g ₁ is selected, first, the signal from the signal line drive circuit 1 is a signal line a, is supplied to the b. Since the scanning line g ₁ is selected, it is written to the pixel A _1, B _1. At this time, no signal is supplied to the signal lines c and d. Next, the signal lines a and b and the pixels A ₁ and B ₁ are held, and conversely, the signal from the signal line driving circuit 1 is supplied to the signal lines c and d, and the scanning line g ₁ is being selected. Therefore, these are written to the pixels C ₁ and D ₁ , respectively. Here, since the case where the entire screen is displayed in black is taken as an example, the same signal is supplied to the signal lines a to d, but usually, the one scanning line (g ₁ ) is selected. During this time, the signal from the signal line driving circuit 1 is switched.

Incidentally, a parasitic capacitance Csd exists between the pixel electrode and the signal line. FIG. 1 shows Csd of only pixels A ₁ , B ₁ , C ₁ , D ₁ , A ₂ , B ₂ , C ₂ , and D _2, but each signal line has a pixel along the signal line. Since the number of Csd's is added, there is actually a capacitance that cannot be ignored compared to the capacitance of the entire signal line. Here, when the application destination of the signal is switched from the first block to the second block, the potential of the signal line c is inverted as shown in FIG. Since the signal line b is capacitively coupled to the signal line c via the pixel electrode (a plurality of pixels in the signal line direction including B2), the potential of the signal line b is raised to a considerable extent by the polarity inversion of the signal line c. Since moreover the scanning lines g ₁ this time is the state of being selected, the push-up was potential is supplied to the pixel B _1, while the scanning line g ₁ in this state is switched to the unselected. Since such an operation is performed in all the scanning lines, only one line corresponding to the signal line b in the display of the entire screen is supplied with a higher voltage than the other pixels, and is displayed as a blacker line. The problem of being visually recognized arises.

Here, the driving in two blocks is described for simplicity. However, for example, when the entire screen is driven in four blocks, three black lines are visually recognized at the boundary of each block. Is a problem.

The above problem also applies to a case other than such a display device, for example, to an X-ray sensor. That is, a light detection unit is provided in which signal lines and scanning lines are formed in a matrix on a substrate, and a plurality of light detection elements are provided there. The light detector detects the X-rays and converts them into an electric signal, which is transmitted to an external display device or the like via a signal line. Even in this case, if the signal is transmitted by dividing the signal line into blocks in the same manner as described above, the potential is written while the potential of the signal line on the boundary line is fluctuated by the parasitic capacitance between the signal line and the adjacent signal line. This causes an error in the data to be transmitted.

In order to solve the above-mentioned problem, a data transmission method according to the present invention is characterized in that a scanning line in a row direction and a signal line in a column direction are formed in a matrix, and within one horizontal period, data corresponding to a position on the matrix is provided. A signal is applied to a signal line corresponding to the position, the signal line is divided into a plurality of blocks, and in each row, the signal lines are sequentially turned on for each block, so that a data signal is transmitted to and received from the matrix unit for each block. In the data transmission method for transmitting data signals to and from a unit, at least one of the blocks having signal lines adjacent to each other, the block having the earlier end time of application of the data signal is referred to as BL1, and the block having the earlier timing is referred to as BL1. The other block is referred to as BL2, and the signal lines belonging to BL1 and BL2 and adjacent to each other are denoted by SL1 and SL2, respectively. In one horizontal period, prior to the end of the application of the data signal as normal conduction, which is the conduction for applying the data signal to BL1, in the row, SL2 is set as conduction in the pre-row. A configuration in which conduction is achieved can be employed.

According to the above configuration, in one row, at least SL2 of the signal lines belonging to BL2 is turned on as conduction in the pre-row in that row prior to the end of the application of the data signal as normal conduction to BL1 in that row. . For example, all signal lines belonging to BL2, including SL2, may be made conductive. In the case of AC driving in which the potential of the signal line is inverted with respect to the reference voltage, prior to the end of the application of the data signal as normal conduction to BL1, the potential of at least SL2 is determined as conduction in the pre-line as the reference conduction. The polarity is inverted with respect to the voltage. That is, within one horizontal period, before the conduction of at least one block in the row ends, the signal line of the block that is to be made conductive next is once made conductive. In the case of the AC drive, the polarity of the signal line of BL2 is inverted beforehand as the polarity inversion of the pre-line before the normal polarity inversion of BL1.

Therefore, the potential of the block BL1 fluctuates due to the rise of the potential due to the above-described conduction, but thereafter, the normal conduction is performed and the correct potential is applied to the BL1, so that the fluctuation is restored. . Thereafter, the application of the data signal to BL1 ends, and the data signal is maintained and transmitted in BL1 based on this correct potential. Therefore, an error occurs in data to be transmitted when a signal line on a block boundary is written with a potential in a state where the potential is fluctuated by a parasitic capacitance between the signal line and an adjacent signal line. It can be effectively prevented. In the case of a display device, a phenomenon in which a pixel on a boundary line is written in a state of being subjected to fluctuation of a potential and is held over a display period does not occur. Therefore, it is possible to reduce a problem that the display state is different from that of the periphery even when the same potential is supplied to the periphery at the boundary of the block.

For example, while the pre-conduction is being conducted in BL2, the signal line of BL2 in which the pre-conduction is conducted is applied to the signal line at the regular conduction time while the row is selected. Signal. In this way, the same signal that should be applied is applied to the signal line that is conducting the pre-run in BL2 at both the pre-conduction conduction time and the normal conduction time. As a result, no potential difference occurs between the two signals. Therefore, the potential of the signal line in BL1 is not lowered by such a potential difference. Therefore, in addition to the effect of the above configuration, the problem that the potential is different from the surroundings even when the same potential as the surroundings is supplied at the boundary of the block can be further reduced.

Further, the data transmission method of the present invention, the scanning line in the row direction and the signal line in the column direction are formed in a matrix, an image display device that displays the image represented by the data signal in the pixels on this matrix, In one horizontal period, a data signal corresponding to a position on the matrix is applied to a signal line corresponding to the position, the signal line is divided into a plurality of blocks, and in each row, the potential of the signal line is set for each block. In a data transmission method for sequentially transmitting a data signal from a data transfer unit to the pixel for each block by sequentially inverting polarity with respect to a reference voltage, at least one set of the blocks includes signal lines adjacent to each other. Regarding the blocks, the earlier block of the application of the data signal is referred to as BL1 and the later block is referred to as BL2. Assuming that signal lines belonging to BL2 and adjacent to each other are SL1 and SL2, respectively, in one horizontal period, normal conduction, which is conduction for applying the data signal to BL1, is applied to BL1 in that row. Prior to the completion of the application of the data signal, the potential of SL2 may be inverted with respect to the reference voltage as a pre-conduction state.

According to the above configuration, in one horizontal period, in the row, prior to the end of application of the data signal as normal conduction, which is conduction for applying the data signal to BL1, the pre-line conduction is performed. The potential of SL2 is inverted with respect to the reference voltage. For example, the potentials of all signal lines belonging to BL2, including SL2, may be inverted with respect to the reference voltage. That is, in the AC drive in which the potential of the signal line is inverted with respect to the reference voltage, prior to the end of the application of the data signal as the normal conduction to the BL1, the potential of at least SL2 is determined as the conduction of the pre-run as the reference. The polarity is inverted with respect to the voltage. That is, within one horizontal period, before the conduction of at least one block is completed in the row, the potential of the signal line of the block to be made conductive next is inverted with respect to the reference voltage. . That is, in the AC driving, the polarity of the signal line of BL2 is inverted beforehand as the polarity inversion of the pre-line before the normal polarity inversion of BL1.

Therefore, the potential of the block BL1 fluctuates due to the rise of the potential due to the above-described conduction, but thereafter, the normal conduction is performed and the correct potential is applied to the BL1, so that the fluctuation is restored. . Thereafter, the application of the data signal to BL1 ends, and the data signal is maintained and transmitted in BL1 based on this correct potential. Therefore, an error occurs in data to be transmitted when a signal line on a block boundary is written with a potential in a state where the potential is fluctuated by a parasitic capacitance between the signal line and an adjacent signal line. It can be effectively prevented. As a result, in the display device, a phenomenon in which a pixel on the boundary line is written in a state where the fluctuation of the potential is received and the pixel is held for a display period does not occur. Therefore, it is possible to reduce a problem that the display state is different from that of the periphery even when the same potential is supplied to the periphery at the boundary of the block.

Further, in addition to the above configuration, the data transmission method of the present invention has a configuration in which the signal lines of a plurality of blocks are simultaneously turned on prior to the end of application of the data signal to BL1 within the one horizontal period. can do.

(4) With the configuration described above, the signal lines of a plurality of blocks are simultaneously turned on before the application of the data signal to the BL1 is completed within the one horizontal period. In the case of the AC drive, the potentials of the signal lines of a plurality of blocks are simultaneously inverted with respect to the reference voltage before the end of the application of the data signal to BL1.

Therefore, even when the drive is divided into many blocks, since the conduction time of the pre-run such as the reversal of the polarity of the pre-run is common, the time required for the conduction of the pre-run is not too long as a whole, Time loss can be reduced when performing normal conduction such as normal polarity inversion. Therefore, in addition to the effect of the above configuration, the signal can be applied with a margin, so that the data transmission processing quality can be improved.

Further, in addition to the above-described configuration, the data transmission method of the present invention may be configured such that, while the pre-line is being conducted in BL2, the signal line of the BL2 that is conducting the pre-line is applied to the signal line. Data signal having a signal strength intermediate between the maximum value and the minimum value of the data signals.

With the above configuration, while the pre-conduction is being conducted in BL2, the signal line of BL2 in which the pre-conduction is conducted has the maximum value and the minimum value of the data signals applied to the signal line. Is applied with a data signal having an intermediate signal strength. For example, in the case of a display device, a halftone data signal that is halfway between black display and white display is applied to a pixel as a data processing unit. As a result, the signal line in BL1 does not receive a significant drop in potential due to a small potential difference in the case of such an intermediate data signal. In general, for example, in the case of a display device, a difference in visibility on display with respect to a slight difference between potentials is determined by a signal having a signal intensity intermediate (halftone) between the maximum value and the minimum value of the data signals. Sometimes most noticeable. Therefore, according to the above configuration, it is possible to effectively suppress the occurrence of the difference in the display state even when the difference is most noticeable. Therefore, in addition to the effect of the above configuration, the problem that the potential is different from the surroundings even when the same potential as the surroundings is supplied at the boundary of the block can be further reduced.

In addition, in addition to the above configuration, the data transmission method of the present invention may be configured to perform the above-described conduction in BL2 during the normal conduction period of BL1 within the one horizontal period.

With the above configuration, during the normal conduction period of BL1, within the one horizontal period, conduction of the pre-run at BL2 is performed.

Therefore, even when the drive is divided into many blocks, the conduction time of the pre-run such as the reversal of the polarity of the pre-run is in the normal conduction period such as the reversal of the normal polarity of the other blocks. The time required for conduction does not become too long, and the time loss in performing regular conduction can be reduced. Therefore, in addition to the effect of the above configuration, the signal can be applied with a margin, so that the data transmission processing quality can be improved.

Further, in addition to the above configuration, the data transmission method of the present invention terminates the conduction of the pre-run at BL2 at the end time of the normal conduction of BL1 within the one horizontal period, and subsequently continues the normal operation at BL2. A configuration in which conduction is performed can be employed.

According to the above configuration, within the one horizontal period, at the end time of the normal conduction of the BL1, the conduction of the pre-run at the BL2 is terminated, and then the normal conduction is performed at the BL2. This is because the normal conduction period of each block slightly shifts with an overlap, so that the normal conduction period in BL2 (the ON period of each control line) overlaps with the normal conduction period in BL1. It can also be considered that the conduction period is divided into a regular conduction period of BL2 after the regular conduction period of BL1 ends.

Therefore, in actuality, such a configuration can be realized by slightly changing the timing of the signal for defining the start timing and end timing of the normal conduction period, and the start timing and end timing of the lead-through conduction period are defined. Therefore, there is no need to create a new signal for performing the operation. Therefore, in addition to the effect of the above configuration, the configuration of the device for driving in this manner can be simplified.

According to the data transmission method of the present invention, a plurality of scanning lines and a plurality of signal lines are formed in a matrix, and within one horizontal period, a data signal corresponding to the matrix position is transmitted to a signal line corresponding to the position. In a data transmission method for transmitting a data signal between a matrix unit and a data transfer unit for each block by applying the applied signal lines to divide the signal line into a plurality of blocks and sequentially conducting the signal lines for each block, One block of input data, which is continuously input in a sequence and corresponds to n signal lines, is sampled by n sampling units, accumulated as n sampling data, and output to the corresponding signal line, respectively. The n sampling units are divided into groups, and the sampling order of the input data for the same scanning line among the blocks is second or later. When one of the groups is BL2 and a group having a sampling unit to which the first sampling data Db1 of the block BL2 is input is GRa, the group GRa has a sampling time for the same scanning line that is higher than that of the block BL2. It is characterized in that an empty sampling unit for storing the sampling data Db1 is prepared in the group GRa from the time when the sampling data of the early block is accumulated until the time when the sampling data Db1 is input at the latest.

In the data transmission method according to the present invention, the scanning lines in the row direction and the signal lines in the column direction are formed in a matrix, and within one horizontal period, the data signal corresponding to the position on the matrix corresponds to the position. The data signal is transmitted between the matrix unit and the data transfer unit for each block by dividing the signal line into a plurality of blocks and sequentially conducting the signal line for each block in each row. In a data transmission method, input data for one block, which is continuously input in time series and corresponds to n signal lines, is sampled by n sampling units, and stored as n sampled data, respectively. Each of the n sampling units is output to a signal line, and the n sampling units are divided into groups. When one of the second and subsequent pulling orders is BL2 and the group having a sampling unit to which the first sampling data Db1 of the block BL2 is input is GRa, the group GRa is the same for the same scanning line. An empty sampling unit for accumulating the sampling data Db1 is provided in the group GRa from the accumulation of the sampling data of the block whose sampling time is earlier than the block BL2 to the input of the sampling data Db1 at the latest. Configuration.

For example, the above-mentioned n sampling units can be divided into groups by those having the same timing at which system switching is performed in the sampling units. In addition, the n sampling units can be divided into groups with the same timing of outputting data signals to be output to one block of the signal line.

If the data signal is not divided into groups, the first to n-th data signals are sampled for the data signal to be output to one of the signal line blocks, and after that, the first data signal is again output. Before sampling a signal, the first to n-th sampled data signals are transferred or latched to a signal line. Therefore, time is required for this transfer or latch. As a result, when trying to transmit a temporally continuous data signal, that is, a data signal that is successively input at a fixed time interval, the time for this transfer or latch is ignored compared to the data signal supply interval. If this is not possible, the sampling cannot catch up and the data signal will be missed. Alternatively, it is necessary to devise some measure to the data signal, such as incorporating an index signal into the data signal to be transmitted in consideration of the time.

On the other hand, according to the configuration of the present invention, the input data for one block, which is continuously input in a time series and corresponds to n signal lines, is sampled by n sampling units to obtain n sampled data. After each accumulation, the signal is output to a corresponding signal line, and the n sampling units are grouped. One of the blocks in which the input data is sampled in the second or subsequent order for the same scanning line Is BL2, and the group having a sampling unit to which the first sampling data Db1 of the block BL2 is input is GRa, and the group GRa performs sampling of a block having the same sampling line and earlier sampling time than the block BL2. After storing the data, the sampling data Db1 Before being input in the group GRa, provide an empty sampling unit for storing the sampling data Db1.

Therefore, when there are n input lines to the signal lines (there are thus an integral multiple of n signal lines), before sampling the first data signal again after sampling the nth data signal, In addition, no time is required for transferring or latching the sampled data signal to the signal line. Therefore, it is not necessary to particularly process the data signal according to the time for the transfer or the latch. Therefore, with a simple configuration, data can be transmitted quickly and data can be processed at high speed.

(4) For the preparation, a group control signal indicating the timing of performing the preparation operation can be output and used as appropriate. For such a group control signal, for example, a plurality of systems (A system, B system, etc.) for storing a data signal in each sampling unit are prepared, and between these systems, the storage destination of the data signal is set to an empty system. This is a group control signal (system switching timing signal) indicating switching timing. Further, for example, it is a group control signal (output timing signal) indicating output timing at which accumulated sampling data is transferred or latched and output while another group is performing input / accumulation operation of another sampling data.

Further, in addition to the above configuration, the data transmission method of the present invention may be configured such that at least one set of the blocks, each of which has a signal line adjacent to each other, has earlier application of the data signal. When the block is BL1 and the later block is BL2, each sampling unit has a plurality of systems for storing the sampling data, and in a certain group GR1, the sampling data of the block BL1 is stored in each sampling unit. Is stored in one of the above-described plural systems, and when the storage is completed, the storage of the next sampling data is started in another group, and then the storage of the sampling data of the next block BL2 is performed in the group GR1. Before the start, the system to be the next storage destination in the group GR1 is It is characterized in that switching to no accumulated data lines.

According to the above configuration, with respect to at least one set of the blocks having signal lines adjacent to each other, the block in which the application end time of the data signal is earlier is BL1 and the block in which the application end time of the data signal is later is BL2. At this time, each of the sampling units has a plurality of systems for storing the sampling data, and in a certain group GR1, the sampling data of the block BL1 is stored in one of the plurality of systems in each sampling unit. When the accumulation is completed, the accumulation of the next sampling data is started in another group, and thereafter, the accumulation of the sampling data of the next block BL2 in the group GR1 is started. Switching the storage destination system to a system that does not currently have stored data . This switching may be performed simultaneously for each group.

For example, the sampling data is stored in one of a plurality of systems in each sampling unit for each group, and when the storage in one system is completed, the next storage destination system is changed to a system having no currently stored data. Switching is performed simultaneously for each group, and input data input while one group is performing the system switching is sampled by another group, for example, by another group that is not performing the system switching at that time. be able to.

Also, for example, among the data signals for the block BL1 whose sampling time is immediately before the block BL2 for the same scanning line, the data signal to be sampled last is accumulated in a certain system A of a certain group, and Accumulates the first sampling data Db1 of the block BL2 in another group GRa while performing the system switching to the system B. The output of the sampling data already stored in one system in the group can be performed while the sampling data is stored in another system of the group. Alternatively, if there is a period during which accumulation is not performed in any of the systems in the group, the output can be made during that period.

Therefore, even if a plurality of systems are provided for each signal line in one block and storage / output is switched between the systems, the group for performing the storage processing is switched and the data signal between the groups is reliably obtained in another group. , And data can be reliably prevented from being missed. Therefore, in addition to the effects of the above configuration, data can be transmitted quickly and data can be processed at high speed with a simpler configuration.

グ ル ー プ For the switching, a group control signal indicating the timing of performing the switching operation can be output and used as appropriate. For such a group control signal, for example, a plurality of systems (A system, B system, etc.) for storing a data signal in each sampling unit are prepared, and between these systems, the storage destination of the data signal is set to an empty system. This is a group control signal (system switching timing signal) indicating switching timing. Thus, the sampling signal is switched at the timing of the group control signal.

Further, in the data transmission method of the present invention, in the above-described configuration, when one of the groups is set to GR1, after storing the sampling data in at least the group GR1, and then storing the sampling data in another group, The sampling data accumulated in the group GR1 is output.

According to the above configuration, when one of the groups is set to GR1, at least after sampling data is accumulated in this group GR1, the sampling data accumulated in the group GR1 is accumulated while sampling data is accumulated in another group. Output.

Therefore, there is no need to provide a plurality of systems for each signal line in one block and switch between accumulation and output between the systems, and it does not require time for switching. Therefore, in addition to the effects of the above configuration, data can be transmitted quickly and data can be processed at high speed with a simpler configuration.

For example, while one group is sampling a data signal, another group may transfer or latch a signal already sampled in that group to a signal line, and the timing of transferring or latching in this manner. Can be configured to be output. For example, data signals to be output to one of the signal line blocks are divided into groups based on the same output timing, and two of the groups, for example, the output order of the data signals is continuous. For example, when the earlier output time is GR1 and the later output time is GR2, while the data signal is being sampled by GR2, the signal already sampled by the group GR1 is transferred or latched from GR1 to the signal line. By doing so, the data signal can be sequentially output to one block of the signal line for each group.

(4) For the output, a group control signal indicating the timing of performing the output operation can be output and used as appropriate. Such a group control signal is, for example, a group control signal indicating an output timing at which accumulated sampling data is transferred or latched and output while another group is performing input / accumulation operations of another sampling data ( Output timing signal). In this manner, at least two or more groups of lines may be independently controlled by different group control signals. That is, in one group GR1, the timing of sampling and transferring or latching is defined by a certain group control signal (CNTa), and in another group GR2, the timing of sampling and transferring or latching is defined by another certain group control signal (CNTa). CNTb).

In the data transmission method according to the present invention, the scanning lines in the row direction and the signal lines in the column direction are formed in a matrix, and within one horizontal period, the data signal corresponding to the position on the matrix corresponds to the position. The data signal is transmitted between the matrix unit and the data transfer unit for each block by dividing the signal line into a plurality of blocks and sequentially conducting the signal line for each block in each row. In the data transmission method, at least one set of the blocks having signal lines adjacent to each other is referred to as a block with the earlier application end time of the data signal as BL1, and a later block as BL2. , The signal lines belonging to BL1 and BL2 and adjacent to each other are designated SL1 and SL2, respectively. In the row, the application of the data signal to SL2 is started prior to the end of application of the data signal as normal conduction, which is the conduction for applying the data signal, to BL1. can do.

For example, in the case of the AC driving, within one horizontal period, before the end of the normal polarity inversion as the normal conduction for applying the data signal to the BL1 in the row, the SL2 is applied to the BL1. A configuration in which normal polarity inversion for application of the data signal is started can be adopted.

According to the above configuration, within one horizontal period, prior to the end of application of the data signal as normal conduction, which is conduction for applying the data signal to BL1, in the row, the signal to SL2 is supplied to the row. The application of the data signal is started. That is, each signal line of BL2 is made conductive in advance by starting normal conduction before the end of data signal application to BL1.

Accordingly, the potential of the block BL1 fluctuates in response to the rise of the potential due to the conduction timing. However, for a while after that, the application of the data signal to the BL1 is still continued. The swing is restored. Thereafter, the application of the data signal to BL1 ends, and the correct potential can be maintained and transmitted in BL1. Therefore, an error is generated in data to be transmitted by writing a potential in a state where a potential of a signal line on a boundary line fluctuates due to a parasitic capacitance between the signal line and an adjacent signal line. Can be prevented.

(4) In the case of a display device, a phenomenon in which a pixel on a boundary line is written in a state of being subjected to fluctuation of a potential and is held over a display period does not occur. Therefore, it is possible to reduce a problem that the display state is different from that of the periphery even when the same potential is supplied to the periphery at the boundary of the block.

In addition, in order to eliminate such an error, the conduction is performed at an earlier timing than usual. However, such a configuration can be achieved by slightly changing the timing of a signal for defining the start timing and end timing of the normal conduction period. Therefore, it is not necessary to newly generate a signal for defining the start time and the end time only for such fast conduction. Therefore, the configuration of the device for driving in this way can be simplified.

Further, the data transmission method of the present invention, the scanning line in the row direction and the signal line in the column direction are formed in a matrix, an image display device that displays the image represented by the data signal in the pixels on this matrix, In one horizontal period, a data signal corresponding to a position on the matrix is applied to a signal line corresponding to the position, the signal line is divided into a plurality of blocks, and in each row, the potential of the signal line is set for each block. In a data transmission method for sequentially transmitting a data signal from a data transfer unit to the pixel for each block by sequentially inverting polarity with respect to a reference voltage, at least one set of the blocks includes signal lines adjacent to each other. Regarding the blocks, the earlier block of the application of the data signal is referred to as BL1 and the later block is referred to as BL2. Assuming that signal lines belonging to BL2 and adjacent to each other are SL1 and SL2, respectively, in one horizontal period, normal conduction, which is conduction for applying the data signal to BL1, is applied to BL1 in that row. The application of the data signal to SL2 may be started prior to the end of the application of the data signal.

That is, in the AC driving, the data signal to SL2 is supplied to SL1 in one row prior to the end of the normal polarity inversion as the normal conduction for applying the data signal to BL1 in that row. To start the normal polarity inversion for the application of.

According to the above configuration, within one horizontal period, prior to the end of application of the data signal as normal conduction, which is conduction for applying the data signal to BL1, in the row, the signal to SL2 is supplied to the row. The application of the data signal is started. That is, each signal line of BL2 is made conductive in advance by starting normal conduction before the end of data signal application to BL1.

Accordingly, the potential of the block BL1 fluctuates in response to the rise of the potential due to the conduction timing. However, for a while after that, the application of the data signal to the BL1 is still continued. The swing is restored. Thereafter, the application of the data signal to BL1 ends, and the correct potential can be maintained and transmitted in BL1. Therefore, an error is generated in data to be transmitted by writing a potential in a state where a potential of a signal line on a boundary line fluctuates due to a parasitic capacitance between the signal line and an adjacent signal line. Can be prevented.

As a result, in the display device, the phenomenon that the pixels on the boundary line are written while being subjected to the fluctuation of the potential and are held for the display period does not occur. Therefore, it is possible to reduce a problem that the display state is different from that of the periphery even when the same potential is supplied to the periphery at the boundary of the block.

In addition, in order to eliminate such an error, the conduction is performed at an earlier timing than usual. However, such a configuration can be achieved by slightly changing the timing of a signal for defining the start timing and end timing of the normal conduction period. Therefore, it is not necessary to newly generate a signal for defining the start time and the end time only for such fast conduction. Therefore, the configuration of the device for driving in this way can be simplified.

In the image display device of the present invention, the scanning lines in the row direction and the signal lines in the column direction are formed in a matrix, and within one horizontal period, the data signal corresponding to the position on the matrix corresponds to the position. The data signal is applied to each signal block, and the signal line is divided into a plurality of blocks, and in each row, the potential of the signal line is sequentially inverted with respect to a reference voltage for each block with respect to a reference voltage, so that the data signal is transmitted and received for each block. In the image display device transmitting from the data transmission method to the pixels on the matrix, and displaying the image represented by the data signal at the pixels, the data signal from the data transfer unit to the pixels on the matrix using the data transmission method according to any of the above Is transmitted.

According to the above configuration, a data signal is transmitted from the data transfer unit to the pixels on the matrix using any of the data transmission methods described above. Therefore, the phenomenon in which the pixels on the boundary line are written in a state where the fluctuation of the potential has been performed as described above and are maintained over the display period does not occur. Therefore, it is possible to reduce a problem that the display state is different from that of the periphery even when the same potential is supplied to the periphery at the boundary of the block.

In the signal line driver circuit according to the present invention, a plurality of scanning lines and a plurality of signal lines are formed in a matrix, and within one horizontal period, a data signal corresponding to the matrix corresponds to the position. The signal line is applied to a signal line, the signal line is divided into a plurality of blocks, and the signal line is sequentially turned on for each block. In a signal line driving circuit that transmits the data signal to an image display device that displays the image represented by the pixel with the pixels, one block of input data that is continuously input in time series and corresponds to n signal lines is represented by n After sampling by the number of sampling units and accumulating them as n pieces of sampling data, the data is output to the corresponding signal line, and the n number of sampling units are divided into Then, among the blocks, one of the same scanning lines whose sampling order of the input data is the second or later is BL2, and a group having a sampling unit to which the first sampling data Db1 of the block BL2 is input is defined as BL2. When GRa is set, the group GRa is stored in the group GRa after the sampling data of the block whose sampling time is earlier than that of the block BL2 for the same scanning line and before the sampling data Db1 is input at the latest. In addition, a group control signal that defines the timing for preparing an empty sampling unit for storing the sampling data Db1 is generated for each group.

In the signal line driving circuit according to the present invention, as the data transfer unit, a signal line driving circuit for transmitting the data signal to the image display device, which is continuously input in time series and corresponds to n signal lines. The input data for the blocks is sampled by the n sampling units and stored as n sampling data, respectively, and then output to the corresponding signal lines. The n sampling units are divided into groups, and When one of the same scanning lines whose sampling order of the input data is the second or later is BL2, and the group having the sampling unit to which the first sampling data Db1 of the block BL2 is input is GRa, The group GRa has a sampling time for the same scanning line that is higher than that of the block BL2. Group control that defines the timing of preparing an empty sampling unit for storing the sampling data Db1 in the group GRa after the sampling data of the new block is stored and before the sampling data Db1 is input at the latest. The signal may be generated for each group.

According to the configuration described above, the group GRa stores the sampling data of a block whose sampling time is earlier than that of the block BL2 for the same scanning line, and thereafter, within the group GRa at the latest until the sampling data Db1 is input. , A group control signal that defines the timing for preparing an empty sampling unit for storing the sampling data Db1 is generated for each group.

Therefore, when there are n input lines to the signal lines (there are thus an integral multiple of n signal lines), before sampling the first data signal again after sampling the nth data signal, In addition, no time is required for transferring or latching the sampled data signal to the signal line. Therefore, it is not necessary to particularly process the data signal according to the time for the transfer or the latch. Therefore, in addition to the effects of the above configuration, data can be transmitted quickly and data can be processed at high speed with a simple configuration.

Further, the signal line driving circuit of the present invention, in the above-described configuration, as to at least one of the blocks having signal lines adjacent to each other, the block in which the application end time of the data signal is earlier is determined. When BL1 and the slower block are BL2, each sampling unit has a plurality of systems for storing the sampling data, and in a certain group GR1, the sampling data of the block BL1 is stored in the sampling unit in each sampling unit. The data is accumulated in one of the plurality of systems, and when the accumulation is completed, accumulation of the next sampling data is started in another group, and then accumulation of the sampling data of the next block BL2 is started in the group GR1. By the time, the system that becomes the next storage destination in the above group GR1 is currently A signal defining a timing for switching to the no-product data system is characterized by generating as the group control signal.

According to the above configuration, with respect to at least one set of the blocks having signal lines adjacent to each other, the block in which the application end time of the data signal is earlier is BL1 and the block in which the application end time of the data signal is later is BL2. At this time, each of the sampling units has a plurality of systems for storing the sampling data, and in a certain group GR1, the sampling data of the block BL1 is stored in one of the plurality of systems in each sampling unit. When the accumulation is completed, the accumulation of the next sampling data is started in another group, and thereafter, the accumulation of the sampling data of the next block BL2 in the group GR1 is started. Switching the storage destination system to a system that does not currently have stored data . This switching may be performed simultaneously for each group.

Therefore, even if a plurality of systems are provided for each signal line in one block and storage / output is switched between the systems, the group for performing the storage processing is switched and the data signal between the groups is reliably obtained in another group. , And data can be reliably prevented from being missed. Therefore, in addition to the effects of the above configuration, data can be transmitted quickly and data can be processed at high speed with a simpler configuration.

Further, in the above configuration, when one of the groups is set to GR1, the signal line driving circuit according to the present invention stores the sampling data in at least the group GR1 and then stores the sampling data in another group. , Wherein a signal defining the timing of outputting the sampling data accumulated in the group GR1 is generated as the group control signal.

According to the above configuration, when one of the groups is set to GR1, at least after sampling data is accumulated in this group GR1, the sampling data accumulated in the group GR1 is accumulated while sampling data is accumulated in another group. Output.

Therefore, there is no need to provide a plurality of systems for each signal line in one block and switch between accumulation and output between the systems, and it does not require time for switching. Therefore, in addition to the effects of the above configuration, data can be transmitted quickly and data can be processed at high speed with a simpler configuration.

Further, as the data transmission device of the present invention, the scanning lines in the row direction and the signal lines in the column direction are formed in a matrix, and within one horizontal period, the data signal corresponding to the position on the matrix corresponds to the position. To be applied to a signal line to be transmitted to a pixel on the matrix to display an image by transmitting a data signal, wherein the signal line is divided into a plurality of blocks, and in each row, the signal line Are sequentially conducted for each block, so that a data signal is transmitted between the matrix unit and the data transfer unit for each block. In the data transmission apparatus, at least one set of The blocks having the earlier application of the data signal are referred to as BL1 and the later blocks are referred to as BL2. Assuming that signal lines belonging to L1 and BL2 and adjacent to each other are SL1 and SL2, respectively, within one horizontal period, a regular line that is conductive for applying the data signal to BL1 in that row is applied in that row. Prior to the end of the application of the data signal as conduction, a conduction control unit that conducts SL2 as conduction in the pre-run may be provided.

According to the above configuration, in one row, at least SL2 of the signal lines belonging to BL2 is turned on as conduction in the pre-row in that row prior to the end of the application of the data signal as normal conduction to BL1 in that row. . For example, all signal lines belonging to BL2, including SL2, may be made conductive. In the case of AC driving in which the potential of the signal line is inverted with respect to the reference voltage, prior to the end of the application of the data signal as normal conduction to BL1, the potential of at least SL2 is determined as conduction in the pre-line as the reference conduction. The polarity is inverted with respect to the voltage. Therefore, the phenomenon in which the pixels on the boundary line are written in a state where the fluctuation of the potential has been performed as described above and are maintained over the display period does not occur. Therefore, it is possible to reduce a problem that the display state is different from that of the periphery even when the same potential is supplied to the periphery at the boundary of the block.

As described above, according to the data transmission method of the present invention, for at least one set of blocks having signal lines adjacent to each other, the block having the earlier application end time of the data signal is the BL1, Assuming that the other block is BL2 and the signal lines belonging to BL1 and BL2 and adjacent to each other are SL1 and SL2, respectively, the data signal is applied to BL1 in one row within one horizontal period. Prior to the end of the application of the data signal as the normal conduction, the SL2 may be turned on as the pre-conduction.

As a result, the potential of the block BL1 fluctuates in response to the rise of the potential due to the above-mentioned conduction of the pre-run, but after that, normal conduction is performed, the correct potential is applied to BL1, and the fluctuation is restored. An error is generated in data to be transmitted by writing a potential in a state where a signal line on a block boundary is fluctuated by a parasitic capacitance between the signal line and an adjacent signal line. This has the effect of being able to be prevented.

Further, in the data transmission method of the present invention, for at least one set of blocks having signal lines adjacent to each other, the block having the earlier application end time of the data signal is referred to as BL1, and the later block is referred to as the later block. Is BL2, and the signal lines belonging to BL1 and BL2 and adjacent to each other are SL1 and SL2, respectively, in one horizontal period, for applying the data signal to BL1 in that row in one row. Prior to the end of the application of the data signal as normal conduction, the potential of SL2 may be inverted with respect to the reference voltage as pre-conduction.

As a result, as described above, the phenomenon that the pixels on the boundary line are written while being subjected to the fluctuation of the potential and the data is held for the display period does not occur. Despite this, it is possible to reduce the problem that the display state is different from the surroundings.

Further, in addition to the above configuration, the data transmission method of the present invention has a configuration in which the signal lines of a plurality of blocks are simultaneously turned on prior to the end of application of the data signal to BL1 within the one horizontal period. can do.

Thus, even if the drive is divided into many blocks, the time required for the conduction of the pre-run such as the reversal of the polarity of the pre-run does not become too long, and the normal conduction such as the normal polarity reversal is performed. In this case, a time loss can be reduced, so that in addition to the effects of the above-described configuration, there is an effect that signals can be applied with a margin and data processing quality can be improved.

Further, in addition to the above-described configuration, the data transmission method of the present invention may be configured such that, while the pre-line is being conducted in BL2, the signal line of the BL2 that is conducting the pre-line is applied to the signal line. Data signal having a signal strength intermediate between the maximum value and the minimum value of the data signals.

As a result, the signal line in BL1 does not receive a significant drop in potential due to a small potential difference in the case of such an intermediate data signal. The disadvantage that the potential is different from the surroundings even when the same potential as the surroundings is supplied can be further reduced.

In addition, in addition to the above configuration, the data transmission method of the present invention may be configured to perform the above-described conduction in BL2 during the normal conduction period of BL1 within the one horizontal period.

Thus, even if the drive is divided into many blocks, the time required for the conduction of the pre-run such as the reversal of the polarity of the pre-run does not become too long, and the normal conduction such as the normal polarity reversal is performed. In this case, a time loss can be reduced, so that in addition to the effects of the above-described configuration, there is an effect that signals can be applied with a margin and data processing quality can be improved.

Further, in addition to the above configuration, the data transmission method of the present invention terminates the conduction of the pre-run at BL2 at the end time of the normal conduction of BL1 within the one horizontal period, and subsequently continues the normal operation at BL2. A configuration in which conduction is performed can be employed.

Accordingly, it is not necessary to newly generate a signal for defining the start time and the end time of the conduction period of the pre-run such as the reversal of the polarity of the pre-run. There is an effect that the configuration of the device can be simplified.

According to the data transmission method of the present invention, after one block of input data that is continuously input in time series and corresponds to n signal lines is sampled by n sampling units and accumulated as n sampling data, The signal is output to a corresponding signal line, the n sampling units are grouped, and one of the blocks in which the input data sampling order is the second or later for the same scanning line is BL2, When a group having a sampling unit to which the first sampling data Db1 of the block BL2 is input is defined as GRa, the group GRa stores sampling data of a block whose sampling time is earlier than that of the block BL2 for the same scanning line. , The sampling data Db1 is input at the latest. In the, in the group GRa, it is configured to provide an empty sampling unit for storing the sampling data Db1.

Further, in the data transmission method of the present invention, one block of input data that is continuously input in time series and corresponds to n signal lines is sampled by n sampling units and stored as n sampled data. Thereafter, the signals are output to the corresponding signal lines, and the n sampling units are divided into groups. Of the blocks, one of the same scanning lines whose sampling order of the input data is the second or later is BL2. When a group having a sampling unit to which the first sampling data Db1 of the block BL2 is input is defined as GRa, the group GRa stores sampling data of a block having a sampling time earlier than that of the block BL2 for the same scanning line. After that, the sampling data Db1 is input at the latest. In until, in the group GRa, can be configured to provide an empty sampling unit for storing the sampling data Db1.

Thus, when there are n input lines to the signal line, the sampled data signal is transferred to the signal line after sampling the nth data signal and before again sampling the first data signal. Or, time for latching is not required. Therefore, it is not necessary to particularly process the data signal according to the time for the transfer or the latch, so that the data can be transmitted quickly and processed at a high speed with a simple configuration. It works.

Further, in addition to the above configuration, the data transmission method of the present invention may be configured such that at least one set of the blocks, each of which has a signal line adjacent to each other, has earlier application of the data signal. When the block is BL1 and the later block is BL2, each sampling unit has a plurality of systems for storing the sampling data, and in a certain group GR1, the sampling data of the block BL1 is stored in each sampling unit. Is stored in one of the above-described plural systems, and when the storage is completed, the storage of the next sampling data is started in another group, and then the storage of the sampling data of the next block BL2 is performed in the group GR1. Before the start, the system to be the next storage destination in the group GR1 is A configuration in which switching to no accumulated data lines.

Accordingly, even if a plurality of systems are provided for each signal line in one block and storage / output is switched between the systems, the group for performing the storage processing is switched and the data signal between the groups is transferred to another group. Sampling can be reliably performed, and data can be reliably prevented from being missed. In addition to the effects of the above configuration, data can be transmitted quickly with a simpler configuration, and data can be processed at high speed. This has the effect.

Further, in addition to the above configuration, when one of the groups is set to GR1, the data transmission method of the present invention stores the sampling data in at least this group GR1 and then stores the sampling data in another group. In this configuration, the sampling data stored in the group GR1 is output.

This eliminates the need to provide a plurality of systems for each signal line in one block and switch between accumulation and output between the systems, and eliminates the need for time for switching. With a simpler configuration, data can be transmitted quickly and data can be processed at high speed.

Further, in the data transmission method of the present invention, for at least one set of the blocks having signal lines adjacent to each other, the block in which the application end time of the data signal is earlier is BL1 and the block in which the application end time of the data signal is later is BL1. When the block is BL2 and the signal lines belonging to BL1 and BL2 and adjacent to each other are SL1 and SL2, respectively, in order to apply the data signal to BL1 in one row in one horizontal period. The application of the data signal to SL2 may be started prior to the end of the application of the data signal as normal conduction, which is the conduction of.

Thus, the application of the data signal to SL2 causes the potential of the block BL1 to fluctuate due to the rise of the potential. Thereafter, normal conduction is performed, and the correct potential is applied to BL1 to correct the fluctuation. Therefore, an error occurs in data to be transmitted when a signal line on a boundary line of a block is written with a potential in a state where the potential swings due to a parasitic capacitance between the signal line and an adjacent signal line. , Which can be effectively prevented.

The data transmission method according to the present invention is also directed to the image display device, wherein at least one of the blocks having the signal lines adjacent to each other has at least one of the blocks having the earlier application end time of the data signal. Is BL1, the slower block is BL2, and the signal lines belonging to BL1 and BL2 and adjacent to each other are SL1 and SL2, respectively. A configuration may be adopted in which the application of the data signal to SL2 is started prior to the end of application of the data signal as normal conduction, which is conduction for applying the data signal.

Thus, the application of the data signal to SL2 causes the potential of the block BL1 to fluctuate due to the rise of the potential. Thereafter, normal conduction is performed, and the correct potential is applied to BL1 to cause the fluctuation. Since the signal is repaired, in the image display device, the potential is written in a state where the potential of the signal line on the boundary line of the block is fluctuated by the parasitic capacitance between the signal line and the adjacent signal line. This has the effect of reducing the problem that the display state is different from the surroundings despite the supply of the same potential as the surroundings.

In addition, the image display device of the present invention can be configured to transmit a data signal from the data transfer unit to the pixels on the matrix by using any one of the data transmission methods described above.

As a result, as described above, the phenomenon that the pixels on the boundary line are written while being subjected to the fluctuation of the potential and the data is held for the display period does not occur. Despite this, it is possible to reduce the problem that the display state is different from the surroundings.

The signal line driving circuit of the present invention samples input data for one block, which is continuously input in time series and corresponds to n signal lines, by n sampling units to obtain n sampled data. After the accumulation, the signals are output to corresponding signal lines, respectively, and the n sampling units are grouped, and one of the blocks whose sampling order of the input data is the second or later for the same scanning line is BL2. When the group having the sampling unit to which the first sampling data Db1 of the block BL2 is input is defined as GRa, the group GRa determines the sampling data of the block having a sampling time earlier than that of the block BL2 for the same scanning line. After accumulation, the sampling data Db1 is input at the latest. In until, in the group GRa, is configured to generate a group control signal defining the timing of providing a blank sampling unit for storing the sampled data Db1 for each group.

Further, the signal line drive circuit of the present invention samples input data of one block, which is continuously input in time series and corresponds to n signal lines, to the image display device by n sampling units. After accumulating as n pieces of sampling data, each is output to a corresponding signal line, and the n number of sampling units are divided into groups, and the sampling order of the input data is the second or later for the same scanning line among the blocks. Is a group having a sampling unit to which the first sampling data Db1 of the block BL2 is input, and GRa is a group having the same scanning line than the block BL2 for the same scanning line. Accumulates the sampling data of the earlier block, Until the input of the sampling data Db1, a group control signal that defines the timing for preparing an empty sampling unit for storing the sampling data Db1 in the group GRa can be generated for each group. .

Thus, when there are n input lines to the signal line, the sampled data signal is transferred to the signal line after sampling the nth data signal and before again sampling the first data signal. Or, time for latching is not required. Therefore, it is not necessary to particularly process the data signal according to the time for the transfer or the latch, so that the data can be transmitted quickly and processed at a high speed with a simple configuration. It works.

In addition, in addition to the above configuration, the signal line driving circuit of the present invention may be configured such that at least one of the blocks, each of which has a signal line adjacent to each other, has earlier application of the data signal. When the block of BL1 is BL1 and the block of the later is BL2, each sampling unit has a plurality of systems for accumulating the sampling data, and the sampling data of the block BL1 is sampled by a certain group GR1. The data is accumulated in one of the plurality of systems in the unit, and when the accumulation is completed, accumulation of the next sampling data is started in another group, and then accumulation of the sampling data of the next block BL2 is performed in the group GR1. Before the start of the operation, the system to be the next storage destination in the group GR1 is A signal defining a timing for switching to no accumulated data system is configured to generate as the group control signal.

Accordingly, even if a plurality of systems are provided for each signal line in one block and storage / output is switched between the systems, the group for performing the storage processing is switched and the data signal between the groups is transferred to another group. Sampling can be reliably performed, and data can be reliably prevented from being missed. In addition to the effects of the above configuration, data can be transmitted quickly with a simpler configuration, and data can be processed at high speed. This has the effect.

In addition, in addition to the above configuration, when one of the groups is set to GR1, the signal line driving circuit of the present invention stores the sampling data in at least this group GR1, and then stores the sampling data in another group. During accumulation, a signal that defines the timing for outputting the sampling data accumulated in the group GR1 is generated as the group control signal.

This eliminates the need to provide a plurality of systems for each signal line in one block and switch between accumulation and output between the systems, and eliminates the need for time for switching. With a simpler configuration, data can be transmitted quickly and data can be processed at high speed.

[Embodiment 1]
An embodiment of the present invention will be described below with reference to FIGS. In the present embodiment, the data transmission device is a liquid crystal display device as a display device which is an active matrix substrate (matrix section), has scanning lines, signal lines, and pixel electrodes, and is driven by an active matrix system. is there. The equivalent circuit will be described with reference to FIG.

Each of the pixel electrodes is provided with pixels A ₁ , B ₁ ,... As a data processing unit, and is connected to a pixel switching element such as a TFT (thin film transistor) (not shown). These pixels are composed of liquid crystal, and they constitute a liquid crystal panel. The liquid crystal panel constitutes a liquid crystal display device that displays an image. Actually, many signal lines and members corresponding to them are provided in addition to those shown in the figure, but here, for convenience of explanation, the signal lines are simplified to f ′ , F, a, b, c, d, e, and e ′, and similarly, only _two scanning lines g ₁ and g ₂ .

One block (referred to as a first block) is constituted by the 'signal lines f', f, a, and b. Another block (referred to as a second block) is constituted by the signal lines c, d, e, and e '. In the present embodiment, a configuration of two blocks will be described. However, it is not limited to this.

Signal line switching elements (SWa, SWb, SWc, SWd, etc.) are provided at the ends of the signal lines f ', f, a, b, c, d, e, e' as shown in FIG. The other end is electrically connected to a signal line drive circuit (data transfer section) 1 as a signal input section for mounting an external circuit, and a signal line is provided between the signal line drive circuit 1 and the switching element. A branch 7 is provided. The signal line switching element can be constituted by a CMOS transistor, or in some cases, an NMOS transistor. Further, the signal line branching unit 7 can be configured by branching wiring.

These signal line switching elements are electrically connected to output lines s ₁ , s ₂ , s ₃ , and s ₄ extending from the output end of the signal line drive circuit 1, respectively. To the control terminal such as the signal line switching element SWa is controlled wire SW ₁ and SW ₂ switches conduction and non-conduction of the signal line switching elements are connected in common to each of a plurality of blocks, by switching to such An image signal (data signal) from the signal line driving circuit 1 is supplied to the signal line in a time sharing manner as a display signal.

That is, a signal line or a scanning line is divided into blocks, and when a signal line is used, a certain scanning line is selected (one selection period of a scanning line, one horizontal period), and when a scanning line is used, one vertical period is used. The block to which the signal is applied is switched over with time so that the data signal and the scanning signal are sequentially applied to each block. In this embodiment, in this embodiment, a signal line is divided into blocks, one selection period of a scanning line is time-divided, and a block to which a signal is applied is changed with time so that a data signal is sequentially applied to each block. I try to switch. When the scanning line is divided into blocks, a block to which a signal is applied may be switched over time so that one vertical period is time-divided and a scanning signal is sequentially applied to each block.

The control wires SW ₁ and SW ₂ are controlled the output by conduction control unit. FIG. 11 shows a configuration example of such a conduction control unit. HSY is a horizontal synchronization signal synchronized with the image. A clock (CLK) is generated by a PLL (phase-locked loop) oscillator 21. The HSY and the clock CLK, H counter ( "H" is the designation herein for "horizontal".) In counted at 22, each decoder based on the value of the counter (SW ₁ decoder 23, SW ₂ decoder 24) Create each pulse. Each decoder is set to a predetermined value in advance, and outputs each pulse according to the value. Predetermined value, such as s _1, etc. g _2, each pixel or, to determine the individual parameters, such as SWa, previously optimized.

FIG. 12 shows another configuration example of the conduction control unit. That is, HSY and CLK are input to the H counter 31 instead of generating the clock CLK by the PLL oscillator 21 of FIG. CLK is synchronized with the dot data of the image. Otherwise, it is the same as FIG.

Next, the configuration of the signal line driving circuit 1 will be described. An example is shown in FIG. FIG. 19 shows a timing chart thereof. As shown in FIG. 18, a sampling circuit (sampling section) at the input of the data line DAT to the output of the S ₁ is configured, the sum n sampling circuits are provided. In the drawing, for convenience, only the first sampling circuit 71 and the n-th sampling circuit 72 are illustrated as representatives.

Data line DAT is input branches into n sampling circuits (sampling section) from each sampling circuit, so the image signal is output to the signal line via the output terminal (S _1, etc.) I have. The data line DAT supplies an image signal, which is a data signal to be displayed on a pixel, to the signal line driving circuit 1. Assuming that the number of outputs is n (n-line output), if the number of blocks is two as described above, the number of signal lines is 2n because the number of signal lines is the product of them. The image signal supplied from the data line DAT is sampled from the first (output terminal S ₁ ) to the n-th (output terminal S _n ) at each timing from the sampling signal (sampling pulse) SAM ₁ to SAM _n. The image signal is branched by the signal line branching unit 7 and sent to 2n signal lines. The sampling signals SAM ₁ to SAM _n can be generated in the signal line driving circuit 1 by a shift register.

(4) The analog switches ASWA and ASWB are connected to the data line DAT as the first output. Here, the data line DAT has a role of transmitting an analog signal. The analog switches ASWA and ASWB are both connected to transmit an image signal input to the data line DAT to the analog switch ASWD. Further, under the control of the analog switch ASWC, the input from the data line DAT is sent to the analog switch ASWD via only one of ASWA and ASWB.

In the input system of the image signal as the data signal, the system via the analog switch ASWC / ASWA / ASWD is called the system A (indicated by DA in the drawing), and the system via the analog switch ASWC / ASWB / ASWD is the system B ( (Indicated by DB in the figure). In other words, the data line DAT has a form in which signal paths A and B are arranged in two lines in parallel.

A sampling and holding capacitor C _SHA is arranged between the analog switch ASWA and the analog switch ASWD. Similarly, a sampling and holding capacitor C _SHB is arranged between the analog switch ASWB and the analog switch ASWD. RL is a reference potential.

Analog switches ASWC a sampling signal SAM ₁ is input and is also the switching control by the control signal CNT0.

The analog switch ASWD outputs an image signal to the output buffer Bu, and is switched by a control signal CNT. The output from the output buffer Bu becomes the _first output terminal S1.

LEV is used when the level to be charged in advance is set to a desired charging voltage, as in the case of FIG. 4 (and FIG. 22 described later). That is, the desired charging voltage may be input to the signal LEV, or the signal LEV may be used as a switching timing signal to perform switching to a desired voltage. This will be described later.

出力 The second and subsequent outputs are performed in the same manner as the first output.

The following operation is performed to drive an active matrix substrate having 2n signal lines. That is, while the display signal corresponding to the first block (data displayed on the left half of the screen) 11 in FIG. 3 is being supplied, the sampling signals (SAM _{1 to} SAM _n ) supplied from the shift register are sequentially supplied. Is done. At this time, the control signal CNT0 has selected the A system (indicated by DA in the figure). Therefore, the analog switch A (ASWA) is turned on, and the data signal of the first block is accumulated in the sampling and holding capacitor (C _SHA ).

When the selection up to SAM _n is completed, the control signal CNT0 is switched to the B system (indicated by DB in the figure), and the sampling signals (SAM _{1 to} SAM _n ) are sequentially supplied again and the image signal is supplied. . While the signal is stored in the B system, the control signal CNT selects the A system and outputs the data signal stored previously.

In the above configuration of Figure 18, (time t ₅ the vicinity of Figure 19) a predetermined period for which the control signal CNT0 is switched to the B lineage from the system A stores the data signals for both sampling and hold capacitor system A · B system I can't. Here, in general, an image signal is supplied from the outside for one horizontal line continuously in time series. Therefore, in the configuration of FIG. 18, if the time required for switching the sampling system between the A and B systems cannot be ignored compared with the supply interval of the image signal, the data signal at the boundary between the first block and the second block is The display will be skipped. In order to avoid this, some processing is performed on the image signal itself to provide a blank period corresponding to the time required for the system switching.

On the other hand, in the configurations shown in FIGS. 5, 7, and 9 below, sampling is performed by the sampling signal SAM ₁ continuously after the sampling signal SAM _n , but it is necessary in the configuration of FIG. No blank period for latching and transfer is required. That is, to sample the horizontal pixel number one roll (1 horizontal pixel of the image display device), it is necessary to use one signal line driving circuit 2 degrees or more, the sampling signal SAM _n immediately after completion continuously Although will be sampled by a sampling signal SAM _1, in the case of the configuration of FIG. 18, time transfer of the data signal on the relationship between required time is required spacing between the SAM _n and SAM ₁ On the other hand, in the configuration as shown in FIGS. 5, 7, and 9, the group control signal is made different between the first half and the second half of the output number, so that the image signal itself is processed in order to provide the above-described blank period. Such continuous sampling can be performed without devising, for example, performing the following.

構成 The configuration example of FIG. 5 will be described. This is different from FIG. 18 in the configuration of the signal for controlling the sampling. In the drawing, for convenience, only the first sampling circuit 15 and the n-th sampling circuit 16 are illustrated as representatives.

Assuming that the number of outputs is n (n-line output) as described above, in the configuration of FIG. 5, unlike the configuration of FIG. 18, the first (S ₁ ) to the (n / 2) -th (S _{n / 2} ) And the second group from the (n / 2 + 1) th ( _{Sn / 2 + 1} ) to the nth ( _Sn ). Here, it is assumed that n is an even number. From the first (S ₁ ) to the (n / 2) -th (S _{n / 2} ), the analog switch ASWC is controlled by the group control signal CNTa for the first half line, and the (n / 2 + 1) -th (S _n ) _{/ 2 + 1)} from to n-th (S _n), the analog switch ASWC is controlled by the group control signal CNTb for late line. In other words, the group control signal for switching the sampling signals SAM ₁ ~ sampling signal SAM _n in system A · B strains, two types presence of CNTa · CNTb. In addition, this switching between CNTa and CNTb is performed almost in the vicinity of SAM _{n / 2} . This is followed immediately after SAM ₁ ~SAM _n ends, is for sampling from SAM _1, in order to eliminate the need to particularly process the data signals entering the data line. The other configuration is the same as that of FIG.

(6) A timing chart is shown in FIG. In the figure, the system selected by the group control signals CNTa, CNTb, and control signal CNT is shown in parentheses. That is, the period for selecting the A system is indicated by (DA), and the period for selecting the B system is indicated by (DB). Also, the output level of the LEV is fixed during the high period shown in the figure, and the effect is the same as in the case of FIG.

Thus, in this configuration, unlike the configuration of FIG. 18, the sampling signals are divided into two groups. That is, the n sampling circuits (sampling units) are connected by dividing them by half, corresponding to the group control signals CNTa and CNTb. Then, half (n / 2 lines) of the data signals of the first block 11 (see FIG. 3) are transmitted at the timing of SAM ₁ to SAM _{n / 2} by selecting the A system in the group control signal CNTa which is a control signal therefor. _Stored in C _SHA . Next, the remaining n / 2 data signals are stored in the C _SHA of the corresponding sampling circuit at the timings of SAM _{n / 2 + 1} to SAM _n. The signal CNTb selects the A system before the timing of SAM _{n / 2 + 1} . Even if the selection is made in advance, there is no effect while SAM _n is not selected from SAM _{n / 2 + 1} .

Then, the SAM n / 2 _{+ 1} When SAM _n starts to be selected, this time the group control signal CNTa selects the B-type, the upcoming second block (data displayed on the right half of the screen) 12 image signals Ready to hold. Of course, during the selection of SAM _{n / 2 + 1} to SAM _n , the first to n / 2th sampling circuits are only on standby, and no actual sampling is performed. When the selection up to SAM _n is completed, the sampling signals (SAM _{1 to} SAM _n ) are sequentially supplied again, and the image signals are supplied. Then, while the signal is stored in the B system, the control signal CNT selects the A system and outputs the stored data signal. With such a configuration, the sampling of the next block from SAM ₁ can be started immediately after the sampling up to SAM _n is completed. As a result, since the image signal of the first block 11 and the image signal of the second block 12 are continuously transmitted, the sampling of the signal of the first block up to SAM _n is completed and the data of the second block is immediately transmitted. Even if signals are continuously transmitted, a data signal (image signal) can be captured without any problem.

Next, a configuration example of FIG. 7 will be described. This is different from FIGS. 5 and 18 in the configuration of the sampling circuit. In the drawing, for convenience, only the first sampling circuit 17 and the n-th sampling circuit 18 are illustrated as representatives. ASWS is an analog switch for sampling. ASWH is an analog switch for hold. _CS is a sampling capacitor. C _H is a hold capacitor.

Grouping is the same as in FIG. That is, if the number of outputs is n (n-line output) as described above, unlike the configuration of FIG. 18, the first (S ₁ ) to (n / 2) -th (S _{n / 2} ) first groups And the (n / 2 + 1) -th (S _{n / 2 + 1} ) to n-th (S _n ) second groups. Here, it is assumed that n is an even number. From the first (S ₁ ) to the (n / 2) -th (S _{n / 2} ), the analog switch ASWH is controlled by the group control signal CNTa for the first half line, and the (n / 2 + 1) -th (S _n ) _{/ 2 + 1} ) to the n-th (S _n ), the analog switch ASWH is controlled by the group control signal CNTb for the latter half line. In other words, the group control signals for controlling the sampling of the sampling signals SAM ₁ ~ sampling signal SAM _n is two kinds presence of CNTa · CNTb. The transfer of the first group is performed almost in the vicinity of SAM _{n / 2} . This is followed immediately after SAM ₁ ~SAM _n ends, is for sampling from SAM _1, in order to eliminate the need to particularly process the data signals entering the data line. Otherwise, it is the same as FIG.

FIG. 8 shows a timing chart. In the drawing, periods during which image signals are transferred by the group control signals CNTa and CNTb are indicated by T ₂₁ and T ₂₂ respectively. Further, LEV is the output level is fixed in the period T _23, the effect is the same as in FIG. 18.

Thus, in this configuration, unlike the configuration of FIG. 18, the sampling signals are divided into two groups. That is, the n sampling circuits (sampling units) are connected by dividing them by half, corresponding to the group control signals CNTa and CNTb. Then, the data signal half (n / 2 duty) of the first block 11 (see FIG. 3) at the timing of the SAM _{n / 2} from the SAM _1, it is accumulated in the C _H of the corresponding sampling circuit. Then the data signal of the remaining n / 2 duty at the timing of the SAM _n from SAM n / 2 _{+ 1,} is accumulated in the C _H of the corresponding sampling circuit.

When the data signal from the SAM n / 2 _{+ 1} is selected SAM _n starts to be accumulated, the group control signals CNTa a control signal, the SAM n / ₂ data signals from the SAM ₁ accumulated in the C _H The image signal is transferred (period T ₂₁ ), and ready to hold the image signal of the coming second block (data to be displayed on the right half of the screen) 12. Of course, during the selection of SAM _{n / 2 + 1} to SAM _n , the first to n / 2th sampling circuits are only on standby, and no actual sampling is performed. When the selection up to SAM _n is completed, the sampling signals (SAM _{1 to} SAM _n ) are sequentially supplied again, and the image signals are supplied. When the data signal from the SAM ₁ is selected SAM n / ₂ starts to be accumulated, the group control signals CNTb a control signal from the SAM n / _{2 + 1} accumulated in C _H data signal SAM _n is transferred (time period T _22). With such a configuration, the sampling of the next block from SAM ₁ can be started immediately after the sampling up to SAM _n is completed.

As described above, the configuration in FIG. 7 has two capacitors in series instead of having two sampling systems in parallel for each output in the configurations in FIG. 5 and FIG. By transferring the data, output and signal capture can be performed simultaneously. In the configuration of FIG. 18, the number of control signals for hold transfer is one (control signal CNT0). On the other hand, in the example of FIG. 7, this is divided into two (group control signals CNTa and CNTb) as in the case of FIG. In the signal capture of the first block, while the sampling signals SAM _{n / 2 + 1} to SAM _n are selected, the data signals of SAM ₁ to SAM _{n / 2} are transferred, and Preparations for holding the image signal are completed. As a result, since the image signal of the first block 11 and the image signal of the second block 12 are continuously transmitted, the sampling of the signal of the first block up to SAM _n is completed and the signal of the second block is immediately transmitted. Even if the data signal is continuously transmitted, the data signal (image signal) can be captured without any problem.

Next, a configuration example of FIG. 9 will be described. FIG. 9 shows the case of m-bit digital data. In the figure, for convenience, only the first sampling circuit 19 and the n-th sampling circuit 20 are illustrated as representatives. The data line DAT has a role of transmitting a digital signal. The number of gradations is m bits. In the figure, an image signal input from the left end terminal is branched, and is sequentially input to m data lines, that is, m data lines DAT, two D-type flip-flops, and a D / A converter DAC. Output (S ₁ , S ₂ ,..., S _n ).

Grouping is the same as in FIGS. That is, if the number of outputs is n (n-line output) as described above, unlike the configuration of FIG. 18, the first (S ₁ ) to (n / 2) -th (S _{n / 2} ) first groups And the (n / 2 + 1) -th (S _{n / 2 + 1} ) to n-th (S _n ) second groups. Here, it is assumed that n is an even number. The first (S ₁ ) to the (n / 2) th (S _{n / 2} ) are controlled by the group control signal LSa for controlling the latch for the first half line, and the (n / 2 + 1) -th (S _{n / 2 + 1} ) to the n-th (S _n ) are controlled by the group control signal LSb for controlling the latch for the first half line. In other words, the group control signals for controlling the sampling of the sampling signals SAM ₁ ~ sampling signal SAM _n is two kinds presence of LSa · LSb. The transfer of the first group is performed almost in the vicinity of SAM _{n / 2} . This is followed immediately after SAM ₁ ~SAM _n ends, is for sampling from SAM _1, in order to eliminate the need to particularly process the data signals entering the data line. Otherwise, it is the same as FIG.

FIG. 10 shows a timing chart. In the drawing, the timings at which the group control signals LSa and LSb transfer the image signals are indicated by t ₃₁ and t ₃₂ , respectively. Further, LEV is the output level in the period T ₃₃ is fixed, the effect is the same as in FIG. 18.

Thus, in this configuration, unlike the configuration of FIG. 18, the sampling signals are divided into two groups. That is, the n sampling circuits (sampling units) are divided and connected in half corresponding to the group control signals LSa and LSb. Then, the data signal half (n / 2 duty) of the first block 11 (see FIG. 3) at the timing of the SAM n / ₂ from the SAM _1, stored in the two D-type flip-flops for the appropriate sampling circuit You. Next, the remaining n / 2 data signals are accumulated in the two D-type flip-flops of the corresponding sampling circuit at timings SAM _{n / 2 + 1} to SAM _n .

Then, SAM n / 2 _{+ 1} from the data signal SAM _n is selected starts to be accumulated, controlled by the signal at a group control signal LSa, 2 two SAM n / ₂ from the SAM ₁ accumulated in the D-type flip-flop Is transferred (time t ₃₁ ), and the image signal of the upcoming second block (data to be displayed on the right half of the screen) 12 is ready to be held. Of course, during the selection of SAM _{n / 2 + 1} to SAM _n , the first to n / 2th sampling circuits are only on standby, and no actual sampling is performed. When the selection up to SAM _n is completed, the sampling signals (SAM _{1 to} SAM _n ) are sequentially supplied again, and the image signals are supplied. Then, when SAM ₁ to SAM _{n / 2} are selected and their data signals start to be accumulated, the group control signal LSb, which is a control signal, causes SAM _{n / 2 + 1} to SAM _n accumulated in the two D-type flip-flops. Is transferred (time t ₃₂ ). With such a configuration, the sampling of the next block from SAM ₁ can be started immediately after the sampling up to SAM _n is completed.

As described above, the configuration of FIG. 9 has two D-type flip-flops in series instead of having two sampling systems in parallel for each output in the configurations of FIGS. By transferring the data for each capture, output and signal capture can be performed simultaneously. In the configuration of FIG. 18, the number of control signals for hold transfer is one (control signal CNT0). On the other hand, in the example of this figure, this is divided into two (group control signals LSa and LSb) as in the case of FIGS. In the signal capture of the first block, while the sampling signals SAM _{n / 2 + 1} to SAM _n are selected, the data signals of SAM ₁ to SAM _{n / 2} are transferred, and Preparations for holding the image signal are completed. As a result, the image signal of the first block 11 and the image signal of the second block 12 are continuously transmitted, so that the sampling of the signal of the first block up to SAMn is completed and the data of the second block is immediately transmitted. Even if signals are continuously transmitted, a data signal (image signal) can be captured without any problem.

FIG. 13 shows an example of the configuration of the generation unit of the control signal CNT and the group control signals CNTa / CNTb. VSY is a vertical synchronization signal synchronized with the image. The input signal to the H counter 41 is the same as in the examples of FIGS. From the H counter 41, a pulse of one horizontal cycle is input to the V counter 42 (“V” represents “vertical” in this case). Counting is performed, and each decoder (CNT decoder 43, CNTa decoder 44, and CNTb decoder 45) generates each pulse based on the value of the counter. Note that the control signal CNT0 of FIG. 18 can be generated in the same manner as the group control signals CNTa and CNTb. In the configuration of FIG. The configuration may be deleted. Each decoder outputs a pulse according to a preset predetermined value, as in the examples of FIGS. Further, each predetermined value differs depending on the number of output lines of the driver and the like, and is determined and optimized based on these. Note that a configuration having a PLL oscillator as in FIG. 11 is also possible.

In the case of FIG. 13, each decoder operates in consideration of the output of the V counter. This can be created only from the H counter as shown in FIGS. 11 and 12 if a pulse that changes periodically at the same timing in one horizontal period is generated. This is because it is not necessary to use the V counter (a counter that counts in one horizontal cycle) since the same change does not occur at the same timing in the above.

FIGS. 14 to 17 show configuration examples of the output buffer Bu. FIG. 14 shows a case where a desired charging voltage is input to the signal LEV in the configurations of FIGS. 5, 7, and 18. FIG. 15 shows a case where switching to a desired charging voltage Vd is performed using the signal LEV as a timing signal in the configurations of FIGS. 5, 7, and 18. 14 and 15, ASWD is the case of FIGS. 5 and 18, and in FIG. 7, it is not ASWD but ASWH. A signal from ASWD is input to an OP amplifier (operational amplifier) 51. In FIG. 14, the LEV is input as it is to the changeover switch 52 as a desired charging voltage, and is input to the changeover switch 52 via the level shifter 53 as a signal indicating a changeover timing. In FIG. 15, the LEV is directly input to the changeover switch 52 as a signal indicating the changeover timing, and the desired charging voltage Vd is input to the changeover switch 52.

FIGS. 16 and 17 show examples of the configuration of a D / A (digital / analog) converter DAC. FIG. 16 shows a case where a desired charging voltage is input to the signal LEV in the configuration of FIG. FIG. 17 shows a case where switching to a desired charging voltage Vd is performed using the signal LEV as a timing signal in the configuration of FIG. In each of the n sampling circuits in FIG. 9, the signal DFF immediately before the DAC, that is, the signal DFF from the Q output of the second-stage D-type flip-flop is input to the digital-to-analog converter 61. In FIG. 16, the LEV is directly input as a desired charging voltage to the changeover switch 62, and is input to the changeover switch 62 via the level shifter 63 as a signal indicating a changeover timing. In FIG. 17, the LEV is directly input to the changeover switch 62 as a signal indicating the changeover timing, while the desired charging voltage Vd is input to the changeover switch 62.

Above, basically, it is relatively easy to configure by using a changeover switch. The above-mentioned desired charging voltage Vd can be inputted from outside the source driver (signal line driving circuit 1). However, the operating power supply of the source driver may be directly applied or a voltage obtained by dividing the resistance from the operating power supply may be used. By doing so, it is possible to save the trouble of taking power from the outside of the driver.

In each of the configurations shown in FIGS. 5, 7, and 9, the sampling circuits need not be strictly divided into half groups, but may be a plurality of groups. Further, the number of groups is not limited to two. More specifically, the number may be divided into desired numbers based on the switching time determined by the clock frequency and the switching speed of each analog switch (such as ASWA). The reason why the boundary of grouping is set to n / 2 in this example is that the margin can be secured most.

Next, the data transmission operation and the state of the image signal according to the above configuration will be described. Note that the display screen will be described as a three-tone vertical stripe screen as shown in FIG.

First, a basic operation will be described. In order to make a signal line switching element (SWa or the like) conductive while a certain scanning line g ₁ (see FIG. 1) is selected, that is, while a certain row is selected. , the control wires SW ₁ and SW _2, in turn, the pulse from the decoder shown in FIG. 11 and FIG. 12 (a signal line switching element control signal) is sent. The first, the signal line switching element SWa, SWb becomes conductive by selection of the SW _1. Thus, the image signal from the signal line driving circuit 1 is supplied to the signal lines a and b. Since the scanning line g ₁ is selected, it is written to the pixel A _1, B _1. At this time, since the SW ₂ is not selected, the signal line c, the image signal is the d is not supplied. Then, SW ₁ becomes unselected, SWa, since SWb becomes nonconductive, the signal lines a, b and the pixel A _1, B ₁ is in a state of holding. The SW ₂ is selected and the signal line switching element SWc, SWd is turned, since the image signal from the signal line drive circuit 1 is a signal line c, is supplied to the d, the scanning line g ₁ is selected, These are written to the pixels C ₁ and D ₁ , respectively.

The scanning lines g ₁ and g ₂ are supplied by the scanning line driving circuit 2 as shown in FIG. 3, and the signal lines are supplied from the signal line driving circuit 1 so that the vertical stripes become thinner in the display regions 3, 4, and 5 in this order. Supply image signal. FIG. 2 shows the state of the image signal at this time. In this embodiment, prior to the normal image signal control line to select normal (t ₃ in FIG, t ₄₎ Timing supplies (data signal) to the signal line, in figure t _1, It has selected as t _2, allowed to reverse the polarity of the advance signal line. Here, regarding the selection of the control wirings SW ₁ and SW _2, the selection as usual and the previous selection are distinguished from each other by referring to normal and pre-line, respectively. In this embodiment, as described above, while one scanning line is ON and one row is selected (selection period, one horizontal period), each row (each row of scanning lines g ₁ , g _2, etc.) Prior to the end of the period in which the image signal is normally applied as normal conduction to the first block 11 (signal lines f ′, f, a, and b), the signal lines c, d, and e belonging to the second block 12. , E ′ are conducted as pre-conduction conduction, and the polarity is inverted. When timing t ₂ when the SW ₂ is selected, but receives a push-up signal line b as in the conventional configuration shown in FIG. 26, the normal timing of the image signal is a t _3, the signal at this time correct potential is supplied by a write to the signal line via the line switching element, the scanning line g ₁ this state is maintained until the non-selected. Therefore, the problem that the boundary is visually recognized as described above is solved.

In the driving method of FIG. 2, as shown in FIG. 2, when image signals are divided into sections T ₁ and T _{2 in} the order of time in one selection period of a scanning line, an image supplied in time series is obtained. to the signal, capture by the first block first signal line driver circuit 1 in multiplexer image signal at intervals T _1, then at intervals T ₂ and so captures an image signal of the second block, sequential signal line driver circuit 1 to the signal line.

By the way, at the timing of t _4, a potential different from that written at t ₂ is applied to the signal line c. Therefore, there is a possibility that the signal line b receives a depression corresponding to this potential difference. Is sufficiently smaller than the polarity reversal of the image signal, and is often invisible to the naked eye. However, if the swing of the signal line b due to the potential difference is at the visual recognition level due to the magnitude of the parasitic capacitance Csd, it is effective to provide an image signal as shown in FIG. This will be described below.

That is, a desired voltage is applied separately from the output signal (image signal) from the signal line driving circuit 1 at the polarity inversion time of the pre-run. In the signal driving method as shown in FIG. 4, a memory function for storing such a desired voltage is added to the signal line driving circuit 1. Specifically, the signal LEV shown in FIGS. 5, 7, and 9 is used. That is, as described above, a desired charging voltage is input to this signal LEV. In this case, the desired charging voltage included in the signal LEV is changed from the signal strength of the first block 11 at the normal polarity inversion time to the signal strength of the second block 12 at the normal polarity inversion time. This is the signal strength that has been increased or decreased. Further, here, as the desired charging voltage to be included in the signal LEV, a signal having the same potential as that applied at the normal polarity inversion timing of the second block 12 for performing the polarity inversion of the pre-run is supplied. I have.

Alternatively, as described above, switching to the separate desired voltage (Vd) may be performed according to the input timing of the signal LEV.

As described above, the image signals corresponding to the first block 11 and the second block 12 are supplied to the output lines s _{1 to} s ₄ corresponding to the timings of t ₁ and t ₂ , respectively, as described above. After the signal line is set to a substantially predetermined voltage, writing to the signal line and the pixel is accurately performed at timings t ₃ and t ₄ . Herein, generally refers to the boundary corresponding to the signal lines during t ₃ and t ₄ are intended to refer to a degree that does not undergo rocking, so that exactly reach the same potential as the output line s ₁ ~s ₄ No need. That is, the length of the period in which the signal line is selected (the data signal is applied) at the timings of t ₁ and t ₂ may be short to some extent.

Also, depending on the time restriction of the signal fetch in the signal line driving circuit 1, the image signals of one line before or one frame before are supplied to t ₁ and t ₂ by appropriately adjusting the polarity and supplying the same to t ₁ and t _2. The effect of is obtained.

In the configuration shown in FIG. 18 described above, while the CNT0 is measuring display signal interval T ₁ by selecting the system A to the sampling hold capacitor C _SHA · C _SHB, section CNT selects the B lineage T ₂ display signal is output. Such a configuration is limited to the case where data signals supplied in time series are output without changing the order. When driving as shown in FIG. 4 is performed, one is output while the other is taken in. Since it is not possible to acquire the data signals of the two systems at a higher speed and then output them at desired timings, increase the number of sampling and holding capacitors (C _SHA , C _SHB ) in parallel, or supply the data signals It is necessary for the executor to have some sort of memory function.

Incidentally, in the configuration of FIG. 18, CNT0 at time t ₅ (see FIG. 19) selects the B-type, start capture new data signal, but it by reversing the polarity prior, of t _3, t ₄ Prior to the selection time, the B-system signal one line before is supplied with the same polarity. Of course, before this, the preceding scanning line signal must be turned off. In the case of a structure in which driving is performed by dividing into a larger number of blocks, a structure such as increasing the number of sampling and holding capacitors in parallel or adding a memory function to the data signal supply side is required instead of this method. .

It is highly probable that the display signal one line before is stochastically in the same display state as the line, and even if it is the boundary where the display in the vertical direction changes, it is more likely that the display signal is written in the opposite polarity as in the conventional example. Since the fluctuation of the voltage is extremely small, and the above-mentioned display problem occurs only in one pixel, the possibility of visual recognition is extremely low.

In the case where the signal line driving circuit 1 has a line memory functioning as the above-mentioned memory function, it is possible to further supply the display signal of the previous frame with only the polarity. In this case, since the above-described display failure occurs only at the moment when the display state of the previous frame is switched, it is impossible to visually recognize the boundary of the block.

Although SW ₂ is applied destination unselected SW ₁ is selected by the image signal is push-up also similar at the moment of switching to the first block from the second block occurs, during selection of the scanning line g ₁ following since SW ₂ at the timing is rewritten to the correct potential is selected, there is no display on the problems with the pixel C _1. Although swinging by Csd during non-conduction of the scanning lines g ₁ is the difference by a signal line to couple the pixel and the capacitance, there is no difference as the effective value of the entire display period, no problems.

According to the present embodiment, it is possible to prevent the deterioration of the display quality due to the fluctuation of the potential of the signal line in this manner. In the present embodiment, the case of two blocks has been described. However, the same applies to the case of driving with more blocks.

In the present embodiment, thus, firstly, if the two blocks, as shown in FIG. 2, among the two ON (High) periods of the control wire SW ₁ during one selection period of the scan line, a polarity inversion period of the dry run, time ON although starting at time t _1, the time OFF and a _1, b _1, respectively, a polarity inversion period of the regular, ON timing although starting at time t _3, the timing OFF each c _1, and d _1. Similarly, of the two ON (High) periods of the control wire SW ₂ in the same period, but starting from time t ₂ ON time, and the time OFF respectively a _2, b _2, ON timing although starting from time t ₄ , OFF timing are c ₂ and d ₂ , respectively. At this time, first, b ₂ ≦ d ₁
And Here, b ₁ ≦ a ₂ ,
d ₁ ≦ c ₂
And Here, it is further assumed that b ₂ ≦ c ₁ .

Similarly, it is assumed that there are N blocks (N is an integer of 2 or more) and the first, second, third,... FIG. 20 shows a configuration example when the number N of blocks is four. That is, as the control _{line, SW 1, SW 2, SW} 3, SW 4 of four is used. At this time, assuming that k is an arbitrary integer not less than 2 and not more than N, for the k-th block, of the two ON (High) periods of the control wiring SW _k during one scanning line selection period, the polarity reversal period of the pre-row is selected ON timing although the timing OFF and a _k, b _k, respectively, although a polarity inversion period of the normal ON time, c _k a timing OFF respectively, and d _k. Here, if it is assumed that d _k-1 ≤c _k , that is, the normal polarity inversion timing (regular data signal application timing) becomes late as the number advances, then b _k ≤d _k-1
And Here, b _k-1 ≦ a _k
That is, as the number advances, the start timing of the polarity reversal of the pre-feed is made later than the end timing of the polarity reversal of the pre-feed one block before. In addition, on the contrary,
b _k ≦ a _k-1
In other words, as the number advances, the end time of the polarity reversal of the pre-feed can be made earlier than the start time of the polarity reversal of the pre-feed one block before. In any case, it is also possible to arrange such that there is an overlap time between the polarity inversion periods of the pre-runs between arbitrary adjacent blocks.

Also, b _N ≦ c ₁ , that is, the end time of the pre-inversion period of the Nth block may be the same as or earlier than the start time of the normal inversion period of the first block. In addition, it is not limited to this. However, it is preferable that the end time of the polarity inversion of the pre-feed of the last N block be before the start time of the normal polarity inversion (data signal application) of the first first block. This is because when a certain block supplies a normal data signal and the signal line switching element (SWa or the like) of another block is on, each part in the signal line drive circuit 1 and the panel (liquid crystal panel), for example, This is because the load applied to the capacitance wiring (not shown) is doubled, and the charging characteristics of the block to which the data signal is normally supplied may be different from those of the other blocks due to the influence of signal delay or the like. However, depending on the driving capability of the signal line driving circuit 1, the magnitude of the load on the panel, and the set charging rate, in other words, depending on the resistance values of the pixel transistors and the signal line switching elements, there may be no problem. Such a configuration is shown in FIG. 24 described later.

Further, as shown in FIG. 3, when the block to which the data signal is applied by the conduction of the control wiring SW1 is the leftmost block (first block 11) of the screen, that is, the block where the normal data signal application timing is the earliest. In addition, the polarity inversion of the pre-run (the polarity inversion at the time t1) is unnecessary. However, in the actual operation, it is preferable that the charging rate and the like be more strictly matched between the blocks, so that the open times and waveforms (such as energization timings) of the control wiring SW ₁ , the control wiring SW ₂ ,... Is preferable. This is the same in any of the embodiments described later.

[Embodiment 2]
The following will describe another embodiment of the present invention with reference to FIGS. 21 and 22. For the sake of convenience of explanation, members having the same functions as those shown in the drawings of the above-described embodiment will be denoted by the same reference numerals, and description thereof will be omitted.

In the present embodiment, as shown in FIG. 21, prior to each block being selected, a plurality of blocks are once selected simultaneously, and the polarity of the signal lines is inverted. Although only two blocks are shown in the drawing, the effect seems to be small. However, in the case of driving with a large number of blocks such as four blocks, it is difficult to simultaneously select them and complete the polarity inversion of the signal line in a short time. This is important in ensuring sufficient time to supply an accurate potential to each subsequent block. The length of the period in which a plurality of signals are simultaneously selected may be such that the signal line at the boundary is not fluctuated as described above, and more specifically, may be twice the time constant given by the signal line switching element and the signal line capacitance. Is enough.

In the present embodiment, as described above, after limiting the driving to each block, prior to sequentially supplying the image signals to the respective signal lines, the signals are supplied simultaneously in advance, and the boundaries of the blocks are not visually recognized. In this way, an inversion signal is given in advance. As a result, it is possible to reduce display problems caused by fluctuations in potential due to Csd.

Incidentally, although it has been described above for receiving the lower thrust slightly signal line b by the potential of the signal line c at a timing t ₄ is changed, that this slight potential fluctuation is most prominently visible in the halftone It is when displaying. Conversely, when set so as not to be visible when the halftone is that it does not occur inconvenience in t _4. In Figure 21, the image signal written first Burokkuhe the t ₁ is given, instead, as shown in FIG. 22, by keeping supplying the image signal of halftone at t _1, the signal line potential variation at the timing of t ₄ when displaying the halftone line corresponding to the b and c is eliminated. Such a halftone image signal may be prepared as the signal LEV as described above. That is, as described in Embodiment 1 with reference to FIG. 4, the LEV is used when the level to be charged in advance is set to a desired charging voltage. In other words, the desired charging voltage may be input to the signal LEV, or switching to the desired voltage may be performed using the signal LEV.

The largest potential fluctuation occurs when a halftone voltage is applied to the signal lines b and c at t ₁ and a black or white voltage is supplied to the signal line c at t _4. even when, when the signal line b is the potential of the black or white in the t _3, the accident of the pixel B ₁ for the liquid crystal transmittance fluctuation is very small with respect to the potential variation is not visible, the signal line at t ₃ b There even when left halftone, since the pixel B ₁ represents corresponds to the boundary just switched tone of the left and right of the pixel, the potential variation is not visible.

When the definition is made as described in the first embodiment, in the present embodiment, if there are two blocks, first, b ₂ ≦ d ₁
And a ₁ = a ₂ , b ₁ = b ₂ ,
d ₁ ≦ c ₂
And Here, it is further assumed that b ₂ ≦ c ₁ .

Similarly, if there are N blocks,
b _k ≦ d _k-1
And then, also _{a 1 = a 2 = ... =} a N, b 1 = b 2 = ... = b N,
d _k-1 ≤c _k
And Further, here, as in the first embodiment, b _N ≦ c ₁ .

[Embodiment 3]
Another embodiment of the present invention will be described below with reference to FIGS. 23 and 24. For convenience of explanation, members having the same functions as those shown in the drawings of the above-described embodiment are denoted by the same reference numerals, and description thereof will be omitted.

In this embodiment, unlike the first and second embodiments, dare, has selected SW ₂ before the SW ₁ is switched to the non-selected, This is illustrated in Figure 23. even if the signal line c is the polarity inversion timing of t _4, since the signal line switching element SW ₁ of when the still signal line b is conductive, has become a voltage exactly the s ₄ is supplying, conventional As in the example, writing to the pixel is not performed while being pushed up, and the pixel is not fixed. Since it is not necessary to provide a period in which the switch SW2 is turned on in advance as in the first and _second embodiments, the time for writing to the normal voltage (voltage applied at the normal polarity inversion timing) via the signal line switching element is required. Can be increased. In general, the capacitance of a signal line is large, and it is often difficult to reduce the resistance of a switching element so that writing can be performed with a sufficiently small time constant. Therefore, in such a case, the driving method according to the present embodiment is used. Is very significant.

Also, since it is not necessary to generate a pulse or the like peculiar to the polarity inversion of the pre-run, the signal waveform of the control wiring is simplified. Thus, a signal generation circuit for controlling signal line driving can be simplified.

Here, depending on the performance and the impedance of wiring in the active matrix substrate of the signal line driver circuit, there is a case where the potential of the image signal output line s ₁ ~s ₄ at the moment of t ₄ in FIG. 23 is lowered. This is because the sudden load increases, although the constant time has elapsed return to a desired voltage, for t ₄ is just before the SW ₁ is not selected, the instantaneous voltage drop pixels In the final stage of writing to the memory, there is a possibility that the voltage may be fixed at the voltage that has been dropped. This will be described below.

Figure 24, in order to prevent this, allowed to polarity inversion of the signal line c to select the SW ₂ in the initial stage of the selection SW _1, then SW ₂ signal line f as a non-conductive, a, accurately to b supplying an image signal, a conducting again SW ₂ after SW ₁ becomes nonconductive, the signal lines c, d, to e and supplies the high precision image signal. Here in particular, a rehearsal conduction start timing of at SW _2, is made to coincide with the conduction start timing of the normal SW _1.

According to this method as well, the time for writing to the normal voltage via the signal line switching element can be increased, and the same effect as in FIGS. Further, in this method, unlike the method of Figure 23, since the taking sufficient time before the end of conduction of the normal SW ₁ from the end of the conduction of the dry run SW _2, the voltage drop as described above It can be effectively prevented and good charging characteristics can be obtained.

In the case of the multi-block driving method instead of the two-block driving method, if the driving method shown in FIG. 23 is used, a part of the period in which the immediately preceding block is selected (the polarity inversion period) is selected by the immediately succeeding block. 24, it is desirable that a part of the period in which the immediately preceding block is selected also overlaps with the period in which the immediately following block is selected. For example, speaking in Figure 24, the pulse SW ₁ starting at time t ₁₁ (period High), the pulse (period High) SW ₂ starting at time t ₁₂ and are overlapped. This is because the display state between adjacent blocks is relatively similar in many cases, and the voltage when the polarity is inverted in advance is often the same as the normal write voltage. This is because the influence of the swing caused by writing to the block after the block becomes non-conductive is often reduced.

As described above, in the example shown in FIG. 23, the normal polarity inversion periods of two blocks in which the data signal application timings are consecutive are shifted from each other so as to have overlapping timings. From a different point of view, as described in the first embodiment, each polarity inversion is defined by dividing the polarity inversion into the normal polarity inversion and the polarity inversion in the pre-run (see FIGS. 2, 21, and 24). It is assumed that the polarity reversal of the pre-run of the next block (second block) ends at the same time as the normal polarity reversal of the block (first block) ends, and then the normal polarity reversal of the second block starts. You can also.

In the example shown in FIG. 24, the polarity inversion of the pre-run of the next block (second block) is performed near the start timing of the normal polarity inversion of a certain block (first block). The configuration of FIG. 24 is modified so that the start timing of the polarity reversal of the pre-feed of the second block is earlier than the start timing of the normal polarity reversal of the first block. It is also possible to adopt a configuration in which the end time of the polarity inversion of the pre-run is also before the start time of the normal polarity inversion of the first block. Further, in FIG. 24, the start timing of the polarity reversal of the pre-feed of the second block is later than the start timing of the normal polarity reversal of the first block in FIG. Is possible before the end of the normal polarity inversion of the first block.

In each of the above embodiments, when the active matrix substrate is used for a color display device, it is desirable that the correspondence of the pixels to the output terminals of the signal line drive circuit does not differ between the blocks. This example, a drive of the two blocks, from the output line s _3, the first block pixel A ₁ receives an image signal, the second block pixel E ₁ (not shown) is set to receive an image signal In this case, both the pixel A ₁ and the pixel E ₁ display a red (R) color. This increases the probability that the voltage of the line in the preceding block is supplied to the signal line when the polarity is inverted prior to the writing of the normal image signal, and is the same as the normal writing voltage of the subsequent block. That's why. For example, in the case of displaying a single-color halftone full screen, the visibility of the boundary in the conventional driving method is extremely high, so it is highly necessary to effectively utilize the structure of the present invention. It is important that they do not differ.

In each of the above embodiments, the active matrix substrate to which the data transmission method of the present invention is applied is used for a display device using pixels, and in particular, a liquid crystal display device using liquid crystal as the pixels has been described. However, the present invention is not limited to this, and the present invention can be used for, for example, a detector using the photoelectric effect, such as an X-ray sensor.

[Embodiment 4]
Another embodiment of the present invention will be described below with reference to FIG. For convenience of explanation, members having the same functions as those shown in the drawings of the above-described embodiment are denoted by the same reference numerals, and description thereof will be omitted.

This embodiment relates to a photodetector such as an X-ray sensor using the photoelectric effect. As shown in FIG. 25, a light detection panel 102, a signal processing unit (data transfer unit) 101, and a data storage unit 110 are connected in this order.

Inside the light detection panel 102, the same signal lines S _k (k = 1, 2,..., N) and scanning lines (not shown) as in the first embodiment are formed in a matrix. As in the first embodiment, the signal line is divided into a plurality of blocks (not shown). A light detection element (not shown) that detects light such as X-rays and converts the light into an electric signal is provided instead of the pixel at the portion where the pixel according to the first embodiment is provided. The scanning lines are driven as in the first embodiment.

An in-panel switch 107 similar to the signal line switching element SWa of the first embodiment is provided inside the light detection panel 102 and at a connection portion between the signal line and the signal processing unit 101. The panel switch 107, depending on the form with similar control wire SW ₁ like the embodiment (not shown), is controlled so as to sequentially select the form 1 likewise each block embodiment. Although only one signal line and one in-panel switch 107 are shown here for convenience of explanation, in practice, one signal processing unit 101 has a plurality of signal lines (S ₁ , S ₂ , .., S _N ) are connected via in-panel switches corresponding to the respective signal lines. Further, the signal processing units 101 are actually provided by the number of signal lines in one block, as in the sampling circuits of FIGS. 5, 7, and 9, and each of the signal processing units is Connected to each signal line through a switch in each panel.

Inside the signal processing unit 101, a preamplifier (PAMP) 103 that converts an electric signal into a voltage, a main amplifier (MAMP) 104 that amplifies the voltage, an m-bit analog-to-digital converter (ADC) 105, and an m-bit digital A latch circuit 106 for latching a signal is connected in this order.

In each row, while the corresponding scanning line is turned on and the row is selected (one horizontal period), the photodetector generates an electric signal (charge) according to the intensity of the light received at the site. Let it. This electric signal is input to the signal processing unit 101 through the signal line. In the signal processing unit 101, the electric signal is converted into a voltage by the preamplifier 103, amplified by the main amplifier 104, converted into a digital signal by the analog / digital converter 105, latched by the latch circuit 106, and then sent to the data storage 110. Is output. The data storage 110 stores the input signal.

In the above configuration, the switch 107 in each panel is controlled as described in each of the above-described embodiments, that is, as shown in, for example, FIGS. it can. Conventionally, as in the first embodiment, in any one row, a block (referred to as BL1) in which selection and generation of an electric signal have been completed, and generation and transmission of the electric signal by a signal line next to the block. When attention is paid to the block to be performed (referred to as BL2), the voltage may fluctuate between adjacent signal lines belonging to BL1 and BL2, respectively. On the other hand, according to the configuration of the present embodiment, by performing control as in each of the above-described embodiments, such a variation is suppressed, and thereby, an error in data output to the data storage 110 is generated. Can be suppressed.

Note that the present invention may be configured as follows. That is, the present invention relates to a method for driving an active matrix substrate, comprising: a plurality of pixel electrodes formed on a substrate; a pixel switching element individually connected to the pixel electrode; and a plurality of pixels for driving the pixel switching element. Scanning lines, a plurality of signal lines connected to the pixel electrodes via the pixel switching elements, a plurality of signal line switching elements each having one end individually connected to the plurality of signal lines, A signal input portion electrically connected to an end, a signal line branching portion provided between the signal input portion and the switching element, and a plurality of signal line switching elements commonly connected to each block; In a method for driving an active matrix substrate having a control wiring for switching between conduction and non-conduction of a signal line switching element, the potential supplied to the signal line is changed every predetermined period. Before the signal line switching element of each block is selected to supply a desired display signal to a signal line and a pixel within each of the predetermined periods, a certain block is inverted in polarity with respect to a reference potential. The signal line switching element is turned on, and the polarity of the voltage supplied to the signal line at this time with respect to the reference potential is the polarity of the voltage supplied during the period in which the block is selected within the predetermined period with respect to the reference potential. It may be configured to be the same as.

According to the above configuration, since the polarity of the signal line is inverted in advance, the pixel on the boundary line is written in a state where the potential has fluctuated as described above, and the pixel is held over the display period. Does not occur. This solves the problem that the display state is different from that of the surroundings even though the same potential as that of the surroundings is supplied at the boundary of the block.

Further, in the above configuration, in each of the predetermined periods, a plurality of blocks are selected before a signal line switching element of each block is selected in order to supply a desired display signal to a signal line and a pixel. You may comprise so that a signal line switching element may be made into a conduction state simultaneously.

According to the above configuration, since a common potential inversion period is provided, even when driving is performed in a number of blocks, time loss required for polarity inversion can be reduced.

Further, in the above configuration, in each of the predetermined periods, a signal of a certain block is selected before a signal line switching element of each block is selected in order to supply a desired display signal to a signal line and a pixel. The line switching element may be turned on, and the signal line may be supplied with a display signal corresponding to a halftone at this time.

According to the above configuration, although the effect in the case of black display is slightly reduced, the above effect can be obtained also in the display of white, halftone, single color, and the like. Since the difference in visibility on display with respect to a slight difference in voltage is the largest in the case of halftone, this structure and driving method are extremely excellent in that visibility of boundaries between blocks on all screens is eliminated.

The present invention also relates to a method for driving an active matrix substrate, comprising: a plurality of pixel electrodes formed on a substrate; a pixel switching element individually connected to the pixel electrode; and a plurality of pixel driving elements for driving the pixel switching element. Scan lines, a plurality of signal lines connected to the pixel electrodes via the pixel switching elements, a plurality of signal line switching elements each having one end individually connected to the plurality of signal lines, A signal input portion electrically connected to an end, a signal line branching portion provided between the signal input portion and the switching element, and a plurality of signal line switching elements commonly connected to each block; In a method for driving an active matrix substrate having a control wiring for switching between conduction and non-conduction of a signal line switching element, a potential supplied to the signal line is changed every predetermined period. The polarity is inverted with respect to the quasi-potential, and the signal line switching element of a certain block is turned on at least before the switching element of the adjacent block selected earlier in the horizontal period is switched off. You may comprise.

According to the above configuration, since the polarity inversion is performed before the adjacent block is deselected, the pixel on the boundary line is written in a state where it has been subjected to the fluctuation of the potential, and is written over the display period. No phenomenon occurs. This solves the problem that the display state at the boundary between blocks is different even though the same potential is supplied to the surrounding area.

The present invention also relates to a method for driving an active matrix substrate, comprising: a plurality of pixel electrodes formed on a substrate; a pixel switching element individually connected to the pixel electrode; and a plurality of pixel driving elements for driving the pixel switching element. Scan lines, a plurality of signal lines connected to the pixel electrodes via the pixel switching elements, a plurality of signal line switching elements each having one end individually connected to the plurality of signal lines, A signal input portion electrically connected to an end, a signal line branching portion provided between the signal input portion and the switching element, and a plurality of signal line switching elements commonly connected to each block; In a method for driving an active matrix substrate having a control wiring for switching between conduction and non-conduction of a signal line switching element, a potential supplied to the signal line is changed every predetermined period. The signal line switching element of a certain block is inverted with respect to the quasi-potential, and the signal line switching element of a certain block is turned on at least once while the switching element of an adjacent block previously selected within the predetermined period is on. May be.

According to the above configuration, since the polarity inversion is performed during the selection of the adjacent block, the pixel on the boundary line is written in a state where the fluctuation of the potential has occurred, and this is held over the display period. However, the problem that the display state of the boundary between blocks is different is solved. Further, it is possible to eliminate a time loss required for the polarity inversion.

The image display device according to the present invention may be configured to include an active matrix substrate driven by each of the above-described methods. A signal line driving circuit according to the present invention is used for driving a signal line of an image display device having an active matrix substrate driven by each of the above-described methods, and controls at least two groups of lines by different control methods. You may comprise so that it may control by a signal. Further, the signal line driving circuit according to the present invention may be configured such that the control signal (group control signal) switches the sampling signal. That is, the sampling signal may be switched at the timing of the control signal. Further, the signal line driving circuit according to the present invention may be configured such that the control signal (group control signal) corresponds to a transfer signal or a latch signal. That is, data may be transferred or latched at the timing of the control signal.

(4) The present invention can be applied to applications such as a data transmission method for transmitting data using a matrix substrate such as an active matrix substrate provided in a liquid crystal display device and a signal line driving circuit.

FIG. 3 is an explanatory diagram illustrating an equivalent circuit of an active matrix substrate. FIG. 3 is an explanatory diagram showing a timing chart according to a driving method using an active matrix substrate. FIG. 2 is an explanatory diagram showing a display state of a liquid crystal display device using the active matrix substrate of FIG. FIG. 3 is an explanatory diagram showing a timing chart according to a driving method using an active matrix substrate. FIG. 3 is a block diagram illustrating a configuration example of a signal line driving circuit. FIG. 6 is an explanatory diagram showing a timing chart of the signal line driving circuit in FIG. 5. FIG. 3 is a block diagram illustrating a configuration example of a signal line driving circuit. FIG. 8 is an explanatory diagram illustrating a timing chart of the signal line driving circuit in FIG. 7. FIG. 3 is a block diagram illustrating a configuration example of a signal line driving circuit. FIG. 10 is an explanatory diagram showing a timing chart of the signal line drive circuit in FIG. 9. FIG. 3 is a block diagram illustrating a schematic configuration example of a conduction control unit. FIG. 3 is a block diagram illustrating a schematic configuration example of a conduction control unit. FIG. 3 is a block diagram illustrating a schematic configuration example of a circuit that generates a group control signal and a control signal. FIG. 3 is a block diagram illustrating a schematic configuration example of an output buffer. FIG. 3 is a block diagram illustrating a schematic configuration example of an output buffer. FIG. 2 is a block diagram illustrating a schematic configuration example of a D / A converter. FIG. 2 is a block diagram illustrating a schematic configuration example of a D / A converter. FIG. 3 is a block diagram illustrating a configuration example of a signal line driving circuit. FIG. 19 is an explanatory diagram showing a timing chart of the signal line driving circuit of FIG. 18. FIG. 4 is an explanatory diagram illustrating a configuration example in which an image signal is applied to a signal line by dividing into more than two blocks. FIG. 3 is an explanatory diagram showing a timing chart according to a driving method using an active matrix substrate. FIG. 3 is an explanatory diagram showing a timing chart according to a driving method using an active matrix substrate. FIG. 3 is an explanatory diagram showing a timing chart according to a driving method using an active matrix substrate. FIG. 3 is an explanatory diagram showing a timing chart according to a driving method using an active matrix substrate. FIG. 3 is a block diagram illustrating a schematic configuration example of a photodetector. FIG. 9 is an explanatory diagram showing a timing chart according to a driving method using a conventional active matrix substrate.

Explanation of reference numerals

1 signal line drive circuit (data transfer section)
2 scanning line driving circuit 3, 4, 5 display area 7 signal line branching section 11 first block 12 second block 15, 16, 17, 18, 19, 20 sampling circuit 21 PLL oscillator 22 H counter 23 SW ₁ decoder 24 SW ₂ decoder 31 H counter 32 SW ₁ decoder 33 SW ₂ decoder 41 H counter 42 V counter 43 CNT decoder 44 CNTa decoder 45 CNTb decoder 51 OP amplifier 52 Switching switch 53 Level shifter 61 Digital / analog converter 62 Switching switch 63 Level shifter 71, 72 sampling Circuit 101 Signal processing unit (data transfer unit)
102 light detection panel 107 in-panel switch 103 preamplifier 104 main amplifier 105 analog-to-digital converter 106 latch circuit 110 data storage a, b, c, d, e, e ′, f, f ′ signal lines A ₁ , B ₁ , C ₁ , D ₁ , A ₂ , B ₂ , C ₂ , D ₂ Pixels ASWA, ASWB, ASWC, ASWD, ASWS, ASWH Analog switch Bu Output buffer CLK Clock CNTa, CNTb Group control signal CNT, CNT0 Control signal Csd Parasitic capacitance C _SHA , C _SHB sampling hold capacitor C _S sampling capacitor C _H hold capacitor DAC D / A converter DAT Data line g ₁ , g ₂ Scan line HSY Horizontal synchronization signal LSa, LSb Group control signal RL Reference potential s ₁ , s ₂ , s _3, s ₄ output lines SAM _1, SAM _n Sampling signals SW ₁ , SW ₂ Control lines SWa, SWb, SWc, SWd Signal line switching element Vd Charge voltage VSY Vertical synchronization signal

Claims (6)

A plurality of scanning lines and a plurality of signal lines are formed in a matrix, and within one horizontal period, a data signal corresponding to the matrix position is applied to the signal line corresponding to the position, and the plurality of signal lines are formed. In the data transmission method of transmitting a data signal between the matrix unit and the data transfer unit for each block by sequentially conducting the signal line for each block,
One block of input data, which is continuously input in a time series and corresponds to n signal lines, is sampled by n sampling units, accumulated as n sampling data, and then output to the corresponding signal line. ,
The above n sampling units are divided into groups,
Among the blocks, one of the blocks in which the sampling order of the input data is the second or later for the same scanning line is BL2,
When a group having a sampling unit to which the first sampling data Db1 of the block BL2 is input is defined as GRa,
The group GRa stores the sampling data Db1 in the group GRa after accumulating the sampling data of the block whose sampling time is earlier than the block BL2 for the same scanning line and before the sampling data Db1 is input at the latest. A data transmission method comprising preparing an empty sampling unit for storing data. As for at least one of the blocks, each of which has a signal line adjacent to each other, when the application end time of the data signal is earlier, BL1 is the earlier block and BL2 is the later block.
Each of the sampling units has a plurality of systems for storing the sampling data,
In a certain group GR1, the sampling data of the block BL1 is accumulated in one of the plurality of systems in each sampling unit.
When the accumulation is completed, accumulation of the next sampling data is started in another group, and thereafter, until accumulation of the sampling data of the next block BL2 is started in the group GR1, the next accumulation destination is stored in the group GR1. 3. The data transmission method according to claim 2, wherein the system to be used is switched to a system having no currently stored data. When one of the above groups is GR1,
2. The data transmission method according to claim 1, wherein after at least sampling data is accumulated in the group GR1, the sampling data accumulated in the group GR1 is output while sampling data is accumulated in another group. A plurality of scanning lines and a plurality of signal lines are formed in a matrix, and within one horizontal period, a data signal corresponding to the matrix position is applied to the signal line corresponding to the position, and the plurality of signal lines are formed. The signal lines are sequentially turned on for each block, so that the data signal is transmitted from the data transfer unit to the pixels in a matrix form for each block, and the image represented by the data signal is displayed on the pixel. In a signal line driving circuit for transmitting the data signal to a display device,
One block of input data, which is continuously input in a time series and corresponds to n signal lines, is sampled by n sampling units, accumulated as n sampling data, and then output to the corresponding signal line. ,
The above n sampling units are divided into groups,
Among the blocks, one of the blocks in which the sampling order of the input data is the second or later for the same scanning line is BL2,
When a group having a sampling unit to which the first sampling data Db1 of the block BL2 is input is defined as GRa,
The group GRa stores the sampling data Db1 in the group GRa after accumulating the sampling data of the block whose sampling time is earlier than the block BL2 for the same scanning line and before the sampling data Db1 is input at the latest. A signal line drive circuit for generating a group control signal for each group that defines a timing for preparing an empty sampling unit for accumulating the data. As for at least one of the blocks, each of which has a signal line adjacent to each other, when the application end time of the data signal is earlier, BL1 is the earlier block and BL2 is the later block.
Each of the sampling units has a plurality of systems for storing the sampling data,
In a certain group GR1, the sampling data of the block BL1 is accumulated in one of the plurality of systems in each sampling unit.
When the accumulation is completed, accumulation of the next sampling data is started in another group, and thereafter, until accumulation of the sampling data of the next block BL2 is started in the group GR1, the next accumulation destination is stored in the group GR1. 5. The signal line drive circuit according to claim 4, wherein a signal defining a timing of switching a system to be used to a system having no stored data is generated as the group control signal. 6. When one of the above groups is GR1,
After accumulating the sampling data in at least this group GR1, while accumulating the sampling data in another group, a signal defining the timing of outputting the sampling data accumulated in the group GR1 is generated as the group control signal. The signal line drive circuit according to claim 4, wherein

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