JPH08248927A - Liquid crystal display device and method for driving liquid crystal display panel - Google Patents

Abstract

PURPOSE: To provide a liquid crystal display device capable of displaying the picture having high resolution. CONSTITUTION: A signal conversion circuit 7 samples video signals of respective RGB colors by the period corresponding to 1.5 pixels to divide them to the signal for the driver 14A of a lower signal side and the signal for the driver 14C of an upper signal side and moreover expands them to signals continuing for the period corresponding to 3 pixels to supply them to drivers 14A, 14C of respective signal sides. The drivers 14a, 14c of respective sides sample the supplied signals and impress voltages corresponding to sampled values onto pixel capacitances via signal electrodes 23L, 23U.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high resolution liquid crystal display device and a method for driving a liquid crystal display panel.

[0002]

2. Description of the Related Art FIG. 12 shows a so-called COG (chip on glass) type liquid crystal display device. This liquid crystal display device includes a signal side driver (source driver) 11 on a glass substrate of a liquid crystal display panel (liquid crystal display element) 111.
2A, 112B and scan side driver (address driver)
113A and 113B are arranged.

The structure of the liquid crystal panel 111 and the signal side drivers 112A and 112B of the liquid crystal display device having such a structure is shown in FIG. As shown, the liquid crystal display panel 111
Is an active matrix type, and each pixel electrode 121 is connected to a corresponding signal line S1, S2, ... Through a TFT (thin film transistor) 122.
In addition, the TFT 122 of each row has a corresponding gate line G
1, G2 ... Signal side driver 112
A and 112B are a plurality of flip-flops 131 that configure a shift register, an analog switch 132 that is turned on / off according to output signals SS1, SS2, ... Of the flip-flop 131, and a BGR via the analog switch 132. Image signal is supplied to the signal line S
, S2, ..., And the charge circuit 133 for driving.

In the circuit configuration shown in FIG. 13, when each horizontal scanning period starts, scanning side drivers 114A and 114 are provided.
B applies a gate pulse to the gate line to be selected,
The TFTs 122 in the corresponding row are turned on. Further, the clear signal CLR is set to the active level, and the charge accumulated in the capacitance (liquid crystal capacitance) of the pixel in the selected row is turned on.
It is discharged through the FT 122 and the charge circuit 133.
Then, the clear signal CLR is turned off and the output enable signal OE is set to the active level. Further, the start signal SRT which is at a high level for the three clock periods shown in FIG. 14B is supplied to the first-stage flip-flop 131. Each flip-flop 131 shifts the start signal SRT according to the clock CK shown in FIG.
Output as signals SS1 to SS4 ... Shown in (C) to (F).

Output signal SS of flip-flop 131
The analog switch 132 is sequentially turned on for 3 clock periods according to 1, SS2, .... Therefore, (G) ~
As shown in (I), the video signals of each BGR color are sampled in the input capacitance of the charge circuit 133 and written in the liquid crystal capacitance of the selected row by the charge circuit 133. With such a configuration and operation, the average value of the video signal for 3 clock periods, that is, the display period of 3 pixels of BRG is written in each liquid crystal capacitor, and the gradation corresponding to the average value is displayed. To be done.

A liquid crystal display panel is required to have a high resolution, and particularly in a liquid crystal display panel for magnifying projection, a small panel is required to have a high resolution. In order to increase the resolution, it is necessary to increase the number of pixels and the number of drivers as the number of pixels increases. In addition, the driver installation space is limited. Therefore, in FIG.
16, the signal lines are alternately drawn up and down (staggered), and as shown in FIG.
It is necessary to arrange the 12D above and below the display area for connection.

When driving the liquid crystal display device having such a structure, the conventional driving method is followed, as shown in FIG.
As shown in (B), (F) and (G), the clock CK2 and the start signal SRT2 delayed by a half clock period from the clock CK1 and the start signal STR1 supplied to the signal side drivers 112A and 112B on the lower side are provided on the upper side. A method of supplying to the signal side drivers 112C and 112D is also conceivable.

According to this driving method, the signal side drivers 112A and 112B on the lower side sequentially sample the video signals of each BRG color as shown in (C) to (E) and write them in the corresponding liquid crystal capacitors. Also, the upper signal side driver 1
12C and 112D sequentially sample the video signals of each color of BRG as shown in (H) to (J) and write them in the corresponding liquid crystal capacitors.

[0009]

However, in the driving method shown in FIG. 17, (C) and (I), (D) and (J),
As is clear from comparison between (E) and (H), the latter half of the video signal sampled by the lower signal side drivers 112A and 112B and the upper signal side drivers 112C and 112B.
The first half of the video signals sampled by D overlap. Therefore, the resolution of the display image is reduced.

The present invention has been made in view of the above circumstances, and an object thereof is to provide a liquid crystal display device and a liquid crystal display panel driving method capable of displaying a high-resolution image.

[0011]

In order to achieve the above object, a liquid crystal display device according to a first aspect of the present invention provides a liquid crystal capacitor, a switching element connected to the liquid crystal capacitor, and a liquid crystal capacitor via the switching element. A liquid crystal display panel in which the signal lines are connected in a zigzag manner in the opposite direction, and the signal lines are arranged on the opposite side with the liquid crystal display panel sandwiched therebetween, and are respectively connected to corresponding signal lines and supplied. First and second drive circuits for driving a signal line according to the generated video signal, and sampling the video signal for the first and second drive circuits at different timings, and the first and second drive circuits And a conversion unit that distributes and supplies the same.

According to a second aspect of the present invention, there is provided a liquid crystal display panel driving method, wherein a liquid crystal capacitor, a switching element connected to the liquid crystal capacitor, and a liquid crystal capacitor via the switching element are alternately connected in opposite directions. First pulled out to
A driving method of a liquid crystal display panel comprising: a second signal line group; and a sampling step of sampling video signals for the first signal line group and the second signal line group at different timings. A step of allocating the sampling signal to the first signal line group and the second signal line group;
The first signal according to the sampling signal for the signal line group of
Driving the signal lines and driving the second signal lines according to the sampling signals for the second signal line group.

[0013]

According to the present invention, the sampling periods of the signals applied to the liquid crystal capacitors do not overlap. Therefore,
High resolution images can be displayed.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A liquid crystal display device and a liquid crystal display panel driving method according to embodiments of the present invention will be described below with reference to the drawings. (First Embodiment) As shown in FIG. 1, a liquid crystal display device of this embodiment includes a TFT liquid crystal display panel 11 including a TFT side glass substrate 12 and a color filter side glass substrate 13,
Four signal side drivers 14A to 14D and two scanning side drivers 15A and 15B arranged on the TFT side glass substrate 12 of the panel, a flexible circuit board (FPB) 16 connected to these drivers, and a signal conversion circuit. 17
And consists of

The signal side drivers 14A and 14B are arranged below the display area of the liquid crystal display panel 11, and the signal side drivers 14C and 14D are arranged above the display area. The scanning drivers 15A and 15B are arranged at the right end of the liquid crystal display panel 11. Signal conversion circuit 17
Are arranged on the flexible circuit board 16 and are connected to the signal side drivers 14A to 14D.

FIG. 2 shows a circuit configuration of the liquid crystal display panel 11 and the signal side drivers 14A to 14D. The liquid crystal display panel 11 is formed by arranging BGR color pixels in a Δ arrangement, and the liquid crystal capacitance of each pixel (the capacitance formed by the pixel electrode 21, the counter electrode, and the liquid crystal between them) is transmitted via the TFT 22 to the signal line ( Data lines) 23L and 23U. The odd-numbered signal lines 23L are drawn to the lower side of the display area and connected to the lower-side signal side drivers 14A and 14B, and the even-numbered signal lines 23U are drawn to the upper side of the display area and the upper-side signal side drivers 14C. , 14D. The gates of the TFTs 22 in each row are connected to the gate line 24, and the scanning side drivers 15A, 15
Connected to B.

The lower signal side drivers 14A and 14B are
A plurality of flip-flops 31 forming a shift register
L and the output of the flip-flop 31L are turned on / off, and the video signal of either BGR is charged to the charge circuit 33L.
To the analog switch 32L and the clear signal CL
R and a charge circuit 33L that charges and discharges each liquid crystal capacitance according to the output enable signal OE.

Similarly, the signal side drivers 14C and 14D on the upper side are turned on / off in accordance with a plurality of flip-flops 31U forming a shift register and the outputs of the flip-flops 31 and the video signal of one of the BGRs is charged into the charge circuit 3.
It is composed of an analog switch 32U for supplying to 3U and a charge circuit 33U for charging / discharging each liquid crystal capacitance according to a clear signal CLR and an output enable signal OE.

The clock CK1 is supplied to each flip-flop 31 of the signal side drivers 14A and 14B on the lower side. Leading flip-flop 31 of the signal side driver 14A
Is supplied with a start signal SRT1. The output signal of the flip-flop 31 at the final stage of the signal side driver 14A is supplied to the head flip-flop 31 of the signal side driver 14B.

CK2 which is an inverted signal of the clock CK1 is supplied to each flip-flop 31 of the signal side drivers 14C and 14D on the upper side. Left signal side driver 14
The start signal SRT1 is sent to the leading flip-flop of C.
Start signal SRT delayed by half a clock cycle
2 is supplied. The output signal of the flip-flop 31 at the final stage of the signal side driver 14C is supplied to the head flip-flop 31 of the signal side driver 14D.

The signal conversion circuit 17 supplies the analog video signals (gradation signals) BGR of the respective colors blue, red and green generated from the television reception signal or the like to the signal conversion circuit 17. BG
The video signal of each R color and the clock CK1 are received, and the video signal of each BGR color is sampled for 1.5 clock periods. Further, the sampling timing of the video signal of each color of BGR is shifted by one clock period. The signal conversion circuit 17 expands the sampled signal (signal segment) into a signal in a 3-clock period, and outputs the odd-numbered sampled video signal to the lower signal side drivers 14A and 14B and the grayscale signal B.
L, GL, RL, and even-numbered sampling video signals are supplied to the upper signal side drivers 14C, 14D as gradation signals RU, BU, GU.

Clear signal CLR, output enable signal O
E, clocks CK1 and CK2, start signal STR1,
The STR2 is generated by the timing control unit 35.

Next, the operation of the liquid crystal display device having the above structure will be described with reference to the timing chart of FIG. When each horizontal scanning period starts, the scanning side drivers 15A and 15B apply a gate pulse to the gate line 24 of the selected row to turn on the TFT 22 of the selected row. Timing control unit 35
Supplies the clear signal CLR to the charge circuits 33L and 33U, and the TFT 2 in which the charge of the liquid crystal capacitance of the selected row is in the ON state
2 is discharged. Then, the clear signal CLR is turned off, and the output enable signal OE becomes active level.

The signal conversion circuit 17 has B shown in (A) to (C) according to the clock CK1 shown in FIG.
The video signals of G and R colors are sampled at timings shifted by one clock period by 1.5 clock periods as shown in (F) to (H). Signal conversion circuit 17
Expands the sampled signal into a signal (signal segment) of 3 clock periods, and further outputs an odd numbered signal (I),
As shown in (K) and (M), the lower signal side driver 14
A and 14B are supplied as gradation signals BL, GL and RL,
As shown in (J), (L), and (N), the even-numbered signals are supplied to the upper signal side drivers 14C and 14D as the gradation signals RU and B.
Supply as U and GU.

The clock CK1 shown in (D) and the start signal SRT1 shown in (O) are supplied to the flip-flops 31 of the lower signal side drivers 14A and 14B, and the flip-flops 31 sequentially transfer the start signal SRT1. Therefore, the control signals SL1, SL2 output from the first-stage, second-stage, third-stage flip-flops 31,
SL3 ... shifts by one clock period at a time and becomes H level for three clock periods, as illustrated in (P) to (R).

Output signal SL of flip-flop 31L
1, SL2, ..., Each analog switch 32L is sequentially turned on for 3 clock periods. Therefore, the signals B1, B3, ... Shown in (I) are supplied to the charge circuits 33L of the first stage, the fourth stage ,.
Are supplied to the charge circuits 33L of the second, fifth, ..., And the signals R1, R3, ... Shown in (K) are the third, sixth.
It is supplied to the charge circuit 33L of the stage.

The signal passing through the analog switch 32L charges the input capacitance of the charge circuit 33L, and the charge circuit 33L supplies a voltage corresponding to the voltage sampled by the input capacitance to the signal line 23L.

The clock CK2 shown in (E) is input to the flip-flop 31U of the upper signal side drivers 14C and 14D.
And the start signal SRT2 shown in (S) is supplied, and the flip-flop 31U sequentially transfers the start signal SRT2. Therefore, the control signals SU1, SU output from the first-stage, second-stage, third-stage ...
2, SU3 ..., As illustrated in (T) to (V),
It shifts by one clock period and becomes H level for three clock periods.

Output signal SU of flip-flop 31U
1, SU2 ..., Each analog switch 32U is sequentially turned on for 3 clock periods. Therefore, the signals R0, R2 ... Shown in (N) are supplied to the charge circuits 33U of the first stage, the fourth stage, ... And the signals B2, B4 ... Shown in (J).
Are supplied to the charge circuits 33U of the second, fifth, ..., And the signals G2, G4, ... Shown in (L) are the third, sixth.
It is supplied to the charge circuits 33U of the stages.

The signal supplied to the charge circuit 33U is
The input capacitance of the charge circuit 33U is charged and sampled. The charge circuit 33U supplies a signal corresponding to the sampling signal to the signal line 23U.

The signals applied to the signal lines 23L and 23U are applied to the liquid crystal capacitors via the TFTs 22 in the selected row to charge the liquid crystal capacitors. When the selection period of each gate line 24 ends, the gate pulse is turned off and the TFT
22 turns off. Therefore, the charge is continuously held in each liquid crystal capacitor until the next selection period, and a desired gradation is displayed.

The signal conversion circuit 17 completes the sampling of the video signal in the 1.5 clock period, expands the sampled signal into the signal of the 3 clock period, and supplies it to the upper and lower signal side drivers 14A to 14D. Therefore, the sampling periods of the video signals of pixels of the same color do not overlap.
Therefore, the signal lines 23L and 23U are drawn out in a zigzag pattern, and the signal side drivers 14A to 1A are arranged above and below the display area.
It is possible to display a high-resolution image on the liquid crystal display device in which 4D is arranged.

For example, in the configuration shown in FIGS. 12 to 14, the sampling period of each driver 112A to 112D is only the first half 1.5 clock period of the three clock periods, and the sampling is performed in the latter half 1.5 clock period. By stopping, it is possible to avoid overlapping sampling periods. However, with this method, the time for charging the input capacitance of the charge circuit 133 is halved, and there is a risk that the charging will not be completed completely. However, according to this embodiment, the charge circuits 33L, 33
The input capacity of U can be charged in 3 clock periods,
The input capacity can be fully charged.

Next, a configuration example of the signal conversion circuit 17 will be described with reference to FIG. The configuration shown in FIG. 4 is for one color, and three sets of the circuits shown in FIG. 4 are arranged for the video signals of three BGR colors. First, the B, G, or R video signal is supplied to one end of each of the signal sampling capacitors C1 to C4 via the analog switches 41 to 44 that are turned on and off according to the channel control signals CH1 to CH4. Capacity C1-C
The reference voltage VBB is applied to the other end of 4. Also,
One ends of the capacitors C1 to C4 are connected to the reference voltage VBB via the analog switches 45 to 48 that conduct according to the clear signals CL1 to CL4.

The capacitors C1 to C4 have a capacitance which is less than half the input capacitance of the charge circuits 33L and 33U, and is 1.5
Charging is completed in the clock period. Alternatively, the capacity C1 to C
The time constant of 4 is 1/2 or less of the time constant of the input capacitance of the charge circuits 33L and 33U. The voltage at one end of the capacitors C1 to C4 is supplied to the amplifiers 53 to 56.

The output signals of the amplifiers 53 and 54 are passed through the analog switches 49 and 50 to the lower signal side driver 14
The grayscale signals BL, GL, and RL for A and 14B are output. A selection signal SE is provided at the control end of the analog switch 49.
L1 is supplied via the inverter IV1, and the selection signal SEL1 is supplied to the control end of the analog switch 50.

The output signals of the amplifiers 55 and 56 are sent through the analog switches 51 and 52 to the signal driver 14 on the upper side.
The grayscale signals RU, BU, and GU for C and 14D are output. The selection signal SE is provided at the control end of the analog switch 51.
L2 is supplied via the inverter INV2, and the selection signal SEL2 is supplied to the control end of the analog switch 52. In addition, the timing logic 57 uses the clock CK1 to select channel selection signals CH1 to CH4, clear signals CL1 to CL4, and select signals SEL1 and SEL2.
Is output.

Next, the operation of the conversion circuit having the above configuration will be described with reference to FIG. First, the timing logic 57
As shown in FIGS. 5B, 5D, 5H, and 5J, the clear signals CL1 to CL4 are sequentially set to the high level every 1.5 clock periods. The clear signals CL1 to CL4 sequentially turn on the analog switches 45 to 48 every 1.5 clock periods. Analog switch 45-4 turned on
The electric charges stored in the capacitors C1 to C4 are discharged via the capacitor 8.

As shown in (B) to (E) and (H) to (K), the channel signals CH1 to CH4 sequentially become high level for 1.5 clock periods after the clear signals CL1 to CL4. The channel switches CH1 to CH4 sequentially turn on the analog switches 41 to 44 every 1.5 clock periods. Video signals turned on analog switches 41-4
4 is supplied to the discharged capacities C1 to C4 and is sampled.

Therefore, the video signal shown in FIG.
The capacitor C1 is sampled at 1, T5, and the period T3, T
6 is sampled in the capacitor C2, and the capacitor C3 is sampled in the period T3.
And the capacitor C4 is sampled in the period T4.

The selection signal SEL1 becomes high level for 3 clock periods in synchronization with the clear signal CL1 as shown in (F). Further, the selection signal SEL2 is a signal that is at the high level for three clock periods in synchronization with the clear signal CL2 as shown in (L). The analog switches 49 and 50 are alternately turned on for 3 clock periods according to the selection signal SEL1,
As shown in (F), the signals held in the capacitors C1 and C2 are output as gradation signals BL, GL, or RL. These signals are supplied to the signal side drivers 14A and 14B on the lower side. The analog switches 51 and 52 are select signals SEL
The signal is alternately turned on for 3 clock periods in accordance with 2, and the signals held in the capacitors C3 and C4 are output as the gradation signals RU, BU, GU as shown in (M). These signals are supplied to the upper signal side drivers 14C and 14D.

A clock CK1 shown in (N) for the lower signal side drivers 14A and 14B, and a lower signal side driver 1
The clock CK2 shown in (O) is supplied to 4C and 14D. The signal side drivers 14A to 14D correspond to the charge circuit 3 corresponding to the signal supplied from the signal conversion circuit 17.
Charged to the input capacitance of 3 L and 33 U, the charge circuit 33
L and 33U apply the signal corresponding to the signal sampled to the input terminal capacitance to the signal lines 23L and 23U.

As described above, according to the configuration shown in FIG. 4, it is possible to expand the video signal of the video signal of each color for 1.5 clock periods into the signal of 3 clock periods. Therefore, by distributing the signals obtained by this circuit to the lower and upper signal side drivers 14A to 14D and supplying the signals,
As described above, a high resolution image can be displayed. In addition, in order to prevent deterioration of the liquid crystal, it is desirable to reverse the polarity of the applied voltage at every predetermined cycle. Therefore, the polarity of the amplification factors of the amplifiers 53 to 56 may be appropriately inverted by the timing logic 57.

(Second Embodiment) The signal conversion circuit 1 shown in FIG.
FIG. 6 shows another configuration example of No. 7. In the circuit configuration shown in FIG. 6, the video signals of B, G, and R colors are converted into digital data by the A / D converter 61, and the flip-flop (F
F) 62 and 64 are supplied. The output of the flip-flop 62 is supplied to the flip-flop 63. The output signals of the flip-flops 63 and 64 are D / A converters 65 and 66.
Are converted into analog signals by the amplifiers 67 and 68 and supplied to the lower signal side drivers 14A and 14B and the upper signal side drivers 14C and 14C. The flip-flop 62 is supplied with the control signal SC of 3 clock cycles, and the flip-flops 63 and 64 are supplied with the control signal SC inverted by the inverter 69.

According to this structure, the video signal is 1.
It is converted into digital data every 5 clock periods, odd-numbered data is supplied to the D / A converter 65, even-numbered data is supplied to the D / A converter 66, and converted into signals of 3 clock periods. It is supplied to the signal side drivers 14A to 14D via the amplifiers 67 and 68.

By making the sampling capacitance of the A / D converter 61 sufficiently smaller than the input capacitance of the charge circuits 33L and 33U, the lower signal side drivers 14A, 14 are provided.
The signals supplied to B and the upper signal side drivers 14C and 14D can be accurately sampled at different timings.

(Third Embodiment) In a normal television receiver,
Interlaced scanning is performed, and every other scanning line is scanned, and two fields form one frame. On the other hand, in a liquid crystal display device, such driving is not preferable considering the driving frequency of each pixel. So 1
It is effective to double the liquid crystal driving frequency of one pixel by performing a double speed driving method in which a video signal for one scanning line is displayed on two scanning lines.

Therefore, a third embodiment will be described which enables double speed driving in a liquid crystal display device having a structure in which signal lines are drawn in a staggered pattern above and below the display area and signal side drivers are arranged above and below the effective pixel area. .

In order to enable the double speed driving, the signal converting circuit for double speed driving shown in FIG. 7 is arranged at the output end of the signal converting circuit 17 shown in FIG. 4, and the clocks CK1 and C shown in FIG.
Double the frequency of K2. In this case, the signal side drivers 14A to 14D are formed so that the charging of the input capacitances of the charge circuits 33L and 33U is completed in 3 clocks.
The conversion circuit shown in FIG. 7 is arranged for each output signal of the signal conversion circuit 17.

The gradation signals BL, GL, RL, RU, BU and GU output from the signal conversion circuit 17 are supplied to the A / D converter 71. The A / D converter 71 converts the supplied signal into digital data according to the A / D clock. The obtained digital data is sequentially stored in the line memory 73 according to the write clock obtained by inverting the A / D clock by the inverter 72. The line memory 73 has a storage capacity for two scanning lines.

The video signal written in the line memory 73 in the immediately preceding horizontal scanning period is read every three clock periods according to the read clock obtained by inverting the D / A clock by the inverter 74. The data read from the line memory 73 is converted into an analog signal by the D / A converter 75, and converted into a signal whose polarity is inverted for each display frame by the normal / inversion amplifier 76, and the grayscale signals BL and GL are converted. , RL, RU, BU, GU.
The controller 77 inverts the polarity of the output signal and the A / D clock of 6 clock cycles, the D / A clock of 3 clock cycles, the memory control signal for switching the write area and the read area for each line of the video signal. A polarity inversion signal for outputting is output.

With such a configuration, the data written in the line memory 73 in the previous scanning period is read out at a speed twice as fast as that in the first embodiment, and the image of one scanning line is continuously displayed on the display panel 11. It can be displayed in two scan lines. Therefore, the quality of the displayed image can be improved.

(Fourth Embodiment) In the third embodiment, the video signal is expanded by the signal conversion circuit 17 and then converted into a signal for double speed driving by the circuit of FIG. In the process of converting into the signal of the above, the signals for the lower signal side drivers 14A and 14B and the upper signal side driver 14
It is also possible to convert to C and 14D signals. FIG.
Shows a configuration example of the signal conversion circuit configured in this way. It should be noted that this circuit is 1 for each BGR video signal.
There will be 3 sets in total.

First, the video signal is supplied to the A / D converter 81. The data D1 output from the A / D converter 81 is supplied to the flip-flops 82 and 84. The output D2 of the flip-flop 82 is supplied to the flip-flop 83. Output data D3 and D of the flip-flops 83 and 84
4 are supplied to the write terminals of the first and second line memories 85 and 86 each having a storage capacity of two scanning lines of the liquid crystal display panel 11.

The data D5 and D6 read from the line memories 85 and 86 are supplied to the D / A converters 87 and 88. The output signals of the D / A converters 87 and 88 are supplied to the normal / inverting amplifiers 9 and 90. Forward / reverse amplifier 89, 9
0 output is the lower and upper signal side driver 14 respectively
A to 14D.

The controller 91 uses A for 3 clock cycles.
The / D clock is supplied to the A / D converter 81. The A / D clock is frequency-divided by 1/2 by the frequency dividing circuit and supplied as a write clock to the clock terminal of the first flip-flop 82 and the write clock terminals of the line memories 85 and 86. The write clock is supplied to the second via the inverter 93.
And the clock terminals of the third flip-flops 83 and 84. Further, the controller 91 supplies the D / A clock of 3 clock cycles to the clock terminals of the D / A converters 87 and 88, and further supplies the read clock terminals of the line memories 85 and 86 via the inverter 94. It also outputs a polarity inversion signal that inverts the polarity of the amplification factors of the normal / inversion amplifiers 89 and 90 every predetermined period.

Next, the operation of the circuit shown in FIG. 8 will be described with reference to the time chart of FIG. The A / D converter 81 is
The video signal illustrated in FIG. 9A is converted into digital data in synchronization with the A / D clock illustrated in FIG. 9B, and the data D1 illustrated in FIG. 9C is sequentially output. The data D1 is latched by the first flip-flop 82 according to the write clock shown in (D). The output data D2 of the first flip-flop 82 shown in (E) is latched by the second flip-flop 84 according to the inverted write clock. Also,
The output data D1 of the A / D converter 81 is latched by the third flip-flop 84 according to the inverted write clock. Output data D3 and D4 of the second and third flip-flops 83 and 84 shown in (F) and (G) are sequentially stored in the line memories 85 and 86 according to the write clock shown in (D).

In the immediately preceding horizontal scanning period, the line memory 85,
The data written in 86 is sequentially read according to the read clock as shown in (H) and (J). The data read from the line memories 85 and 86 is D / A
The signals are converted into analog signals by the converters 87 and 88, amplified by the forward / inversion amplifiers 89 and 90, and output.
The controller 91 inverts the polarity of the output signal for each common, for example. The output signal of the first forward / inversion amplifier 89 is supplied to the lower signal side driver 14A, 14B, and the second signal driver 14A.
The output signal of the normal / inversion amplifier 90 is supplied to the upper signal side drivers 14C and 14D.

In the case of this configuration, as shown in (I) and (K), the clock CK1 'supplied to the lower signal side drivers 14A and 14B and the upper signal side drivers 14C and 1C.
The clock CK2 ′ supplied to 4D has a frequency twice that of the clock CK1 during normal driving shown in (L). Also,
The clocks CK1 'and CK2' are in-phase signals.

The flip-flops 31L of the signal side drivers 14A and 14B on the lower side sequentially transfer the start signal SRT1 and keep the signals SL1 and S at the high level for three clock periods.
L2, ... are sequentially output, and the upper signal-side driver 14
The flip-flop 31U of C and 14D has a start signal S
RT2 is sequentially transferred, and signals SU1, SU2, ... Which are at a high level for three clock periods are sequentially output. The analog switches 32L and 32U corresponding to these signals are sequentially turned on. Each of the video signals shown in (H) and (J) is supplied to the corresponding charge circuit 33L or 33U via the turned-on analog switches 32L and 32U to charge the input capacitance. The charge circuit 33L or 33U outputs a signal corresponding to the signal sampled by the input capacitance to the signal line 23.
Writing is performed so as to face the liquid crystal capacitance in the selected state through L, 23U and the TFT 22 which is on.

According to this structure, since the image is displayed on the two scanning lines of the liquid crystal display device during one scanning period of the television by the double speed driving, it is possible to display a high quality image. Further, the signal supplied to each pixel is obtained by timing sampling of the video signal without overlapping,
It is possible to prevent a decrease in resolution.

In the configuration shown in FIG. 8, the video signal is A / D converted and the lower and upper signal side drivers 14A and 14B,
After sorting for 14C and 14D, each data was stored in the line memories 85 and 86. However, after the A / D converted data is stored in the memory, it may be distributed to the lower and upper signal side drivers 14A and 14B and 14C and 14D.

FIG. 10 shows the configuration of the drive circuit having such a configuration.
Shown in In the configuration of FIG. 10, the video signal is the A / D converter 8
1 and the output D11 of the A / D converter 81 is sequentially supplied to the write terminal of the line memory 95. The data D12 read from the line memory 95 is supplied to the flip-flops 82 and 84. Flip-flop 82
The output D13 of the above is supplied to the flip-flop 84. Output data D14 and D15 of the flip-flops 83 and 84
The output signals of the D / A converters 87 and 88 are supplied to the normal / inversion amplifiers 89 and 90. Forward / reverse amplifier 89, 9
0 output is the lower and upper signal side driver 14 respectively
A to 14D.

The controller 91 uses the A / D clock as A
It is supplied to the / D converter 81. The A / D clock is supplied to the line memory 95 as a write clock via the inverter 96.
Is supplied to. Further, the controller 91 supplies a memory control signal for switching the read target storage area and the write target storage area to the line memory 95 for each scanning line period of the video signal. The controller 91 supplies the read clock to the line memory 95. The read clock is frequency-divided by a frequency divider circuit 97 to obtain a D / A clock as a first flip-flop 82 and D / A converters 87 and 88.
Is supplied to. The D / A clock is inverted by the inverter 98 and supplied to the second and third flip-flops 83 and 84.

According to such a configuration, the video signal shown in FIG. 11A is converted into the digital data D11 shown in FIG. 11B by the A / D converter 81 in accordance with the A / D clock, and the line memory 95. Are sequentially stored in. On the other hand, the data stored in the previous scanning period is sequentially read as shown in (C) according to the read clock.

The read data D12 is stored in the first flip-flop 82 as shown in (D) according to the D / A clock. Further, the data D12 and the output data D13 of the first flip-flop 82 are the second and third as shown in (E) and (G) according to the inverted D / A clock.
Stored in the flip-flops 83 and 84. The output data D14 of the second and third flip-flops 83 and 84,
The D15 is supplied to the D / A converters 87 and 88, converted into an analog signal, further amplified to a polarity according to the polarity inversion signal, and supplied to the signal side drivers 14A to 14D. Clocks CK1 and CK2 shown in (F) and (H) are supplied to the signal side drivers 14A to 14D, and the signal side drivers 14A to 14D sample the supplied signals in accordance with the clocks and generate corresponding signal lines. 23L and 23U are applied. With such a configuration, it is possible to display a high resolution image.

The present invention is not limited to the above embodiment, and various modifications and applications are possible. For example, the configuration of the signal conversion circuit 17 is not limited to the configurations shown in FIGS. 4, 8, and 10, and other circuits that realize the same function may be adopted. In addition, the signal conversion circuit 17 is connected to the signal side driver 14
Although the configuration is shown to be arranged outside A to 14D, it may be arranged inside each signal side driver 14A to 14D.

Furthermore, the present invention is not limited to the above embodiment. For example, the liquid crystal display panel 11 is not limited to a color liquid crystal display panel composed of BGR three-color pixels, and may be a monochrome liquid crystal display panel or a birefringence control type color liquid crystal display panel in which the display color changes according to an applied voltage. Good. In this case, the signal conversion circuit 17 samples the video signal for one image period, expands it for two pixel periods in the case of normal driving, and supplies it to the signal side drivers 14A to 14D. The charge circuits 31L and 31U sample the supplied signals for a display period of two pixels of the video signal,
A signal corresponding to the sampled value is applied to the liquid crystal capacitance via the signal line. Further, in the case of double speed driving, it is extended in the period of one pixel and supplied to the signal side drivers 14A to 14D. Each of the charge circuits 31L and 31U samples the supplied signal for a display period of one pixel of the video signal, and applies a signal corresponding to the sampled value to the liquid crystal capacitance via a signal line. Then, two scanning lines are driven during one horizontal scanning period of the video signal.

The present invention can be applied to not only normal drive and double speed drive but also triple drive and quadruple drive.
Further, although the active matrix type liquid crystal display panel using the TFT as the switching element is exemplified, other active elements such as MIM may be used as the switching element.

[0070]

As described above, according to the present invention, the sampling period of the video signal is made different between the period for the driver on one side and the period for the driver on the other side. It is possible to display a high-resolution image while preventing the resolution from being lowered without duplicating sampling.

[Brief description of drawings]

FIG. 1 is a plan view of a liquid crystal display device according to an embodiment of the present invention.

FIG. 2 is a circuit diagram showing a configuration of a liquid crystal display panel and a signal side driver shown in FIG.

3A to 3V are timing charts for explaining the operation of the liquid crystal display device having the configuration shown in FIGS. 1 and 2.

FIG. 4 is a circuit diagram showing a configuration example of a signal conversion circuit shown in FIGS. 1 and 2.

5A to 5O are timing charts for explaining the operation of the signal conversion circuit shown in FIG.

6 is a circuit diagram showing another configuration example of the signal conversion circuit shown in FIGS. 1 and 2. FIG.

FIG. 7 is a circuit diagram showing an example of a configuration of an additional circuit for enabling double speed driving.

FIG. 8 is a circuit diagram showing an example of a configuration of a signal conversion circuit that enables double speed driving.

9A to 9L are timing charts for explaining the operation of the signal conversion circuit shown in FIG.

FIG. 10 is a circuit diagram showing another example of a configuration of a signal conversion circuit that enables double speed driving.

11A to 11H are timing charts for explaining the operation of the signal conversion circuit shown in FIG.

FIG. 12 is a plan view showing a configuration of a conventional liquid crystal display device.

13 is a circuit diagram showing a configuration of a liquid crystal display panel and a signal side driver shown in FIG.

14A to 14I are timing charts for explaining the operation of the liquid crystal display device configured as shown in FIGS. 12 and 13.

FIG. 15 is a circuit diagram showing a wiring example of a signal line.

FIG. 16 is a plan view showing a modified example of the liquid crystal display device.

17A to 17J are diagrams showing drive waveforms of the liquid crystal display panel of the wiring shown in FIGS. 15 and 16. FIG.

[Explanation of symbols]

11 ... Liquid crystal display panel (liquid crystal display element), 12 ... Lower glass substrate (TFT substrate), 13 ... Upper glass substrate,
14A to 14D ... Signal side driver, 15A, 15B ...
Scanning side driver, 16 ... Flexible circuit board, 17 ...
..Signal conversion circuits, 21 ... Pixel electrodes, 22 ... TFTs, 2
3L, 23U ... signal line, 24 ... gate line, 3
1L, 31U ... Flip-flop, 32L, 32U ...
Analog switch, 33L, 33U ・ ・ ・ Driver, 35 ・
..Timing control units 41 to 52 ... Analog switches, 61 ... A / D converters, 62 to 64 ... Flip-flops, 65, 66 ... D / A converters, 67, 68 ... ..Amplifiers, 71 ... A / D converters, 72 ... Inverters, 73 ...
・ Line memory, 74 ... Inverter, 75 ... D / A converter, 76 ... Forward / inversion amplifier, 77 ... Controller, 81 ... A / D converter, 82-84. ..Flip-flops, 85, 86 ... Line memories, 87, 88 ... D /
A converter, 89, 90 ... Forward / inversion amplifier, 91 ... Controller, 92 ... Dividing circuit, 93, 94 ... Inverter

Claims (14)

[Claims] 1. A liquid crystal display panel comprising a liquid crystal capacitor, a switching element connected to the liquid crystal capacitor, and a signal line connected to the liquid crystal capacitor through the switching element, and the signal lines are drawn in a zigzag pattern in opposite directions. And first and second drive circuits which are arranged on opposite sides of the liquid crystal display panel and which are respectively connected to corresponding signal lines and which drive the signal lines according to the supplied video signals, A liquid crystal display device comprising: a conversion unit that samples the first and second drive circuits at different timings and distributes and supplies them to the first and second drive circuits. 2. The conversion means comprises expansion means for expanding the sampling signal on the time axis and distributing and supplying the sampling signal to the first and second drive circuits. The described liquid crystal display device. 3. The converting means sequentially supplies a plurality of sampling capacitors, the video signal to the sampling capacitors for a predetermined period, and the signals held in the sampling capacitors for a predetermined period. 3. A liquid crystal display device according to claim 1 or 2, further comprising: 4. The converting means comprises A / D converting means for converting the video signal into digital data, and output data of the A / D converting means for the first drive circuit and the second drive circuit. 3. The liquid crystal display device according to claim 1, further comprising: a means for allocating the data, and a D / A conversion means for converting the data distributed by the distribution means into an analog signal and outputting the analog signal. 5. The conversion means includes A / D conversion means for converting the video signal into digital data, and output data of the A / D conversion means for the first drive circuit and the second drive circuit. And a D / A conversion unit that sequentially reads the stored data in the memory, converts the stored data into an analog signal, and outputs the analog signal. The liquid crystal display device according to item 2. 6. The conversion speed of the A / D conversion means and the D
The liquid crystal display device according to claim 5, wherein the conversion speeds of the / A conversion means are substantially equal to each other. 7. The converting means sequentially converts A / D converting means for converting the video signal into digital data, a memory for storing data output from the A / D converting means, and data stored in the memory. A means for allocating the read data and the read data to the first drive circuit and the second drive circuit; and a D / A conversion means for converting the data distributed by the conversion means into an analog signal and outputting the analog signal. The liquid crystal display device according to claim 1 or 2, further comprising: 8. The conversion speed of the D / A conversion means is the A / D
8. The liquid crystal display device according to claim 7, wherein the conversion speed of the conversion means is substantially twice. 9. The video signal includes a video signal of three colors of BGR, and in the liquid crystal display panel, pixels of each color of BGR are regularly arranged in a predetermined order, and the conversion means is configured to The first and second drive circuits include means for sampling each video signal for a period corresponding to 5 pixels and expanding the sampled signal into a signal for a period corresponding to 3 pixels. ,
The liquid crystal display device according to claim 1, further comprising: a unit that performs sampling for a period corresponding to the three pixels and applies a signal corresponding to the sampled signal to a corresponding signal line. 10. The video signal includes a video signal of three colors of BGR, and in the liquid crystal display panel, pixels of each color of BGR are regularly arranged in a predetermined order, and the conversion means is configured to Sampling means for sequentially sampling the video signals of each color for a period corresponding to 5 pixels, storage means for storing the signals sampled by the sampling means, reading the signals stored in the storage means at a predetermined cycle, and The liquid crystal display device according to claim 1, further comprising: a first driving unit and a second driving unit. 11. The first and second driving means display a video signal for one horizontal scanning period on a plurality of scanning lines of the liquid crystal display panel.
0. The liquid crystal display device according to any one of 0. 12. A liquid crystal comprising a liquid crystal capacitor, a switching element connected to the liquid crystal capacitor, and first and second signal line groups connected to the liquid crystal capacitor via the switching element and alternately drawn out in opposite directions. A method of driving a display panel, comprising: a sampling step of sampling video signals for the first signal line group and the second signal line group at different timings; and a sampling signal for the first signal line group. And a allocating step for allocating to the second signal line group, driving the first signal line according to the sampling signal for the first signal line group, and responsive to the sampling signal for the second signal line group. A driving step of driving the second signal line; and a driving method of the liquid crystal display panel, comprising: 13. The video signal includes a video signal of three colors of BGR, and in the liquid crystal display panel, pixels of each color of BGR are regularly arranged in a predetermined order, and the sampling step includes the steps of 1. The video signal is sampled for a period corresponding to 5 pixels, and the driving step applies the supplied video signal to a corresponding signal line for a period corresponding to 3 pixels of the video signal. The method for driving a liquid crystal display panel according to claim 12, wherein: 14. The video signal includes a video signal of three colors of BGR, and in the liquid crystal display panel, pixels of each color of BGR are regularly arranged in a predetermined order, and in the sampling step, the sampled signal is stored in a memory. And a step of reading the signal stored in the memory a plurality of times during one horizontal scanning period of the video signal, and a step of driving the image for one scanning line. 14. The method for driving a liquid crystal display panel according to claim 12, further comprising: displaying on a plurality of scanning lines of the liquid crystal display panel.