JP5382178B2 - Driving circuit for liquid crystal display device - Google Patents

Description

  The present invention relates to a driving circuit for a liquid crystal display device, and more particularly to a driving circuit for an active matrix type liquid crystal display device.

In recent years, a liquid crystal display device of LCOS (Liquid Crystal on Silicon) type is often used as a central part for projecting images in projector devices and projection televisions. This LCOS liquid crystal display device has a structure in which a transparent electrode, a liquid crystal layer, a reflective electrode arranged in a matrix, a liquid crystal driving element in which a liquid crystal driving circuit is formed on a silicon substrate, and the like overlap.

FIG. 22 shows a basic configuration diagram of an example of a liquid crystal driving element used in a conventional liquid crystal display device.
The liquid crystal driving element includes a horizontal driving circuit 10, a vertical driving circuit 20, and an input video signal 71.
To the video switches 1-1, 1-2, 1-3,..., The horizontal signal line 5 and the pixel unit 3
0, data lines 6-1, 6-2, 6-3,..., And gate lines 8-1, 8-2, 8-3,
... and so on. In the drawing, the suffix number after the hyphen of each symbol indicates that the same type of component is in a different position. FIG. 22 shows a part of the entire component.

The pixel unit 30 includes data lines (6-1, 6-2,...) And gate lines (8-1, 8-2).
,...)) Pixels 11 to 13, 21 to 23, 31 to 3 arranged in a matrix.
It consists of 3 mags. Each pixel includes an enlarged view of the pixel 33 and a pixel selection transistor 2 (Q in FIG. 23), a signal holding capacitor 3 (Cs in FIG. 23), and a reflective electrode 4 as shown in FIG.
(PE in FIG. 23). The pixel selection transistor 2 (Q) has a gate connected to the gate line 6 (G in FIG. 23) which is a row scanning line, and a drain connected to the data line 6 (D in FIG. 23).
It is connected to the. Further, as shown in FIG. 23, the liquid crystal element has a configuration in which a liquid crystal display (liquid crystal layer) LCM is sandwiched between a reflective electrode (pixel drive electrode) PE and a counter electrode (common electrode) CE facing each other. ing.

In FIG. 22, the controller 60 supplies various clock signals generated so as to be synchronized with the input video signal 71 to the horizontal direction driving circuit 10 and the vertical direction driving circuit 20 (path is not shown), and the input video signal 71 and By driving the data lines (6-1, 6-2,...) And the gate lines (8-1, 8-2,...) In a synchronized manner, the horizontal and vertical scans are accompanied. Select the selected pixel.

Thus, the data lines (6-1, 6-2,...) And the gate lines (8-1, 8-2,...)
When the pixel at the intersection is selected, the video signal 71 input from the outside is written to the signal holding capacitor 3 via the video switch, the data line, and the vertical pixel selection transistor 2 in each pixel. . Then, the liquid crystal is driven through the reflective electrode (pixel drive electrode) 4 connected to the signal holding capacitor 3.

In the liquid crystal element shown in FIG. 23, the fixed voltage Vcom is applied to the common electrode CE, and various voltages corresponding to the video signal are supplied to the reflective electrode (pixel drive electrode) PE, whereby the light modulation of the liquid crystal display LCM is performed. Control rate and display as video. Normally, since the liquid crystal element can be AC driven for long-term reliability, the reflection electrode (pixel drive electrode) PE modulates light according to the video signal with respect to the fixed voltage Vcom of the common electrode CE. AC driving is performed by alternately applying positive and negative voltages that have the same rate.

Depending on the case, for the purpose of reducing the dynamic range of the video signal, there is an application example in which the voltage of the counter electrode is switched according to the timing of driving with the positive and negative voltages,
The basic idea is the same.

In the liquid crystal driving element as in the example of FIG. 22, the writing of the video signal to each pixel is normally performed once per frame, and alternately on the positive side and the negative side with respect to the common electrode every frame. The video signal is written in the signal holding capacitor 3 (Cs), and the liquid crystal is AC driven. In this case, there is an example of double speed driving in which the liquid crystal is AC driven at a frequency twice as high as the writing frequency, but the frequency is about 60 Hz to 120 Hz, and is not a high frequency in any case.

This is because the video signal is written to the signal holding capacitor 3 (Cs) when the video switch (1
-1, 1-2,...) And the parasitic capacitance of the data lines (6-1, 6-2,...)
Alternatively, since it is performed by charging / discharging in the relationship between the on-resistance of the pixel selection transistor 2 (Q) and the signal holding capacitor 3 (Cs), it is not easy from the viewpoint of device cost to increase the writing frequency. There are also circumstances.

On the other hand, if the liquid crystal element is AC driven at a higher frequency so that the DC component between the reflective electrode (pixel drive electrode) 4 (PE) and the common electrode CE can be reduced to zero, reliability such as burn-in prevention can be achieved. This leads to an improvement in image quality.

Until now, prevention of deterioration of written signals such as countermeasures against feedthrough caused by parasitic capacitance of the pixel selection transistor (for example, refer to Patent Document 1) and countermeasures for leakage of a storage capacitor (for example, refer to Patent Document 2). A method is disclosed. However, it seems that efforts to drive alternating current at higher frequencies have not been studied much.

For each of a plurality of pixels connected to the same scanning line, the storage capacitor of each pixel is alternately connected to the storage capacitor line corresponding to the scanning line and another storage capacitor line corresponding to the adjacent scanning line. The compensation voltage for compensating the direct current component between the pixel drive electrode and the counter electrode is inverted for each storage capacitor line, so that the image quality deterioration caused by the potential fluctuation of the common electrode line or the common electrode is reduced. A liquid crystal display device that prevents generation thereof has been conventionally known (see, for example, Patent Document 3).

JP 2006-10897 A JP 2002-250938 A JP 2004-354742 A

As described above, it is desirable to drive the liquid crystal element with an alternating current at a high frequency as a means for improving reliability such as prevention of burn-in of the liquid crystal element, but it is positive with respect to the counter electrode voltage due to restrictions such as writing time to the pixel. It is difficult to alternately write video signals on the negative side and the negative side at high speed, and conventionally, the frequency of AC drive is only performed at a frame rate or about twice that frequency.

Further, in the liquid crystal display device described in Patent Document 3, the polarity of the compensation voltage can be reversed only for each frame, and the image signal voltage has two types of voltages, positive and negative, with respect to the common electrode voltage Vcom. is necessary.

The present invention has been made in view of the above points, and in an analog drive type liquid crystal display device, each pixel has two kinds of voltages corresponding to positive and negative polarities, so that it is several tens of times the frame frequency. be to polarity reversal at a rate, liquid crystals can be AC driven faster than the prior art, further provides a driving circuits of a liquid crystal display device that give improved productivity to increase the tolerance of the variation of the liquid crystal The purpose is to do.

A liquid crystal display device including a driving circuit according to the present invention includes a plurality of pixels provided at intersections where a plurality of sets of data lines and a plurality of gate lines intersect each other. Provided for each of a plurality of sets of data lines, supplying a positive video signal to one of a pair of two data lines and supplying a negative video signal to the other data line. A plurality of switches that sequentially perform a plurality of sets of data lines in units of sets, a horizontal drive that drives a plurality of switches in units of sets within a horizontal scanning period, and a plurality of gate lines are selected for each horizontal scanning period. Each of the plurality of pixels includes a liquid crystal element in which a liquid crystal layer is sandwiched between the opposing pixel drive electrode and the common electrode, and a positive electrode A certain period of time Holding a first sampling and holding means; a second sampling and holding means for sampling a negative video signal and holding it for a fixed period; a positive video signal voltage held by the first sampling and holding means; and a negative polarity image signal voltage held by the second sampling and holding means, Ru and a switching means for applying alternately to the pixel driving electrode is switched at a predetermined short period from the vertical scanning period.

As a result , a positive voltage and a negative voltage corresponding to the video signal are simultaneously held in parallel in the first and second sampling and holding means in each pixel, so that the video signal of the next frame is written. By switching the positive / negative driving voltage by the switching means at an arbitrary period in the middle of the one frame period, the liquid crystal element can be AC driven at a frequency higher than the one frame scanning period. Chi words, the AC driving frequency of the liquid crystal element, regardless of the vertical scanning frequency, it is possible to freely set the switching period of the drive voltages of the positive and negative polarity, the liquid crystal driving frequency as compared with the conventional liquid crystal display device It can be improved dramatically.

Also, a liquid crystal display device having a drive circuit according to the present invention includes a first buffer amplifier converting the first impedance sampling and positive image signal voltage held by the holding means, a second sampling and holding And a second buffer amplifier for impedance conversion of the negative video signal voltage held by the means, and the switching means has a positive video signal voltage and a negative polarity output from the first and second buffer amplifiers. Ru alternately switching the video signal voltage at a predetermined period.

Thus , when the liquid crystal element is AC driven by switching the positive / negative driving voltage by the switching means, the signal voltage held by the first and second sampling and holding means is not directly transmitted to the pixel drive electrode. In addition, since the pixel drive electrode is driven via the first and second buffer amplifiers, the level of the signal voltage does not decrease even when the switching elements are alternately switched at a plurality of times at a high speed. The advantage that driving can be realized is obtained.

Also, a liquid crystal display device having a drive circuit according to the present invention, Ru Connecting to a common load elements of the first and second buffer amplifier between the output terminal and the ground potential of the switching means.

Thus, since the load element of the buffer amplifier is shared by both the positive and negative first and second buffer amplifiers, the number of transistors per pixel can be reduced, and a higher pixel density can be realized. Further, by reducing the number of transistors, features such as high yield and low cost of the pixel circuit can be obtained.

Also, a liquid crystal display device having a drive circuit according to the present invention, first and second buffer amplifiers, the impedance converting transistors respectively, a constant capable of controlling channel current characteristic by a bias voltage applied to the gate and a current load transistor, in synchronism with the switching timing of the predetermined period of the switching means, Ru provided with a control means for intermittently controlling actively the constant current load transistor by controlling the bias voltage.

As a result , the control of the load currents of the first and second buffer amplifiers is synchronized with the control timing of the polarity switching switching means of the pixel drive voltage, and the polarity switching is limited to only a short period of the polarity switching cycle. By controlling so that current does not always flow at times other than the time, an increase in current consumption can be suppressed.

Also, a liquid crystal display device having a drive circuit according to the present invention, the entire pixel portion comprising a plurality of pixels constituting a display screen, by dividing each pixel of a plurality consecutive rows into a plurality of groups in which one group when, obtain Preparations division control unit when controlling the plurality of constant current load transistor in the plurality of divided groups, in a time division manner active in each divided group.

As a result , the display pixel unit is divided into a plurality of groups in units of a plurality of pixel rows, and the polarity inversion control and the control of the load current of the buffer amplifier are controlled with a predetermined time difference for each group. Prevent pixel buffer amplifiers from becoming active at the same time. As a result, it is possible to prevent current consumption due to the buffer amplifier from flowing in a concentrated manner in all pixels, and to ensure the reliability of the power supply system wiring pattern and the like and to stabilize the operation.

Also, a liquid crystal display device having a drive circuit according to the present invention, in synchronism with the switching period of the positive polarity video signal voltage and a negative polarity video signal voltage applied to the pixel driving electrode, the potential difference across the liquid crystal layer absolute value obtain always Bei common electrode voltage control means for varying between two different levels of common electrode voltage applied to the common electrode so as to be substantially the same.

When the common electrode is driven with a fixed reference voltage by switching the level of the common electrode voltage, which is the reference of the drive voltage applied to the liquid crystal element, so that the polarity is opposite to the polarity of the pixel drive electrode voltage. In comparison with the above, the amplitude of the drive voltage on the pixel side can be reduced to about 1/2 or less. This ensures that the required withstand voltage of the transistors constituting the picture element circuit and peripheral scanning circuits is greatly reduced, special high-voltage structure, application of the process is not necessary, can be reduced device cost. Also, low-voltage, it is possible to configure the drive unit such as a pixel circuit in a small transistor, a higher pixel density liquid crystal display device can be realized, the adoption of the transistor having high driving ability per unit channel width by reducing the transistor breakdown voltage Therefore, it becomes easy to cope with a high-speed driving operation.

Also, a liquid crystal display device having a drive circuit according to the present invention, the common electrode voltage control means, prior to switching timing of the positive polarity video signal voltage and a negative polarity video signal voltage applied to the pixel driving electrode , Ru changing the common electrode voltage applied to the common electrode between two different levels.

As a result , even if the pixel drive electrode potential in a floating state is fluctuated due to capacitive coupling formed between the pixel drive electrode and the common electrode formed by the liquid crystal layer between the pixel drive electrode and the common electrode, the liquid crystal drive The drive voltage can be efficiently applied to the liquid crystal layer without reducing the amplitude of the voltage.

Also, a liquid crystal display device having a drive circuit according to the present invention includes a pixel inspection switching means connected between one of the data lines of the same set of two data lines and the pixel driving electrode, When the image is displayed by alternately switching the positive video signal voltage and the negative video signal voltage to the pixel drive electrode, the inspection switching unit is turned off, and when the pixel is inspected, the inspection switching unit is turned on and the pixel drive electrode is turned on. through the inspection switching means pixel driving electrode voltage from that having a pixel inspection control means for reading out the one of the data lines.

Thereby , in the drive voltage inspection mode of the pixel drive electrode, the inspection switching means is turned on in units of rows, and the configuration is such that the drive voltage of the pixel drive electrode can be read out on the signal line side, thereby obtaining pixel defect information and Since the variation information of the buffer amplifier characteristics for each pixel can be acquired, the manufacturing cost can be reduced, and the processing for canceling the variation of the pixel characteristics by the correction processing of the input video data can be easily introduced, and the image quality can be improved. .

Here, the pixel inspection control means controls all the inspection switching means in the plurality of pixels constituting the display screen to be turned off during image display, and to the same pixel row among the plurality of pixels at the time of pixel inspection. to turn on the inspection switching means is in each pixel, that control in units of pixel row.

In addition, the liquid crystal display device including the driving circuit according to the present invention has a switching cycle between the positive and negative video signal voltages applied to the pixel driving electrode by the switching unit and the common electrode voltage control unit. The level change period of the electrode voltage is N times the horizontal scanning period (N is an arbitrary natural number) that is a selection period of a plurality of gate lines, and a constant phase in each frame with respect to the vertical scanning start reference timing obtain Bei timing control means for controlling to operate in relation.

As a result , video noise generated by interference between signals related to polarity inversion control (control signal of the switching switch, common electrode voltage) and pixel writing operation flows on the screen, and degradation of video quality can be suppressed.

Timing control means of the upper SL, in the period that is writing the video signal to each pixel of the plurality of rows successively in the same polarity period of the polarity inversion control, and the polarity of the level change period of the common electrode voltage, the pixel driving electrode and the polarity of the switching period of voltage, that controls the mutual timing of switching by the common electrode voltage control means and the switching means so as to reverse each scan frame.

As a result , even if there is a difference between the positive polarity and the negative polarity with respect to the above-described signal related to the polarity inversion control (control signal of the changeover switch, common electrode voltage) and the video noise and luminance fluctuation caused by the interference of the pixel writing operation, Since the phase relationship between the vertical scanning and the polarity inversion is changed for each frame, these effects are temporally averaged between the frames, and the image quality can be improved.

To achieve the above object, driving dynamic circuit of the liquid crystal display device according to the present invention includes a shift register circuit for sequentially storing digital video signals when the pixel data is time series synthesis of a plurality of bits by one line, A latch circuit that holds one line of digital video signals sequentially stored in the shift register circuit, and a gradation that outputs reference gradation data in which a plurality of gradation values change sequentially within the horizontal scanning period A comparator that compares the value of pixel data for one line output from the latch circuit with the gradation value of the reference gradation data output from the gradation counter, and generates a coincidence pulse when they match. And a period in which the level changes from the black level to the white level of the video in the horizontal scanning period cycle or the level decreases from the white level to the black level. A first reference voltage which is No.引信, a reference voltage generating circuit generating a second reference voltage is a periodic sweep signal in inverted relationship for a given potential with respect to the first reference voltage, a plurality In the plurality of pixels arranged at the intersections of each of the gate lines and the plurality of sets of data lines each including two data lines and connected to each of the gate lines and the two data lines, the same column A first drive signal of a level corresponding to the generation timing of the coincidence pulse is generated by sampling the first reference voltage with the coincidence pulse. The first analog switch and the second reference voltage output to one of the two data lines are sampled by the coincidence pulse simultaneously with the sampling of the first analog switch. A second driving signal having a level corresponding to generation timing of the pulses, and a plurality of sets of analog switches to a second analog switch, a pair of outputting the other data line of the two data lines,
Characterized in that it comprises a.

Here, the reference voltage generation circuit includes a first wiring that transmits the first reference voltage and a second wiring that transmits the second reference voltage in a plurality of sets of wiring groups. The first and second reference voltages are divided and output, and the plurality of pixels are divided into a plurality of groups of pixel columns, and each of the first and second analog switches of a set of analog switches in each group of pixel columns input terminals of, among a plurality of sets of wire group, may be connected to the first and second wires each set of wire groups assigned to correspond.

To achieve the above object, driving dynamic circuit of the liquid crystal display device according to the present invention, first and second reference from the reference voltage generating circuit to the first and second input terminals of the plurality of sets of analog switches A plurality of feeding points having different positions in the longitudinal direction of the first and second wirings for transmitting voltages are provided.

Also, the driving method of a liquid crystal display device having a drive circuit according to the present invention, provided at the intersections of a plurality of sets of data lines and a plurality of gate lines and two data lines and one set intersect each In each of the plurality of pixels, a driving voltage corresponding to the positive video signal transmitted on one of the two data lines in each set is sampled on the pixel driving electrode at a predetermined cycle shorter than the vertical scanning period to be a first constant. Corresponding to the negative video signal transmitted on the other of the two data lines in each set at the timing of the time difference between the first sampling step for holding the period and the time difference of half the predetermined cycle from the sampling time point in the first step A second sampling step in which the driving voltage is sampled on the pixel driving electrode at a predetermined period and held for a first fixed period, and is synchronized with the sampling by the first sampling step. The first impedance conversion step in which the first buffer amplifier for impedance conversion of the held positive video signal voltage is activated for the second fixed period, and the sampling is held in synchronization with the sampling by the second sampling step. A second impedance conversion step in which a second buffer amplifier for impedance conversion of the negative video signal voltage is activated for a second fixed period; and a first positive video signal whose impedance has been converted by the first and second impedance conversion steps. a voltage and a negative polarity image signal voltage, is provided in each of a plurality of pixels, the pixel driving electrode voltage applying step and the including applied alternately to the pixel driving electrode of the liquid crystal element.

Also, the driving method of a liquid crystal display device having a drive circuit according to the present invention, the entire pixel portion comprising a plurality of pixels constituting a display screen, a plurality of one group of pixels of the plurality of rows of successive groups when divided, the load element of the first and second buffer amplifiers in a plurality of divided groups, including the sharing control step when controlling the time division manner active in each divided group.

Also, the driving method of a liquid crystal display device having a drive circuit according to the present invention, in synchronism with the switching period of the positive polarity video signal voltage and a negative polarity video signal voltage applied to the pixel driving electrode, the liquid crystal element A common electrode voltage control step of changing a common electrode voltage applied to the common electrode facing the pixel driving electrode of the liquid crystal element between two different levels so that the absolute value of the potential difference applied to the liquid crystal layer is always substantially the same; after changing the level of the common electrode voltage by the common electrode voltage control step, it intends sequentially line the sampling by the sampling of the first sampling step the second sampling step.

Also, the driving method of a liquid crystal display device having a drive circuit according to the present invention includes a switching period of the positive polarity video signal voltage and a negative polarity video signal voltage according to the pixel driving electrode voltage applying step, by the common electrode voltage control step The level change period of the common electrode voltage is N times (N is an arbitrary natural number) the horizontal scanning period, which is the selection period of the plurality of gate lines, and is constant in each frame with respect to the vertical scanning start reference timing. further including a timing control step of controlling to operate in phase relationship.

Also, the driving method of a liquid crystal display device having a drive circuit according to the present invention, the timing control step is performed writing of the video signal to each pixel of the plurality of rows successively in the same polarity period of the polarity inversion control In the period, the polarity of the level change period of the common electrode voltage and the polarity of the switching period of the pixel drive electrode voltage are reversed between the pixel drive electrode voltage application step and the common electrode voltage control step so that the polarity is reversed every scan frame. that controls the timing.

According to the present invention, since the liquid crystal can be AC driven at high speed without increasing the writing frequency to the pixel, the DC component between the pixel drive electrode and the common electrode can be reduced, and image quality such as prevention of liquid crystal burn-in can be achieved. And the reliability can be improved, and the margin for adjusting the voltage of the common electrode can be increased to improve the productivity. This makes it possible to greatly improve the reliability and stability and display quality degradation when the AC drive of the liquid crystal is at a low frequency, as well as the effect of improving the manufacturing yield and reducing the size of the drive circuit. Thus, a low-cost liquid crystal display device can be realized. This also means that the tolerance for variations in liquid crystal characteristics increases, leading to cost reduction.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram of a first embodiment of a pixel circuit in a liquid crystal display device according to the present invention, and FIG. 2 is a basic configuration of an embodiment of a liquid crystal driving element used in the liquid crystal display device according to the present invention. The figure is shown. In both drawings, the same components are denoted by the same reference numerals.

Each pixel in the liquid crystal display device of the present embodiment has the configuration of the pixel circuit shown in FIG. As shown in FIG. 1, the pixel circuit of the present embodiment has pixel selection transistors Q1 and Q2 each having a gate connected to a gate line 8-1, and one end connected to each source of the pixel selection transistors Q1 and Q2. , The storage capacitors (capacitors) C1 and C2 whose other ends are commonly connected to the common electrode line 7, the connection point between the pixel selection transistor Q1 and the storage capacitor C1, and the connection point between the pixel selection transistor Q2 and the storage capacitor C2. Buffer amplifiers A1 and A2 whose input ends are connected to each other, selector switches S1 and S2 whose one ends are connected to the output ends of the buffer amplifiers A1 and A2, and common connection points of the other ends of the selector switches S1 and S2, respectively. And a common electrode line 7 and a storage capacitor C3 for driving liquid crystal, and a reflective electrode (hereinafter also referred to as a pixel driving electrode) 4. There. The drains of the pixel selection transistors Q1 and Q2 are separately connected to the data lines 6-1a and 6-1b. The liquid crystal element according to the present embodiment is a liquid crystal element having a known structure shown in FIG. 23, and corresponds to a pixel drive electrode PE corresponding to the reflective electrode 4 and a counter electrode facing the pixel drive electrode PE. A liquid crystal display (liquid crystal layer) LCM is sandwiched between the common electrode CE.

A basic configuration of an embodiment of a liquid crystal driving element used in the liquid crystal display device according to the present invention is shown in FIG. 2, which is the same as the basic configuration of FIG. However, in this embodiment, as shown in FIG. 2, two horizontal signal lines, data lines, and switches are provided. That is, the liquid crystal driving element of the present embodiment includes a horizontal driving circuit 10, a vertical driving circuit 20,
A video signal 71a on the positive side and a video signal 71b on the negative side with respect to the common electrode voltage are separately supplied to the two video switches 1-1a and 1-1b, 1-2a and 1-2b,. Two horizontal signal lines 5a and 5b, a pixel unit 30, and two data lines 6-1a and 6-1b and 6-2.
are composed of a and 6-2b,..., and gate lines 8-1, 8-2,.
In the drawing, the suffix number after the hyphen of each symbol indicates that the same type of component is in a different position. Also, the lowercase letter a following the suffix number indicates the first system of the two systems, and b indicates the second system. FIG. 2 shows a part of the entire component.

The pixel unit 30 includes two data lines (6-1a and 6-1b,...) And a gate line (8-1).
, 8-2,...) Arranged in a matrix at pixels 41, 42, 51, 52 and the like having the circuit configuration of FIG. The horizontal driving circuit 10 has two systems of switches 1-1.
a, 1-1b and pixels 41, 51 in the first column via two data lines 6-1a, 6-1b.
Are connected to the drains of the pixel selection transistors Q1 and Q2, respectively.

Similarly, the horizontal driving circuit 10 includes pixels 42, 52,... In the second column via two systems of switches 1-2a and 1-2b and two systems of data lines 6-2a and 6-2b. Are connected to the drains of the pixel selection transistors Q1 and Q2, respectively, and are connected to the drains of the two pixel selection transistors of the pixels in the third and subsequent columns in the same manner via two systems of switches and two systems of data lines. Yes.

The vertical driving circuit 20 includes the pixels 41 in the first row in the pixel unit 30 via the gate line 8-1.
, 42,... Are commonly connected to the gates of two pixel selection transistors Q1 and Q2. Similarly, the vertical driving circuit 20 is commonly connected to the gates of two pixel selection transistors of each pixel in the same row in the pixel unit 30 through each gate line.

Further, the controller 60 supplies various clock signals generated so as to be synchronized with the input video signals 71a and 71b to the horizontal direction driving circuit 10 and the vertical direction driving circuit 20 (paths are not shown), and the input video signal 71a, Data lines (6-1a, 6-1b,... In synchronization with 71b
..., By driving the gate lines (8-1, 8-2,...), Pixel selection with horizontal and vertical scanning is performed. Thereby, in this Embodiment, it becomes possible to perform alternating current drive of a liquid crystal at high speed.

Next, the operation of the pixel circuit of the first embodiment shown in FIG. 1 will be described. Data line 6-
1a supplies a video signal 71a on the positive side with respect to the common electrode voltage of the liquid crystal. At the same time, the data line 6-1b supplies the video signal 71b on the negative side with respect to the common electrode voltage. The pixel selection transistors Q1 and Q2 are simultaneously turned on by a voltage applied to the gate via the gate line 8-1. Thus, the positive video signal 7 supplied from the data line 6-1a.
1a is written into the storage capacitor C1 through the drain and source of the pixel selection transistor Q1. On the other hand, at the same time, the negative video signal 71b supplied from the data line 6-1b is
Data is written into the storage capacitor C2 through the drain and source of the pixel selection transistor Q2.

Subsequently, the pixel selection transistors Q1 and Q2 are simultaneously turned off by a voltage applied to the gate via the gate line 8-1. As a result, the positive and negative video signals 71a and 71b are held in the holding capacitors C1 and C2, respectively, until the next video signals 71a and 71b for which the pixel selection transistors Q1 and Q2 are next turned on are written.

The positive and negative video signals 71a and 71b held in the holding capacitors C1 and C2, respectively, are read out through buffer amplifiers A1 and A2 which are impedance conversion circuits having high input resistances, respectively, and changeover switches S1 and S2 Are alternately selected, and the liquid crystal is AC driven by changing the voltage of the reflective electrode 4 (pixel drive electrode PE).

According to this pixel configuration, once the positive and negative video signals 71a and 71b are written to the holding capacitors C1 and C2 once per frame, one frame period until the video signal of the next frame is written. The liquid crystal can be AC driven by alternately switching the changeover switches S1 and S2 any number of times.

In other words, according to the pixel circuit of the present embodiment in FIG. 1, the liquid crystal can be AC driven at a high frequency, for example, several tens of times the frame frequency, independently of the video signal writing cycle. As a result, the present embodiment provides effects such as prevention of burn-in, improvement of reliability, and improvement of display quality where no spots or irregularities are visible. In this embodiment, the voltage of the counter electrode of the liquid crystal can be shaken (changed) in accordance with the polarity inversion, and the signal voltage can be reduced to half or less of the conventional voltage.

Further, since the liquid crystal display device of this embodiment can be manufactured using a standard CMOS process, two selection pixel transistors Q1 and Q2, two buffer amplifiers A1 and A2, and two changeover switches S1 per pixel. S2 and two holding capacitors C1 and C2, and even if the number of elements is relatively large, the increase in the number of elements does not necessarily increase the cost.

Here, each pixel has buffer amplifiers A1 and A2, and if a direct current continues to flow even though the current is small, the liquid crystal drive element as a whole usually has one million pixels or more.
There may be adverse effects such as increased power consumption and heat generation.

As a preventive measure, the buffer amplifiers A1 and A2 and the changeover switches S1 and S2 are
It is effective to perform pulse driving that enables only for a period necessary for signal readout. The holding capacitor C3 is for performing this operation. During the enable period, the signal that has passed through the change-over switch S1 or S2 is written into the holding capacitor C3, and when both are off, the written signal is stored in the holding capacitor. The liquid crystal is driven while being held at C3. As a result, the liquid crystal can be AC driven at a higher frequency than before while suppressing a significant increase in power consumption, and many effects as described above can be obtained.

FIG. 3 is a detailed circuit diagram showing the pixel circuit of the first embodiment of the liquid crystal display device according to the present invention shown in FIG. 1 in more detail. As shown in FIG. 3, one pixel circuit of the liquid crystal display device of this embodiment includes pixel selection transistors Q1 and Q2 for writing positive and negative pixel signals, and image signal voltages of respective polarities in parallel. And two independent storage capacitors Cs1 and Cs2 (corresponding to C1 and C2 in FIG. 1), transistors Q3 to Q8, and a liquid crystal element having the same configuration as shown in FIG. .

The source follower circuit for impedance conversion comprising the transistors Q3 and Q7 is shown in FIG.
Buffer amplifier A1. The impedance conversion source follower circuit including the transistors Q4 and Q8 constitutes the buffer amplifier A2 of FIG. A transistor Q5 having a drain connected to the source of the transistor Q3 and a transistor Q6 having a drain connected to the source of the transistor Q4 are switching transistors corresponding to the changeover switches S1 and S2 in FIG. 1, respectively. The sources of the transistors Q5 and Q6 are connected to the reflective electrode CE of the liquid crystal element. Note that the storage capacitor C3 in FIG. 1 is not shown in FIG. This is because the holding capacitor C3 can be substituted by the parasitic capacitances of the transistors Q5 and Q6 and the parasitic capacitance of the liquid crystal, and may not be formed if the leakage current of the node of the reflective electrode PE is sufficiently small. .

The pixel portion data line is composed of a pair of positive data line D + and negative data line D− for each pixel circuit, and video signals having different polarities sampled by a data line driving circuit (not shown). Is supplied. The drain terminals of the pixel selection transistors Q1 and Q2 are respectively connected to a positive polarity data line Di + (corresponding to 6-1a in FIG. 1) and a negative polarity data line Di− (6-1 in FIG. 1).
b), each gate terminal is connected to a row scanning line Gj (gate line 8 in FIG. 1) for the same row.
-1).

When a scanning pulse is supplied from a vertical scanning circuit (not shown), the pixel selection transistors Q1, Q
2 is turned on at the same time, and positive and negative signal voltages are accumulated in the holding capacitors Cs1 and Cs2, respectively. The circuit part composed of the transistors Q3 and Q7 and the circuit part composed of the transistors Q4 and Q8 are so-called source follower buffers. The transistors Q3 and Q4 function as signal input transistors and the transistors Q7 and Q8 function as constant current source loads. . The constant current source load transistors Q7 and Q8 are configured such that the gates are commonly wired to the row direction wiring B for the same row pixel, and the bias control of the constant current load is possible. MOS transistor Q
3, Q7, Q4, and Q8 input resistance of the source follower buffer is almost infinite.
For this reason, as in the conventional active matrix liquid crystal display device, the charge accumulated in the storage capacitor terminal does not leak and is held until a signal is newly written after one vertical scanning period.

The switching transistors Q5 and Q6 switch and send the output signal of the source follower buffer to the pixel display unit composed of the reflective electrode (pixel drive electrode) PE, the liquid crystal display LCM, and the common electrode CE. The gate terminals of the transistor Q5 for switching the positive polarity signal and the transistor Q6 for switching the negative polarity signal are independent, and each is connected to the wirings S + and S− in the row direction for the same row pixel. Yes.

The gate control signal supplied alternately to the wirings S + and S-
5 and Q6 can be turned on alternately to give a liquid crystal drive signal that is inverted between positive polarity and negative polarity to the pixel drive unit. In the conventional active matrix liquid crystal display device, the polarity inversion can be realized only in the vertical scanning period, whereas in the present embodiment, the pixel circuit itself has a polarity inversion function, which can be controlled at high speed. With no restriction of vertical scanning frequency,
AC drive at a high frequency is possible.

Next, a pixel circuit according to a second embodiment of the present invention will be described. FIG. 4 is a detailed circuit diagram of the pixel circuit of the second embodiment of the active matrix type liquid crystal display device according to the present invention. In the figure, the same components as those in FIG. The basic configuration and function of the pixel circuit of the present embodiment shown in FIG. 4 are similar to those of the pixel circuit of the first embodiment shown in FIG. 1 and FIG. . A feature of the pixel circuit of the present embodiment shown in FIG. 4 is that a constant current load transistor Q9 forming a source follower buffer is arranged at the subsequent stage of the polarity switching switching transistors Q5 and Q6, that is, at the node of the pixel drive electrode PE. In this configuration, the positive and negative source follower circuits function in common as loads.

Therefore, according to the present embodiment, the number of transistor elements per pixel circuit is as shown in FIGS.
One less than the pixel circuit of the first embodiment shown in FIG. 1 and the positive and negative electrodes caused by variations in the load of the positive and negative buffer amplifiers in the same pixel. There is an advantage that the difference in characteristics can be suppressed.

Next, a pixel circuit according to a third embodiment of the liquid crystal display device according to the present invention will be described. FIG. 5 is a circuit diagram of a pixel circuit of a third embodiment of the liquid crystal display device according to the present invention, and FIG. 6 is an embodiment of the liquid crystal display device according to the present invention using the circuit of FIG. 5 as the pixel circuit. The block diagram of the principal part of a form is shown. In both figures, the same components as those in FIG. In the pixel circuit of this embodiment shown in FIG. 5, as compared with the pixel circuit of FIG. 4 described above, a transistor as an inspection switching means is further provided between the pixel drive electrode and the video signal writing data line 6-1a. Q10
This is characterized by the addition of.

The gates that are the read control terminals of the transistors Q10 in the pixel circuits in the same row are commonly wired to the read switch selection line RD. The selection control signal applied to the gate of the transistor Q10 via the selection line RD controls the transistors Q10 in all the pixel rows in the normal image display mode, and controls the transistors in the pixel row to be inspected in the pixel inspection mode. Q10 is sequentially turned on. Here, the pixel inspection mode is a mode in which pixel values are read out to the data line pixel by pixel from a pixel portion in which a plurality of pixels are arranged in a matrix, and the presence or absence of defects is inspected pixel by pixel. Accordingly, in the pixel inspection mode, the video signal for writing is not input to the data line, and the pixel portion is set to the reading mode.

The row selection means in such a pixel inspection mode is realized with the same configuration as that of the vertical driving circuit formed of a shift register, similarly to the writing of the video signal. It is also possible to share the shift register of the vertical driving circuit for signal writing with the row selection means in the pixel inspection mode.

FIG. 6 shows an overall configuration diagram of an embodiment of a liquid crystal display device corresponding to the pixel inspection mode. In the figure, the same components as those in FIG. In FIG. 6, the pixel circuit 8
1 is provided in n rows in the vertical direction, and m columns are provided in the horizontal direction although not shown. A gate line 8-1 and a read switch selection line RD1 are commonly connected to the m pixel circuits 81 in the first row. A gate line 8-n and a read switch selection line RDn are commonly connected to the m pixel circuits 81 in the n-th row. M pixel circuits 81 in each other row i
Similarly, the gate line 8-i and the read switch selection line RDi are commonly connected to each pixel row.

The AND circuit 1-1 includes a selection control signal from the control terminal WT / RD and the vertical driving circuit 20.
And the vertical direction drive signal from the output terminal of the first row is subjected to AND operation and output to the gate line 8-1. The AND circuit 1-2 performs an AND operation on a signal obtained by logically inverting the selection control signal from the control terminal WT / RD by the inverter INV and the vertical direction drive signal from the output terminal of the first row of the vertical direction drive circuit 20. Then, the data is output to the selection line RD1 of the read switch.

The AND circuit n-1 includes a selection control signal from the control terminal WT / RD and the vertical driving circuit 20.
The vertical direction drive signal from the output terminal of the nth row is ANDed and output to the gate line 8-n. The AND circuit n-2 performs a logical AND operation on the signal obtained by logically inverting the selection control signal from the control terminal WT / RD by the inverter INV and the vertical direction drive signal from the nth row output terminal of the vertical direction drive circuit 20. And output to the selection line RDn of the read switch.

Similarly, each pixel circuit in the other pixel row i performs a logical product operation on the selection control signal and the vertical direction drive signal from the output terminal of the i-th row of the vertical direction drive circuit 20 and outputs it to the gate line 8-i. AN
A D switch, a signal obtained by logically inverting the selection control signal by the inverter INV, and a vertical direction drive signal from the output terminal of the i-th row of the vertical direction drive circuit 20 are subjected to a logical product operation to select the read switch selection line RDi. Is connected to an AND circuit. These selection lines RD1 to RD
i is connected to the gate of the transistor Q10 shown in FIG. 5 in the pixel circuit 81 in the same pixel row.

The control terminal WT / RD is supplied with a high-level selection control signal in the normal image display mode (pixel writing mode), and in the pixel inspection mode (pixel readout mode).
A low level selection control signal is supplied. A configured in each output stage of the vertical driving circuit 20
Due to the gate function of the ND gates (AND1-1, AND1-2,..., ANDn-1, ANDn-2), the gate lines 8-1 of the pixel circuit 81 in the normal image display mode (pixel writing mode),. ..Selection pulses are sequentially output to 8-n, etc.

On the other hand, in the pixel inspection mode (pixel readout mode), an AND gate (AND1-1, A
ND1-2,..., ANDn-1, ANDn-2) sequentially outputs selection pulses to the read switch selection lines RD1,. Thus, the mode switching can be performed by sharing the vertical driving circuit 20 by the selection control signal input via the control terminal WT / RD.

In the pixel inspection mode, the transistor Q10 shown in FIG. 5 in the pixel circuit in the selected pixel row is turned on by a selection pulse applied to the gate through the selection line RD of the readout switch. As a result, the pixel drive electrode (reflecting electrode) 4 and the data line become conductive, and the pixel drive electrode voltage is output to the data line. At this time, when the buffer amplifier (load element) of the pixel circuit in the selected row in the pixel inspection mode is activated and one of the polarity switching control switches Q5 and Q6 is turned on, the pixel drive electrode is set to buffer output during that period. It is possible to read the driving voltage applied to the pixel driving electrode to the signal line side as a voltage output.

The pixel drive electrode voltage read to the data line side is driven by the horizontal direction drive circuit 10 in FIG. 6, and thereby the video data common input terminal (in the example of FIG. 6) via the sampling switch.
Video (+)) is output as a time series signal. By detecting this time series signal, inspection of the pixel circuit (detection of pixel defects) can be performed.

Furthermore, the same signal voltage is written to all the pixels in the pixel row to be inspected, and then reading is performed. By detecting variations in the readout signal on the video data common input terminal side, it is possible to detect variations in the characteristics of the buffer amplifier for each pixel. It can be carried out. By creating correction data for pixel characteristic variations based on the read voltage variation information and correcting the input video signal, it is possible to correct pixel characteristic variations and obtain uniform display characteristics. Further, in order to individually detect and measure the characteristics of the buffer amplifier on the positive polarity side and the negative polarity side, inspection and measurement may be performed while switching the polarity changeover switches Q5 and Q6.

In the conventional active matrix liquid crystal display device, the pixel is driven by the voltage held in the form of the charge held in the holding capacitor, so the pixel readout inspection is a highly accurate detection that detects a minute current change during charge movement. Whereas an amplifier or the like is required, in the combination of the pixel circuit according to the present embodiment and its inspection / reading means, the voltage of the pixel drive electrode, that is, the voltage of the pixel drive electrode driven with a low output impedance by the buffer amplifier output itself Therefore, pixel defect detection and pixel characteristic detection can be performed more easily.

In addition, as described in FIG. 1, FIG. 3, or FIG. 4, when the configuration in which the pixel circuit is provided with the buffer amplifier as in the liquid crystal display device of the present invention, the characteristic variation of each pixel of the buffer amplifier is large. The brightness difference appears as fixed pattern noise. On the other hand, since the embodiment of FIGS. 5 and 6 can be provided with means for accurately detecting variations in pixel characteristics, correction processing is applied to input video data based on the detection results of variations in pixel characteristics. By doing so, it is possible to realize high-quality image display with little influence of pixel variation.

  The embodiments of the pixel circuit of the liquid crystal display device according to the present invention have been described above.

Next, an outline of AC drive control of the liquid crystal display device according to the present invention will be described. FIG. 7 is a timing chart for explaining an outline of AC drive control of the liquid crystal display device according to the present invention. 7A shows the vertical synchronization signal VD, and FIG. 7B shows the load characteristic control signal of the wiring B applied to the gates of the transistors Q7 and Q8 in the pixel circuits of FIGS. FIG. 7C shows a gate control signal of the wiring S + applied to the gate of the switching transistor Q5 for transferring the positive side drive voltage in the pixel circuit, and FIG. 7D shows the negative electrode in the pixel circuit. 4 shows each signal waveform of a gate control signal of the wiring S− applied to the gate of the switching transistor Q6 that transfers the active drive voltage. The transistors Q7 and Q8 are constant current loads of the source follower buffer circuit in the pixel circuit as described above.

FIG. 8 shows the relationship from the black level to the white level of the positive polarity video signal I and the negative polarity video signal II written to the pixel. The positive video signal I has a black level when the level is minimum and a white level when the level is maximum, whereas the negative video signal II has a white level when the level is minimum and a black level when the level is maximum. The inversion center of the positive video signal I and the negative video signal II is indicated by III.

In FIG. 8, the positive polarity video signal I indicates the black level when the level is minimum and the white level when the level is maximum, and the negative polarity video signal II indicates the white level when the level is minimum and the black level when the level is maximum. However, in the pixel circuit of the liquid crystal display device of the present invention, the positive video signal I is a white level when the level is minimum, a black level when the level is maximum, and the negative video signal II is black when the level is minimum. The level may be a white level at the maximum.

In the pixel circuits shown in FIGS. 3 and 4, the positive polarity side switching transistor Q5 is turned on during the period when the gate control signal of the wiring S + shown in FIG. When the load characteristic control signal to be performed is set to a high level as shown in FIG.
The source follower buffer circuit becomes active, and the pixel drive electrode PE node is charged to the positive video signal level. When the potential of the pixel drive electrode PE is fully charged, the load characteristic control signal of the wiring B is set to a low level, and at that time, the gate control signal of the wiring S + is also switched to a low level. The drive electrode PE is in a floating state, and a positive drive voltage is held in the liquid crystal capacitor.

On the other hand, the negative side switching transistor Q6 is turned on while the gate control signal of the wiring S- shown in FIG. 7D is at a high level, and the load characteristic control signal supplied to the wiring B during this period is shown in FIG. ), The source follower buffer circuit becomes active and the pixel drive electrode PE node is charged to the negative video signal level. When the potential of the pixel drive electrode PE is fully charged, the load characteristic control signal of the wiring B is set to the low level, and the gate control signal of the wiring S- is also switched to the low level at that time. The drive electrode PE is in a floating state, and the negative drive voltage is held in the liquid crystal capacitor.

Hereinafter, in synchronization with the switching in which the switching transistors Q5 and Q6 are alternately turned on, the operation of intermittently activating the constant current load transistors Q7 and Q8 or Q9 is repeated, thereby repeating the pixel driving electrode PE of the liquid crystal element. A drive voltage VPE converted into an alternating current with each of the positive and negative video signals is applied to the terminal as shown in FIG.

In the present embodiment, the held charge is not directly transferred to the pixel driver, but is supplied with a voltage via the source follower buffer circuit. There is no problem of sum, and driving without voltage level attenuation can be realized even if polarity switching is performed many times.

Further, Vcom shown in FIG. 7F represents a voltage applied to the common electrode CE formed on the counter substrate of the liquid crystal display device. The substantial AC drive voltage of the liquid crystal display LCM is a difference voltage between the applied voltage Vcom of the common electrode CE and the applied voltage of the pixel drive electrode PE. In the present embodiment, as shown in FIG. 7F, the applied voltage Vcom of the common electrode CE is synchronized with the pixel polarity switching with respect to a reference level substantially equal to the inversion reference level Vc of the pixel drive electrode potential. Inverted. As a result, the absolute value of the potential difference between the applied voltage Vcom of the common electrode CE and the applied voltage of the pixel drive electrode PE is always the same, and the liquid crystal display LCM does not have a DC component as shown in FIG. VLC is applied. The applied voltage Vcom of the common electrode CE is output from the controller 60 shown in FIG.

As described above, in the present embodiment, the amplitude of the drive voltage on the pixel (PE) side can be reduced to about ½ or less by switching the voltage applied to the common electrode CE in a phase opposite to that of the pixel drive electrode PE. As a result, the required withstand voltage of the transistors constituting the pixel circuit and the peripheral scanning circuit is greatly reduced, the application of a special high withstand voltage structure and process is not required, and the device cost can be reduced. Also,
In this embodiment mode, a driver unit such as a pixel circuit can be configured with a low breakdown voltage, small transistor as described above, so that a liquid crystal display device with higher pixel density can be realized, and driving per unit channel width can be achieved by reducing transistor breakdown voltage. Since it is possible to employ a transistor with high capability, it is possible to obtain an effect that it is easy to cope with a high-speed driving operation.

Further, in this embodiment, as shown in FIG. 7A, the load characteristic control signal of the wiring B is used as a pulse train, and the constant current load transistors (Q7 and Q8 in FIG. 3) of the source follower buffer circuit are used.
Is not always active, and is controlled so as to be active only in a limited period within the conduction period of the polarity switching switching transistors (Q5 and Q6 in FIG. 3). This is because a reduction in current consumption in the liquid crystal display device is taken into consideration. For example, even if the current of the steady source follower buffer circuit per pixel circuit is a very small current of 1 μA, a large current is consumed under the condition that all the pixels of the liquid crystal display device constantly consume the current. There is a problem that. For example, in a full high-definition (2 million pixels) liquid crystal display device, the current consumption reaches 2 A.

For this reason, in the present embodiment, as shown in FIGS. 7A to 7C, the polarity switching switching transistors (Q5, Q) supplied with the gate control signals through the wirings S + and S− are at a high level. Only during the conduction period of Q6), the constant current load transistor of the source follower buffer circuit with the load characteristic control signal supplied via the wiring B set to high level (Q7, Q8 in FIG. 3)
The driving period is limited. As a result, immediately after the electrode voltage VPE of the liquid crystal element is charged / discharged to the target level as shown in FIG. 7D, the load characteristic control signal is immediately set to the low level and the constant current load transistors (Q7, Q8) are turned on. It turns off and the current of the source follower buffer circuit stops. Therefore, according to the present embodiment, it is possible to suppress a substantial current consumption even though the configuration includes a buffer amplifier in all pixels.

Next, another embodiment of the control means of the source follower buffer circuit will be described with reference to FIGS. In the embodiment described with the timing chart of FIG. 7, an example in which intermittent active control is performed so that current does not constantly flow through the source follower buffer circuit has been described. In contrast, the present embodiment is further characterized in that a control means is provided so that all the pixels are not turned on at the same time.

FIG. 9 shows a configuration diagram of an embodiment of a main part of a liquid crystal display device according to the present invention. In this embodiment, polarity inversion control and active control of the source follower buffer circuit are realized with a time difference in the vertical direction of the screen. As shown in FIG. 9, in the present embodiment, divided pixel units 90-1, 90-2,..., In which the pixel unit 30 in FIG. 2 is divided into h in the vertical direction (h is a natural number of 2 or more). 90-h, and a shift register of h stages for shifting the polarity switching gate control signal of the wiring S +, the polarity switching gate control signal of the wiring S-, and the load characteristic control signal of the wiring B in synchronization with the same shift clock SCK. 91a, 91b, and 91c. The shift registers 91a, 91b, and 91c correspond to the vertical driving circuit 20 shown in FIG. FIG. 9 shows only circuit portions necessary for active control of the source follower buffer circuit, and illustration of the horizontal direction drive circuit 10 and the like is omitted.

Each of the divided pixel portions 90-1, 90-2,..., And 90-h is a divided pixel portion of groups # 1, # 2,. is there. The shift register 91a includes the input terminals S + (1) of the divided pixel units 90-1, 90-2,.
, S + (2), ... and S + (h), the gate control signal for switching the polarity of the wiring S + is in the first stage, the second stage,
... Supply from the output terminal of the h-th stage. The shift register 91b includes a divided pixel unit 90.
-1, 90-2,... And 90-h input terminals S- (1), S- (2),.
A gate control signal for switching the polarity of the wiring S- is supplied from the output terminals of the first stage, the second stage,. Further, the shift register 91c includes divided pixel units 90-1, 90-2,.
Load characteristic control signal of wiring B is 1 to each input terminal B- (1), B- (2), ... and B- (h) of 0-h.
Supplied from the output terminals of the 2nd stage,..., H stage.

FIG. 10 is a timing chart of signals at various parts in FIG. FIG. 10A shows the shift clock SCK supplied to the shift registers 91a, 91b and 91c. In synchronism with this shift clock SCK, the shift register 91a shifts the polarity switching gate control signal of the wiring S + shown in FIG. 10B, and outputs it from the output terminals of the first, second and h stages. (C),
The gate control signals shown in (D) and (E) are output, and the divided pixel units 90-1, 90-2, 90-
It is supplied to each input terminal S + (1), S + (2), S + (h) of h.

Similarly, the shift register 91b shifts the polarity switching gate control signal for the wiring S- shown in FIG. 10F, and outputs the output signals from the first, second, and h-stage output terminals in FIG. (H), (I
) And are supplied to the input terminals S- (1), S- (2), and S- (h) of the divided pixel portions 90-1, 90-2, and 90-h. Further, the shift register 91c shifts the load characteristic control signal of the wiring B shown in FIG. 10 (J) from the output terminals of the first stage, the second stage, and the h stage.
The load characteristic control signals shown in (K), (L), and (M) are output, and the divided pixel units 90-1 and 90- are output.
2 and 90-h input terminals B- (1), B- (2), and B- (h).

According to this embodiment, it is possible to perform polarity inversion and buffer active control with a time difference for the divided group in the vertical direction of the screen, and the current value is dispersed and averaged in time, so that the instantaneous overcurrent is caused. Malfunctions and failures can be avoided. In order to prevent the influence of the control time difference from affecting the display characteristics, the frequency of the shift clock SCK may be selected to be sufficiently higher than the polarity inversion frequency.

Next, an example of optimizing mutual timing control for switching the polarity of the pixel drive electrode (reflecting electrode) and the common electrode will be described with reference to FIGS. FIGS. 11A1 to 11E1 are timing charts when the polarity switching of the pixel drive electrode precedes the polarity switching timing of the common electrode. FIGS. 11A2 to 11E2 are timing charts when the polarity switching of the common electrode precedes the polarity switching timing of the pixel drive electrode.

11A1 and 11A2 show the voltage Vcom applied to the common electrode CE of the liquid crystal element. 11B1 and 11B2 are gate control signals of the wiring S + applied to the gate of the switching transistor Q5 that transfers the positive drive voltage in the pixel circuit of FIG. C2) shows a gate control signal of the wiring S− applied to the gate of the switching transistor Q6 that transfers the negative polarity side driving voltage in the pixel circuit. 11D1 and 11D2 show load characteristic control signals of the wiring B applied to the gates of the transistors Q7 and Q8 in the pixel circuit. The transistors Q7 and Q8 are constant current loads of the source follower buffer circuit in the pixel circuit as described above. Furthermore, FIG.
1) and (E2) indicate the drive voltage VPE applied to the pixel drive electrode PE of the liquid crystal element.

First, prior to the timing when the polarity of the common electrode voltage VCOM shown in FIG. 11A1 switches at time t3, the gate control signal of the wiring S + becomes high level as shown in FIG. 11B1 at time t1 to t2. A case where the positive polarity side switching transistor is turned on will be described. In this case, the on-period (t1 to t2) of the positive polarity side switching transistor
In addition, as shown in FIG. 11D1, when the load characteristic control signal of the wiring B applied to the gate of the constant current load transistor of the source follower buffer circuit in the pixel circuit is set to the high level, the source on the positive polarity side The follower buffer circuit and the switching transistor (Q5 in FIG. 3) become active, and a positive drive voltage corresponding to the video signal is applied to the pixel drive electrode (PE in FIG. 3) of the liquid crystal element.

The positive drive voltage is transmitted to the pixel drive electrode PE, and the pixel drive electrode voltage VPE is changed to FIG.
When the positive voltage is reached as shown in 1), the load characteristic control signal of the wiring B is set to the low level, as shown in (D1), and the positive-side source follower buffer circuit is made inactive. Subsequently, when the gate control signal of the wiring S + is set to the low level at time t2, the positive-side switching transistor is also turned off, and the pixel drive electrode node of the liquid crystal element shifts to a floating state. However, as shown in FIG. 11E1, the pixel drive electrode voltage VPE is continuously held by the parasitic capacitance of the pixel drive electrode node after time t2.

Next, at time t3, as shown in FIG. 11A1, the polarity of the common electrode voltage Vcom is switched to a polarity opposite to the pixel drive electrode holding voltage. At this time, due to the presence of capacitive coupling by the liquid crystal display (LCM in FIG. 3) formed between the common electrode and the pixel drive electrode, the pixel drive electrode voltage VPE held in the floating state is Under the influence of the change in the common electrode voltage Vcom, it varies by ΔVp as shown in FIG. 11 (E1).

Similarly, a sequence for switching the pixel drive electrode voltage Vcom from positive polarity to negative polarity (time t
4 to t6), the pixel drive electrode voltage VPE is affected by the change in the common electrode voltage Vcom at time t6 due to capacitive coupling by the liquid crystal display formed between the common electrode and the pixel drive electrode. As shown in FIG. 11 (E1), it fluctuates by ΔVm.

As described above, at the control timings shown in FIGS. 11A1 to 11E1, the voltage fluctuations ΔVp and ΔVm of the pixel drive electrodes generated when the polarity of the common electrode voltage Vcom is switched due to the influence of capacitive coupling of the liquid crystal display body. Since the pixel drive electrode voltage VPE is generated at a timing after the polarity switching of the pixel drive electrode, the pixel drive electrode voltage VPE deviates from a value corresponding to the original video signal immediately after the polarity switch, and the difference is an AC amplitude of the pixel drive electrode voltage VPE. There is a problem that the effective voltage applied to the liquid crystal is reduced by that amount because it acts in the direction of decreasing.

Therefore, in this embodiment, as shown in FIGS. 11A2 to 11E2, the above-described problem is solved by controlling the polarity switching of the common electrode to precede the polarity switching timing of the pixel drive electrode. It is characterized by solving.

In this embodiment, as shown in FIG. 11A2, first, the common electrode voltage V at time t7.
The polarity of com switches. Subsequently, at time t8 to t9 after the polarity switching from the positive polarity to the negative polarity of the common electrode voltage Vcom is completed, the gate control signal of the wiring S + becomes a high level as shown in FIG. The switching transistor is turned on. Further, during this ON period (t8 to t9), as shown in FIG. 11D2, the load characteristic control signal of the wiring B is set to the high level, and the positive-side source follower buffer circuit and the switching transistor (FIG. 3). Then, Q5) becomes active, and a positive drive voltage corresponding to the video signal is applied to the pixel drive electrode (PE in FIG. 3) of the liquid crystal element. A positive drive voltage is transmitted to the pixel drive electrode PE.

Here, the pixel drive electrode voltage VPE is a time t at which the polarity of the common electrode voltage Vcom is switched due to the presence of capacitive coupling by the liquid crystal display formed between the common electrode and the pixel drive electrode.
7, the potential fluctuation ΔVm occurs as shown in FIG. 11 (E2). However, in the on period (t8 to t9) of the positive polarity side switching transistor immediately after that, the polarity of the pixel drive electrode side is switched, and the pixel drive electrode voltage VPE in this on period is as shown in FIG. 11 (E2). The positive voltage corresponding to the original video signal not affected by the potential fluctuation is switched.

Similarly, in the negative polarity switching control operation, first, as shown in FIG. 11 (A2), the polarity of the common electrode voltage Vcom is switched from negative polarity to positive polarity at time t10. Subsequently, within the period from time t11 to t12 after completion of the polarity switching of the common electrode voltage Vcom, FIG.
, (D2), since the gate control signal of the wiring S- is set to the high level and the load characteristic control signal of the wiring B is set to the high level, the source follower buffer circuit and the switching transistor (on the negative polarity side) In FIG. 3, Q5) becomes active.

As a result, in the pixel drive electrode voltage VPE, as shown in FIG. 11E2, as shown in FIG. 11E2, a potential variation of ΔVp occurs at time t10. The polarity is switched and the voltage is switched to a negative voltage corresponding to the original video signal that is not affected by the potential fluctuation.

As is apparent from the above description of FIG. 11, the present embodiment is the same as that of FIGS. 11 (A2) to (E2).
As shown in FIG. 6, the switching timing of the common electrode voltage Vcom and the pixel driving electrode voltage VPE is controlled so that the polarity inversion switching timing of the common electrode voltage Vcom precedes the polarity inversion switching timing of the pixel driving electrode voltage VPE. By doing so, even if the pixel drive electrode potential in a floating state is fluctuated due to capacitive coupling formed between the pixel drive electrode and the common electrode formed by the liquid crystal display body between the pixel drive electrode and the common electrode, The influence of the fluctuation is limited to a short time corresponding to a slight time difference from the polarity switching time of the common electrode voltage Vcom to the polarity reversal time of the pixel driving electrode voltage VPE, and the pixel driving electrode voltage is imaged for most other periods. The original driving voltage corresponding to the signal can be maintained. Therefore, according to the present embodiment, the problem of the decrease in effective voltage applied to the liquid crystal in the timing control shown in FIGS. 11A1 to 11E is solved, and the drive voltage is efficiently applied to the liquid crystal. Can do.

FIG. 12 is a circuit diagram of a timing generation circuit that realizes the timing control according to the present embodiment described with reference to FIGS. 11 (A2) to (E2). The timing generation circuit 100 shown in FIG. 12 includes five D-type flip-flops (hereinafter referred to as D-FF) 101 to 105 connected in cascade and an inverter 106 that inverts the Q output signal of the second-stage D-FF 102.
And the inverter 107 for inverting the Q output signal of the fifth stage D-FF 105, the two 2-input AND circuits 108 and 109, and the Q output signals of the third and fourth stage D-FFs 103 and 104, respectively. Exclusive OR circuit (hereinafter referred to as EX-OR circuit) 110 for performing exclusive OR operation
It consists of.

Each of the D-FF 101 to D-FF 105 is a 1-bit latch circuit, and a basic clock CLK having a period corresponding to a time unit of timing control of the present embodiment is provided at a clock terminal.
Are input in common. The five D-FFs 101 to 105 connected in cascade constitute a shift register, and a control timing pulse that matches the polarity switching period of the common electrode voltage Vcom is input to the data input terminal D of the first-stage D-FF 101. This is each D-FF101
Are output with a delay of one clock time unit to the Q output terminals a, b, c, d, e, and f.

In this embodiment, since the polarity switching of the common electrode voltage Vcom is controlled to precede the polarity switching of the pixel drive electrode voltage VPE, the Q output signal of the first stage D-FF 101 is set as the common electrode voltage Vcom. A signal obtained by logically ANDing a signal obtained by logically inverting the Q output signal of the D-FF 102 by the inverter 106 and a Q output signal of the D-FF 105 by the AND circuit 108 is a gate control signal (hereinafter referred to as a gate control signal) transmitted through the wiring S +. , Also referred to as a positive polarity switch control signal). A signal obtained by performing an AND operation on the Q output signal of the D-FF 102 and a signal obtained by logically inverting the Q output signal of the D-FF 105 by the inverter 107 by the AND circuit 109 is a gate control signal ( Hereinafter, it is also referred to as a negative polarity switch control signal. E
The X-OR circuit 110 performs an exclusive OR operation on the Q output signal of the D-FF 103 and the Q output signal of the D-FF 104 to activate the constant current load transistor of the source follower buffer circuit of the pixel circuit. A load control signal for the wiring B is generated.

Since the control for shifting the constant current load transistor of the source follower buffer circuit of the pixel circuit from on to off needs to be completed during the period in which the pixel polarity changeover switch is kept on, the constant current load transistor Is generated from the Q output signal of the D-FF 104, and the off timing of the pixel polarity changeover switch is generated from the Q output signal of the D-FF 105 delayed therefrom.

As described above, in the timing generation circuit 100 shown in FIG. 12, the control of the common electrode, the pixel switch, and the pixel buffer load can be reliably realized with a predetermined timing relationship in the cycle of the reference clock CLK.

In the timing generation circuit 100 shown in FIG. 12 of the present embodiment, the reference clock CLK
Although the timing is generated by shifting each control timing by one clock in this cycle, it is of course possible to perform control with a time difference of a plurality of clock cycles. Further, the timing generation circuit 100 shown in FIG. 12 is configured to generate a desired timing control signal by delaying the original input signal as a common electrode control signal. However, the timing generation circuit is not shown in FIG.
The circuit configuration is not limited to the circuit configuration shown in FIG. 2 and may be any circuit that realizes the basic timing control described with reference to FIGS.

Next, an embodiment of the timing control of the video signal writing operation and the above-described pixel polarity switching synchronization operation in the liquid crystal display device of the present invention will be described with reference to FIGS.

FIG. 13 is a timing chart for explaining an example of the above timing control. FIG.
3 (A) is a vertical synchronizing signal V corresponding to the vertical scanning period of the video signal supplied to the liquid crystal display device.
D, (B) in the figure shows a horizontal synchronizing signal HD corresponding to the horizontal scanning period. In this embodiment, the polarity switching timing of the liquid crystal driving voltage, that is, the polarity switching control of the common electrode voltage and the polarity switching control timing of the pixel driving electrode voltage are set to the period (vertical scanning period) of the vertical synchronizing signal VD of the video signal and the horizontal synchronizing signal. The synchronous control is performed so as to maintain a constant phase relationship with the HD cycle (horizontal scanning cycle).

In this embodiment, the polarity inversion period is 2n times the horizontal scanning period of the video signal, that is, control is performed so that the polarity is inverted every n line scanning period period, and the polarity inversion period is constant with respect to the start timing of the vertical scanning. It is set to synchronize with the phase. In principle, the polarity inversion control of the liquid crystal drive according to this embodiment can be set at an arbitrary timing independently of the scanning cycle of the video signal.

However, in reality, the polarity inversion control of the liquid crystal drive is performed by the common electrode voltage switching period controlled by the polarity inversion control, the positive polarity switch control signal, the negative polarity switch control signal and the timing signal of the pixel drive electrode voltage polarity switching control, and There is a problem that the state of a signal such as a load characteristic control signal interferes with the voltage on the writing side through various parasitic capacitances and appears as image noise reflecting the switching timing of polarity switching. In particular, when the video signal scanning timing and the polarity switching control timing are asynchronous, noise due to these interferences is generated randomly, appearing as beats in the vertical direction of the screen, and there is a problem that the display quality is remarkably lowered. .

On the other hand, in the present embodiment, as shown in the timing chart of FIG. 13, the load characteristic control signal shown in FIG. 4D and the positive polarity switch shown in FIG. The polarity switching operation by the control signal and the negative polarity switch control signal shown in FIG. As a result, in the present embodiment, the period from the first line to the n-th line of horizontal scanning is as shown in FIG.
The AC voltage VLC applied to the liquid crystal display shown in FIG. 11 is positive (the pixel drive electrode voltage VPE shown in FIG. 13G is positive, and the common electrode voltage shown in FIG. 13C is negative) and remains constant. , N (n
In the +1) line to second n line period, the AC voltage VLC is in a negative state (the pixel drive electrode voltage VPE shown in FIG. 13G is negative, and the common electrode voltage shown in FIG. 13C is positive) and constant. Keep. In this embodiment, the polarity switching state at the timing at which the scanning is selected for all the scanning lines is determined under a certain condition.

As described above, in this embodiment, by synchronizing the scanning cycle of the video signal and the polarity switching operation timing cycle, it is possible to reduce the display quality deterioration due to the generation of image noise due to the mutual interference between the polarity switching operation and the video scanning operation.

In FIG. 13, the vertical sync signal VD, the horizontal sync signal HD, and the polarity switching reference common electrode voltage switching phase coincide at the same time so that the synchronization relationship between the video signal scanning cycle and the polarity switching operation timing cycle can be easily understood. However, the purpose of the mutual timing synchronization in the present invention is not limited to this.

For example, the common electrode voltage switching and the polarity switching phase of the pixel drive electrode voltage may be any period within the horizontal scanning period, such as during the video signal effective period of the horizontal scanning period of the video or during the horizontal blanking period of the video signal. May be set. That is, in the mutual timing synchronization according to the present invention, the video signal scanning operation and the polarity switching control operation are performed under the condition of synchronizing the scanning cycle of the video signal and the polarity switching operation timing cycle. Arbitrary conditions that can most reduce the influence of noise due to the interference may be selected.

FIG. 14 is a circuit diagram of a timing control circuit as control means for synchronously controlling the video signal writing timing described with reference to FIG. 13, that is, the vertical scanning and horizontal scanning timing and the pixel polarity switching timing. In the figure, the same components as those in FIG.

The timing control circuit 120 shown in FIG. 14 includes a 2n frequency dividing circuit 121, five D-FFs 101 to 105 connected in cascade, an inverter 106 that inverts the Q output signal of the second stage D-FF 102, and five stages. Inverter 107 for inverting the Q output signal of D-FF 105 of the eye
And two 2-input AND circuits 108 and 109, and an EX-OR circuit 110 that performs an exclusive OR operation of the Q output signals of the third-stage and fourth-stage D-FFs 103 and 104. That is, the timing control circuit 120 shown in FIG. 14 is configured to supply the signal divided by the 2n divider circuit 121 to the data input terminal of the D-FF 101 of the timing generation circuit shown in FIG.

The 2n frequency dividing circuit 121 is a counter circuit in which the clock input is the horizontal synchronizing signal HD and the reset input is the vertical synchronizing signal VD, and the polarity is inverted to the high level or the low level every time n horizontal synchronizing signals HD are counted. Generates a symmetric square wave. Since the 2n frequency dividing circuit 121 is reset every time the vertical synchronizing signal VD is input, a counter output synchronized with the vertical scanning can be obtained.

The frequency division ratio of the 2n frequency dividing circuit 121 is selected so that the switching cycle of the frequency division output becomes a desired polarity inversion cycle. As a result, the divided output signal of the 2n divider circuit 121 can be used as a basic timing signal for switching the polarity of the liquid crystal drive voltage. The symmetrical rectangular wave output from the 2n frequency dividing circuit 121 is applied to the data input terminal of the D-FF 101 as the original signal of the common electrode voltage switching control signal synchronized with the horizontal and vertical scanning timings. Since the circuit after D-FF 401 has the same configuration as the timing generation circuit shown in FIG. 12, detailed description thereof is omitted here.

Although not shown in the drawing, a delay circuit that delays the signal for a certain period is interposed between the output terminal of the 2n frequency dividing circuit 121 and the data input terminal D of the D-FF 101 to thereby generate the horizontal synchronization signal HD. It is also possible to set the phase of the reference voltage of the polarity switching timing by shifting by the delay amount by this delay circuit. In this case, by adjusting the above delay amount,
It is possible to adjust the mutual phase while maintaining the synchronization between the operation timing of the horizontal scanning and the polarity switching operation, and select the condition that reduces the noise generated by the mutual interference between the video signal scanning and the polarity switching operation. It becomes possible.

In the present embodiment, the horizontal synchronization signal HD is divided by the 2n frequency dividing circuit 121, and various timing signals are generated synchronously based on this, but the circuit configuration is limited to the circuit of FIG. It is not limited to this, as long as it synchronizes the video signal scanning and the polarity switching control, which are the basic timing control of FIG.

Next, in the synchronous operation of the video signal writing timing and the pixel polarity switching described above, an example of drive control for inverting the polarity of polarity switching at the scanning time for each scanning line for each vertical scanning period is shown in FIG. And it demonstrates with FIG.

FIG. 15 is a timing chart for explaining an example of the drive control described above. FIG.
) Denotes a vertical synchronizing signal VD corresponding to the vertical scanning period of the video signal supplied to the liquid crystal display device, and FIG. 5B shows a horizontal synchronizing signal HD corresponding to the horizontal scanning period. In this embodiment, the polarity switching timing of the liquid crystal driving voltage, that is, the polarity switching control of the common electrode voltage and the polarity switching control timing of the pixel driving electrode voltage are set to the period of the vertical synchronizing signal VD (vertical scanning period) and the horizontal synchronizing signal. Synchronize so as to maintain a constant phase relationship with the HD cycle (horizontal scanning cycle), and further switch the pixel polarity at the time of scan selection in each scan selection line in the kth frame and (k + 1) th frame of the input video signal. The polarity is controlled so as to be reversed.

15, similar to the timing control of FIG. 13, the load characteristic control signal shown in FIG. 4D, the positive switch control signal shown in FIG. The polarity switching operation by the negative polarity switch control signal shown in (F) is synchronized. Also,
In this embodiment, in the k-th frame period, the applied AC voltage VLC of the liquid crystal display shown in FIG. 15H is positive (shown in FIG. 15G) during the first to n-th line periods of horizontal scanning. The pixel drive electrode voltage VPE is positive, the common electrode voltage shown in FIG. 10C is negative, and is kept constant, and the AC voltage VLC is negative during the (n + 1) -th to second n-line periods (FIG. 15). (
G) pixel drive electrode voltage VPE shown in negative polarity, common electrode voltage shown in FIG.
Hereinafter, with respect to all the scanning lines, the polarity switching control of pixel driving is performed every n line scanning period.

Next, in the (k + 1) th frame period, the applied AC voltage VLC of the liquid crystal display shown in FIG. 15H is negative (shown in FIG. 15G) in the first to n-th line periods of horizontal scanning. The pixel drive electrode voltage VPE is negative and the common electrode voltage shown in FIG. 5C is constant, and the AC voltage VLC is maintained positive in the period from the (n + 1) th line to the second nth line (FIG. 15).
The pixel drive electrode voltage VPE shown in (G) is positive, and the common electrode voltage shown in FIG. (C) is negative). For all scan lines, pixel drive polarity switching control is performed every n line scan periods. Do.

Thus, according to the present embodiment, focusing on the scanning period of the first line to the nth line, the polarity switching of the pixel circuit is positive in the kth frame and negative in the (k + 1) th frame. The polarity of the pixel drive electrode voltage during the scanning period is inverted every frame. Similarly, (
If attention is paid to the scanning period from the (n + 1) th line to the second nth line, the polarity switching of the pixel circuit is kth.
The polarity of the pixel drive electrode voltage during the scanning period is also reversed every frame, such as negative in the frame and positive in the (k + 1) th frame.

As described above, according to this embodiment in which the operation timing control shown in the timing chart of FIG. 15 is performed, the polarity of the pixel drive electrode voltage at the time of selecting the row scan is inverted every frame for every line. Even if a display characteristic difference occurs between the case where the pixel drive electrode voltage is scanned in a positive state and the case where it is scanned in a negative state due to interference between the video signal scanning operation and the polarity switching operation, For each line, the polarity of the pixel drive electrode voltage at the row scanning selection timing is inverted and averaged for each frame. As a result, according to the present embodiment, it is possible to realize a high-definition video display that is less affected by interference noise (such as light and dark bands in the horizontal direction) due to various parasitic capacitances between the video signal scanning operation and the polarity switching operation. Features can be obtained.

FIG. 16 is a circuit diagram of a timing control circuit of an embodiment that performs the operation timing control shown in the timing chart of FIG. The timing control circuit 130 shown in FIG. 16 includes a 2n frequency dividing circuit 131 that divides the horizontal synchronization signal HD, a polarity control circuit 132 that generates various control signals based on an output signal of the 2n frequency dividing circuit 131, and a vertical control circuit 132. A D-type flip-flop (D-FF) 133 to which a synchronization signal VD is input to a clock terminal, selector circuits 134, 135, and 136, and an inverter 137 are included.

The 2n frequency dividing circuit 131 is a counter circuit in which the clock input is the horizontal synchronizing signal HD and the reset input is the vertical synchronizing signal VD, and the polarity is inverted to the high level or the low level every time n horizontal synchronizing signals HD are counted. A symmetric rectangular wave is generated, and the rectangular wave is supplied to the polarity control circuit 132 as a reference voltage. Since the 2n frequency dividing circuit 131 is reset every time the vertical synchronizing signal VD is input, a counter output synchronized with the vertical scanning can be obtained.

The polarity control circuit 132 has a circuit configuration similar to that of the timing generation circuit 100 shown in FIG. 12, and is necessary for the polarity switching control of the pixel drive electrode voltage based on the reference voltage supplied from the 2n divider circuit 131. Various control signals (S ′ (+), S ′ (−), B, Vcom ′) are generated. Here, the control signal S ′ (+) is a positive polarity switch control signal, the control signal S ′ (−) is a negative polarity switch control signal, and the control signal B is an active signal for the constant current load transistor of the source follower buffer circuit of the pixel circuit. This is a load characteristic control signal. The control signal Vcom ′ is
This signal corresponds to the common electrode voltage Vcom of the liquid crystal element.

The D-FF 133 is a divide-by-2 circuit, which generates a symmetric rectangular wave whose polarity is inverted to a high level or a low level every time the vertical synchronizing signal VD is input, and uses the symmetric rectangular wave as a select signal FR.
M is supplied to each select terminal of the selector circuits 134 to 136 for control. Therefore, the select signal FRM is a signal whose logic level is inverted every vertical synchronization signal period, that is, every frame period.

The selector circuit 134 and the selector circuit 135 receive the positive polarity switch control signal S ′ (+) and the negative polarity switch control signal S ′ (−) as inputs, and when the select signal FRM is at a high level, one selector circuit Selects the positive polarity switch control signal S ′ (+), and the other select circuit selects the negative polarity switch control signal S ′ (−). In the selector circuit 134 and the select circuit 135, when the select signal FRM is at a high level, one selector circuit selects the negative polarity switch control signal S ′ (−), and the other selector circuit controls the positive polarity switch. The signal S ′ (+) is selected. As a result, the selector circuit 134 outputs a positive polarity switch control signal whose polarity is inverted every frame. The selector circuit 135 outputs a negative polarity switch control signal that undergoes a semi-polarity change for each frame.

The selector circuit 136 also sends the control signal Vcom ′ and the control signal Vcom ′ to the inverter 13.
The control signal whose polarity has been inverted in step 7 is alternately selected for each frame based on the select signal FRM and is output as the common electrode voltage Vcom.

Therefore, the timing control circuit 130 of this embodiment shown in FIG.
) Is output. By using the control signal output from the timing control circuit 130, as described with reference to FIG. 15, video signal writing, that is, vertical scanning and horizontal scanning timing and pixel polarity switching timing are synchronized and row scanning is performed. The polarity of the pixel drive electrode voltage at the selection timing is inverted and averaged for each frame. As a result, according to the present embodiment, a liquid crystal display device capable of displaying a high-quality image with less influence of interference noise due to various parasitic capacitances between the image signal scanning operation and the polarity switching operation can be realized. Note that the configuration of the timing control circuit is not limited to the configuration shown in FIG. 16, and may be other configurations as long as the timing control shown in the timing chart of FIG. 15 is realized.

According to the liquid crystal display devices of the embodiments and examples described above, the AC driving frequency of the liquid crystal is
Regardless of the vertical scanning frequency, it can be freely set in the inversion control cycle in the pixel circuit. For example, assuming that the vertical scanning frequency is 60 Hz used for a general TV video signal and the number of vertical periodic scanning lines is 1125 lines, and the polarity switching of the pixel circuit is performed with a period of about 15 line periods, The AC driving frequency of the liquid crystal of the liquid crystal display device of the present invention described above is 2.25 kHz (= 60 (Hz) × 1125 ÷ (15 × 2)).

On the other hand, the AC drive frequency of the liquid crystal of the conventional active matrix liquid crystal display device that converts the vertical scanning frequency 60 Hz of the video signal to 120 Hz, which is doubled in the frame memory, and reverses the polarity of the video signal every vertical scanning cycle is converted. It is 60 Hz, which is 1/2 of the later frequency. Under such driving conditions where the AC driving frequency of the liquid crystal is on the order of several tens of Hz to 100 Hz, the influence of residual charges is likely to occur on the liquid crystal, and there is a problem in reliability and stability. There is a tendency that the influence of display quality deterioration due to spot-like display defects due to mixing or the like appears remarkably.

In contrast, as described above, the AC driving frequency of the liquid crystal of the active matrix type liquid crystal display device of the present invention is dramatically higher than the 60 Hz that is the AC driving frequency of the liquid crystal of the conventional active matrix type liquid crystal display device. Therefore, according to the liquid crystal display device of the present invention, it is possible to significantly improve the reliability, stability, display quality degradation such as spots, and the like as compared with the conventional liquid crystal display device.

Next, a more specific overall configuration of the liquid crystal display device according to the present invention and an embodiment of a video signal sampling circuit (horizontal direction driving circuit) will be described.

FIG. 17 is an overall configuration diagram of an embodiment of a liquid crystal display device according to the present invention, and FIG. 18 is a circuit diagram of a horizontal driver circuit in FIG. As shown in FIG. 17, the liquid crystal display device 200 includes shift register circuits 201a and 201b, a one-line latch circuit 202, and a comparator 20
3, a gray scale counter 204, an analog switch 205, a pixel circuit 206 arranged in a matrix form with m pieces in the horizontal direction and n pieces in the vertical direction, a timing generator 207,
A polarity switching control circuit 208 and a vertical shift register and level shifter 209 are included.

The shift register circuits 201a and 201b, the one-line latch circuit 202, the comparator 203, and the gradation counter 204 constitute a horizontal driver circuit. This horizontal driver circuit corresponds to the horizontal driving circuit 10 shown in FIG. 2 and constitutes a data line driving circuit together with the analog switch 205. The data line driving circuit is also shown in FIG. In addition,
The comparator 203 is shown as a single block in FIG. 17 for simplicity of illustration.
Actually, it is provided for each pixel column as shown in FIG.

The analog switch 205 shown in FIGS. 17 and 18 has a configuration in which a pair of sampling analog switches for positive polarity and negative polarity are arranged for each pixel column. The sampling analog switch for positive polarity corresponds to the switches 1-1a, 1-2a and the like shown in FIG. 2, and the analog switch for sampling for negative polarity is the switches 1-1b, 1--1 shown in FIG.
This corresponds to 2b and the like. The pixel circuit 206 shown in FIG. 17 includes two data lines (D1 + and D1-,.
.., Dm + and Dm−) and gate lines (G1,..., Gn). Each of the n · m pixel circuits 206 has the circuit configuration shown in FIG. 3 (FIG. 1) or FIG.

The polarity switching control circuit 208 shown in FIG. 17 is based on the timing signal from the timing generator 207, the positive switch control signal for the wiring S +, the negative switch control signal for the wiring S-, and the load characteristic for the wiring B. Control signals are output respectively. Polarity switching control circuit 20
Reference numeral 8 denotes a circuit configuration shown in FIG. 12, FIG. 14 or FIG. A vertical shift register and level shifter 209 shown in FIG. 17 corresponds to the vertical driving circuit 20 shown in FIG.
1 to Gn are sequentially output in one horizontal scanning period, and 1 to the gate lines G1 to Gn.
Select sequentially in the horizontal scanning cycle.

Next, the operation of FIGS. 17 and 18 will be described with reference to the timing chart of FIG. In FIG. 17 and FIG. 18, a digital video signal in which a plurality of bits of pixel data (DATA) shown in FIG. 19B, which are synchronized with the horizontal synchronization signal HD shown in FIG. The data is sequentially developed as data for one line by the shift register circuits 201a and 201b, and is latched by the one-line latch circuit 202 when the development for one line is completed.

Of the pixel data (DATA) shown in FIG. 19 (B), horizontal even-numbered column pixel data DATA (even) shown every other white background is supplied to the shift register circuit 201a, and the remaining hatched portions. Every other odd-numbered pixel data DATA (odd) in the horizontal direction is the shift register circuit 2
01b. This is because it is easy to cope with high-speed operation on a high-resolution panel.

The one-line latch circuit 202 includes odd-numbered column pixel data DATA (odd) output from the shift register circuit 201a and even-numbered column pixel data DAT output from the shift register circuit 201b.
After the pixel data DATA of one line period of the same line consisting of A (even) is held as schematically shown in FIG. 19D, it is supplied to the first data input section of the comparator 203 of each pixel column. .

The gradation counter 204 counts the clock Count-CK shown in FIG.
F), the reference gradation data C-out in which a plurality of gradation values sequentially change from the minimum value to the maximum value within the horizontal scanning period is output for each horizontal scanning period, and the comparator 203 of each pixel column Second
To the data input section. The comparator 203 compares the value of the input pixel data DATA of the first data input unit with the value of the input reference gradation data C-out (gradation value) of the second data input unit, and the two values match. A coincidence pulse is generated and output at the same timing.

Of the two sampling analog switches for positive polarity and negative polarity that constitute the analog switch 205, the sampling analog switch for positive polarity applies the reference ramp voltage Ref_Ramp (+) to the common wiring on the input side. Is done. On the other hand, in the sampling analog switch for negative polarity, the reference ramp voltage Ref_Ramp (−) is applied to the input side common wiring. The reference ramp voltage Ref_ generated by the reference voltage generation circuit existing in the controller 60 shown in FIG.
Of Ramp (+) and Ref_Ramp (-), Ref_Ramp (+) is a periodic change in which the level increases from the black level to the white level in the horizontal scanning period as shown in FIG. 19 (I). Sweep signal. On the other hand, the reference ramp voltage Ref_Ramp (−) is a periodic sweep signal that changes in a direction in which the level decreases from the black level to the white level of the image in the horizontal scanning period as shown in FIG. . Therefore, the reference lamp voltages Ref_Ramp (+) and Ref_Ramp (−) have an inversion relationship with respect to a predetermined reference potential.

The analog switch 205 receives the SW-Start signal shown in FIG. 19G and turns on at the same time at the start of the horizontal scanning period, and then turns off when the coincidence pulse is received from the comparator 203. Open / close controlled. In the timing chart of FIG. 19, as an example, the opening / closing timing of the analog switch 205 of the pixel column corresponding to the pixel data DATA of the gradation level k is shown as a waveform SPk shown in FIG. As a result, the reference ramp voltage Ref_Ramp (+) at the time when the pair of sampling analog switches for positive polarity and negative polarity constituting the analog switch 205 of the pixel column are simultaneously turned off in response to the coincidence pulse. And Ref
Corresponding levels of _Ramp (−) (points P and Q in FIGS. 19 (I) and (J)) are simultaneously sampled and output to the pixel data lines D (+) and D (−) of the pixel column. The

As described above, according to the horizontal driver circuit of this embodiment, the configuration and operation of which are described, it is possible to supply positive and negative pixel data to each pixel with a simple configuration. Further, according to the horizontal driver circuit of the present embodiment, it is possible to interface the video input to the liquid crystal display device with a digital signal as shown in FIG. Since an analog circuit block for processing is not necessary, the circuit cost can be reduced.

Next, another embodiment of the horizontal driver circuit in the liquid crystal display device according to the present invention will be described. FIG. 20 is a circuit diagram showing another embodiment of the horizontal driver circuit in the liquid crystal display device according to the present invention. In the figure, the same components as those in FIG. 18 are denoted by the same reference numerals, and the description thereof is omitted.
The horizontal driver circuit shown in FIG. 20 is different from the horizontal driver circuit shown in FIG. 18 in that the supply lines of the reference lamp voltages Ref_Ramp (+) and Ref_Ramp (−) are each divided into a plurality (two in this case). Different.

In FIG. 20, the feed line of the positive reference lamp voltage Ref_Ramp1 (+) is connected to the input terminal of the analog switch 205a corresponding to the even-numbered column pixels in the horizontal direction, and the supply of the other positive reference lamp voltage Ref_Ramp2 (+). The wires are analog switches 205 corresponding to the odd-numbered pixels in the horizontal direction.
connected to the input terminal b. Similarly, the feed line for the negative reference lamp voltage Ref_Ramp1 (-) is connected to the input terminal of the analog switch 205a corresponding to the even-numbered column pixels in the horizontal direction, and the feed line for the other negative reference lamp voltage Ref_Ramp2 (-). Is connected to the input terminal of the analog switch 205b corresponding to the odd-numbered pixels in the horizontal direction.

According to the horizontal driver circuit shown in FIG. 18, when a uniform halftone screen (gray) is to be displayed, a period until the analog switch 205 of the pixel column corresponding to the corresponding gradation level is turned off, The period during which all analog switches 205 are on continues. During this continuous ON period, the pixel data line on the output side of the analog switch 205 acts as a load with respect to the reference lamp voltage power supply line. Therefore, according to the driver circuit, a uniform halftone screen (
In the case of displaying (gray), there is a possibility that the reference lamp voltage waveform is delayed by the load and the luminance is lower than the original gray.

On the other hand, when displaying a pattern in which the gray and black are mixed in the horizontal direction, the analog switch 205 of the pixel column corresponding to black is turned off in advance, and the load on the reference lamp voltage power supply line is cut off and reduced. Therefore, the brightness of the gray portion increases. As a result, according to the driver circuit, the gray displayed on both sides of black is brighter than the gray displayed uniformly in the entire horizontal direction, and so-called “laterally-drawn” image noise may occur. is there.

On the other hand, in the horizontal driver circuit of this embodiment shown in FIG. 20, the reference lamp voltage power supply line is divided into two groups, so that the analog switches 205a and 205b of each pixel column are divided.
The load connected to the reference lamp voltage power supply line is reduced during the ON period, and the delay of the reference lamp voltage waveform is reduced. As a result, according to the horizontal driver circuit of the present embodiment, it is possible to realize high-quality display characteristics in which the “horizontal pulling” noise is reduced.

In this embodiment, an example in which the reference lamp voltage power supply line for each polarity is divided into two parts is shown. However, it is possible to obtain better display characteristics by further increasing the number of divisions.

Next, an embodiment relating to the supply of the reference voltage to the horizontal driver circuit in the liquid crystal display device according to the present invention will be described.

FIG. 21 shows a block diagram of an embodiment relating to the supply of the reference voltage to the horizontal driver circuit in the liquid crystal display device according to the present invention. In the figure, the same components as those in FIGS. 17 and 18 are denoted by the same reference numerals, and the description thereof is omitted. In the present embodiment, a plurality of reference lamp voltage power supply lines to the analog switch 205 constituting the horizontal driver circuit shown in FIG. 18 have a plurality of positions different in position in the longitudinal direction of the reference lamp voltage power supply line (pixel array arrangement direction). Feed point (X1 and X2, Y1 and Y
It is characterized in that 2) is provided.

In the horizontal driver circuit shown in FIG. 18, during the on period of the analog switch 205 of each pixel column, as described above, a large load is connected to the reference lamp voltage power supply line, and the resistance in the wiring direction of the power supply line is reduced. There is a problem that the transfer characteristic of the reference lamp voltage is not uniform depending on the component, and the followability with respect to the reference lamp voltage waveform becomes worse as the pixel row is farther from the feeding point. That is, the power supply characteristic of the reference lamp voltage changes along the wiring length direction of the reference lamp voltage power supply line. On the other hand, since the horizontal length of the reference lamp voltage power supply line is equal to the horizontal size of the display unit, the wiring length of the reference lamp voltage power supply line becomes long. Therefore, the “lateral pulling” noise cannot be easily avoided in the pixel portion far from the feeding point of the reference lamp voltage feeding line. For example, in the case of an aluminum wiring having a sheet resistance of 100 mΩ, a wiring having a wiring width of 10 microns and a wiring length of 20 mm, the total resistance in the wiring length direction is 200Ω, and the transfer characteristic of the reference lamp voltage is not negligible.

Therefore, in the embodiment shown in FIG. 21, the positive reference ramp voltage Ref_Ramp of the input terminal portion 221 is used.
(+) Feeding points X1 and X2 are provided at both ends of a positive reference lamp voltage feed line connected to the input terminal, and a negative polarity connected to the negative reference lamp voltage Ref_Ramp (−) input terminal of the input terminal unit 221. The power supply points Y1 and Y2 are provided at both ends of the reference lamp voltage power supply line. With this configuration, according to the present embodiment, since the influence of the resistance component in the wiring length direction of the reference lamp voltage power supply line is mitigated, the above-mentioned “laterally-drawn” noise is greatly reduced, and a higher image quality display is achieved. Is possible.

In the embodiment shown in FIG. 21, the feeding points are two at both ends of the feeding line, but more feeding points may be provided as necessary. In addition, the present embodiment may be used in combination with a configuration in which the power supply line as shown in FIG. 20 is divided into a plurality of groups. Further, in this embodiment, one input terminal portion 221 connected to an external circuit is provided for each reference lamp voltage power supply line. However, a plurality of input terminal portions are allocated and power is supplied using a plurality of input terminal portions. Also good.

1 is a circuit diagram of a pixel circuit according to a first embodiment of a liquid crystal display device of the present invention. 1 is a basic configuration diagram of an embodiment of a liquid crystal driving element used in a liquid crystal display device of the present invention. FIG. 2 is a detailed circuit diagram illustrating the pixel circuit of the first embodiment illustrated in FIG. 1 in more detail. It is a detailed circuit diagram of a second embodiment of the pixel circuit in the liquid crystal display device of the present invention. FIG. 6 is a circuit diagram of a third embodiment of a pixel circuit in a liquid crystal display device of the present invention. It is a block diagram of the principal part of one Embodiment of the liquid crystal display device of this invention using the circuit of FIG. 5 as a pixel circuit. It is a timing chart for demonstrating the outline | summary of the alternating current drive control of the liquid crystal display device of this invention. It is a figure which shows the relationship from the black level of a positive polarity video signal written in the pixel of a liquid crystal display device, and a negative polarity video signal to a white level. It is a block diagram of one Embodiment of the principal part of the liquid crystal display device of this invention. FIG. 10 is a timing chart of signals at various parts in FIG. 9. FIG. It is a timing chart explaining an example of optimization of mutual timing control of the polarity switching of the pixel drive electrode and common electrode of the liquid crystal display device of the present invention. FIG. 12 is a circuit diagram of a timing generation circuit that realizes timing control according to the embodiment of the present invention described in FIG. 11. 4 is a timing chart for explaining an embodiment of timing control of a video signal writing operation and a pixel polarity switching synchronization operation in the liquid crystal display device of the present invention. FIG. 14 is a circuit diagram of a timing control circuit for synchronously controlling the video signal writing timing and the pixel polarity switching timing described in FIG. 13. It is a timing chart explaining the Example of the drive control which reverses the polarity of polarity switching at the time of a scanning about each scanning line for every vertical scanning period. FIG. 16 is a circuit diagram of a timing control circuit of an embodiment that performs the operation timing control described in FIG. 15. 1 is an overall configuration diagram of an embodiment of a liquid crystal display device of the present invention. FIG. 18 is a circuit diagram of the horizontal driver circuit in FIG. 17. FIG. 19 is a timing chart for explaining operations in FIGS. 17 and 18; FIG. It is a circuit diagram of the other Example of the horizontal driver circuit in the liquid crystal display device of this invention. It is a block diagram of one Example regarding the reference voltage electric power feeding to the horizontal driver circuit in the liquid crystal display device of this invention. It is a basic block diagram of an example of the liquid crystal drive element used for the conventional liquid crystal display device. It is a block diagram of an example of the liquid crystal element which comprises the pixel of a liquid crystal display device.

1-1a, 1-1b, 1-2a, 1-2b Video switch 4, PE Reflective electrode (pixel drive electrode)
5a. 5b Horizontal signal lines 6-1a, 6-1b, 6-2a, 6-2b, D1 (+) to Dm (+), D1 (-) to Dm (-), Di +,
Di- Data line 7 Common electrode line 8-1, 8-2, Gj, G1 to Gn Gate line 10 Horizontal direction drive circuit 20 Vertical direction drive circuit 30 Pixel unit 41, 42, 51, 52 Pixel 60 Controller circuit 71a Positive side Video signal (positive video signal)
71b Negative video signal (negative video signal)
81, 206 Pixel circuit 90-1 to 90-h Divided pixel unit 91a, 91b, 91c Shift register 100 Timing generation circuit 101-105, 133 D-type flip-flop (D-FF)
106, 107, 137 Inverter 108, 109 AND circuit 110 Exclusive OR circuit 120, 130 Timing control circuit 121, 131 2n frequency divider circuit 132 Polarity control circuit 134-136 Selector circuit 200 Liquid crystal display device 201a, 201b Shift register circuit 202 1-line latch circuit 203 comparator 204 gradation counter 205 analog switch 207 timing generator 208 polarity switching control circuit 209 vertical shift register / level shifter 221 input terminal section S1, S2 selector switch C1, C2, C3, Cs1, Cs2 signal holding capacity A1 , A2 Buffer amplifier Q1, Q2 Pixel selection transistor Q3, Q4 Buffer amplifier transistor Q5, Q6 Switching transistor Q7, Q8 For constant current source load Transistor Q9 constant current source transistor Q10 inspection switching transistor CE common electrode (counter electrode)
LCM liquid crystal display (liquid crystal layer)

Claims (3)

A shift register circuit that sequentially stores a digital video signal in which a plurality of bits of pixel data are synthesized in time series for each line;
A latch circuit for holding one line of digital video signals sequentially stored in the shift register circuit for one horizontal scanning period;
A gradation counter that outputs reference gradation data in which a plurality of gradation values sequentially change within a horizontal scanning period;
The pixel data value for one line output from the latch circuit is compared with the gradation value of the reference gradation data output from the gradation counter, and a coincidence pulse is generated when the two coincide with each other. A comparator,
A first reference voltage, which is a periodic sweep signal that changes in a direction in which the level increases from the black level to the white level of the video in a horizontal scanning period cycle or in a direction in which the level decreases from the white level to the black level; A reference voltage generating circuit that generates a second reference voltage that is a periodic sweep signal in an inverted relationship with respect to a predetermined potential with respect to one reference voltage;
A plurality of pixels arranged at intersections of a plurality of gate lines and a plurality of sets of data lines each including two data lines, and connected to the gate lines and the two data lines, respectively; , Provided corresponding to each set of data lines of the pixels arranged in the same column direction, the first reference voltage is sampled by the coincidence pulse and a level corresponding to the generation timing of the coincidence pulse is obtained. The first analog switch that generates one drive signal and outputs it to one of the two data lines, and the second reference voltage simultaneously with the sampling of the first analog switch The second drive signal sampled by the coincidence pulse and having a level corresponding to the coincidence pulse generation timing is output to the other data line of the two data lines. A plurality of sets of analog switches analog switch, the one set,
Driving circuit of a liquid crystal display device characterized in that it comprises a. The reference voltage generation circuit includes the first wiring that transmits the first reference voltage and the second wiring that transmits the second reference voltage in a plurality of sets of wiring groups. And dividing the second reference voltage and outputting it,
The plurality of pixels are divided into a plurality of groups of pixel columns, and the input terminals of the first and second analog switches of the set of analog switches of each group of pixel columns are the plurality of sets of wiring groups. 2. The driving circuit for a liquid crystal display device according to claim 1, wherein the driving circuit is connected to the first and second wirings of each set of wiring groups corresponding to each other. The first and second wirings for transmitting the first and second reference voltages from the reference voltage generating circuit to the first and second input terminals of the plurality of sets of analog switches, respectively, The drive circuit for a liquid crystal display device according to claim 1, wherein a plurality of feeding points having different positions in the direction are provided.

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