JP5493547B2 - Liquid crystal display device and driving method of liquid crystal display device - Google Patents

Description

  The present invention relates to a liquid crystal display device and a driving method of the liquid crystal display device, and more particularly to an active matrix type liquid crystal display device and a driving method of the liquid crystal display device.

  In recent years, a liquid crystal display device of LCOS (Liquid Crystal on Silicon) type is often used as a central part for projecting images in projector devices and projection televisions. This LCOS liquid crystal display device has a structure in which a transparent electrode, a liquid crystal layer, a reflective electrode arranged in a matrix, a liquid crystal driving element in which a liquid crystal driving circuit is formed on a silicon substrate, and the like overlap.

  In a conventional liquid crystal display device, pixels are arranged in a matrix at each intersection of a plurality of data lines (column signal lines) and a plurality of gate lines (row scanning lines). As shown in FIG. 24, each pixel includes a pixel selection transistor Q, a signal holding capacitor Cs, and a reflective electrode PE. The pixel selection transistor Q has a gate connected to a gate line (row scanning line) G and a drain connected to a data line (column signal line) D. Further, as shown in FIG. 24, the liquid crystal element LC has a configuration in which a liquid crystal display (liquid crystal layer) LCM is sandwiched between a reflective electrode (pixel drive electrode) PE and a counter electrode (common electrode) CE facing each other. Has been.

  In the liquid crystal element LC, the fixed voltage Vcom is applied to the common electrode CE, and various voltages according to the video signal are supplied to the reflective electrode (pixel drive electrode) PE, thereby controlling the light modulation rate of the liquid crystal display LCM. Display as video. Normally, the liquid crystal element LC can be stabilized for a long time by AC driving, so that the reflection electrode (pixel driving electrode) PE receives light according to the video signal with respect to the fixed voltage Vcom of the common electrode CE. AC driving is performed by alternately applying positive and negative voltages that have the same modulation rate.

  In some cases, there is an application example in which the voltage of the common electrode is switched according to the timing of driving with the positive and negative voltages for the purpose of reducing the dynamic range of the video signal, but the basic idea is the same It is.

  In the liquid crystal element LC as in the example of FIG. 24, video signal writing to each pixel is normally performed once per frame, and alternately on the positive side with respect to the common electrode every frame. The negative video signal is written in the signal holding capacitor Cs, and the liquid crystal is AC driven. In this case, there is an example of double speed driving in which the liquid crystal is AC driven at a frequency twice as high as the writing frequency, but the frequency is about 60 Hz to 120 Hz, and is not a high frequency in any case.

  This is because video signal writing to the signal holding capacitor Cs is performed by charging / discharging in the relationship between the on-resistance of the video switch and the parasitic capacitance of the data line, or the on-resistance of the pixel selection transistor Q and the signal holding capacitor Cs. For this reason, it is not easy to increase the writing frequency any more from the viewpoint of device cost.

  On the other hand, if the liquid crystal element is driven with alternating current at a higher frequency so that the direct current component between the reflective electrode (pixel drive electrode) PE and the common electrode CE can be reduced to zero, it is possible to improve reliability such as prevention of burn-in. Connection and image display quality are also improved.

  Up to now, written signal components such as countermeasures against feedthrough caused by the parasitic capacitance of the pixel selection transistor (see, for example, Patent Document 1) and leakage countermeasures for holding capacitors (for example, see, Patent Document 2). A method for preventing the deterioration of the resin is disclosed. However, it seems that efforts to drive the liquid crystal element with an alternating current at a higher frequency have not been studied much.

  For each of a plurality of pixels connected to the same scanning line, the storage capacitor of each pixel is alternately connected to the storage capacitor line corresponding to the scanning line and another storage capacitor line corresponding to the adjacent scanning line. The compensation voltage for compensating the direct current component between the pixel drive electrode and the counter electrode is inverted for each storage capacitor line, so that the image quality deterioration caused by the potential fluctuation of the common electrode line or the common electrode is reduced. A liquid crystal display device that prevents generation thereof has been conventionally known (see, for example, Patent Document 3).

JP 2006-10897 A JP 2002-250938 A JP 2004-354742 A

  As described above, it is desirable to drive the liquid crystal element with an alternating current at a high frequency as a means for improving reliability such as prevention of burn-in of the liquid crystal element, but it is positive with respect to the counter electrode voltage due to restrictions such as writing time to the pixel. It is difficult to alternately write the negative video signal and the negative video signal at high speed, and conventionally, the frequency of AC drive is only performed at a frame rate or about twice that frequency.

  Further, in the liquid crystal display device described in Patent Document 3, the polarity of the compensation voltage can be reversed only for each frame, and the image signal voltage has two types of positive and negative sides with respect to the voltage Vcom of the common electrode. Voltage is needed.

  The present invention has been made in view of the above points. The liquid crystal element is AC driven at a higher speed than before, and the entire pixel portion is divided into a plurality of groups of divided pixels each having a plurality of rows as one group. It is an object of the present invention to provide a liquid crystal display device and a liquid crystal display device driving method capable of visually reducing interference noise between adjacent wirings that may occur when the device is driven and displaying a high-quality image.

In order to achieve the above object, a liquid crystal display device according to a first aspect of the present invention is an intersection in which a plurality of sets of data lines and a plurality of gate lines intersect each other. A plurality of pixels and a plurality of sets of data lines, each of which supplies a positive video signal to one of a set of two data lines, and the other A plurality of switches for sequentially supplying a negative video signal to a plurality of sets of data lines in units of sets and driving the plurality of switches in units of sets within a horizontal scanning period. Horizontal and vertical driving means for performing horizontal driving and vertical driving for selecting a plurality of gate lines for each horizontal scanning period;
Each of the plurality of pixels
A liquid crystal element in which a liquid crystal layer is sandwiched between an opposing pixel drive electrode and a common electrode, a first sampling and holding means for sampling a positive video signal and holding it for a certain period, and sampling a negative video signal A second sampling and holding means for holding for a certain period, a positive video signal voltage held by the first sampling and holding means, and a negative video signal voltage held by the second sampling and holding means. Switching means for alternately applying to the pixel drive electrode by switching at a predetermined cycle shorter than the vertical scanning period,
When the entire pixel portion composed of a plurality of pixels constituting the display screen is divided into a plurality of groups in which each pixel in a plurality of consecutive rows is one group, a plurality of switching in the plurality of divided groups is performed. A switching control means for controlling the means in a time-sharing manner in units of each divided group by a polarity switching pulse having a predetermined period shorter than the vertical scanning period ;
The switching control means transfers the polarity switching pulse within the horizontal blanking period of the positive video signal and the negative video signal, and actively controls the switching means .

To achieve the above object, a liquid crystal display device of the second invention, instead of the switching control means in the first invention, the switching control means, the positive polarity video signals and the negative polarity video signal an intermediate or more The switching means is actively controlled by transferring a polarity switching pulse in gradation.

To achieve the above object, a liquid crystal display device of the third invention, instead of the switching control means in the first invention, the switching control means, one horizontal scanning of positive polarity video signals and the negative polarity video signal The switching means is actively controlled by transferring the polarity switching pulse at a rate of once per period.

In order to achieve the above object, a liquid crystal display device according to a fourth aspect of the present invention is provided in a liquid crystal layer in synchronization with a switching cycle between a positive video signal voltage and a negative video signal voltage applied to a pixel drive electrode. Common electrode voltage control means for changing the common electrode voltage applied to the common electrode between two different levels so that the absolute value of the potential difference is always substantially the same, and a positive video signal applied to the pixel drive electrode by the switching means Timing changing means for changing the switching timing of the voltage and the negative video signal voltage and the polarity inversion timing of the common electrode voltage by the common electrode voltage control means in units of frames of the positive video signal and the negative video signal; Is further provided.

In order to achieve the above object, in the liquid crystal display device of the fifth invention, the common electrode voltage control means is set to a switching timing between the positive video signal voltage and the negative video signal voltage applied to the pixel drive electrode. In advance, the common electrode voltage applied to the common electrode is changed between two different levels.

In order to achieve the above object, a driving method for a liquid crystal display device according to a sixth aspect of the present invention includes a plurality of data lines and a plurality of gate lines each including two data lines. A driving voltage corresponding to a positive video signal transmitted from one of the two data lines in each group at each of the plurality of pixels provided at the intersection where the two intersect each other is applied to the pixel driving electrode from the vertical scanning period. Two sets of data lines each at a timing of a time difference between a first sampling step that samples at a short predetermined cycle and holds for a first fixed period, and a half of the predetermined cycle from the sampling time point of the first step The second sampling step for sampling the drive voltage corresponding to the negative polarity video signal transmitted on the other side of the pixel drive electrode at a predetermined period and holding it for a first fixed period, and the first and second sampling steps. The pixel drive that alternately applies the positive video signal voltage and the negative video signal voltage, which are switched at a predetermined cycle shorter than the vertical scanning period, to the pixel drive electrodes of the liquid crystal elements provided in each of the plurality of pixels. An electrode voltage application step , wherein the pixel drive electrode voltage application step includes a positive video signal voltage and a negative video signal voltage in a predetermined cycle shorter than the vertical scanning period, and a positive video signal and a negative video signal. Switching is performed by polarity switching pulses transferred within a horizontal blanking period of the signal, and the signals are alternately applied to the pixel drive electrodes of the liquid crystal elements provided in each of the plurality of pixels .

Further, in the driving method of the liquid crystal display device according to the seventh aspect of the invention, the pixel driving electrode voltage application step includes a positive video signal voltage and a negative video signal voltage at a predetermined cycle shorter than the vertical scanning period, and It is switched by polarity switching pulses transferred in the middle or higher gradation between the positive video signal and the negative video signal, and alternately applied to the pixel drive electrodes of the liquid crystal elements provided in each of the plurality of pixels. To do.

Further, in the driving method of the liquid crystal display device according to the eighth aspect of the invention, the pixel driving electrode voltage applying step includes a positive video signal voltage and a negative video signal voltage at a predetermined cycle shorter than the vertical scanning period, and The positive polarity video signal and the negative polarity video signal are switched by the polarity switching pulse transferred at a rate of once in one horizontal scanning period, and alternately applied to the pixel drive electrodes of the liquid crystal elements provided in each of the plurality of pixels. It is characterized by doing.

In order to achieve the above object, a driving method of a liquid crystal display device according to a ninth aspect of the present invention is that the entire pixel portion composed of the plurality of pixels constituting the display screen is divided into one group of pixels in a plurality of consecutive rows. When the pixel drive electrode voltage application step divides the positive video signal voltage and the negative video signal voltage into a polarity switching pulse having a predetermined cycle shorter than a vertical scanning period. Thus, switching is performed in a time-sharing manner for each division group, and alternately applied to the pixel drive electrodes of the liquid crystal element provided in each of the plurality of pixels.
Furthermore, in order to achieve the above object, a driving method of a liquid crystal display device according to a tenth aspect of the invention is synchronized with a switching cycle between a positive video signal voltage and a negative video signal voltage applied to a pixel drive electrode. A common electrode voltage control step for changing the common electrode voltage applied to the common electrode facing the pixel drive electrode of the liquid crystal element between two different levels so that the absolute value of the potential difference applied to the liquid crystal layer of the liquid crystal element is always substantially the same; The switching timing of the positive video signal voltage and the negative video signal voltage by the pixel drive electrode voltage application step and the polarity inversion timing of the common electrode voltage by the common electrode voltage control step are expressed as the positive video signal voltage and the negative video signal. A timing change step for changing the signal voltage in frame units, and the common electrode voltage control step changes the level of the common electrode voltage. After allowed to, and performing successively a sampling by the sampling and a second sampling step of the first sampling step.

  According to the present invention, it occurs when the liquid crystal element is AC driven at a higher speed than before and the entire pixel portion is divided into a plurality of divided pixel portions each having a plurality of rows as one group and is driven in a time division manner. It is possible to visually reduce horizontal linear noise and display a high-quality image.

1 is a circuit diagram of a pixel circuit according to a first embodiment of a liquid crystal display device of the present invention. 1 is a basic configuration diagram of a first embodiment of a liquid crystal display device of the present invention. FIG. 2 is a detailed circuit diagram showing one pixel of the first embodiment shown in FIG. 1 in more detail. It is a detailed circuit diagram of 2nd Embodiment of 1 pixel in the liquid crystal display device of this invention. 3 is a timing chart for explaining an outline of AC drive control of the liquid crystal display device of the present invention. It is a figure which shows the relationship from the black level of a positive polarity video signal written in the pixel of a liquid crystal display device, and a negative polarity video signal to a white level. It is a block diagram of other embodiment of the principal part of the liquid crystal display device of this invention. FIG. 8 is a timing chart of signals at various parts in FIG. 7. FIG. It is explanatory drawing of the subject which may arise in embodiment shown in FIG. It is waveform explanatory drawing of the cause which the subject shown in FIG. 9 generate | occur | produces. FIG. 3 is a circuit diagram of a timing control circuit used in the first and second embodiments of the liquid crystal display device driving method of the present invention. 12 is a timing chart for explaining a first embodiment of a driving method of a liquid crystal display device of the present invention using the timing control circuit shown in FIG. 12 is a timing chart for explaining a second embodiment of the driving method of the liquid crystal display device of the present invention using the timing control circuit shown in FIG. FIG. 6 is a circuit diagram of a timing control circuit used in a third embodiment of a driving method of a liquid crystal display device of the present invention. 15 is a timing chart for explaining a third embodiment of the driving method of the liquid crystal display device of the present invention using the timing control circuit shown in FIG. 7 is a timing chart for explaining fourth to sixth embodiments of the liquid crystal display driving method according to the present invention. It is a circuit diagram of the timing control circuit used in the fourth to sixth embodiments of the driving method of the liquid crystal display device of the present invention. FIG. 18 is a diagram for explaining a fourth embodiment of the driving method of the liquid crystal display device of the present invention using the timing control circuit shown in FIG. 17. FIG. 18 is a diagram for explaining a fifth embodiment of the driving method of the liquid crystal display device of the present invention using the timing control circuit shown in FIG. 17. FIG. 18 is a diagram for explaining a sixth embodiment of the driving method of the liquid crystal display device of the present invention using the timing control circuit shown in FIG. 17. 1 is an overall configuration diagram of an embodiment of a liquid crystal display device of the present invention. FIG. 22 is a circuit diagram of the horizontal driver circuit in FIG. 21. FIG. 23 is a timing chart for explaining the operation of FIGS. 21 and 22. FIG. It is a block diagram of an example of the liquid crystal element which comprises the pixel of a liquid crystal display device.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  FIG. 1 is a circuit diagram of a first embodiment of a pixel circuit in a liquid crystal display device according to the present invention, and FIG. 2 is a basic configuration diagram of the first embodiment of a liquid crystal display device according to the present invention. In both drawings, the same components are denoted by the same reference numerals.

  Each pixel in the liquid crystal display device of this embodiment is represented by a pixel circuit shown in FIG. In this specification, the pixel circuit refers to a pixel represented by an equivalent circuit, and both are substantially the same. As shown in FIG. 1, one pixel circuit of the present embodiment includes pixel selection transistors Q1 and Q2 each having a gate connected to a gate line 8-1, and each of the pixel selection transistors Q1 and Q2. Retention capacitors (capacitors) C1 and C2, one end of which is connected to the source and the other end of which is commonly connected to the common electrode line 7, a connection point between the pixel selection transistor Q1 and the retention capacitor C1, and the pixel selection transistor Buffer amplifiers A1 and A2 each having an input terminal connected to a connection point between Q2 and the holding capacitor C2, switching switches S1 and S2 having one terminal connected to each output terminal of the buffer amplifiers A1 and A2, and a switching switch S1 and A storage capacitor C3 for driving liquid crystal connected between the common connection point at each other end of S2 and the common electrode line 7, and a reflective electrode (hereinafter also referred to as a pixel drive electrode) 4 It has been made. The drains of the pixel selection transistors Q1 and Q2 are separately connected to the data lines 6-1a and 6-1b.

  Further, the liquid crystal element of each pixel is a liquid crystal element having a known structure shown in FIG. 24, and corresponds to a pixel drive electrode PE corresponding to the reflective electrode 4 and a counter electrode facing the pixel drive electrode PE. A liquid crystal display (liquid crystal layer) LCM is sandwiched between the common electrode CE.

  The basic configuration of the first embodiment of the liquid crystal display device according to the present invention shown in FIG. 2 is the same as the conventional one. However, in this embodiment, as shown in FIG. 2, two horizontal signal lines, data lines, and switches are provided. That is, in this embodiment, the horizontal direction drive circuit 10, the vertical direction drive circuit 20, the video signal 71a on the positive side with respect to the common electrode voltage, and the video signal 71b on the negative side are divided into two systems of video switches 1-1a. , 1-1b, 1-2a and 1-2b,..., Two horizontal signal lines 5a and 5b, pixel unit 30, and two data lines 6-1a and 6- 1b, 6-2a and 6-2b,..., And gate lines 8-1, 8-2,.

  In FIG. 1 and FIG. 2, the suffix number after the hyphen of each symbol indicates that the same type of component is in a different position. Also, the lowercase letter a following the suffix number indicates the first system of the two systems, and b indicates the second system. FIG. 2 shows a part of the entire component.

  The pixel unit 30 is arranged in a matrix at the intersection of the two data lines (6-1a and 6-1b,...) And the gate lines (8-1, 8-2,...). The pixel 41, 42, 51, 52 and the like having the circuit configuration of FIG. The horizontal driving circuit 10 includes pixels of the first column of pixels 41, 51,... Via two systems of switches 1-1a, 1-1b and two systems of data lines 6-1a, 6-1b. The transistors are connected to the drains of the selection transistors Q1 and Q2, respectively.

  Similarly, the horizontal driving circuit 10 includes pixels 42, 52,... In the second column via two systems of switches 1-2a, 1-2b and two systems of data lines 6-2a, 6-2b. .. are connected to the drains of the pixel selection transistors Q1 and Q2, respectively, and the drains of the two pixel selection transistors of the pixels in the third column and thereafter are similarly connected via two switches and two data lines. Each is connected.

  The vertical driving circuit 20 is connected to the gates of the two pixel selection transistors Q1 and Q2 of the pixels 41, 42,... In the first row in the pixel unit 30 through the gate line 8-1. Commonly connected. Similarly, the vertical driving circuit 20 is commonly connected to the gates of two pixel selection transistors of each pixel in the same row in the pixel unit 30 through each gate line.

  Further, the controller 60 supplies various clock signals generated so as to be synchronized with the input video signals 71a and 71b to the horizontal direction drive circuit 10 and the vertical direction drive circuit 20 (path is not shown), and the input video signal. By driving the data lines (6-1a, 6-1b,...) And the gate lines (8-1, 8-2,...) In synchronization with 71a, 71b, Pixel selection with horizontal and vertical scanning is performed. Thereby, in this Embodiment, it becomes possible to perform alternating current drive of a liquid crystal at high speed.

  Next, the operation of the pixel circuit of the first embodiment shown in FIG. 1 will be described. The data line 6-1a supplies a video signal 71a on the positive side with respect to the common electrode voltage of the liquid crystal. At the same time, the data line 6-1b supplies the video signal 71b on the negative side with respect to the common electrode voltage. The pixel selection transistors Q1 and Q2 are simultaneously turned on by a voltage applied to the gate via the gate line 8-1. As a result, the positive video signal 71a supplied from the data line 6-1a is written to the storage capacitor C1 via the drain and source of the pixel selection transistor Q1. On the other hand, at the same time, the negative video signal 71b supplied from the data line 6-1b is written into the holding capacitor C2 via the drain and source of the pixel selection transistor Q2.

  Subsequently, the pixel selection transistors Q1 and Q2 are simultaneously turned off by a voltage applied to the gate via the gate line 8-1. As a result, the positive and negative video signals 71a and 71b are held in the holding capacitors C1 and C2, respectively, until the next video signals 71a and 71b for which the pixel selection transistors Q1 and Q2 are next turned on are written.

  The positive and negative video signals 71a and 71b respectively held in the holding capacitors C1 and C2 are read out through the buffer amplifiers A1 and A2 which are impedance conversion circuits having high input resistances, respectively, and the changeover switch S1. , S2 are alternately selected, and the liquid crystal is AC driven by changing the voltage of the reflective electrode 4 (pixel drive electrode PE).

  According to this pixel configuration, once the video signals 71a and 71b on the positive and negative sides are written to the holding capacitors C1 and C2 once per frame, the video signal of the next frame is written. The liquid crystal can be AC driven by alternately switching the selector switches S1 and S2 any number of times during one frame period.

  That is, according to the pixel circuit of the present embodiment shown in FIG. 1, the liquid crystal can be AC driven at a high frequency, for example, several tens of times the frame frequency, independently of the video signal writing cycle. As a result, the present embodiment provides effects such as prevention of burn-in, improvement of reliability, and improvement of display quality where no spots or irregularities are visible. In the present embodiment, the voltage of the common electrode of the liquid crystal can be shaken (changed) in accordance with the polarity inversion, and the signal voltage can be reduced to half or less of the conventional voltage.

  Further, since the liquid crystal display device of this embodiment can be manufactured using a standard CMOS process, two selection pixel transistors Q1 and Q2, two buffer amplifiers A1 and A2, and two changeover switches S1 per pixel. S2 and two holding capacitors C1 and C2, and even if the number of elements is relatively large, the increase in the number of elements does not necessarily increase the cost.

  Here, each pixel has buffer amplifiers A1 and A2. If a direct current continues to flow even though the current is small, the liquid crystal drive element generally has more than 1 million pixels. There are also possible adverse effects such as.

  As a preventive measure, it is effective to perform pulse driving that enables the buffer amplifiers A1 and A2 and the changeover switches S1 and S2 only during a period necessary for signal reading. The holding capacitor C3 is for performing this operation. During the enable period, the signal that has passed through the change-over switch S1 or S2 is written to the holding capacitor C3, and when both are turned off, the written signal is written. The liquid crystal is driven while being held in the holding capacitor C3. As a result, the liquid crystal can be AC driven at a higher frequency than before while suppressing a significant increase in power consumption, and many effects as described above can be obtained.

  FIG. 3 is a detailed circuit diagram showing one pixel in the first embodiment of the liquid crystal display device according to the present invention shown in FIG. 1 in more detail. As shown in FIG. 3, one pixel of the liquid crystal display device of this embodiment includes pixel selection transistors Q1 and Q2 for writing positive and negative pixel signals, and image signal voltages of respective polarities in parallel. A liquid crystal display (liquid crystal layer) LCM between two independent storage capacitors Cs1 and Cs2 (corresponding to C1 and C2 in FIG. 1), transistors Q3 to Q8, and the pixel drive electrode PE and the common electrode CE. Is composed of a liquid crystal element having the same structure as shown in FIG.

  The impedance conversion source follower circuit including the transistors Q3 and Q7 constitutes the buffer amplifier A1 shown in FIG. The impedance conversion source follower circuit including the transistors Q4 and Q8 constitutes the buffer amplifier A2 of FIG. A transistor Q5 having a drain connected to the source of the transistor Q3 and a transistor Q6 having a drain connected to the source of the transistor Q4 are switching transistors corresponding to the changeover switches S1 and S2 in FIG. is there. The sources of the transistors Q5 and Q6 are connected to the pixel drive electrode PE of the liquid crystal element.

  Note that the storage capacitor C3 in FIG. 1 is not shown in FIG. The storage capacitor C3 can be substituted by the parasitic capacitances of the transistors Q5 and Q6 and the parasitic capacitance of the liquid crystal. If the leak current at the node of the pixel drive electrode PE is sufficiently small, the storage capacitor C3 is not created. It is because it is good.

  The pixel portion data line is composed of a set of two data lines, that is, a positive data line D + and a negative data line D- for each pixel circuit, and is sampled by a data line driving circuit (not shown). The video signals having different polarities are supplied. The drain terminals of the pixel selection transistors Q1 and Q2 are respectively positive data line Di + (corresponding to 6-1a in FIG. 1) and negative data line Di- (corresponding to 6-1b in FIG. 1). The gate terminals are commonly connected to the row scanning line Gj (corresponding to the gate line 8-1 in FIG. 1) for the same row.

  The pixel selection transistors Q1 and Q2 are simultaneously turned on when a scanning pulse is supplied to the gates from a vertical scanning circuit (not shown) via a common row scanning line Gj. The pixel selection transistor Q1 that has been turned on applies and accumulates a positive signal voltage input via the positive data line Di + to the storage capacitor Cs1. In addition, the pixel selection transistor Q2 that has been turned on applies and accumulates the negative polarity signal voltage input via the negative polarity data line Di- to the storage capacitor Cs2.

  The circuit part composed of the transistors Q3 and Q7 and the circuit part composed of the transistors Q4 and Q8 are so-called source follower buffers. The transistors Q3 and Q4 function as signal input transistors and the transistors Q7 and Q8 function as constant current source loads. To do. The constant current source load transistors Q7 and Q8 are configured such that the gates are commonly wired to the row direction wiring B for the same row pixel, and the bias control of the constant current load is possible. The input resistance of the source follower buffer by the MOS transistors Q3, Q7, Q4, Q8 is almost infinite. Therefore, similarly to the conventional active matrix liquid crystal display device, the accumulated charges in the holding capacitors Cs1 and Cs2 are not leaked until a signal voltage is newly written in the holding capacitors Cs1 and Cs2 after one vertical scanning period. Retained.

  The switching transistors Q5 and Q6 switch and send the output signal of the source follower buffer to the liquid crystal element composed of the reflective electrode (pixel drive electrode) PE, the liquid crystal display LCM, and the common electrode CE. The gate terminals of the transistor Q5 for switching the positive signal and the transistor Q6 for switching the negative signal are independent, and each is connected to the wirings S + and S- in the row direction for the same row pixel. Has been.

  The gate control signal supplied alternately to the wirings S + and S- turns on the switching transistors Q5 and Q6 alternately. When the switching transistor Q5 is in the on state, the positive signal voltage held in the holding capacitor Cs1 is supplied to the liquid crystal element through the source follower buffer including the transistors Q3 and Q7 and the drain source of the transistor Q5. Applied to the pixel drive electrode PE. When the switching transistor Q6 is in the ON state, the negative signal voltage held in the holding capacitor Cs2 is liquid crystal through the source follower buffer including the transistors Q4 and Q8 and the drain source of the transistor Q6. Applied to the pixel drive electrode PE of the element.

  Here, the two gate control signals supplied to the wirings S + and S− are pulse trains having a predetermined cycle shorter than one vertical scanning cycle and having logical values opposite to each other. Therefore, the liquid crystal element in the pixel of the present embodiment is given a liquid crystal drive signal that is alternately inverted between positive polarity and negative polarity in synchronization with the two gate control signals to the pixel drive electrode PE. . In the conventional active matrix type liquid crystal display device, the polarity inversion can be realized only in the vertical scanning period. On the other hand, in the present embodiment, since the pixel circuit itself has a polarity inversion function as described above, there is no restriction on the vertical scanning frequency in synchronization with the two gate control signals for the liquid crystal element. AC drive at a high frequency is possible.

  Note that the pixel circuit is not limited to the configuration shown in FIG. 3, and may have the configuration shown in FIG. In the pixel circuit shown in FIG. 4, a constant current load transistor Q9 forming a source follower buffer is arranged at the subsequent stage of the polarity switching switching transistors Q5 and Q6, that is, at the node of the pixel drive electrode PE. It is in the point which becomes a structure which functions in common as a load of both negative polarity source follower circuits.

  Next, an outline of AC drive control of the liquid crystal display device according to the present invention will be described. FIG. 5 shows a timing chart for explaining the outline of the AC drive control of the liquid crystal display device according to the present invention. 5A shows the vertical synchronization signal VD, and FIG. 5B shows the load characteristic control signal of the wiring B applied to the gates of the transistors Q7 and Q8 in the pixel circuits of FIGS. Show. FIG. 5C shows the gate control signal of the wiring S + applied to the gate of the switching transistor Q5 for transferring the positive side drive voltage in the pixel circuit, and FIG. Each signal waveform of the gate control signal of the wiring S− applied to the gate of the switching transistor Q6 that transfers the negative polarity side drive voltage in the pixel circuit is shown. The transistors Q7 and Q8 are constant current loads of the source follower buffer circuit in the pixel circuit as described above.

  FIG. 6 shows the relationship from the black level to the white level of the positive video signal I and the negative video signal II written to the pixel. The positive video signal I has a black level when the level is minimum and a white level when the level is maximum, whereas the negative video signal II has a white level when the level is minimum and a black level when the level is maximum. The inversion center of the positive video signal I and the negative video signal II is indicated by III.

  In FIG. 6, the positive video signal I indicates a black level when the level is minimum and a white level when the level is maximum, and the negative video signal II indicates a white level when the level is minimum and a black level when the level is maximum. However, in the pixel circuit of the liquid crystal display device of the present invention, the positive video signal I is a white level when the level is minimum, a black level when the level is maximum, and the negative video signal II is black when the level is minimum. The level may be a white level at the maximum.

  In the pixel circuits shown in FIGS. 3 and 4, the positive polarity side switching transistor Q5 is turned on while the gate control signal of the wiring S + shown in FIG. 5C is at a high level. When the load characteristic control signal supplied to the wiring B during the period when the transistor Q5 is on is set to the high level as shown in FIG. 5B, the source follower buffer circuit becomes active. As a result, the pixel drive electrode PE node is charged through the source follower buffer circuit in which the positive video signal level held in the holding capacitor Cs1 is activated. When the potential of the pixel drive electrode PE is fully charged, the load characteristic control signal of the wiring B is set to low level, and at that time, the gate control signal of the wiring S + is also set to low level. When switched, the pixel drive electrode PE becomes floating, and the positive drive voltage is held in the liquid crystal capacitor.

  On the other hand, the negative polarity side switching transistor Q6 is turned on while the gate control signal of the wiring S- shown in FIG. When the load characteristic control signal supplied to the wiring B during the period when the transistor Q6 is ON is set to the high level as shown in FIG. 5B, the source follower buffer circuit becomes active. Thereby, the pixel drive electrode PE node is charged through the source follower buffer circuit in which the negative video signal level held in the holding capacitor Cs2 is activated. When the potential of the pixel drive electrode PE is fully charged, the load characteristic control signal of the wiring B is set to the low level, and at that time, the gate control signal of the wiring S- is also set to the low level. When switched, the pixel drive electrode PE becomes floating, and the negative drive voltage is held in the liquid crystal capacitor.

  In the following, in synchronization with the switching in which the switching transistors Q5 and Q6 are alternately turned on, the constant current load transistors Q7 and Q8 in FIG. 3 or the constant current load transistor Q9 in FIG. By repeating, the drive voltage VPE converted into the positive and negative video signals is applied to the pixel drive electrode PE of the liquid crystal element as shown in FIG.

  In the present embodiment, the held charges of the holding capacitors Cs1 and Cs2 are not directly transferred to the pixel drive electrode PE, but a voltage is supplied to the pixel drive electrode PE via the activated source follower buffer circuit. Due to the configuration, there is no problem of charge neutralization even when repeated charging and discharging with positive and negative polarity are performed, and driving without voltage level attenuation can be realized even when the polarity is switched many times.

  Further, Vcom shown in FIG. 5F represents a voltage applied to the common electrode CE formed on the counter substrate of the liquid crystal display device. The substantial AC drive voltage of the liquid crystal display LCM is a difference voltage between the applied voltage Vcom of the common electrode CE and the applied voltage VPE of the pixel drive electrode PE. In the present embodiment, as shown in FIG. 5F, the applied voltage Vcom of the common electrode CE is set to the wirings S + and S− with respect to a reference level substantially equal to the inversion reference level Vc of the pixel drive electrode voltage VPE. Inverted in synchronization with the pixel polarity switching by the gate control signal. As a result, the absolute value of the potential difference between the applied voltage Vcom of the common electrode CE and the applied voltage VPE of the pixel drive electrode PE is always the same, and the liquid crystal display LCM does not have a DC component as shown in FIG. A voltage VLC is applied. The applied voltage Vcom of the common electrode CE is output from the controller 60 shown in FIG.

  As described above, in the present embodiment, the amplitude of the drive voltage on the pixel (PE) side can be reduced to about ½ or less by switching the applied voltage Vcom of the common electrode CE in a phase opposite to that of the pixel drive electrode PE. As a result, the required withstand voltage of the transistors constituting the pixel circuit and the peripheral scanning circuit is greatly reduced, the application of a special high withstand voltage structure and process becomes unnecessary, and the device cost can be reduced. Further, in this embodiment mode, a driver unit such as a pixel circuit can be configured with a low withstand voltage and small transistor as described above, so that a higher pixel density liquid crystal display device can be realized, and the per unit channel width can be reduced by reducing the transistor withstand voltage. Therefore, it is possible to employ a transistor having a high driving capability, and thus it is possible to easily cope with a high-speed driving operation.

  In the present embodiment, as shown in FIG. 5A, the load characteristic control signal of the wiring B is used as a pulse train, and the constant current load transistors (Q7 and Q8 in FIG. 3) of the source follower buffer circuit are always set. Control is performed so that the polarity switching switching transistors (Q5 and Q6 in FIG. 3) do not become active but become active only within a limited period of the conduction period. This is because a reduction in current consumption in the liquid crystal display device is taken into consideration. For example, even if the current of the steady source follower buffer circuit per pixel circuit is a minute current of 1 μA, a large amount of current is consumed under the condition that all pixels of the liquid crystal display device constantly consume current. There is a problem of becoming. For example, in a full high-definition (2 million pixels) liquid crystal display device, the current consumption reaches 2 A.

  Therefore, in this embodiment, as shown in FIGS. 5A to 5C, the polarity switching switching transistor in which the gate control signal supplied through the wirings S + and S- is at a high level. Only during the conduction period of (Q5, Q6), the load characteristic control signal supplied via the wiring B is set to the high level to drive the constant current load transistors (Q7, Q8 in FIG. 3) of the source follower buffer circuit. Restricted.

  Thereby, in this embodiment, immediately after the electrode voltage VPE of the liquid crystal element is charged / discharged to the target level as shown in FIG. 5E, the load characteristic control signal is immediately set to the low level and the constant current load is set. The transistors (Q7, Q8) can be turned off to stop the current in the source follower buffer circuit. Therefore, according to the present embodiment, it is possible to suppress a substantial current consumption even though the configuration includes a buffer amplifier in all pixels.

  Next, other control means of the source follower buffer circuit will be described with reference to FIGS.

  FIG. 7 shows a configuration diagram of a main part of another embodiment of the liquid crystal display device according to the present invention. In this embodiment, polarity inversion control and active control of the source follower buffer circuit are realized with a time difference in the vertical direction of the screen. In the embodiment described with the timing chart of FIG. 5, an example in which intermittent active control is performed so that current does not constantly flow through the source follower buffer circuit has been described. On the other hand, the liquid crystal display device of the present embodiment shown in FIG. 7 is further characterized in that a control means is provided so that all the pixels are not turned on at the same time.

  As shown in FIG. 7, in the present embodiment, divided pixel units 90-1, 90-2,..., In which the pixel unit 30 in FIG. 2 is divided into h in the vertical direction (h is a natural number of 2 or more). 90-h, the polarity switching gate control signal for the wiring S +, the polarity switching gate control signal for the wiring S-, and the load characteristic control signal for the wiring B are shifted in synchronization with the same shift clock SCK. The configuration includes h-stage shift registers 91a, 91b, and 91c. The shift registers 91a, 91b, and 91c correspond to the vertical driving circuit 20 shown in FIG. FIG. 7 shows only circuit portions necessary for active control of the source follower buffer circuit, and illustration of the horizontal driving circuit 10 and the like is omitted.

  Each of the divided pixel portions 90-1, 90-2,..., And 90-h includes groups # 1, # 2,. This is a divided pixel portion. The shift register 91a is connected to the input terminals S + (1), S + (2),..., And S + (h) of the divided pixel portions 90-1, 90-2,. The gate control signal for polarity switching (hereinafter also referred to as a positive polarity switch control signal) is supplied from the output terminals of the first stage, the second stage,. Further, the shift register 91b includes input terminals S- (1), S- (2),..., And S- (h) of the divided pixel units 90-1, 90-2,. In addition, a gate control signal for switching the polarity of the wiring S- (hereinafter also referred to as a negative polarity switch control signal) is supplied from the output terminals of the first stage, the second stage,. Further, the shift register 91c is connected to the input terminals B (1), B (2),..., And B (h) of the divided pixel portions 90-1, 90-2,. The B load characteristic control signal is supplied from the output terminals of the first stage, the second stage,.

  FIG. 8 shows a timing chart of signals at the respective parts in FIG. FIG. 8A shows the shift clock SCK supplied to the shift registers 91a, 91b and 91c. In synchronization with the shift clock SCK, the shift register 91a shifts the polarity switching gate control signal of the wiring S + shown in FIG. 8B to output the first, second and h-stage output terminals. 8C output the gate control signals shown in FIGS. 8C, 8D, and 8E, and input each of the input terminals S + (1), S + () of the divided pixel portions 90-1, 90-2, 90-h. 2) Supply to S + (h).

  Similarly, the shift register 91b shifts the polarity switching gate control signal of the wiring S- shown in FIG. 8F, and shifts the output signal from the output terminals of the first stage, the second stage, and the h stage from FIG. ), (H), and (I) to output gate control signals, and input terminals S- (1), S- (2), 90-h of the divided pixel units 90-1, 90-2, and 90-h. Supply to S- (h). Note that the pixel circuit switching cycle by the polarity switching gate control signal for the wiring S + supplied to the shift register 91a and the polarity switching gate control signal for the wiring S- supplied to the shift register 91b is: Each of the divided pixel portions 90-1 to 90-h corresponds to each pixel row (number of lines).

  Further, the shift register 91c shifts the load characteristic control signal of the wiring B shown in FIG. 8 (J) and shifts the output terminals of the first stage, the second stage, and the h stage from FIG. 8 (K), (L), The load characteristic control signal shown in (M) is output and supplied to the input terminals B (1), B (2), and B (h) of the divided pixel units 90-1, 90-2, and 90-h.

  According to this embodiment, it is possible to perform polarity reversal and buffer active control with a time difference for the division group in the vertical direction of the screen. Malfunctions and failures due to current can be avoided. In order to prevent the influence of the control time difference from affecting the display characteristics, the frequency of the shift clock SCK may be selected to be sufficiently higher than the polarity inversion frequency.

  According to the liquid crystal display device of each embodiment described above, the AC driving frequency of the liquid crystal can be freely set in the inversion control cycle in the pixel circuit, regardless of the vertical scanning frequency. For example, assuming that the vertical scanning frequency is 60 Hz used for general television video signals and the number of scanning lines is 1125 lines, and the polarity switching of the pixel circuit is performed at a cycle of about 15 line periods, The AC driving frequency of the liquid crystal element of the liquid crystal display device of the present invention described is 2.25 kHz (= 60 (Hz) × 1125 ÷ (15 × 2)).

  On the other hand, the AC drive frequency of the liquid crystal element of the conventional active matrix liquid crystal display device that converts the vertical scanning frequency 60 Hz of the video signal to 120 Hz, which is doubled by the frame memory, and reverses the polarity of the video signal every vertical scanning period is , 60 Hz which is ½ times the converted frequency. Under such driving conditions where the AC driving frequency of the liquid crystal element is on the order of several tens of Hz to 100 Hz, the liquid crystal element is likely to be affected by residual charges, and there is a problem in reliability and stability, and the characteristics of the liquid crystal material include ionic components. There is a tendency that the influence of display quality deterioration due to spot-like display defects due to contamination of foreign matter or the like appears remarkably.

  On the other hand, the AC drive frequency of the liquid crystal element of the active matrix type liquid crystal display device of the present invention is dramatically higher than the 60 Hz which is the AC drive frequency of the liquid crystal element of the conventional active matrix type liquid crystal display device. Therefore, according to the liquid crystal display device of the present invention, it is possible to significantly improve the reliability, stability, display quality degradation such as spots, and the like as compared with the conventional liquid crystal display device.

  However, in the liquid crystal display device according to the present invention, the AC drive frequency of the liquid crystal element can be drastically increased as described above. However, as shown in FIG. 1, FIG. 3, or FIG. In addition, since it is necessary to provide two storage capacitors C1 and C2 (or Cs1 and Cs2), the number of transistors in the pixel circuit is increased by 7 times or 8 times compared to the pixel circuit shown in FIG. As a result, the wiring density is high. For this reason, in the liquid crystal display device according to the present invention, it is sometimes necessary to take measures against interference noise (hereinafter referred to as crosstalk noise) between adjacent wires.

  It is known that when this crosstalk noise exists in a pixel, a correct voltage is not applied to the liquid crystal element, thereby adversely affecting the display image. Crosstalk noise is a signal change in one of adjacent wirings that affects the other signal via the inter-wiring capacitance. If the parallel wiring length is long and the inter-wiring capacitance is large, or one of the signals changes suddenly. Is more likely to occur. Therefore, in order to reduce the crosstalk noise, it is necessary to reduce the inter-wiring capacitance between adjacent wirings or to loosen the signal change on the side that gives noise.

  To reduce the capacitance between adjacent wires, it is necessary to change one of the adjacent wiring routes, such as increasing the distance between adjacent wires, moving the wires to another wiring layer, or implementing shielded wiring. There is. For this reason, if the wiring around the location where the crosstalk noise occurs is congested, a sufficient wiring area for changing the wiring path cannot be secured, and it becomes difficult to improve the crosstalk noise. To do. Actually, the wiring in which crosstalk noise occurs often has a long parallel wiring length. However, in many cases, it is unlikely that all wiring areas for wiring change are secured to improve crosstalk noise. Further, as the pixels become finer and higher in definition, it becomes more difficult to take measures against crosstalk by changing the wiring.

  Further, in the method of loosening the signal change on the side giving noise, the signal change is loosened by reducing the driving element capability on the side giving crosstalk noise. In this method, there is almost no need to change the route of the adjacent wiring, so that it can be improved even when the surrounding wiring is congested. However, in this method, the number of process steps increases due to a mixture of various types of drive element voltages as the drive element voltage is changed. Further, the liquid crystal display device according to the present invention has a fatal problem that the supply voltage to the pixel is insufficient, and is difficult to realize.

  Further, in the third embodiment of the liquid crystal display device of the present invention shown in FIG. 7, each of the pixel units 30 in FIG. 2 is divided into groups # 1, # 2,. ... And #h divided pixel portions 90-1, 90-2,..., 90-h and then sequentially controlled according to the timing chart shown in FIG. As shown in FIG. 9, in the adjacent image display positions 94-1 to 94- (h-1) of the image display sections 93-1 to 93-h corresponding to the divided pixel sections 90-1 to 90-h. In some cases, a defect (a change in gradation) on the display image may occur. The adjacent image display positions 94-1 to 94- (h-1) are the polarity switching rows of the gate control signals for the wirings S + and S- and the load characteristic control signal for the wiring B.

  Defects in the display image (grayscale fluctuations) that occur in this polarity switching row are caused by the above-mentioned gate control signal and load characteristic control signal crossing over the data signals of the data lines Di + and Di-. This is probably because FIG. 10A shows the waveform of a data signal (lamp reference voltage described later) transmitted through the data line Di-, and the portion indicated by 95 in the waveform is shown in FIG. It is slightly deformed by the crosstalk of the gate control signal transmitted through the wiring S-. Although the above-described modified waveform portion 95 is improved to some extent by narrowing the pulse width of the gate control signal, it is impossible to completely eliminate gradation fluctuations due to crosstalk. This is a common problem regardless of whether the pixel circuit is shown in FIG. 3 (FIG. 1) or FIG.

  Therefore, in each embodiment of the driving method of the liquid crystal display device according to the present invention described below, each of the plurality of pixels has a plurality of transistors as shown in FIG. 3 (FIG. 1) or FIG. 7 is divided by a plurality of divided pixel portions as shown in FIG. 7, even when crosstalk noise between wirings occurs or the data signal fluctuates due to crosstalk, the drive timing of the transistor is changed. By optimizing, adverse visual effects of the displayed image are reduced or eliminated.

FIG. 11 is a circuit diagram of a timing control circuit used in the first and second embodiments of the driving method of the liquid crystal display device according to the present invention. The timing control circuit 140 shown in FIG. 11 includes a 2n frequency dividing circuit 141 that divides the horizontal synchronization signal HD, and x + 2 D-type flip-flops (hereinafter referred to as D-FFs) 142 _{1 to} 142 _{x that are} cascade-connected. ₊₂ , a selector circuit 143 that selects the Q output signal of the second to (x-1) th stage D-FFs, an inverter 144 that inverts the output signal of the selector circuit 143, and (x + 2) stages inverter for inverting the eye D-FF of the Q output signal - a motor 145, two 2-input aND circuits 146 and 147, each of the x-th (x + 1) -th stage D-FF 142 _x and 142 _{x + 1} And an exclusive OR (hereinafter referred to as EX-OR) circuit 148 that performs an exclusive OR operation on the Q output signal. The delay circuit 149 includes D-FFs 142 _{2 to} 142 _{x + 2} and the selector circuit 143 of the _second and subsequent stages among the _{x + 2} D-FFs 142 _{1 to} 142 _{x + 2} that are cascade-connected.

  The 2n divider circuit 141 is a counter circuit in which the clock input is the horizontal synchronizing signal HD and the reset input is the vertical synchronizing signal VD, and the polarity is inverted to high level or low level every time n horizontal synchronizing signals HD are counted. To generate a symmetric square wave. Since the 2n frequency dividing circuit 141 is reset every time the vertical synchronizing signal VD is input, a counter output synchronized with the vertical scanning can be obtained.

The frequency division ratio of the 2n frequency dividing circuit 141 is selected so that the switching cycle of the frequency division output becomes a desired polarity inversion cycle. As a result, the divided output signal of the 2n divider circuit 141 can be used as a basic timing signal for switching the polarity of the liquid crystal drive voltage. Symmetrical square wave output from the 2n-divider circuit 141, horizontal, as the original signal of the common electrode voltage switching control signal synchronized with the vertical scan timing, the first-stage D-FF 142 ₁ de - applied to the data input terminal.

Further, the delay circuit 149 in FIG. 11 plays a role of delaying the signal for a certain period by the number of stages of the D-FF, and the phase of the signal generation timing of the horizontal synchronization signal HD and the wirings S + and S− is changed. It is also possible to set by shifting by the delay amount due to. In this case, the delay amount of the delay circuit 149 can be adjusted by selecting one Q output signal among the Q output signals of the D-FFs 142 _{2 to} 142 _x−1 by the selector circuit 143. By adjusting the delay amount, it becomes possible to adjust the mutual phase while maintaining the synchronization between the horizontal scanning operation timing and the polarity switching operation, and the noise generated by the mutual interference between the video signal scanning and the polarity switching operation is reduced most. It is possible to select the conditions to be played.

Each of the D-FFs 142 _{1 to} 142 _{x + 2} is a 1-bit latch circuit, and a basic clock CLK having a period corresponding to the time unit of timing control according to the present embodiment is commonly input to the clock terminals. The D-FFs 142 _{1 to} 142 _{x + 2} constitute a shift register. Its first stage D-FF 142 ₁ de shift register - the data input terminal D, output from the 2n-divider circuit 141, control timing pulse that matches the polarity switching period of the common electrode voltage Vcom is supplied, which each The signals are output to the Q output terminals of the D-FFs 142 _{1 to} 142 _x−1 with a delay of one clock time unit. Further, the output signal of the selector circuit 143 is output with a delay of one clock time unit from the Q output terminals of the three D-FFs 14x to 142x _{+ 2} .

In the present embodiment, since the polarity switching of the common electrode voltage Vcom is controlled to precede the polarity switching of the pixel drive electrode voltage VPE, the Q output signal of the _first stage D-FF 1421 is set as the common electrode voltage Vcom. The AND circuit 146 performs a logical product operation on the signal obtained by logically inverting the output signal of the selector circuit 143 by the inverter 144 and the Q output signal of the D-FF 142 _{x + 2} and is transmitted through the wiring S +. -Output a control signal (hereinafter also referred to as a positive polarity switch control signal). The AND circuit 147 performs a logical AND operation on the output signal of the selector circuit 143 and the signal obtained by logically inverting the Q output signal of the D-FF 142 _{x + 2} by the inverter 145 and is transmitted through the wiring S−. -Output a control signal (hereinafter also referred to as a negative polarity switch control signal).

Further, EX-OR circuit 148, and exclusive OR operation and the Q output signal of the D-FF 142 _x and D-FF142 _{x + 1} of the Q output signal of the pixel circuits Seo - source-follower buffer circuit of the constant current A load characteristic control signal of the wiring B that activates the load transistor is output.

Note that the control to shift the constant current load transistor (Q7 and Q8 in FIG. 3 or Q9 in FIG. 4) of the pixel circuit source switch circuit from on to off is the pixel polarity changeover switch (FIG. 3, FIG. 4). The timing control circuit 140 determines the off timing of the constant current load transistor as the Q output of the (D _{+ 1)} -stage D-FF 142 _{x + 1} . The pixel polarity change-off switch is generated from the Q output signal of the D ₊ FF 142 _{x + 2} at the (x + 2) stage delayed therefrom.

  Next, each embodiment of the driving method of the liquid crystal display device of the present invention performed using the timing control circuit 140 shown in FIG. 11 will be described together with a timing chart.

  FIG. 12 shows a timing chart for explaining the first embodiment of the driving method of the liquid crystal display device according to the present invention using the timing control circuit 140 shown in FIG. The driving method of this embodiment supplies the shift clock SCK shown in FIG. 12A to the shift registers 91a, 91b and 91c of the embodiment of the liquid crystal display device according to the present invention shown in FIG. 11 is adjusted within the horizontal blanking (H.BLK) period of the horizontal synchronization signal HD shown in FIG. 12 (J) by adjusting the delay amount of the delay circuit 149 of the timing control circuit 140 shown in FIG. The positive polarity switch control signal shown in FIG. 12B is output from 146, and the load characteristic control signal shown in FIG. 12F is output from the EX-OR circuit 148 of FIG.

  The positive polarity switch control signal shown in FIG. 12B and the negative polarity switch control signal output from the AND circuit 147 in FIG. 11 are the divided pixel units 90-1 to 90-h shown in FIG. Are alternately output every horizontal scanning period corresponding to the number of lines (number of lines). Also, the load characteristic control signal shown in FIG. 12F is output at a period of the horizontal scanning period corresponding to the number of rows (number of lines) of each of the divided pixel portions 90-1 to 90-h shown in FIG. Is done.

  Thereby, the positive polarity switch control signals shown in FIGS. 12C, 12D, and 12E are sent from the shift register 91a shown in FIG. 7 to the divided pixel portions 90-1, 90-2, 90-h. Horizontal scanning corresponding to twice the number of lines (number of lines) of each of the divided pixel portions 90-1 to 90-h at the input terminals S + (1), S + (2), and S + (h) Supplied every period. Further, from the shift register 91c shown in FIG. 7, the load characteristic control signals shown in FIGS. 12G, 12H, and 12I are sent to the divided pixel portions 90-1, 90-2, and 90-h. The input terminals B (1), B (2), and B (h) are supplied for each horizontal scanning period corresponding to the number of rows (number of lines) of each of the divided pixel portions 90-1 to 90-h.

  Although not shown in FIG. 12, the number of lines (number of lines) of each of the divided pixel units 90-1 to 90-h is a period in which the positive polarity switch control signal is not output and within the H.BLK period. ), A negative polarity switch control signal is output from the AND circuit 147 of FIG. 11 and supplied to the shift register 91b of FIG. Thereby, the positive switch control signal is not output to each of the input terminals S- (1) to S- (h) of the divided pixel units 90-1 to 90-h shown in FIG. The negative polarity control signal is supplied within another H.BLK period.

  The ramp waveform shown in FIG. 12 (K) has a constant slope used to convert a digital video signal into an analog video signal and supply it to the positive data line Di + shown in FIG. The reference lamp voltage for positive polarity is described in detail later. The reference ramp voltage used for converting the digital video signal to be displayed into the analog video signal and supplying the same to the negative data line Di- shown in FIG. 3 and the like is not shown in FIG. It is.

  According to the driving method of this embodiment, the reference lamp voltage fluctuates due to the crosstalk, and the positive video signal and the negative data line Di− supplied to the positive data line Di +. Even if the negative polarity video signal supplied to fluctuates, the correct video signal can be written if the ramp waveform returns to the original waveform within the H.BLK period. Accordingly, in the adjacent image display positions 94-1 to 94- (h-1) of the image display units 93-1 to 93-h corresponding to the divided pixel units 90-1 to 90-h illustrated in FIG. Even if a defect (grayscale variation) occurs in the display image, in this embodiment, the influence of the crosstalk is within the H.BLK period, and therefore the visual image quality deterioration of the display image is removed. be able to.

  FIG. 13 shows a timing chart for explaining the second embodiment of the driving method of the liquid crystal display device according to the present invention using the timing control circuit shown in FIG.

  In the driving method of this embodiment, the shift clock SCK shown in FIG. 13A is supplied to the shift registers 91a, 91b and 91c of the third embodiment of the liquid crystal display device according to the present invention shown in FIG. In addition, the positive polarity switch control signal shown in FIG. 13B is output from the AND circuit 146 of FIG. 11, and the load characteristic control signal shown in FIG. 13F is output from the EX-OR circuit 148 of FIG. To do.

  Accordingly, the positive polarity switch control signals shown in FIGS. 13C, 13D, and 13E are sent from the shift register 91a shown in FIG. 7 to the divided pixel portions 90-1, 90-2, 90-h. Are supplied to the input terminals S + (1), S + (2), and S + (h). Further, from the shift register 91c shown in FIG. 7, the load characteristic control signals shown in FIGS. 13 (G), (H), and (I) are sent to the divided pixel portions 90-1, 90-2, and 90-h. The input terminals B (1), B (2), and B (h) are supplied for each horizontal scanning period corresponding to the number of rows (number of lines) of each of the divided pixel portions 90-1 to 90-h.

  Although not shown in FIG. 13, a negative polarity switch control signal is output from the AND circuit 147 of FIG. 11 and supplied to the shift register 91b of FIG. The positive polarity switch control signal shown in FIG. 13B and the negative polarity switch control signal output from the AND circuit 147 in FIG. 11 are the divided pixel units 90-1 to 90-90 shown in FIG. -H is alternately output for each horizontal scanning period corresponding to the number of rows (number of lines). Further, the load characteristic control signal shown in FIG. 13F is output at a cycle of the horizontal scanning period corresponding to the number of rows (number of lines) of each of the divided pixel portions 90-1 to 90-h shown in FIG. Is done. FIG. 13K shows a reference lamp voltage for a positive video signal described later.

  In the first embodiment of the driving method of the present invention described with reference to FIG. 12, it is necessary to transfer the positive polarity switch control signal, the negative polarity switch control signal, and the load characteristic control signal within the H.BLK period. Therefore, it is necessary to select a sufficiently high shift clock frequency. However, when the vertical scanning frequency is changed from 60 Hz to 120 Hz or 240 Hz for the purpose of improving the response of the moving image or when the bit depth is improved, the H.BLK period of sufficient time cannot be secured. There is.

  Therefore, in the second embodiment of the timing chart driving method of the present invention shown in FIG. 13, the delay amount of the delay circuit 149 of the timing control circuit 140 shown in FIG. The signal, the negative polarity switch control signal, and the load characteristic control signal are transferred after the intermediate point X of the reference lamp voltage (the gradation on the high luminance side) as shown in FIG. 13K in one horizontal scanning period.

  As a result, according to the driving method of the present embodiment, the above-described time problem associated with higher frequency is solved. Further, according to the driving method of the present embodiment, the reference lamp voltage fluctuates due to the crosstalk noise generated when the positive polarity switch control signal, the negative polarity switch control signal, and the load characteristic control signal are switched. In the adjacent image display positions 94-1 to 94- (h-1) of the image display units 93-1 to 93-h corresponding to the divided pixel units 90-1 to 90-h shown in FIG. Even if the tone changes, the changing gradation becomes a gradation on the high luminance side, so that it is difficult for human eyes to visually recognize.

  By the way, in the liquid crystal display device according to the present invention, the AC driving frequency of the liquid crystal element can be freely set by the inversion control period in the pixel circuit. For example, it is assumed that the vertical scanning frequency is 60 Hz used for a general television image signal, and the number of scanning lines of full high vision is 1125 lines. If the polarity switching of the pixel circuit is performed at a cycle of about 15 line periods, each of the divided pixel units 90-1 to 90-h shown in FIG. The AC drive frequency of the liquid crystal elements of −1 to 90-h is 2.25 (= 60 (Hz) × 1125 ÷ (15 × 2) kHz. At this time, the positive polarity switch control signal and the negative polarity switch control signal are also 15 lines. Will be transferred once.

  In this case, as described with reference to FIG. 9, the adjacent image display positions 94-1 to 94- (h-1) are once per 15 lines by the crosstalk of the positive polarity switch control signal and the negative polarity switch control signal. In FIG. 5, the gradation in which the reference lamp voltage fluctuates is displayed as a horizontal stripe.

Therefore, a third embodiment of the driving method of the liquid crystal display device according to the present invention that solves this phenomenon will be described below. FIG. 14 is a circuit diagram of a timing control circuit used in the third embodiment of the driving method of the liquid crystal display device according to the present invention. The timing control circuit 150 shown in FIG. 14 includes a 2n frequency dividing circuit 151 that divides the horizontal synchronization signal HD, and x D-type flip-flops (hereinafter referred to as D-FFs) 152 _{1 to} 152 _{x that are} cascade-connected. When, D-FF) 152 ₁ of the Q output signal inverter for logically inverting - a motor 153, an aND circuit 154, third stage ~ (x-2) selector for selecting the Q output signal of the stage of D-FF the circuit 155, an exclusive logical oR-oR circuit (EX-oR) circuits 156, each Q output of the output signal and x-1 stage and final x-th _{D-FF152 x-1} and 152 _x of the selector circuit 155 An OR circuit 157 that performs a logical OR operation of the signals, an inverter 158 that logically inverts the output signal of the 2n frequency dividing circuit 151, and two selector circuits 159 and 160 that perform switching of the output signal of the OR circuit 157 Is The The delay circuit 161 includes a third stage and subsequent D-FFs 142 _{3 to} 142 _x and a selector circuit 155 among _x D-FFs 142 _{1 to} 142 _{x that} are cascade-connected.

  The 2n frequency dividing circuit 151 has the same configuration as the 2n frequency dividing circuit 141, and the frequency dividing ratio of the 2n frequency dividing circuit 151 is selected so that the switching period of the frequency division output becomes a desired polarity inversion period. . As a result, the frequency-divided output signal of the 2n frequency dividing circuit 151 can be used as a basic timing signal for switching the polarity of the liquid crystal driving voltage. The symmetric rectangular wave output from the 2n frequency dividing circuit 151 is a common electrode voltage switching control signal synchronized with the horizontal and vertical scanning timings.

Each of the D-FFs 152 _{1 to} 152 _x is a 1-bit latch circuit, and a basic clock CLK having a period corresponding to a time unit of timing control according to the present embodiment is commonly input to the clock terminals. The D-FFs 152 _{1 to} 152 _x constitute a shift register. The horizontal synchronization signal HD is input to the data input terminal D of the first stage D-FF 152 ₁ of the shift register, which is delayed by one clock time unit from the Q output terminals of the D-FFs 152 ₁ and 152 _2. Is output. Further, from each Q output terminal of the D-FFs 152 _{3 to} 152 _x-2 , the horizontal synchronizing signal HD output from the AND circuit 154 or the horizontal synchronizing signal logically inverted by the inverter 153 is sequentially supplied in units of one clock time. Output with a delay. Further, the output signal of the selector circuit 155 is output from each of the Q output terminals of the D-FFs 152 _{x-1 to} 152 _x with a delay of one clock time unit.

The timing control circuit 150 of this embodiment, the AND circuit 154, inverter the first stage D-FF152 ₁ of the Q output signal - a logically inverted signal data 153, the second stage of the D-FF152 ₂ the Q output signal And a signal obtained thereby is supplied to the OR circuit 157 through the delay circuit 161. The timing control circuit 150 supplies the signals output from the OR circuit 157 to the selector circuits 159 and 160, respectively, and causes the selector circuits 159 and 160 to alternately perform the selection operation according to the common electrode voltage switching control signal. A positive polarity switch control signal to be supplied to S + is output, and a negative polarity switch control signal to be supplied from the selector circuit 160 to the wiring S− is output.

Further, the EX-OR circuit 156 performs an exclusive OR operation on the output signal of the selector circuit 155 and the Q output signal of the D-FF 152 _x−1 to obtain a constant current load transistor of the source follower buffer circuit of the pixel circuit. Is output as a load characteristic control signal for the wiring B.

Note that the control to shift the constant current load transistor (Q7 and Q8 in FIG. 3 or Q9 in FIG. 4) of the pixel circuit source switch circuit from on to off is the pixel polarity changeover switch (FIG. 3, FIG. 4). Therefore, the timing control circuit 150 determines the off timing of the constant current load transistor of the D-FF 152 _x-1 at the x-1 stage. It is generated from the Q output signal, and the OFF timing of the pixel polarity changeover switch is generated from the Q output signal of the D-FF 142 _x at the x stage delayed from that.

The delay circuit 161 in the timing control circuit 150 plays a role of delaying the signal for a certain period depending on the number of stages of the D-FF, and the phase of the switch control signal generation timing of the horizontal synchronization signal HD and the wirings S + and S- It is possible to set by shifting the delay amount by the delay circuit 161. In this case, the delay amount of the delay circuit 161 can be adjusted by selecting one Q output signal among the Q output signals of the D-FFs 152 _{3 to} 152 _x−2 by the selector circuit 155. By adjusting the delay amount, it becomes possible to adjust the mutual phase while maintaining the synchronization between the horizontal scanning operation timing and the polarity switching operation, and the noise generated by the mutual interference between the video signal scanning and the polarity switching operation is reduced most. It is possible to select the conditions to be played.

  Next, an embodiment of the driving method of the liquid crystal display device of the present invention, which is performed using the timing control circuit 150 shown in FIG. 14, will be described with reference to the timing chart of FIG.

  FIG. 15 shows a timing chart for explaining the third embodiment of the driving method of the liquid crystal display device according to the present invention using the timing control circuit 150 shown in FIG. The driving method of this embodiment supplies the shift clock SCK shown in FIG. 15A to the shift registers 91a, 91b and 91c of the third embodiment of the liquid crystal display device according to the present invention shown in FIG. At the same time, the delay amount of the delay circuit 161 of the timing control circuit 150 shown in FIG. 14 is adjusted, and the positive polarity switch control signal shown in FIG. 15B is output from the selector circuit 159 of FIG. 14 EX-OR circuit 156 outputs the load characteristic control signal shown in FIG.

  Here, the load characteristic control signals shown in FIGS. 12 (F) and 13 (F) are generated every horizontal scanning period corresponding to the number of rows (number of lines) of each of the divided pixel portions 90-1 to 90-h. (In the above example, the cycle is 15H), the positive polarity switch control signal shown in FIGS. 12B and 13B and the negative polarity switch control signal (not shown) are alternately supplied every 15H. On the other hand, in the driving method of the present embodiment, the positive polarity switch control signal shown in FIG. 15B and the load characteristic control signal shown in FIG. It is characterized in that it is output every 1H during the 15H output period.

  That is, in the driving method of the present embodiment, the positive polarity switch control signal is output every 1H during a certain 15H period, and the negative polarity switch control signal is held at a constant level, and the negative polarity switch control signal is maintained during the subsequent 15H period. The signal is output every 1H and the positive polarity switch control signal is held at a constant level alternately at 15H cycles.

  Although not shown in FIG. 15, the negative polarity switch control signal is also output every 1H in the 15H output period. In each of the embodiments shown in FIGS. 12 to 15, the common electrode voltage Vcom is the pixel electrode polarity switching pulse (that is, the positive polarity switch control signal and the negative polarity switch control signal) and the load characteristic control signal. The waveforms are inverted every 15H in synchronization. Further, the above 15H is an example, and is set according to the number of rows (number of lines) of the pixels of each of the divided pixel portions 90-1 to 90-h shown in FIG.

  The ramp waveform shown in FIG. 15K has a constant slope used to convert the digital video signal into an analog video signal and supply it to the positive polarity data line Di + shown in FIG. The reference lamp voltage for positive polarity is described in detail later. Similarly, the reference ramp voltage used for converting the digital video signal to the analog video signal and supplying it to the negative polarity data line Di- shown in FIG. 3 etc. is not shown in FIG. is there.

  As a result, the shift register 91a shown in FIG. 7 supplies the input terminals S + (1), S + (2), S + (h) of the divided pixel units 90-1, 90-2, 90-h in FIG. The positive polarity switch control signals shown in (C), (D), and (E) are 1H-cycle signals having different phases. Similarly, FIG. 15 supplied from the shift register 91c shown in FIG. 7 to the input terminals B (1), B (2), and B (h) of the divided pixel portions 90-1, 90-2, and 90-h. The load characteristic control signals shown in (G), (H), and (I) are also signals of a 1H period with different phases.

  Although not shown in FIG. 15, during the period in which the positive polarity switch control signal is not output, the negative polarity switch control signal of 1H cycle is output from the selector circuit 160 in FIG. 14 and supplied to the shift register 91b in FIG. The The positive polarity switch control signal and the negative polarity switch control signal are alternately output for each horizontal scanning period corresponding to a plurality of rows (the number of a plurality of lines) of each of the divided pixel units 90-1 to 90-h. The

  Thus, in the driving method of the present embodiment, the positive polarity switch control signal and the negative polarity switch control are adjusted by adjusting the delay amount of the delay circuit 161 with respect to the horizontal synchronization signal HD shown in FIG. Since the signal and the load characteristic control signal are transferred once in 1H, that is, once in one line and the polarity is switched, the crosstalk gradation generated at the time of polarity switching is the pixel portion of the liquid crystal display device. As a result, it is possible to display an image in which horizontal stripes are not noticeable as a whole screen.

  Next, fourth to sixth embodiments of the driving method of the liquid crystal display device according to the present invention will be described.

  In the fourth to sixth embodiments of the liquid crystal display driving method according to the present invention, as shown in FIG. 16, the pixel polarity switching control pulse transfer and the common electrode voltage polarity inversion are changed for each frame. In this way, the horizontal stripes (horizontal line noise) are made inconspicuous by scattering the cross-talked horizontal stripes generated when the polarity of the pixel circuit is switched. . Here, the pixel polarity switching control pulses are a positive polarity switch control signal and a negative polarity switch control signal, and may include a load characteristic control signal.

  16 (A), (B), (C), and (D) show the vertical synchronization signal VD in the first frame, the second frame, the third frame, and the nth frame, respectively. Waveform of the load characteristic control signal transmitted through the wiring B, the positive polarity switch control signal transmitted through the wiring S +, the negative polarity switch control signal transmitted through the wiring S−, and the common electrode voltage Vcom of the liquid crystal element Indicates. Here, the first frame and the n-th frame are the same. As shown in FIGS. 16A to 16D, the load characteristic control signal, the positive polarity switch control signal, the negative polarity switch control signal, and the common electrode voltage Vcom with respect to the vertical synchronization signal VD are set for each frame. The phase is shifted.

  Accordingly, for example, as described above, each of the divided pixel portions 90-1 to 90-h is composed of 15 lines of pixels, and adjacent image display positions 94-1 every 15 lines shown in FIG. ~ 94- (h-1), even if horizontal stripes due to defects on the display image (grayscale fluctuations) occur, the vertical line positions that occur vary from frame to frame. As the integrated value that appears, gradation fluctuations due to crosstalk are averaged, and it is possible to display an image in which horizontal stripes are not noticeable visually.

  FIG. 17 is a circuit diagram of a timing control circuit used in the fourth to sixth embodiments of the driving method of the liquid crystal display device according to the present invention. In this example, it is assumed that the vertical scanning frequency is 60 Hz used for a general television image signal, and the scanning line number is 1125 lines for full high vision. In addition, the liquid crystal display device to which this timing control circuit is applied switches the polarity of the pixel circuit in a cycle of 5 line periods, and the AC drive frequency of the liquid crystal element is 6.75 (= 60 (Hz) × 1125 ÷ 5 × 2) The reference lamp voltage fluctuates once every five lines due to the influence of the crosstalk caused by the polarity switching control pulses (positive polarity switch control signal, negative polarity switch control signal, load characteristic control signal) as described above. It is assumed that the gradation is displayed as a horizontal stripe.

The timing control circuit 170 shown in FIG. 17 includes an initial value table 171, a 2n frequency dividing circuit 172 that divides the horizontal synchronizing signal HD, and five cascade-connected D-FFs 173 _{1 to} 173 ₅ . , An inverter 174 that logically inverts the Q output signal of the D-FF 173 ₂ , an inverter 175 that logically inverts the Q output signal of the D-FF 173 ₅ , AND circuits 176 and 177, D-FF 173 ₃ and D An EX-OR circuit 178 that performs an exclusive OR operation on each Q output signal of the FF 173 ₄ is configured.

  The 2n frequency dividing circuit 172 includes an HD counter and a VD counter, and generates a waveform according to these count values. In other words, the 2n frequency dividing circuit 172 uses the horizontal synchronization signal HD as the clock input, and generates the horizontal synchronization signal HD from the next value of the initial data loaded from the initial value table 171 every time the vertical synchronization signal VD is input. The counter circuit starts counting and generates a symmetric rectangular wave whose polarity is inverted to high level or low level every time n horizontal synchronization signals HD are counted. Here, it is assumed that the 2n frequency dividing circuit 172 generates a symmetric square wave whose polarity is inverted every time five horizontal synchronizing signals are counted. Accordingly, the positive polarity switch control signal and the negative polarity switch control signal output from the timing control circuit 170 are alternately output every 5H and supplied to the shift registers 91a and 91b shown in FIG. In this case, each of the divided pixel portions 90-1 to 90-h is divided every five lines.

  Returning to FIG. The initial value table 171 counts the vertical synchronization signal VD, and according to the number of counts, the initial value of the timing indicated by the driving method of each embodiment shown in FIGS. To load. For example, when the vertical synchronization signal VD is input, the initial value table 171 loads an initial value corresponding to the VD counter value at that time into the 2n frequency dividing circuit 172. As a result, when “0” is loaded as the initial value, the 2n divider circuit 172 starts counting the horizontal synchronization signal HD from “1” after the vertical synchronization signal VD is input, and the fifth horizontal synchronization signal. Since the HD count value becomes “5” when HD is input, it becomes a predetermined level, and thereafter, a symmetrical square wave that is inverted every time five horizontal synchronization signals HD are input is generated. Further, when “1” is loaded as an initial value, the 2n frequency dividing circuit 172 starts counting the horizontal synchronization signal HD from “2” after the vertical synchronization signal VD is input, and the fourth horizontal synchronization signal HD. Since the HD count value becomes “5” when “” is input, it becomes a predetermined level, and thereafter a symmetrical square wave that is inverted every time five horizontal synchronizing signals HD are input is generated.

The frequency dividing ratio of the 2n frequency dividing circuit 172 is selected so that the switching cycle of the frequency dividing output becomes a desired polarity inversion cycle. As a result, the divided output signal of the 2n divider circuit 172 can be used as a basic timing signal for switching the polarity of the liquid crystal drive voltage. Symmetrical square wave output from the 2n-divider circuit 172, horizontal, as the original signal of the common electrode voltage switching control signal synchronized with the vertical scan timing, D-FF173 ₁ de - applied to the data input terminal D.

Although not shown, the output terminal and the D-FF173 ₁ of data of 2n-divider circuit 172 - between the data input terminal D, by interposing a delay circuit for delaying a certain period signal, a horizontal synchronization It is also possible to set the phase between the signal HD and the reference voltage of the polarity switching timing by shifting by the delay amount by the delay circuit. In this case, by adjusting the delay amount, it is possible to adjust the mutual phase while maintaining the synchronization between the horizontal scanning operation timing and the polarity switching operation, and the mutual interference between the video signal scanning and the polarity switching operation. It becomes possible to select a condition in which the generated noise is most reduced.

Each of the D-FFs 173 _{1 to} 173 ₅ is a 1-bit latch circuit, and a basic clock CLK having a period corresponding to a time unit of timing control according to the present embodiment is commonly input to a clock terminal. The five cascade-connected D-FFs 173 _{1 to} 173 ₅ constitute a 5-stage shift register, and the data input terminal D of the _first -stage D-FF 173 ₁ is shared by the 2n divider circuit 172. control timing pulse that matches the polarity switching period of the voltage Vcom is input, which is output with a delay by one clock time unit each Q output terminal of the D-FF173 ₁ ~173 _5.

In this embodiment, since the polarity switching of the common electrode voltage Vcom is controlled to precede the polarity switching of the pixel drive electrode voltage VPE, the Q output signal of the _first stage D-FF 173 ₁ is set as the common electrode voltage Vcom. The AND circuit 176 performs an AND operation on a signal obtained by logically inverting the Q output signal of the second stage D-FF 173 ₂ by the inverter 174 and the Q output signal of the fifth stage D-FF 173 ₅ to perform wiring. A positive polarity switch control signal transmitted in S + is output. The AND circuit 177 performs an AND operation on a signal obtained by logically inverting the Q output signal of the fifth stage D-FF 173 ₅ by the inverter 175 and the Q output signal of the second stage D-FF 173 ₂ , and wiring. A negative polarity switch control signal transmitted in S- is output.

  Accordingly, the AND circuits 176 and 177 output the positive polarity switch control signal and the negative polarity switch control signal alternately every 5H in synchronization with the change of the common electrode voltage Vcom every 5H, and the shift register shown in FIG. 91a and 91b. Further, the EX-OR circuit 178 generates a load control signal for the wiring B that activates the constant current load transistor of the source follower buffer circuit of the pixel circuit shown in FIG. 3 or FIG. Supplied to the shift register 91c.

The control for shifting the constant current load transistor (Q7 and Q8 in FIG. 3 or Q9 in FIG. 4) of the pixel follower buffer circuit of the pixel circuit from on to off is a pixel polarity changeover switch (FIG. 3, FIG. since the fourth Q5 and Q6) needs to be completed in a period that retain the on-state, generated from D-FF173 ₄ of the Q output signal of the fourth stage of the off timing of the constant current load transistor, also, the pixel The off timing of the polarity changeover switch is generated from the Q output signal of the fifth stage D-FF 173 ₅ delayed therefrom.

  As described above, the timing control circuit 170 can reliably realize control of the common electrode, the pixel switch, and the pixel buffer load with a predetermined timing relationship with the cycle of the reference clock CLK.

  Note that the timing control circuit 170 illustrated in FIG. 17 is configured to generate a desired timing control signal by delaying the original input signal as a common electrode control signal. However, the timing control circuit is not limited to the circuit configuration shown in FIG. 17, and may be any circuit that realizes the basic timing control described in FIG.

  Next, each embodiment of the driving method of the liquid crystal display device of the present invention performed using the timing control circuit 170 shown in FIG. 17 will be described with reference to FIGS.

  FIG. 18 is an explanatory diagram of the fourth embodiment of the driving method of the liquid crystal display device according to the present invention using the timing control circuit 170 shown in FIG. In the driving method of this embodiment, as shown in FIG. 18A, the polarity of the first frame is switched on line 1, and then, in the vertical scanning direction, line 6, line 11,. The polarity is switched every 5 lines.

  Subsequently, when the next frame (second frame) is reached, as shown in FIG. 18A, the line is shifted by one line in the vertical scanning direction and switched from line 2, and thereafter, in the vertical scanning direction. The polarity is switched every 5 lines in order of line 7, line 12,. Similarly, as shown in FIG. 18A, the polarity of the third frame is switched every 5 lines sequentially from the line 3, and the fourth frame is sequentially switched every 5 lines from the line 4. Switch polarity. Then, after switching the polarity every 5 lines sequentially from the line 5 at the fifth frame, the same polarity switching as that performed at the line 1 is performed again at the sixth frame. Repeat with.

  In order to perform the above operation, the timing control circuit 170 shown in FIG. 17 has the VD counter value “1” in the initial value table 171 when the first frame vertical synchronization signal is input. At this time, the initial value “4” is loaded into the 2n frequency dividing circuit 172. Accordingly, the 2n frequency dividing circuit 172 starts counting the horizontal synchronization signal HD from “4” after the vertical synchronization signal VD is input, and the HD count value is “5” when the first horizontal synchronization signal HD is input. Therefore, it becomes a predetermined level, and thereafter, a symmetrical square wave is generated that is inverted every time five horizontal synchronizing signals HD are inputted. Therefore, in the first frame, the positive polarity switch control signal and the negative polarity control signal are alternately output and the load control signal is output every five lines in order of line 1, line 6, line 11,. Switch polarity.

  Subsequently, when the second frame vertical synchronizing signal is input, the initial value table 171 indicates that the VD counter value is “2”. At this time, the initial value “3” is transferred to the 2n frequency dividing circuit 172. Load it. As a result, the 2n frequency dividing circuit 172 starts counting the horizontal synchronization signal HD from “3” after the vertical synchronization signal VD is input, and the HD count value is “5” when the second horizontal synchronization signal HD is input. Therefore, it becomes a predetermined level, and thereafter, a symmetrical square wave is generated that is inverted every time five horizontal synchronizing signals HD are inputted. Therefore, in the second frame, the positive polarity switch control signal and the negative polarity control signal are alternately output and the load control signal is output every five lines in order of line 2, line 7, line 12,. Switch polarity.

  Similarly, the initial value table 171 indicates that the initial value “2” is input when the third frame vertical synchronizing signal is input, and the initial value table 171 is initial when the fourth frame vertical synchronizing signal is input. When the vertical synchronization signal of the fifth frame is input as the value “1”, the initial value “0” is loaded into the 2n frequency dividing circuit 172. As a result, the 2n frequency dividing circuit 172 receives the third horizontal synchronization signal HD after the vertical synchronization signal VD is input in the third frame, and the fourth horizontal synchronization signal HD after the vertical synchronization signal VD is input in the fourth frame. In the fifth frame from the input time point, a symmetrical square wave that is inverted every time five horizontal synchronization signals HD are input is generated from the fifth horizontal synchronization signal HD input point after the vertical synchronization signal VD is input. The initial value table 171 and the 2n frequency dividing circuit 172 perform the above-described operation at a cycle of 5 frames.

  In this way, according to the driving method of the present embodiment, as schematically shown in FIG. 18B, the line positions where horizontal stripes are generated due to the polarity switching of the pixel circuit are displayed on the screen. And the line position changes at a cycle of 5 frames, so that the fluctuations in gradation due to the crosstalk appear to be averaged by the integration effect of the human eye, resulting in the generation of visual horizontal stripes. The position can be made inconspicuous.

  FIG. 19 is an explanatory diagram of the fifth embodiment of the driving method of the liquid crystal display device according to the present invention using the timing control circuit 170 shown in FIG. In the driving method of this embodiment, as described above, when the liquid crystal display device displays a full high-definition video signal having a vertical scanning frequency of 60 Hz and a scanning line number of 1125 lines, as shown in FIG. As shown in A), the polarity of the first frame is switched at line 1, and then the polarity is switched every 5 lines in the order of line 6, line 11,... In the vertical scanning direction.

  Subsequently, at the next frame (second frame), as shown in FIG. 19A, the line is shifted by two lines in the vertical scanning direction and switched from the line 3, and thereafter, in the vertical scanning direction. The polarity is switched every 5 lines in order of line 8, line 13,. Similarly, as shown in FIG. 19A, the polarity of the third frame is switched every five lines sequentially from the fifth line. In this way, in the 1st frame to the 3rd frame, the polarity switching start line position is set to the odd line position among the 1st line to the 5th line, and the position is changed. Then, for the fourth frame for which the designation of the start line position for the polarity switching of the odd lines has been completed, the polarity switching is performed every five lines sequentially from the even-numbered line 2 out of the first to fifth lines. Then, after switching the polarity every 5 lines sequentially from the even-numbered line 4 in the 5th frame, the same polarity switching as in the line 1 is performed again in the 6th frame. -Repeat every 2 seconds.

  In order to perform the operation described with reference to FIG. 19A, the timing control circuit 170 shown in FIG. 17 is different from the case in which the initial value table 171 has a relationship between the count value of the vertical synchronization signal and the initial value to be loaded in FIG. The same operation as described above is performed with only differences.

  That is, in the timing control circuit 170 shown in FIG. 17, when the vertical synchronization signal of the first frame is input, the initial value table 171 indicates that the VD counter value is “1”. “4” is loaded into the 2n frequency dividing circuit 172. Accordingly, the 2n frequency dividing circuit 172 starts counting the horizontal synchronization signal HD from “4” after the vertical synchronization signal VD is input, and the HD count value is “5” when the first horizontal synchronization signal HD is input. Therefore, it becomes a predetermined level, and thereafter, a symmetrical square wave is generated that is inverted every time five horizontal synchronizing signals HD are inputted. Therefore, in the first frame, the positive polarity switch control signal and the negative polarity control signal are alternately output and the load control signal is output every five lines in order of line 1, line 6, line 11,. Switch polarity.

  Subsequently, when the second frame vertical synchronization signal is input, the initial value table 171 indicates that the VD counter value is “2”. At this time, the initial value “2” is input to the 2n frequency dividing circuit 172. Load it. Accordingly, the 2n frequency dividing circuit 172 starts counting the horizontal synchronization signal HD from “2” after the vertical synchronization signal VD is input, and the HD count value is “5” when the third horizontal synchronization signal HD is input. Therefore, it becomes a predetermined level, and thereafter, a symmetrical square wave is generated that is inverted every time five horizontal synchronizing signals HD are inputted. Therefore, in the second frame, the positive polarity switch control signal and the negative polarity control signal are alternately output and the load control signal is output every five lines in order of line 3, line 8, line 13,. Switch polarity.

  Similarly, the initial value table 171 indicates that the initial value “0” is input when the third frame vertical synchronizing signal is input, and the initial value table 171 is initial when the fourth frame vertical synchronizing signal is input. When the vertical synchronization signal of the fifth frame is input as the value “3”, the initial value “1” is loaded into the 2n frequency dividing circuit 172. As a result, the timing control circuit 170 alternately switches the positive polarity switch control signal and the negative polarity control signal every 5 lines from the line 5 in the third frame, from the line 2 in the fourth frame, and from the line 4 in the fifth frame. In addition to outputting, a load control signal is output to switch the polarity.

  In this way, according to the driving method of the present embodiment, as schematically shown in FIG. 19B, the line position where horizontal stripes are generated due to the polarity switching of the pixel circuit is displayed on the screen. Since the line start positions where the horizontal stripes of each frame are generated are dispersed (scattered) in a cycle of 5 frames in the order indicated by the circled numbers, the gradation by the crosstalk is displayed. Fluctuations appear to be averaged by the integration effect of the human eye, and the occurrence position of horizontal stripes can be made inconspicuous.

  FIG. 20 is an explanatory diagram of the sixth embodiment of the driving method of the liquid crystal display device according to the present invention using the timing control circuit 170 shown in FIG. In the driving method of this embodiment, as described above, when the liquid crystal display device displays a full high-definition video signal having a vertical scanning frequency of 60 Hz and a scanning line number of 1125 lines, as shown in FIG. As shown in A), the polarity of the first frame is switched at line 1, and then the polarity is switched every 5 lines in the order of line 6, line 11,... In the vertical scanning direction.

  Subsequently, at the next frame (second frame), as shown in FIG. 20 (A), the line is shifted to the farthest line in the vertical scanning direction and the polarity is switched from the line 5, and then In the vertical scanning direction, the polarity is switched every five lines in order of line 10, line 15,. Subsequently, at the next frame (third frame), as shown in FIG. 20A, the polarity is switched from the farthest line 2 where the polarity is not switched, and then in the vertical scanning direction. The polarity is switched every 5 lines in order of line 7, line 12,. Similarly, as shown in FIG. 20A, the polarity of the 4th frame is switched from the line 4 every 5 lines, and the polarity of the 5th frame is switched from the line 3 every 5 lines. Do. Then, the same polarity switching as that performed on the line 1 is performed again at the 6th frame, and the operation is repeated at a cycle of 5 frames.

  In order to perform the operation described with reference to FIG. 20A, the timing control circuit 170 illustrated in FIG. 17 loads the timing control circuit 170 illustrated in FIG. 17 with the initial value table 171 loaded with the count value of the vertical synchronization signal. The same operation as described above is performed except that the relationship between the initial values is different from that in FIGS.

  That is, in the timing control circuit 170 shown in FIG. 17, when the vertical synchronization signal of the first frame is input, the initial value table 171 indicates that the VD counter value is “1”. “4” is loaded into the 2n frequency dividing circuit 172. Accordingly, the 2n frequency dividing circuit 172 starts counting the horizontal synchronization signal HD from “4” after the vertical synchronization signal VD is input, and the HD count value is “5” when the first horizontal synchronization signal HD is input. Therefore, it becomes a predetermined level, and thereafter, a symmetrical square wave is generated that is inverted every time five horizontal synchronizing signals HD are inputted. Therefore, in the first frame, the positive polarity switch control signal and the negative polarity control signal are alternately output and the load control signal is output every five lines in order of line 1, line 6, line 11,. Switch polarity.

  Subsequently, when the vertical synchronization signal of the second frame is input, the initial value table 171 indicates that the VD counter value is “2”. At this time, the initial value “0” is input to the 2n frequency dividing circuit 172. Load it. Accordingly, the 2n frequency dividing circuit 172 starts counting the horizontal synchronization signal HD from “0” after the vertical synchronization signal VD is input, and the HD count value is “5” when the fifth horizontal synchronization signal HD is input. Therefore, it becomes a predetermined level, and thereafter, a symmetrical square wave is generated that is inverted every time five horizontal synchronizing signals HD are inputted. Accordingly, in the second frame, the positive polarity switch control signal and the negative polarity control signal are alternately output and the load control signal is output every five lines in order of line 5, line 10, line 15,. Switch polarity.

  Similarly, the initial value table 171 indicates that the initial value “3” is input when the third frame vertical synchronizing signal is input, and the initial value table 171 is initial when the fourth frame vertical synchronizing signal is input. When the vertical synchronization signal of the fifth frame is input as the value “1”, the initial value “2” is loaded into the 2n frequency dividing circuit 172. Accordingly, the timing control circuit 170 alternately switches the positive polarity switch control signal and the negative polarity control signal every 5 lines from the line 2 in the third frame, from the line 4 in the fourth frame, and from the line 3 in the fifth frame. In addition to outputting, a load control signal is output to switch the polarity.

  In this manner, according to the driving method of the present embodiment, as schematically shown in FIG. 20B, the line position where the horizontal stripes are generated due to the polarity switching of the pixel circuit is displayed on the screen. Are displayed every 5 lines, and the line start positions where the horizontal stripes of each frame are generated are distributed (scattered) in a cycle of 5 frames in the order indicated by the circled numbers. Since this dispersion is performed so as to shift to the most distant line in the vertical direction where polarity switching is not performed, the gradation fluctuation due to the crosstalk appears to be further averaged by the integration effect of the human eye. The occurrence position of horizontal stripes can be made less noticeable.

  In the embodiment shown in FIGS. 18 to 20, the first frame polarity switching line has been described as line 1, but the present invention is not limited to this, and from which line polarity switching is performed. May be started.

  Next, a more specific overall configuration of the liquid crystal display device according to the present invention and an embodiment of a video signal sampling circuit (horizontal direction driving circuit) will be described.

  FIG. 21 is an overall configuration diagram of an embodiment of a liquid crystal display device according to the present invention, and FIG. 22 is a circuit diagram of a horizontal driver circuit in FIG. As shown in FIG. 21, the liquid crystal display device 200 includes shift register circuits 201a and 201b, a one-line latch circuit 202, a comparator 203, a gradation counter 204, analog switches 205, and m pieces in the horizontal direction. N pixel circuits 206 arranged in a matrix in the vertical direction, a timing generator 207, a polarity switching control circuit 208, and a vertical shift register and level shifter 209. Note that each of the pixel circuits 206 includes a liquid crystal element and is also a pixel.

  The shift register circuits 201a and 201b, the one-line latch circuit 202, the comparator 203, and the gradation counter 204 constitute a horizontal driver circuit. This horizontal driver circuit corresponds to the horizontal driving circuit 10 shown in FIG. 2 and constitutes a data line driving circuit together with the analog switch 205. The data line driving circuit is also shown in FIG. The comparator 203 is shown as one block in FIG. 21 for the sake of simplicity, but actually, it is provided for each pixel column as shown in FIG.

  The analog switch 205 shown in FIGS. 21 and 22 has a configuration in which a pair of sampling analog switches for positive polarity and negative polarity are arranged for each pixel column. The sampling analog switch for positive polarity corresponds to the switches 1-1a, 1-2a and the like shown in FIG. 2, and the analog switch for sampling for negative polarity is the switches 1-1b, 1--1 shown in FIG. This corresponds to 2b and the like. The pixel circuit 206 shown in FIG. 21 is at the intersection of two data lines (D1 + and D1-,..., Dm + and Dm-) and the gate lines (G1,..., Gn). Has been placed. Each of the n · m pixel circuits 206 has the circuit configuration shown in FIG. 3 (FIG. 1) or FIG.

  Based on the timing signal from the timing generator 207, the polarity switching control circuit 208 shown in FIG. 21 receives the first gate control signal (positive polarity switch control signal) on the above-described wiring S + and the first on the wiring S-. 2 gate control signal (negative polarity switch control signal) and a load characteristic control signal are output to the wiring B, respectively. A vertical shift register and level shifter 209 shown in FIG. 21 corresponds to the vertical driving circuit 20 shown in FIG. 2, and sequentially outputs gate signals to the gate lines G1 to Gn in one horizontal scanning cycle. The gate lines G1 to Gn are sequentially selected in one horizontal scanning cycle. In FIG. 21, when the pixel circuit 206 is grouped into a plurality of rows to form the divided pixel portions 90-1 to 90-h shown in FIG. 14 and the configuration of the timing control circuit of FIG.

  Next, the operation of FIGS. 21 and 22 will be described with reference to the timing chart of FIG. 21 and 22, a digital video signal in which a plurality of bits of pixel data (DATA) shown in (B) in FIG. 23 (B) is synthesized in time series in synchronization with the horizontal synchronizing signal HD shown in (A) of FIG. Are sequentially developed as data for one line by the shift register circuits 201a and 201b, and are latched by the one-line latch circuit 202 when the development for one line is completed.

  Of the pixel data (DATA) shown in FIG. 23 (B), even-numbered column pixel data DATA (even) in the horizontal direction shown every other white background is supplied to the shift register circuit 201a, and the hatched lines are shown. Odd column pixel data DATA (odd) in the horizontal direction shown in every other remaining one is supplied to the shift register circuit 201b. This is because it is easy to cope with high-speed operation on a high-resolution panel.

  The one-line latch circuit 202 is the same line composed of odd-numbered column pixel data DATA (odd) output from the shift register circuit 201a and even-numbered column pixel data DATA (even) output from the shift register circuit 201b. After the pixel data DATA of one line period is held as schematically shown in FIG. 23D, it is supplied to the first data input section of the comparator 203 in each pixel column.

  The gradation counter 204 counts the clock Count-CK shown in FIG. 23 (E), and as shown in FIG. 23 (F), a plurality of gradation values are sequentially obtained from the minimum value to the maximum value within the horizontal scanning period. The changing reference gradation data C-out is output every horizontal scanning period, and supplied to the second data input section of the comparator 203 of each pixel column. The comparator 203 has a value of the input pixel data DATA of the first data input unit and a value (tone value) of the input reference gradation data C-out of the second data input unit. And a coincidence pulse is generated and output at a timing when both values coincide.

  Of the two sampling analog switches for positive polarity and negative polarity that constitute the analog switch 205, the sampling analog switch for positive polarity applies the reference ramp voltage Ref_Ramp (+) to the common wiring on the input side. Is done. On the other hand, in the sampling analog switch for negative polarity, the reference ramp voltage Ref_Ramp (−) is applied to the input side common wiring. Of the reference lamp voltages Ref_Ramp (+) and Ref_Ramp (−) generated by the reference voltage generation circuit existing in the controller 60 shown in FIG. 2, Ref_Ramp (+) is shown in FIG. Thus, the periodic sweep signal changes in the direction in which the level increases from the black level to the white level of the video in the horizontal scanning period cycle. On the other hand, the reference ramp voltage Ref_Ramp (−) is a periodic sweep signal that changes in a direction in which the level decreases from the black level to the white level of the image in the horizontal scanning period as shown in FIG. . Accordingly, the reference lamp voltages Ref_Ramp (+) and Ref_Ramp (−) have an inversion relationship with respect to a predetermined reference potential.

  The analog switch 205 receives the SW-Start signal shown in FIG. 23 (G), turns on at the same time at the start of the horizontal scanning period, and then turns off when the coincidence pulse is received from the comparator 203. The opening and closing is controlled as follows. In the timing chart of FIG. 23, for example, the opening / closing timing of the analog switch 205 of the pixel column corresponding to the pixel data DATA of the gradation level k is shown as a waveform SPk shown in FIG. As a result, the reference ramp voltage Ref_Ramp (+) at the time when the pair of sampling analog switches for positive polarity and negative polarity constituting the analog switch 205 of the pixel column are simultaneously turned off in response to the coincidence pulse. And Ref_Ramp (−) corresponding levels (points P and Q in FIGS. 23 (I) and (J)) are simultaneously sampled, and pixel data lines D (+) and D (−) of the pixel column are sampled simultaneously. Is output.

  As described above, according to the horizontal driver circuit of this embodiment, the configuration and operation of which are described, it is possible to supply positive and negative pixel data to each pixel with a simple configuration. Further, according to the horizontal driver circuit of this embodiment, it is possible to interface the video input to the liquid crystal display device with a digital signal as shown in FIG. Since an analog circuit block for processing with high accuracy is not required, circuit cost can be reduced.

1-1a, 1-1b, 1-2a, 1-2b Video switch 4, PE Reflective electrode (pixel drive electrode)
5a, 5b Horizontal signal lines 6-1a, 6-1b, 6-2a, 6-2b, D1 (+) to Dm (+), D1 (-) to Dm (-), Di +, Di- data line 7 Common electrode lines 8-1, 8-2, Gj, G1 to Gn Gate lines 10 Horizontal drive circuit 20 Vertical drive circuit 30 Pixel section 41, 42, 51, 52 Pixel 60 Controller 71a Positive side Video signal (positive polarity video signal)
71b Negative video signal (negative video signal)
206 pixel circuits 90-1~90-h divided pixel unit 91a, 91b, 91c shift register 140,150,170 timing control circuit _{142 1 ~142 x + 2, 152} 1 ~152 x, 173 1 ~173 5 D -type flip (D-FF)
144, 145, 153, 174, 175 Inverter 146, 147, 176, 177 AND circuit 148, 156, 178 Exclusive OR circuit (EX-OR circuit)
141, 151, 172 2n frequency dividing circuit 143, 155, 159, 160 selector circuit 149, 161 delay circuit 157 OR circuit 171 initial value table 200 liquid crystal display device 201a, 201b shift register circuit 202 1 line latch circuit 203 comparator 204 Gradation counter 205 Analog switch 207 Timing generator 208 Polarity switching control circuit 209 Vertical shift register / level shifter 221 Input terminal section S1, S2 selector switch C1, C2, C3, Cs1, Cs2 Signal holding capacity A1, A2 Buffer amplifier Q1 , Q2 Pixel selection transistor Q3, Q4 Buffer amplifier transistor Q5, Q6 Switching transistor Q7, Q8 Constant current source load transistor Q9 Constant current source transistor CE Common electrode Counter electrode)
LCM liquid crystal display (liquid crystal layer)
LC liquid crystal element

Claims (10)

A plurality of pixels provided at intersections where a plurality of sets of data lines and a plurality of gate lines intersect each other, each of which includes two data lines as a set;
Provided for each of the plurality of sets of data lines, supplying a positive video signal to one of the two sets of data lines, and negative polarity to the other data line A plurality of switches for sequentially supplying video signals to the plurality of sets of data lines in units of sets;
Horizontal and vertical driving means for performing horizontal driving for driving the plurality of switches in the set unit within a horizontal scanning period and vertical driving for selecting the plurality of gate lines for each horizontal scanning period. When,
Each of the plurality of pixels includes:
A liquid crystal element in which a liquid crystal layer is sandwiched between an opposing pixel drive electrode and a common electrode;
First sampling and holding means for sampling and holding the positive video signal for a certain period;
Second sampling and holding means for sampling and holding the negative video signal for the predetermined period;
Switching between the positive video signal voltage held by the first sampling and holding means and the negative video signal voltage held by the second sampling and holding means at a predetermined cycle shorter than the vertical scanning period. Switching means for alternately applying to the pixel drive electrodes,
When the entire pixel portion including the plurality of pixels constituting the display screen is divided into a plurality of groups each including pixels in a plurality of consecutive rows as a group, a plurality of the plurality of divided groups are included. The switching means is controlled in a time-sharing manner in units of each divided group by a polarity switching pulse having a predetermined cycle shorter than the vertical scanning period, and the switching control means has the positive polarity A liquid crystal display device , wherein the switching means is actively controlled by transferring the polarity switching pulse within a horizontal blanking period of the video signal and the negative video signal . A plurality of pixels provided at intersections where a plurality of sets of data lines and a plurality of gate lines intersect each other, each of which includes two data lines as a set;
Provided for each of the plurality of sets of data lines, supplying a positive video signal to one of the two sets of data lines, and negative polarity to the other data line A plurality of switches for sequentially supplying video signals to the plurality of sets of data lines in units of sets;
Horizontal and vertical driving means for performing horizontal driving for driving the plurality of switches in the set unit within a horizontal scanning period and vertical driving for selecting the plurality of gate lines for each horizontal scanning period. When,
Each of the plurality of pixels includes:
A liquid crystal element in which a liquid crystal layer is sandwiched between an opposing pixel drive electrode and a common electrode;
First sampling and holding means for sampling and holding the positive video signal for a certain period;
Second sampling and holding means for sampling and holding the negative video signal for the predetermined period;
Switching between the positive video signal voltage held by the first sampling and holding means and the negative video signal voltage held by the second sampling and holding means at a predetermined cycle shorter than the vertical scanning period. Switching means for alternately applying to the pixel drive electrodes,
With
When the entire pixel portion including the plurality of pixels constituting the display screen is divided into a plurality of groups each including pixels in a plurality of consecutive rows as a group, a plurality of the plurality of divided groups are included. Switching control means for controlling the switching means to be active in a time-sharing manner in units of each divided group by a polarity switching pulse having a predetermined cycle shorter than the vertical scanning period,
It said switching control means, wherein the intermediate or the tone of the positive polarity video signals and the negative polarity video signal and transfers the polarity switching pulses, the liquid crystal display you and controls said switching means to activate apparatus. A plurality of pixels provided at intersections where a plurality of sets of data lines and a plurality of gate lines intersect each other, each of which includes two data lines as a set;
Provided for each of the plurality of sets of data lines, supplying a positive video signal to one of the two sets of data lines, and negative polarity to the other data line A plurality of switches for sequentially supplying video signals to the plurality of sets of data lines in units of sets;
Horizontal and vertical driving means for performing horizontal driving for driving the plurality of switches in the set unit within a horizontal scanning period and vertical driving for selecting the plurality of gate lines for each horizontal scanning period. When,
Each of the plurality of pixels includes:
A liquid crystal element in which a liquid crystal layer is sandwiched between an opposing pixel drive electrode and a common electrode;
First sampling and holding means for sampling and holding the positive video signal for a certain period;
Second sampling and holding means for sampling and holding the negative video signal for the predetermined period;
Switching between the positive video signal voltage held by the first sampling and holding means and the negative video signal voltage held by the second sampling and holding means at a predetermined cycle shorter than the vertical scanning period. Switching means for alternately applying to the pixel drive electrodes,
When the entire pixel portion including the plurality of pixels constituting the display screen is divided into a plurality of groups each including pixels in a plurality of consecutive rows as a group, a plurality of the plurality of divided groups are included. Switching control means for actively controlling the switching means in a time-sharing manner for each divided group by a polarity switching pulse having a predetermined period shorter than the vertical scanning period.
With
The switching control means transfers the polarity switching pulse at a rate of once in one horizontal scanning period of the positive video signal and the negative video signal to actively control the switching means. that liquid crystal display device. A plurality of pixels provided at intersections where a plurality of sets of data lines and a plurality of gate lines intersect each other, each of which includes two data lines as a set;
Provided for each of the plurality of sets of data lines, supplying a positive video signal to one of the two sets of data lines, and negative polarity to the other data line A plurality of switches for sequentially supplying video signals to the plurality of sets of data lines in units of sets;
Horizontal and vertical driving means for performing horizontal driving for driving the plurality of switches in the set unit within a horizontal scanning period and vertical driving for selecting the plurality of gate lines for each horizontal scanning period. When,
Each of the plurality of pixels includes:
A liquid crystal element in which a liquid crystal layer is sandwiched between an opposing pixel drive electrode and a common electrode;
First sampling and holding means for sampling and holding the positive video signal for a certain period;
Second sampling and holding means for sampling and holding the negative video signal for the predetermined period;
Switching between the positive video signal voltage held by the first sampling and holding means and the negative video signal voltage held by the second sampling and holding means at a predetermined cycle shorter than the vertical scanning period. Switching means for alternately applying to the pixel drive electrodes,
With
When the entire pixel portion including the plurality of pixels constituting the display screen is divided into a plurality of groups each including pixels in a plurality of consecutive rows as a group, a plurality of the plurality of divided groups are included. Switching control means for controlling the switching means to be active in a time-sharing manner in units of each divided group by a polarity switching pulse having a predetermined cycle shorter than the vertical scanning period,
In synchronization with the switching cycle between the positive video signal voltage and the negative video signal voltage applied to the pixel driving electrode, the common electrode is configured so that the absolute value of the potential difference applied to the liquid crystal layer is always substantially the same. Common electrode voltage control means for changing the applied common electrode voltage between two different levels;
The switching timing between the positive video signal voltage and the negative video signal voltage applied to the pixel drive electrode by the switching means, and the polarity inversion timing of the common electrode voltage by the common electrode voltage control means, positive video signal and the negative polarity video signal frame - further liquid crystal display device you characterized in that a timing change means for changing at unitless. The common electrode voltage control means outputs two common electrode voltages to be applied to the common electrode prior to a switching timing between the positive video signal voltage and the negative video signal voltage applied to the pixel driving electrode. 5. The liquid crystal display device according to claim 4 , wherein the liquid crystal display device is changed between different levels. Each group of two data lines and each of a plurality of pixels provided at an intersection where a plurality of sets of data lines and a plurality of gate lines intersect each other, each group includes two data lines. A first sampling step of sampling a drive voltage corresponding to a positive video signal transmitted on one of the data lines on the pixel drive electrode at a predetermined period shorter than the vertical scanning period and holding it for a first fixed period;
Pixel drive is performed with a drive voltage corresponding to a negative video signal transmitted on the other of the two data lines in each set at a time difference of a half of the predetermined period from the sampling time in the first step. A second sampling step of sampling the electrode at the predetermined period and holding the first fixed period;
The positive-polarity video signal voltage and the negative-polarity video signal voltage held in the first and second sampling steps are switched at a predetermined cycle shorter than a vertical scanning period, and provided to each of the plurality of pixels. A pixel drive electrode voltage application step for alternately applying to the pixel drive electrode of the liquid crystal element;
Including
The pixel driving electrode voltage applying step includes a step of applying the positive video signal voltage and the negative video signal voltage to a predetermined cycle shorter than a vertical scanning period, and horizontally between the positive video signal and the negative video signal. A driving method of a liquid crystal display device , wherein switching is performed by a polarity switching pulse transferred within a blanking period, and the switching is applied alternately to the pixel driving electrodes of the liquid crystal elements provided in each of the plurality of pixels . Each group of two data lines and each of a plurality of pixels provided at an intersection where a plurality of sets of data lines and a plurality of gate lines intersect each other, each group includes two data lines. A first sampling step of sampling a drive voltage corresponding to a positive video signal transmitted on one of the data lines on the pixel drive electrode at a predetermined period shorter than the vertical scanning period and holding it for a first fixed period;
Pixel drive is performed with a drive voltage corresponding to a negative video signal transmitted on the other of the two data lines in each set at a time difference of a half of the predetermined period from the sampling time in the first step. A second sampling step of sampling the electrode at the predetermined period and holding the first fixed period;
The positive-polarity video signal voltage and the negative-polarity video signal voltage held in the first and second sampling steps are switched at a predetermined cycle shorter than a vertical scanning period, and provided to each of the plurality of pixels. A pixel drive electrode voltage application step for alternately applying to the pixel drive electrode of the liquid crystal element;
Including
The pixel driving electrode voltage application step includes the positive video signal voltage and the negative video signal voltage at a predetermined cycle shorter than a vertical scanning period and between the positive video signal and the negative video signal. switch the polarity switching pulses to be transferred in the above gradation, the drive of the plurality of the pixel driving electrode liquid crystal display device you characterized in that alternately applied to the liquid crystal element provided in each pixel Method. Each group of two data lines and each of a plurality of pixels provided at an intersection where a plurality of sets of data lines and a plurality of gate lines intersect each other, each group includes two data lines. A first sampling step of sampling a drive voltage corresponding to a positive video signal transmitted on one of the data lines on the pixel drive electrode at a predetermined period shorter than the vertical scanning period and holding it for a first fixed period;
Pixel drive is performed with a drive voltage corresponding to a negative video signal transmitted on the other of the two data lines in each set at a time difference of a half of the predetermined period from the sampling time in the first step. A second sampling step of sampling the electrode at the predetermined period and holding the first fixed period;
The positive-polarity video signal voltage and the negative-polarity video signal voltage held in the first and second sampling steps are switched at a predetermined cycle shorter than a vertical scanning period, and provided to each of the plurality of pixels. A pixel drive electrode voltage application step for alternately applying to the pixel drive electrode of the liquid crystal element;
Including
In the pixel driving electrode voltage application step, the positive video signal voltage and the negative video signal voltage are set to a predetermined cycle shorter than a vertical scanning period, and one of the positive video signal and the negative video signal. switch the polarity switching pulses to be transferred once every horizontal scanning period, the liquid you and applying alternately to the pixel driving electrode of the liquid crystal element provided in each of the plurality of pixels crystals A driving method of a display device. When the entire pixel portion composed of the plurality of pixels constituting the display screen is divided into a plurality of groups in which each pixel in a plurality of consecutive rows is one group, the pixel drive electrode voltage application step includes: The positive video signal voltage and the negative video signal voltage are switched in a time-sharing manner for each divided group by a polarity switching pulse having a predetermined period shorter than a vertical scanning period, and provided to each of the plurality of pixels. 9. The method of driving a liquid crystal display device according to claim 6 , wherein the liquid crystal display device is alternately applied to the pixel driving electrodes of the liquid crystal element. Each group of two data lines and each of a plurality of pixels provided at an intersection where a plurality of sets of data lines and a plurality of gate lines intersect each other, each group includes two data lines. A first sampling step of sampling a drive voltage corresponding to a positive video signal transmitted on one of the data lines on the pixel drive electrode at a predetermined period shorter than the vertical scanning period and holding it for a first fixed period;
Pixel drive is performed with a drive voltage corresponding to a negative video signal transmitted on the other of the two data lines in each set at a time difference of a half of the predetermined period from the sampling time in the first step. A second sampling step of sampling the electrode at the predetermined period and holding the first fixed period;
The positive-polarity video signal voltage and the negative-polarity video signal voltage held in the first and second sampling steps are switched at a predetermined cycle shorter than a vertical scanning period, and provided to each of the plurality of pixels. A pixel drive electrode voltage application step for alternately applying to the pixel drive electrode of the liquid crystal element;
Including
The absolute value of the potential difference applied to the liquid crystal layer of the liquid crystal element is always substantially the same in synchronization with a switching cycle between the positive video signal voltage and the negative video signal voltage applied to the pixel driving electrode. A common electrode voltage control step of changing a common electrode voltage applied to the common electrode facing the pixel drive electrode of the liquid crystal element between two different levels;
The switching timing between the positive video signal voltage and the negative video signal voltage in the pixel driving electrode voltage application step, and the polarity inversion timing of the common electrode voltage in the common electrode voltage control step are the positive video signal. And a timing changing step for changing the voltage and the negative video signal voltage in frame units, and after changing the level of the common electrode voltage by the common electrode voltage control step, the driving method of a liquid crystal display device you and performing the sampling by the sampling second sampling step sequentially.

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