JP2012145798A - Electro-optical device, driving circuit of the same and electronic apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent reduction in a holding voltage of a liquid crystal capacitor due to an off-leak of a transistor.SOLUTION: Individual pixels 110 are disposed corresponding to intersections between scanning lines 112 and data lines 114 in such a manner that the scanning lines 112 and capacitance lines 132 are disposed for each line and that the data lines 114 are disposed for each row. Here, a capacitance line driving circuit 160 fixes a voltage to Vcom when one scanning line 112 is selected with respect to a capacitance line 132 corresponding to a scanning line 112 of a certain line, and changes the voltage from Vcom as time elapses when the time amount Ta has just elapsed after a completion of a selection of the one scanning line 112. With reference to a changing direction of the voltage in this case, the changing direction after a positive polarity writing is set to a rising direction and the changing direction after a negative polarity writing is set to a falling direction.

Description

  The present invention relates to an active matrix electro-optical device having a transistor for each pixel, a driving circuit for the electro-optical device, and an electronic apparatus having the electro-optical device.

In an electro-optical device, for example, a liquid crystal display device, pixels including transistors and auxiliary capacitors are generally provided corresponding to intersections of a plurality of scanning lines and a plurality of data lines. The transistor functions as a switching element. One end of the transistor is connected to the data line, the other end is connected to one end of the auxiliary capacitor, and the transistor is turned on during the scanning line selection period. In this configuration, the gradation of the pixel is defined according to the potential held at the other end of the transistor, but the holding potential changes during the non-selection period of the scanning line, that is, the off-period of the transistor, and display unevenness is caused. Prone to cause.
For this reason, a technique for making the specific number of common electrodes equal to the time constant of the capacitance line (see Patent Document 1) has been proposed. In addition, a technique for adjusting the data signal supplied to one end of the transistor according to the position of the pixel by considering the cause as the influence of the light source distribution unevenness and the noise according to the position of the pixel is also proposed (see Patent Document 2). Has been.

JP 2000-98337 A (see FIG. 1) Japanese Patent Laying-Open No. 2004-287113 (see FIGS. 1 and 3)

However, any of the above-described techniques has a problem in that the change in the holding potential that occurs during the off-period of the transistor cannot be compensated and display unevenness cannot be sufficiently suppressed.
The present invention has been made in view of the above-described circumstances, and one of its purposes is to provide a technique for suppressing display unevenness by compensating for a change in holding potential during an off period of a transistor.

  In the present invention, the cause of the change in the holding potential during the off-period of the transistor is regarded as the off-leakage of the transistor, and in order to suppress the influence of the off-leakage, the following configuration is adopted. That is, in the drive circuit of the electro-optical device according to the invention, a scanning line, a transistor electrically connected to the scanning line, and an auxiliary capacitor provided in the pixel corresponding to the transistor are provided. A scanning line driving circuit for selecting the scanning line; and supplying a predetermined potential to the capacitor line electrically connected to the auxiliary capacitor during the scanning line selection period. And a capacitor line driver circuit that changes the potential of the capacitor line so that the gradation of the pixel does not change during the non-selection period of the scanning line. According to the present invention, since the change in the holding potential caused by the off-leakage of the transistor during the non-selection period of the scanning line is compensated by the change in the potential of the capacitor line, the influence of the off-leakage can be suppressed. Here, regarding the potential change of the capacitor line, not only the change of the holding potential due to the off-leakage, but also the change of the field through of the transistor, and further, the data signal is sampled on the data line by the sampling transistor. For example, the change in field through of the sampling transistor may be compensated.

In the present invention, it is preferable that the capacitor line driving circuit change the potential of the capacitor line in a direction in which an absolute value of a potential difference from the predetermined potential increases in a non-selection period of the scanning line.
Further, in the present invention, a second scanning line, a second transistor electrically connected to the second scanning line, a second auxiliary capacitor provided in the second pixel corresponding to the second transistor, The scanning line driving circuit selects the second scanning line following the scanning line, and the capacitor line driving circuit electrically connects the second auxiliary capacitor during the selection period of the second scanning line. A predetermined potential is supplied to the second capacitor line connected to the second capacitor line, and the potential of the second capacitor line is changed so that the gradation of the second pixel does not change during the non-selection period of the second scan line. It is good also as a structure made to do. According to this configuration, the operation of correcting the change in the holding potential due to the off-leakage by the change in the potential of the capacitor line is performed over each scanning line. For this reason, the situation where brightness changes with the position of a screen, for example can be prevented.
In the present invention, it is preferable that the capacitor line driving circuit starts a change from the predetermined potential to the capacitor line when a predetermined time elapses after selection of the scanning line is completed. According to this configuration, it is possible to reduce the influence of the coupling noise or the like generated at the timing when the selection of the scanning line is completed on the capacitor line.
In the present invention, the capacitor line driving circuit includes a selector that is provided for the capacitor line and selects either the first terminal or the second terminal, and after the selection of the scanning line has started. The first terminal is selected until a predetermined time elapses after selection of the scanning line, and the second terminal is selected when a predetermined amount of time elapses after the selection of the scanning line is completed, The predetermined potential is applied to the first terminal, an off transistor is connected to the second terminal, and the predetermined potential is maintained until a predetermined time elapses after selection of the scanning line is completed. Is preferably set. According to this configuration, since the off-leakage of the transistor can be simulated by the off-transistor connected to the second terminal, the change in the holding potential during the non-selection period of the scanning line can be represented by It becomes possible to compensate more effectively.
In the present invention, the capacitor line driving circuit may be configured such that the potential of the electrode not connected to the capacitor line among the pair of electrodes of the auxiliary capacitor is higher than a predetermined potential of the capacitor line. The potential of the electrode on the side that is not connected to the capacitor line among the pair of electrodes of the auxiliary capacitor is changed from the predetermined potential to increase with respect to the predetermined potential as time elapses. When the potential is lower than the predetermined potential of the line, it is preferable that the predetermined potential is changed so as to decrease with respect to the predetermined potential as time elapses. According to this configuration, the pixel can be driven with both polarities.

The object is to provide a scanning line, a transistor electrically connected to the scanning line, an auxiliary capacitor provided in a pixel corresponding to the transistor, and a pixel electrode and a common electrode provided in parallel with the auxiliary capacitor. A scanning line driving circuit for selecting the scanning line, and supplying a predetermined potential to the common electrode during the selection period of the scanning line. In addition, this can be achieved by a driving circuit of an electro-optical device that includes a common electrode driving circuit that changes the potential of the common electrode so that the gradation of the pixel does not change during the non-selection period of the scanning line. This is because, according to this drive circuit, the change in the holding potential caused by the off-leakage of the transistor during the non-selection period of the scanning line is compensated by the change in the potential of the common electrode.
In addition to the drive circuit for the electro-optical device, the present invention can be conceptualized as an electro-optical device itself, and also as an electronic apparatus including the electro-optical device. As such an electronic apparatus, there is a projector that enlarges and projects a light modulation image by an electro-optical device.

1 is a block diagram illustrating a configuration of an electro-optical device according to a first embodiment. It is a figure which shows the equivalent circuit of the pixel in an electro-optical apparatus. It is a figure which shows the flame | frame and field in an electro-optical apparatus. It is a figure which shows the structure of the scanning line drive circuit in an electro-optical apparatus. 3 is a timing chart illustrating an operation of a scanning line driving circuit. It is a figure which shows the structure for 1 line of the capacitive line drive circuit in an electro-optical apparatus. 6 is a timing chart illustrating the operation of the capacitor line driving circuit. It is a figure which shows the structure of the data line drive circuit in an electro-optical apparatus. 3 is a timing chart showing the operation of the data line driving circuit. It is a figure for demonstrating operation | movement of an electro-optical apparatus. It is a figure for demonstrating operation | movement of an electro-optical apparatus. FIG. 6 is a block diagram illustrating a configuration of an electro-optical device according to a second embodiment. It is a figure which shows the equivalent circuit of the pixel in an electro-optical apparatus. It is a figure which shows the structure of a common electrode drive circuit. It is a timing chart which shows operation | movement of a common electrode drive circuit. It is a figure for demonstrating operation | movement of an electro-optical apparatus. It is a figure for demonstrating operation | movement of an electro-optical apparatus. It is a figure which shows the structure of the projector to which the electro-optical apparatus is applied. FIG. 10 is a diagram for explaining the operation of an electro-optical device according to a comparative example.

  Embodiments of the present invention will be described below with reference to the drawings. First, the electro-optical device according to the first embodiment will be described. The electro-optical device is a transmissive liquid crystal display device suitable as a light valve for a projector, for example.

<First Embodiment>
FIG. 1 is a block diagram illustrating an overall configuration of the electro-optical device according to the first embodiment. As shown in this figure, the electro-optical device 10a includes a control circuit 20, a memory 30, a D / A conversion circuit 40, and a liquid crystal panel 100.
The liquid crystal panel 100 is provided with 480 scanning lines 112 along the row (X) direction in the drawing. Capacitor lines 132 are provided along the row direction so as to form pairs with the scanning lines 112 of each row. On the other hand, 640 columns of data lines 114 are provided along the column (Y) direction so as to be electrically insulated from each other with respect to each scanning line 112 and each capacitance line 132.
The pixels 110 are arranged corresponding to the intersections of the scanning lines 112 of 480 rows and the data lines 114 of 640 columns, respectively. Therefore, in this embodiment, the pixels 110 are arranged in a matrix of 480 rows × 640 columns to form the display area Ma. However, the present invention is not limited to this arrangement.
In this description, in order to distinguish the rows of the scanning lines 112, the capacitor lines 132, or the pixels 110, they may be called the first row, the second row,. Similarly, in order to distinguish the columns of the data lines 114 or the pixels 110, they may be referred to as the first column, the second column,.

The liquid crystal panel 100 is a peripheral circuit built-in type in which a scanning line driving circuit 140, a capacitor line driving circuit 160, and a data line driving circuit 190 are formed around the display area Ma.
Among these, the scanning line driving circuit 140 generates scanning signals Y1, Y2, Y3,..., Y480 based on the start pulse Dy and the clock signal Cly supplied from the control circuit 20, and 1, 2, 3,. The output is supplied to each of the scanning lines 112 in the 480th row.
The capacitance line driving circuit 160 is configured to output capacitance signals Com1, Com2, Com3,... Based on the voltage Vcom supplied from the outside, the reset signal Rst supplied from the control circuit 20, and the scanning signals Y1, Y2, Y3,. ..., Com 480 is generated and supplied to the capacitor lines 132 in the first, second, third,.
Based on the start pulse Dx and the clock signal Clx supplied from the control circuit 20, the data line driving circuit 190 applies the data signal Vid to the data lines 114 in the first, second, third,. Sampling is performed as X1, X2, X3,..., X640.
Note that details of the scan line driver circuit 140, the capacitor line driver circuit 160, and the data line driver circuit 190 will be described later.

Video data Da is repeatedly supplied to the electro-optical device 1 in units of frames in synchronization with a vertical synchronization signal Vs, a horizontal synchronization signal Hs, and a dot clock signal Clk from a host device (not shown). The video data Da is, for example, 8-bit digital data, and the shade (gradation level) of the pixel 110 is designated by 256 gradations from the darkest “0” to the brightest “255”.
The control circuit 20 generates a control signal, a clock signal, and the like based on the vertical synchronization signal Vs, the horizontal synchronization signal Hs, and the dot clock signal Clk, and controls each unit.
The memory 30 has storage areas corresponding to the respective pixels 110 arranged in 480 rows × 640 columns. Each storage area of the memory 30 stores the video data Da of the corresponding pixel according to the instruction from the control circuit 20, while responding to the writing scan in the liquid crystal panel 100 after one frame, for example. Thus, the video data Db is read twice in total in the first field and the second field.
The D / A conversion circuit 40 converts the read video data Db into a data signal Vid having a voltage corresponding to the gradation level and having a polarity designated by the polarity designation signal Pol. . Specifically, the D / A conversion circuit 40 converts the voltage Vc to the higher voltage when the positive polarity is instructed by the polarity designation signal Pol, while the voltage Vc is the reference when the negative polarity is instructed. As a data signal Vid.

The voltage Vc is the center of the amplitude of the data signal Vid, is a reference for the writing polarity to the pixel 110, and is substantially an intermediate voltage between power supply voltages VH and VL (see FIG. 5, FIG. 9 and the like) described later. . In other words, in the present embodiment, regarding the polarity of the data signal Vid, the higher side than the voltage Vc has a positive polarity, and the lower side has a negative polarity. On the other hand, the voltage VL (= Gnd) is used as a reference unless otherwise specified.
The reason for inverting the polarity of the data signal is to drive the pixel AC. In the present embodiment, a surface inversion method is adopted in which all pixels have the same polarity over a field to be described later, and the polarity is inverted for each field.

FIG. 2 is a diagram showing an equivalent circuit of the pixel 110. The i-th row and the (i + 1) th row adjacent to the i-th row in the downward direction, the j-th column and the (j + 1) -th column adjacent to the j-th row in the right direction, and FIG. A configuration of a total of 4 pixels of 2 × 2 corresponding to the intersections is shown.
Here, i and (i + 1) are symbols for generally indicating the row in which the pixels 110 are arranged, are integers of 1 to 480, and j and (j + 1) are columns in which the pixels 110 are arranged. In general, the symbol is an integer of 1 to 640.

As shown in FIG. 2, each pixel 110 includes an n-channel thin film transistor (hereinafter simply referred to as “TFT”) 116 that functions as a pixel transistor, a liquid crystal capacitor (pixel capacitor) 120, And an auxiliary capacitor 130.
Since each pixel 110 has the same configuration, a description will be given by representatively assuming that the pixel 110 is located in the i row and j column. In the pixel 110 in the i row and j column, the gate electrode of the TFT 116 is connected to the scanning line 112 in the i row. On the other hand, the source electrode is connected to the data line 114 in the j-th column, and the drain electrode is connected to the pixel electrode 118 that is one end of the liquid crystal capacitor 120 and one end of the auxiliary capacitor 130, respectively.
The other end of the liquid crystal capacitor 120 is connected to the common electrode 108. The common electrode 108 is common to all the pixels 110 as shown in FIG. In the first embodiment, the common electrode 108 is configured to be applied with a constant voltage LCcom from the outside.
On the other hand, the other end of the auxiliary capacitor 130 is connected to the i-th capacitor line 132. In the first embodiment, the other end of the i-th auxiliary capacitor 130 is commonly connected to the i-th capacitor line 132.

  In FIG. 2, Y (i) and Y (i + 1) indicate scanning signals supplied to the scanning lines 112 in the i and (i + 1) th rows, respectively, and Com (i) and Com (i + 1). ) Indicate capacitance signals supplied to the capacitance lines 132 in the i and (i + 1) th rows, respectively. Pix (i, j) and Pix (i + 1, j) are symbols for identifying the voltages of the pixel electrodes 118 of the auxiliary capacitor 130 in i row and j column and (i + 1) row and j column, respectively. is there. Cpix represents the capacitance value of the liquid crystal capacitor 120, and Cs represents the capacitance value of the auxiliary capacitor 130.

Although not particularly illustrated, the liquid crystal panel 100 has a certain gap between a pair of substrates, an element substrate on which the pixel electrode 118 is formed and a counter substrate on which the common electrode 108 is formed, so that the electrode formation surfaces face each other. For example, a VA (Vertical Alignment) type liquid crystal 105 is sandwiched in the gap. For this reason, the liquid crystal capacitor 120 is set in a normally black mode, and the pixel electrode 118 and the common electrode 108 sandwich the liquid crystal 105 which is a kind of dielectric, and the voltage of the data signal applied to the pixel electrode 118 A voltage corresponding to the difference from the voltage LCcom applied to the common electrode 108 is held.
In the liquid crystal capacitor 120, since the alignment state of the liquid crystal 105 changes according to the electric field generated by the pixel electrode 118 and the common electrode 108, the liquid crystal capacitor 120 has a transmittance according to the holding voltage. Therefore, in the liquid crystal panel 100, since the transmittance changes for each liquid crystal capacitor 120, the liquid crystal capacitor 120 corresponds to a pixel that is the minimum unit of an image to be displayed. However, in this description, for convenience or custom, a circuit including the TFT 116, the liquid crystal capacitor 120, and the auxiliary capacitor 130 is referred to as a pixel 110.

Next, the relationship between the video data Da supplied from the host device and the writing scan of the liquid crystal panel 100 will be described with reference to FIG. In this figure, the vertical axis indicates the row of pixels defined by the video data Da and Db, and the horizontal axis indicates the elapsed time.
The video data Da is synchronized with the vertical synchronizing signal Vs, the horizontal scanning signal Hs and the dot clock signal Clk from the host device, and more specifically, 1 row 1 column to 1 row 640 column, 2 rows 1 column to 2 rows 640 column. 3 rows and 1 column to 3 rows and 640 columns,... 480 rows and 1 column to 480 rows and 640 columns are supplied for each pixel. For this reason, the supply state of the video data Da in one frame is indicated by a slanting line that descends to the right as shown in FIG.
This video data Da is temporarily stored in the memory 30, and after one frame has elapsed, it is read out twice at a higher rate than when it is supplied from the host device in one frame. For this reason, as shown in FIG. 3B, the inclination of the oblique line indicating the supply of the video data Db is larger than the inclination indicating the supply of the video data Da.

In this description, a frame refers to a period during which video data for one cut (frame) is supplied from the host device. When the frequency of the vertical synchronization signal Vs is 60 Hz, 16.67 for one cycle thereof. A period of milliseconds. Here, since video data Da of a certain frame (denoted as “n frame”) is temporarily stored in the memory 30 and then read out as video data Db, in the present embodiment, for the frame defined by the video data Da. Thus, the frame defined by the video data Db (the frame defining the writing scan of the liquid crystal panel 100) has a delayed relationship, but the time length of the frame is the same.
In the present embodiment, since the video data Db is read twice in one frame, one frame is divided into two periods. Among these, a period earlier in time is called a first field, and a period later in time is called a second field.
In the present embodiment, as shown in FIG. 3C, the control circuit 20 designates the polarity designation signal Pol as the H level in the first field, for example, and designates the positive polarity writing, and designates the negative polarity as the L level in the second field. Specifies sex writing.

Next, the configuration of the scanning line driving circuit 140 will be described with reference to FIG. FIG. 4 is a circuit diagram illustrating an example of the scanning line driving circuit 140.
As shown in this figure, the scanning line driving circuit 140 includes inverters (NOT circuits) 141 and 142, a plurality of sets of n-channel TFTs 143a, 143b, 143c, and 143d, a plurality of buffers 144, and a plurality of AND circuits 145. . Among these, the buffer 144 and the AND circuit 145 are provided corresponding to each row.
The inverter 141 inverts the logic level of the clock signal Cly supplied from the control circuit 20 and outputs it as the inverted clock signal / Cly, and the inverter 142 reinverts and outputs the logic level of the inverted clock signal / Cly. . Therefore, the logic level of the clock signal output from the inverter 142 is the same as that of the clock signal Cly.

The TFTs 143a and 143b are also received corresponding to the even (0, 2, 4, ..., 478, 480) rows, and the TFTs 143c and 143d are the odd (1, 3, 5, ..., 479, 481) rows. It is provided corresponding to.
In the liquid crystal panel 100, the scanning lines 112 in the 1st to 480th rows are provided, but in the scanning line driving circuit 140, they correspond to dummy 0th and 481th rows. However, the 0th and 481th rows do not contribute to the vertical scanning of the liquid crystal panel 100 at all.

In the even-numbered row, the source electrode of the TFT 143a is in principle connected to the source electrode of the TFT 143d corresponding to the odd-numbered row one row before, and the drain electrodes of the TFTs 143a and 143b corresponding to the even-numbered row are connected to the even-numbered row. It is commonly connected to the input terminal of the buffer 144 corresponding to the line. Note that the source electrode of the TFT 143a corresponding to the first 0th row is exceptionally connected to the signal line 146 to which the start pulse Dy is supplied. The inverted clock signal / Cly is supplied to the gate electrode of the TFT 143a, and the clock signal Cly is supplied to the gate electrode of the TFT 143b.
On the other hand, the source electrode of the TFT 143c corresponding to the odd-numbered row is connected to the source electrode of the TFT 143b corresponding to the even-numbered row before the first row, and the drain electrodes of the TFTs 143c and 143d corresponding to the odd-numbered row are connected to the odd-numbered row. Commonly connected to the input terminal of the buffer 144 corresponding to the eyes. The clock signal Cly is supplied to the gate electrode of the TFT 143c, and the inverted clock signal / Cly is supplied to the gate electrode of the TFT 143d.

The output terminal of the buffer 144 corresponding to the even-numbered row has a connection point between the source electrode of the TFT 143b corresponding to the own row and the source electrode of the TFT 143c corresponding to the next row, and one of the input ends of the AND circuit 145 corresponding to the next row. , And the other input terminal of the AND circuit 145 corresponding to the own row.
On the other hand, the output end of the buffer 144 corresponding to the odd-numbered row is the connection point between the source electrode of the TFT 143d corresponding to the own row and the source electrode of the TFT 143a corresponding to the next row, and the input end of the AND circuit 145 corresponding to the next row. One is connected to the other input terminal of the AND circuit 145 corresponding to the own row. However, since the output terminal of the buffer 144 corresponding to the dummy 481 line does not have the next 482 line, the other of the source electrode of the TFT 143 d corresponding to the own line and the input terminal of the AND circuit 481 corresponding to the own line Only connected to.
Also, the signals output from the buffers 145 in the 0th, 1st, 2nd, 3rd,..., 480, 481 rows are denoted as N0, N1, N2, N3,.

In principle, the AND circuit 145 of each row inputs the output signal of the buffer 144 corresponding to the previous row to one of the input ends, and inputs the output signal of the buffer 144 corresponding to the own row to the other input end, The logical product signal of is output. However, since the AND circuit 145 corresponding to the first 0th row has no previous row, one input terminal is exceptionally connected to the signal line 146, and the start pulse Dy and the buffer corresponding to the 0th row are connected. A logical product signal with the output signal 144 is output.
Note that logical product signals (pulse signals) output from the AND circuits 145 in the 0th, 1st, 2nd, 3rd,... ,..., Y480, Y481 are output.

The operation of the scanning line driving circuit 140 having such a configuration will be briefly described.
When the clock signal Cly is at the L level corresponding to the low voltage VL of the power supply and the inverted clock signal / Cly is at the H level corresponding to the high voltage VH of the power supply, the TFT 143c is turned off (source- The drain electrode is in a non-conductive state), and the TFT 143d is turned on (the source / drain electrode is in a conductive state). For this reason, the buffer 144 in the odd-numbered row constitutes a holding circuit by connecting its output terminal to the input terminal. On the other hand, since the TFT 143a in the even row next to the odd row is turned on, the voltage state held by the buffer 144 in the odd row is also output from the buffer 144 in the even row next to the odd row. Become.
Next, when the clock signal Cly becomes H level (the inverted clock signal / Cly is L level), the TFT 143d is turned off, so that the holding operation by the buffer 144 in the odd-numbered row is released. In addition, since the TFT 143a is also turned off, the state where the output terminal of the odd-numbered buffer 144 preceding the even-numbered line is connected to the input terminal of the even-numbered buffer 144 is also released.
On the other hand, when the clock signal Cly is at the H level, the TFT 143b is turned on, and this time, the even-numbered buffer 144 constitutes a holding circuit and holds the previous voltage state. Since the TFT 143c is also turned on, the voltage state held by the even-numbered buffer 144 is also output from the buffer 144 in the odd-numbered row next to the even-numbered row.

As shown in FIG. 5, when the start pulse Dy is supplied prior to the start of the first field and the second field, the H level of the start pulse Dy becomes the L level (inverted clock signal / Cly). Is at the H level), the signal N0 that is the output of the buffer 144 at the 0th row is at the H level.
Next, when the clock signal Cly becomes H level, the TFTs 143b and 143c are turned on, so that the buffer 144 in the 0th row holds the H level state which is the previous voltage state and the voltage state is 1 row. Also output from the eye buffer 144. Therefore, the signal N1 becomes H level.
When the clock signal Cly becomes L level again, the L level portion of the start pulse Dy is captured when the TFT 143a in the 0th row is turned on, so that the signal N0 becomes L level. Further, since the TFTs 143a and 143d are turned on, the buffer 144 in the first row holds the H level state which is the previous voltage state, and the voltage state is output from the buffer 144 in the second row. Therefore, the signal N2 becomes H level.
Thereafter, such an operation is repeated every time the logic level of the clock signal Cly is inverted, so that the signals N1, N2, N3,..., N479, N480 sequentially delay the signal N0 by half a cycle of the clock signal Cly. It will be what you let.

The AND circuit 145 outputs a logical product signal of the output signal from the buffer 144 one row before the own row and the output signal from the buffer 144 of the own row as a scanning signal. For this reason, the scanning signal Y1 is an overlapping portion of the H level of the signal N1 and the H level of the signal N1, and hereinafter, the scanning signals Y2, Y3,..., Y479, Y480 are the scanning signal Y1 and the half cycle of the clock signal Cly. It will be the one that is made to sequentially.
In FIG. 5, a period F1a is a vertical effective scanning period of the liquid crystal panel 100 in the first field, and the scanning signal Y1 changes to H level by the start pulse Dy supplied prior to the start of the first field. Until the scanning signal Y480 changes to L level. The period F1b is a vertical blanking period of the liquid crystal panel 100 in the first field, and the start of the second field after the scanning signal Y480 changes to L level by the start pulse Dy supplied prior to the start of the first field. This is a period until the scanning signal Y1 is changed to the H level by the start pulse Dy supplied prior to.
Similarly, the period F2a is a vertical effective scanning period of the liquid crystal panel 100 in the second field, and the scanning signal Y1 changes to H level by the start pulse Dy supplied prior to the start of the second field. This is the period until Y480 changes to the L level. The period F2b is a vertical blanking period of the liquid crystal panel 100 in the second field, and after the scanning signal Y480 changes to L level by the start pulse Dy supplied prior to the start of the second field, This is a period until the scanning signal Y1 changes to the H level by the start pulse Dy supplied prior to the start of one field.

Next, for convenience of description, the configuration of the data line driving circuit 190 will be described with reference to FIG. FIG. 8 is a circuit diagram illustrating an example of the data line driving circuit 190.
As shown in this figure, the data line driving circuit 190 includes a sampling signal output circuit 192 and an n-channel TFT 194 provided for each data line 114. Further, the data signal Vid converted by the D / A conversion circuit 40 is supplied to the signal line 196.
The sampling signal output circuit 192 outputs sampling signals S1, S2, S3,..., S639, S640 corresponding to each column based on the start pulse Dx and the clock signal Clx supplied from the control circuit 20, respectively. .
The TFT 194 provided in each column has a source electrode connected to the signal line 196, a drain electrode connected to the data line 114 corresponding to the column, and a sampling signal corresponding to the column supplied to the gate electrode. . Therefore, when the sampling signal of a certain column becomes H level, the TFT 194 of the column is turned on, and the data signal Vid supplied to the signal line 196 is sampled on the data line 114 of the column.

FIG. 9 is a diagram showing waveforms of sampling signals S1, S2, S3,..., S639, S640 output by the sampling signal output circuit 192. As shown in FIG. Similar to the scanning line driving circuit 140, the sampling signal output circuit 192 sequentially transfers the start pulse Dx according to the clock signal Clx and outputs it as a sampling signal. Therefore, the sampling signals S1, S2, S3,..., S639, S640 are obtained by sequentially delaying the H level pulse corresponding to the half cycle of the clock signal Clx by the half cycle of the clock signal Clx.
FIG. 9 also shows an example of the voltage waveform of the data signal Vid supplied to the first field and the second field.
Since positive polarity writing is designated in the first field as shown in FIG. 3, as shown in FIG. 9, the data signal Vid in the first field is white from the voltage Vb (+) corresponding to black. In the range up to the voltage Vw (+) corresponding to, the voltage becomes higher than the voltage Vc as the designated gradation level becomes higher (brighter).
Further, since negative polarity writing is designated in the second field, the data signal Vid is designated within the range from the voltage Vb (−) corresponding to black to the voltage Vw (−) corresponding to white. As the gradation level becomes higher (brighter), the voltage becomes lower than the voltage Vc.

In such a configuration, when the i-th scanning line 112 is selected, that is, when the i-th scanning signal Y (i) becomes H level, the i-th scanning line 112 is connected to the gate electrode. All the TFTs 116 are turned on, and the pixel electrode 118 is electrically connected to the data line 114. Therefore, when the data signal Vid having a voltage corresponding to the gradation level is sampled on the data lines 114 in the first to 640th columns when the scanning signal Y (i) is at the H level, the data signal Vid is obtained. Is applied to the pixel electrode 118 via the TFT 116 which is turned on. When the scanning signal Y (i) becomes the L level, the TFT 116 is turned off, but the voltage applied to the pixel electrode 118 is held by the capacities of the liquid crystal capacitor 120 and the auxiliary capacitor 130.
Such an operation is executed in order from the first row to the 480th row in the first field, and for a certain one row, it is executed for the pixels from the first column to the 640th column. In the first field, a positive voltage corresponding to the gradation level is applied to each pixel electrode 118, so that each liquid crystal capacitor 120 has a transmittance corresponding to the applied / holding voltage.
Similarly, in the second field, the process is executed sequentially from the first line to the 480th line. In the second field, a negative voltage corresponding to the gradation level is applied to each pixel electrode 118, but the first field shows that each liquid crystal capacitor 120 has a transmittance corresponding to the applied / holding voltage. It is the same.
In one frame, a positive voltage corresponding to the gradation level is applied to the pixel electrode 118 in the first field, and a negative voltage corresponding to the same gradation level is applied to the pixel electrode 118 in the second field. Thus, AC driving of the liquid crystal capacitor 120 is completed in the one frame.

  By the way, it is desirable that the resistance between the source and drain electrodes when the TFT 116 is off, that is, the off-resistance is infinite and can be ignored. However, in the actual liquid crystal panel 100, the off-resistance cannot be ignored. For this reason, the voltage applied to the pixel electrode 118 when the TFT 116 is turned on gradually approaches the voltage LCcom over time due to leakage after the TFT 116 turns off, that is, the holding voltage of the liquid crystal capacitor 120 is In other words, a phenomenon occurs that decreases when viewed as an effective value. The direction of voltage change of the pixel electrode 118 due to leakage is downward after positive writing, and is upward after negative writing. Further, the leak amount (degree) is often different between positive polarity writing and negative polarity writing.

  The influence of this off-leak will be described with reference to FIG. This diagram is not an embodiment but a diagram showing off-leakage that occurs in the comparison configuration in which the capacitor lines 132 in the first to 480th rows, that is, the capacitor signals Com1 to Com480 are all kept constant at the voltage Vcom. This figure also shows the voltage change between the pixel electrode Pix (i, j) in the pixel 110 in the i row and j column and the pixel electrode Pix (i + 1, j) in the pixel 110 in the (i + 1) row and j column. It is also a figure shown in relation to scanning signals Y (i) and Y (i + 1) corresponding to each.

Here, when the scanning signal Y (i) becomes H level in the first field, a positive data signal corresponding to the gradation level of i row and j column is sampled on the data line 114 of the j column. It shall be. The voltage of the data signal at this time is Vj. If the scanning signal Y (i) is at the H level, the TFT 116 in the i row and the j column is turned on, so that the pixel electrode Pix (i, j) which is one end of the liquid crystal capacitor 120 has the voltage Vj as shown in FIG. become. Next, when the scanning signal Y (i) is changed from H to L level, the voltage of the pixel electrode Pix (i, j) is caused by field through when the TFT 116 in i row and j column changes from on to off. The voltage Vf decreases.
Here, field through refers to a phenomenon in which the potential of the pixel electrode 118 connected to the drain electrode changes due to the parasitic capacitance between the gate and drain electrodes of the TFT 116 when the TFT 116 turns from on to off. . This phenomenon is sometimes called “push-down” (when the TFT is an n-channel type), “push-through”, or the like. Further, the voltage change direction due to field through is a constant direction regardless of the write polarity, and if the TFT 116 is an n-channel type as in this embodiment, it is a downward direction. If the TFT 116 is a p-channel type, the direction of voltage change due to field through is an upward direction.

The voltage of the pixel electrode Pix (i, j) decreases by the voltage Vf due to the field through of the TFT 116 and then gradually decreases with time due to off-leakage of the TFT 116.
When the scanning signal Y (i) becomes H level in the second field, the pixel electrode Pix (i, j) becomes the voltage of the negative polarity data signal according to the gradation level of i row and j column. Next, when the scanning signal Y (i) changes from H to L level, the voltage of the pixel electrode Pix (i, j) rises due to the field through of the TFT 116, and further, due to off-leakage of the TFT 116. It will gradually rise over time.
In the next (i + 1) -th row, the operation is delayed by one horizontal scanning period (H) with respect to the i-th row.

Thus, when the holding voltage of the liquid crystal capacitor 120 is reduced due to off-leakage, it causes display unevenness and deterioration of the liquid crystal 105 due to application of a DC component.
Therefore, in the first embodiment, first, a configuration in which the decrease in the holding voltage of the liquid crystal capacitor 120 due to off-leakage is compensated for by the voltage change of the capacitor line 132 to reduce the influence of off-leakage. Here, the period during which the TFT 116 has an off-leakage is a period in which the scanning signal Y (i) is at the L level in the i-th row and the scanning in the (i + 1) -th row, as shown in FIG. Since this is a period in which the signal Y (i + 1) is at the L level, it differs for each row. For this reason, in order to uniformly reduce the influence of off-leakage for each row, the voltage of the capacitor line 132 must be changed for each row.
Thus, in the first embodiment, secondly, the unit circuit 170 is provided for each row in the capacitor line driving circuit 160, and the voltage to the corresponding capacitor line 132 is individually changed.

FIG. 6 is a circuit diagram showing a configuration of a unit circuit 170 for driving one row of capacitor lines 132 in the capacitor line driving circuit 160, and FIG. 7 is a diagram for explaining an operation in the unit circuit 170. It is a voltage waveform diagram. In FIG. 6 and FIG. 7, it is assumed that the unit circuit 170 corresponds to the i-th row.
First, as shown in FIG. 6, the unit circuit 170 includes a delay circuit 1702, a buffer 1704, a NOR circuit 1706, an inverter 1708, a T-FF (toggle flip-flop) 1710, and n-channel TFTs 1720 and 1722. 1724, 1726, 1730, 1732, 1734, 1736.
In the unit circuit 170 in the i-th row, the scanning signal Y (i) in the i-th row receives the delay circuit 1702, one input terminal of the NOR circuit 1706, and the inverted clock input terminal (CL) of the T-FF 1710. Are supplied to each.
The delay circuit 1702 delays the input signal by a time amount Ta, and supplies the delayed signal D (i) to the input terminal of the buffer 1704 and the other input terminal of the NOR circuit 1706, respectively. In the present embodiment, as will be described later, the time amount Ta is set to a time from when the scanning signal changes to the L level until the influence of coupling noise or the like due to the change becomes negligible. The output signal of the delay circuit 1702 is supplied to the common gate electrode of the TFTs 1722 and 1732 via the buffer 1704.
Here, since the buffer 1704 does not change the logic level of the output signal from the logic level of the input signal, the logic level of the signal output from the buffer 1704 is equated with the delay signal D (i) from the delay circuit 1702. .

  The NOR circuit 1706 obtains a negative logical sum signal of the scanning signal Y (i) and the delayed signal D (i) of the scanning signal Y (i), and uses the negative logical sum signal as the selection signal L in the i-th row. As (i), it is supplied to the gate electrode of the TFT 1726. The inverter 1708 outputs a signal obtained by inverting the logical level of the negative logical sum signal from the NOR circuit 1706, that is, a logical sum signal of the scanning signal Y (i) and the delay signal D (i), and a selection signal R ( i) is supplied to the gate electrode of the TFT 1736. Therefore, since the logic levels of the selection signals L (i) and R (i) are mutually exclusive, the TFTs 1726 and 1736 are turned off when one is turned on and turned off when the other is turned off. Is turned on.

  A reset signal Rst is supplied from the control circuit 20 to a toggle (T) input terminal of the T-FF 1710. The reset signal Rst is maintained at the H level after the power is turned on. For this reason, when the scanning signal Y (i) falls from the H level to the L level for the first time after the power is turned on, the normal output terminal Q of the T-FF 1710 changes to the H level, and thereafter the scanning signal Y (i) is changed. Each time the signal falls from the H level to the L level, the logic level output from the normal output terminal Q is inverted. Here, the output signal from the normal output terminal Q of the T-FF 1710 is supplied to the gate electrode of the TFT 1724 as the selection signal Sel (i) of the i-th row, and the output signal from the inverted output terminal / Q is supplied to the i-th row. The selection signal / Sel (i) is supplied to the gate electrode of the TFT 1734. Therefore, the TFTs 1724 and 1734 also have a relationship in which the other is turned off when one is turned on, and the other is turned on when one is turned off.

The source electrode of the TFT 1720 is connected to the power supply line of the high voltage VH of the power supply, and the drain electrode thereof is connected to the drain electrode of the TFT 1722 and the source electrode of the TFT 1724. For convenience, when the source electrode of the TFT 1724 (drain electrodes of the TFTs 1720 and 1722) is represented as a terminal Np, a capacitance Cp is parasitic on the terminal Np.
On the other hand, the source electrode of the TFT 1730 is connected to the power supply line of the lower voltage VL of the power source, that is, grounded, and the drain electrode thereof is connected to the drain electrode of the TFT 1732 and the source electrode of the TFT 1734. Similarly, when the source electrode of the TFT 1734 (drain electrodes of the TFTs 1730 and 1732) is expressed as a terminal Nm, a capacitance Cm is parasitic on the terminal Nm.
The gate electrode of the TFT 1720 and the gate electrode of the TFT 1730 are grounded to the power supply line of the voltage VL corresponding to the L level. For this reason, the TFT 1720 and the TFT 1730 are always off. The drain electrode of the TFT 1724 and the drain electrode of the TFT 1734 are commonly connected to the source electrode of the TFT 1726.

A voltage Vcom supplied from the outside is applied to each source electrode of the TFTs 1722, 1732, and 1736 in the unit circuit 170. For convenience, the connection point of the source electrodes of the TFTs 1722, 1732, and 17363 is defined as a terminal Nr.
In the unit circuit 170 in the i-th row, the drain electrodes of the TFTs 1726 and 1736 are connected to the capacitor line 132 in the i-th row.

The voltage of the capacitance signal Com (i) supplied to the i-th row capacitance line 132 is determined according to exclusive ON / OFF of the TFTs 1726 and 1736. More specifically, if the TFT 1736 is on, the voltage Vcom of the terminal Nr is obtained. If the TFT 1726 is on, the voltage of either the terminal Np or the terminal Nm is further controlled according to the exclusive on / off of the TFTs 1724 and 1734. It becomes.
In other words, since the source electrode of the TFT 1736 is connected to the terminal Nr and the source electrode of the TFT 1726 is connected to either the terminal Np via the TFT 1724 or the terminal Nm via the TFT 1734, the TFTs 1736 and 1726 are The terminal Nr (first terminal), or the terminal Np or the terminal Nm (second terminal) is selected and functions as the selector 172 connected to the capacitor line 132.

Next, whether one of the TFTs 1726 and 1736 is turned on is determined only by the scanning signal Y (i). Specifically, the selection signal R (i) becomes H level (the selection signal L (i) is L level), the TFT 1736 is turned on, and the TFT 1726 is turned off because the scanning signal Y (i) or the scanning signal Y A period when the delayed signal D (i) obtained by delaying (i) by the amount of time Ta is at the H level, that is, after the scanning signal Y (i) rises to the H level as shown in FIG. This is the period from when Y (i) falls to the L level until the time amount Ta has elapsed.
Note that during this period, the i-th capacitance line 132 is connected to the terminal Nr, and is denoted as “Nr” in FIG.

On the other hand, the selection signal R (i) becomes L level (the selection signal L (i) is H level), the TFT 1736 is turned off, and the TFT 1726 is turned on, that is, the scanning signal Y (i). Is a period from when the time Ta has fallen to the L level until the scanning signal Y (i) rises to the H level again.
In the period in which the TFT 1726 is turned on, either the TFT 1724 or 1734 is turned on as described above. Whether one of the TFTs 1724 and 1734 is turned on in this period is determined depending on whether the TFT is the first field or the second field, as will be described below.
In the T-FF 1710, as described above, the reset signal Rst supplied to the toggle (T) input terminal is maintained at the H level after the power is turned on, so that the scanning signal Y (i) is the H to L level for the first time after the power is turned on. The control signal Sel (i) becomes H level when the signal falls to H, and the logic level is inverted every time the scanning signal Y (i) falls from H to L level thereafter.
In writing scanning with respect to the liquid crystal panel 100, the first field is the first field and the second field is the second field. Therefore, when the scanning signal Yi) falls from the H level to the L level for the first time after the power is turned on, it is the first field, and when the scanning signal Y (i) falls from the H level to the L level next time, the second field. It is defined to be a field. Thereafter, this pattern is repeated.
For this reason, as shown in FIG. 7, the selection signal Sel (i) changes to the H level when the scanning signal Y (i) falls to the L level in the first field. When the scanning signal Y (i) falls to the L level again in the second field, it changes to the L level. On the contrary, the selection signal / Sel (i) changes to the L level when the scanning signal Y (i) falls to the L level in the first field, and thereafter, the scanning signal Y (( When i) falls to L level again, it changes to H level.

  Here, the voltages at the terminals Np and Nm will be described. When the delay signal D (i) becomes H level, the TFTs 1722 and 1732 are turned on, so that the voltage Vcom is set to the terminals Np and Nm, respectively. Thereafter, when the delay signal D (i) becomes L level, the TFTs 1722 and 1732 are turned off. The TFTs 1720 and 1730 are always off, but off-leakage occurs. For this reason, the terminal Np gradually rises from the set voltage Vcom as time elapses from the turning off of the TFT 1722 due to the off-leakage of the TFT 1720, and conversely, the terminal Nm takes time from the turning-off of the TFT 1732 due to the off-leaking of the TFT 1730. As time elapses, the voltage gradually falls from the set voltage Vcom.

Accordingly, the voltage of the capacitance signal Com (i) in the i-th row is as shown in FIG.
That is, the capacitance signal Com (i) is first turned on by turning on the TFT 1736 during a period from the time when the scanning signal Y (i) rises to H level in the first field until the time Ta falls after falling to L level. The voltage is fixed to Vcom. For this reason, in the selection period in which the scanning signal Y (i) is at the H level and the positive voltage is written to the pixel 110 in the i-th row, the capacitance line 132 in the i-th row does not vary from the voltage Vcom. In addition, the voltage is accurately written to the liquid crystal capacitor 120, and even if the coupling noise through the auxiliary capacitor 130 propagates to the capacitor line 132 at the time of writing, the influence does not affect the capacitor line. Yes.
Next, when the scanning signal Y (i) falls to the L level in the first field and the amount of time Ta has elapsed in the first field, the capacitance signal Com (i) is connected to the capacitance line 132 of the i-th row by turning on the TFTs 1724 and 1726. Since it is connected to Np, it gradually rises from the voltage Vcom over time. This voltage increase period is indicated as “Np” in FIG.
Subsequently, when the scanning signal Y (i) rises to the H level in the second field, the capacitance signal Com (i) becomes the voltage Vcom again when the TFT 1736 is turned on. Thereafter, the TFT 1736 continues to be on for a period until the scanning signal Y (i) falls to the L level and the time amount Ta elapses, so that the voltage Vcom is kept fixed.
When the scanning signal Y (i) falls to the L level in the second field and the amount of time Ta has elapsed in the second field, the capacitance signal Com (i) is connected to the terminal Nm by turning on the TFTs 1734 and 1726. Therefore, the voltage gradually decreases from the voltage Vcom over time. This voltage drop period is represented as “Nm” in FIG.
If the amount of time Ta is ignored, the capacitance signal Com (i) becomes the voltage Vcom when the scanning signal Y (i) is at the H level in the first field, and the scanning signal Y (i) is L. When the scanning signal Y (i) is at the H level in the second field, the voltage Vcom is increased again. When the scanning signal Y (i) is at the L level, the voltage Vcom gradually increases from the voltage Vcom. It will be descended to.

  The unit circuit 170 is actually provided corresponding to the first, second, third,. Therefore, the capacitance signals Com1, Com2, Com3,..., Com480 have voltage waveforms corresponding to the scanning signals Y1, Y2, Y3,.

  Next, an effect when the voltage of the capacitor line 132 is changed for each row in accordance with the scanning signal will be described with reference to FIG. FIG. 11 shows voltage changes between the pixel electrode Pix (i, j) in the pixel 110 in the i row and j column and the pixel electrode Pix (i + 1, j) in the pixel 110 in the (i + 1) row and j column, respectively. It is a figure shown in the relationship with the corresponding scanning signal Y (i) and Y (i + 1).

For comparison, an off-leakage voltage change indicated by a solid line in FIG. 19 is indicated by a broken line in FIG. Note that the operation in the scanning line selection period is the same as that in FIG. That is, if the scanning signal Y (i) is at the H level, the TFTs 116 in i rows and j columns are turned on, so that the pixel electrode Pix (i, j) which is one end of the liquid crystal capacitor 120 is as shown in FIG. Each voltage becomes Vj.
On the other hand, when the scanning signal Y (i) is at the H level, the TFT 1736 is turned on in the unit circuit 170 in the i-th row, so that the capacitance signal Com (i) in the i-th row becomes the voltage Vcom. On the other hand, in the first embodiment, the common electrode 108 is constant at the voltage LCcom regardless of the scanning signal Y (i). For this reason, the voltage (Vj−LCcom) is charged in the liquid crystal capacitor 120 in the i row and j column, and the voltage (Vj−Vcom) is charged in the auxiliary capacitor 130.
Note that when the scanning signal Y (i) changes from H to L level, the pixel electrode Pix (i, j) is applied only to the voltage Vf due to field through when the TFT 116 in the i row and j column changes from on to off. descend.

In the first embodiment, when the scanning signal Y (i) becomes L level in the first field, the TFT 1724 is turned on in the unit circuit 170 in the i-th row. Further, after the scanning signal Y (i) becomes L level and the time Ta passes, the TFT 1726 is turned on and the TFT 1736 is turned off in the unit circuit 170 in the i-th row, so that the voltage of the capacitance signal Com (i) is As shown in FIG. 11, the voltage gradually increases from the voltage Vcom over time. The increase change from the voltage Vcom in the capacitance signal Com (i) at this time is expressed as a function ΔV (t) of the elapsed time from the voltage change start timing.
The capacitance signal Com (i) gradually rises from the voltage Vcom over time, whereas the common electrode 108 is constant at the voltage LCcom, so that the charge stored in the liquid crystal capacitor 120 moves to the auxiliary capacitor 130. . Specifically, in the series connection of the liquid crystal capacitor 120 and the auxiliary capacitor 130 in the pixel 110, the other end (common electrode) of the liquid crystal capacitor 120 is maintained at a constant voltage, and the other end of the auxiliary capacitor 130 is ΔV from the voltage Vcom. Since it rises by (t), the voltage of the pixel electrode 118 also works in a direction to rise according to the capacitance ratio.
That is, the voltage of the pixel electrode Pix (i, j) which is the series connection point is
(Vj−Vf) + {Cs / (Cs + Cpix)} · ΔV (t)
It becomes.
Therefore, in the first embodiment, the increase in the voltage of the capacitance signal Com (i) is caused by the voltage (Vj−) in which the voltage of the pixel electrode Pix (i, j) is decreased by the field-through voltage Vf from the voltage Vj of the data signal. Starting from Vf), the voltage change ΔV (t) of the capacitance line 132 in the i-th row is multiplied by the capacitance ratio {Cs / (Cs + Cpix)} (to gradually increase with time). become.
On the other hand, the off-leakage of the TFT 116 when the scanning signal Y (i) is at the L level in the first field gradually increases with time from the voltage (Vj−Vf) of the pixel electrode Pix (i, j). It is made to act in the direction to descend.

As a result, in the first embodiment, when the scanning signal Y (i) becomes L level in the first field, the effect of the voltage increase of the capacitance line 132 in the i-th row is the voltage decrease due to off-leakage in the pixels in the i-th row and j-th column. This cancels the action of. Therefore, according to the first embodiment, the pixel electrode Pix (i, j) has almost zero voltage fluctuation after the scanning signal Y (i) changes to the L level as shown by the solid line in FIG. Therefore, voltage fluctuation due to off-leakage as shown by a broken line can be suppressed.
In the second field, except for field through, the direction of voltage change is opposite to that of the first field. Specifically, in the pixel in i row and j column, when the scanning signal Y (i) becomes L level in the second field, the voltage drop of the i-th capacitance line 132 and the voltage rise due to off-leakage cancel each other. Therefore, similarly, voltage fluctuation due to off-leakage can be suppressed.
In the first embodiment, the capacitance signal Com (i + 1) is i rows in the (i + 1) th row except that the capacitance signal Com (i + 1) is delayed by one horizontal scanning period (H) with respect to the capacitance signal Com (i). An operation similar to that of the eye is performed. In addition, here, the i-th row and the (i + 1) -th row have been representatively described, but the processing is executed in the order of the 1st to 480th rows in each of the first field and the second field.

As described above, according to the first embodiment, the decrease in the holding voltage of the liquid crystal capacitor 120 due to the off-leakage of the TFT 116 after the positive polarity writing in the first field is caused by the voltage increase due to the capacitance line 132 and in the second field. After the negative writing, the decrease in the holding voltage of the liquid crystal capacitor 120 due to the off-leakage of the TFT 116 is offset by the voltage drop by the capacitor line 132. For this reason, it is possible to suppress the influence due to the off-leakage of the TFT 116.
In addition, the voltage change of the capacitor line is not pulse-like, but is given to change gradually with time. Therefore, the capacitance component and the resistance component in the pixel cause a bias depending on the vertical and horizontal positions of the pixel. The phenomenon is suppressed.

  By the way, the voltage change due to field-through is in the downward direction in the case of the n-channel TFT 116 regardless of the write polarity. On the other hand, in the first embodiment, compensation is made so that the voltage fluctuation due to off-leakage becomes substantially zero. For this reason, when the voltage LCcom of the common electrode 108 is set slightly lower than the voltage reference Vc as shown in FIG. 11 so as to cancel the voltage change due to field through, the liquid crystal capacitance is obtained by positive writing. The effective voltage value applied to 120 and the effective voltage value applied to the liquid crystal capacitor 120 by negative-polarity writing can be made substantially equal to suppress the occurrence of flicker or so-called burn-in phenomenon due to the application of a DC component. It becomes.

However, in the actual liquid crystal panel 100, the factors that cause the holding voltage of the liquid crystal capacitor 120 to fluctuate during the non-selection period include the polarity difference between the element substrate and the counter substrate, the liquid crystal 105 Examples thereof include a resistance component possessed by itself. Further, the field through occurs not only in the TFT 116 but also in the TFT 194 that samples the data signal on the data line 114.
Therefore, it is desirable to determine the voltage change characteristic of the capacitor line 132 so as to cancel out the variation in the holding voltage of the liquid crystal capacitor 120 due to these factors. For example, the off-leakage characteristics of the TFT 1720 and the capacitance added to the terminal Np may be determined so as to cancel out fluctuations due to off-leakage and field through after positive polarity writing. Further, a voltage other than the voltage VH may be applied to the source electrode of the TFT 1720. On the other hand, the off-leakage characteristics of the TFT 1730 and the capacitance added to the terminal Nm may be determined so as to cancel the fluctuation after the negative polarity writing. Similarly, a voltage other than the voltage VL may be applied to the source electrode of the TFT 1730.
As described above, in the first embodiment, the characteristic for canceling the fluctuation of the holding voltage after the positive polarity writing and the characteristic for canceling the fluctuation of the holding voltage after the negative polarity writing are individually set. Therefore, highly accurate compensation is possible.

Furthermore, according to the first embodiment, after the scanning signal falls from the H level to the L level (strictly speaking, when the scanning signal falls to the L level and only the amount of time Ta has elapsed), the scanning signal is then set to the H level. The operation of changing the voltage of the capacitor line over a period until it rises to is performed for each row by the unit circuit 170 provided for each capacitor line. For this reason, the period for offsetting the decrease in the holding voltage due to the off-leakage of the TFT 116 is a period from the selection of the scanning line in each row to the selection of the scanning line again, and is aligned over each row. . Therefore, in the first embodiment, it is possible to suppress display unevenness in which the brightness varies depending on the scanning line position on the screen, for example.
In addition, since one unit circuit 170 is configured to drive one row of capacitor lines 132, the driving load in the unit circuit 170 may be smaller than the configuration in which a plurality of capacitor lines 132 are simultaneously driven. .

  In addition, the unit circuit 170 has a configuration in which the voltage of the capacitor line 132 is changed by changing the set voltage Vcom using the off leakage of the TFTs 1720 and 1730 that are always off. For this reason, when the TFTs 1720 and 1730 are designed so that the off-leak characteristics of the TFTs 1720 and 1730 simulate the off-leak characteristics of the TFT 116 of the pixel 110, the decrease in the holding voltage of the liquid crystal capacitor 120 due to the off-leak of the TFT 116 is caused by the capacitance line 132. It becomes possible to cancel with high accuracy by increasing the voltage.

  In the unit circuit 170, in the i-th row, when the scanning signal Y (i) changes from H to L level and the time Ta passes, the common signal Com (i) is changed from the voltage Vcom. It is changing. Here, when the voltage change of the common signal Com (i) is started at the same time when the scanning signal Y (i) changes to the L level, the coupling noise due to the voltage change of the scanning line 112 is caused by the capacitance line 132. May affect voltage. For this reason, in the first embodiment, it is considered that the coupling noise due to the voltage change of the scanning line 112 has sufficiently converged when the scanning signal Y (i) changes to the L level and the time amount Ta elapses. When this is done, the voltage change of the common signal Com (i) is started. With this configuration, in the first embodiment, it is possible to avoid the coupling noise due to the voltage change of the scanning line 112 from adversely affecting the voltage of the capacitor line 132.

In the first embodiment, the capacitor lines 132 are driven one row at a time. However, a plurality of rows of capacitor lines 132 or all the capacitor lines 132 may be driven all at once. Specifically, the voltage of the capacitor lines of the plurality of rows may be changed in the same manner after the selection of the scanning lines of the plurality of rows, or after the selection of all the scanning lines, that is, in the vertical blanking period, The voltage of the capacitor line may be changed in the same way.
However, in the configuration in which the plurality of rows of capacitor lines 132 are driven together, there is a difference in the canceling of the holding voltage as seen between the plurality of rows, and in the configuration in which all the capacitor lines 132 are collectively driven, The difference in canceling the holding voltage between the first line and the last line 480 becomes large, and display unevenness in which the brightness varies depending on the scanning line position on the screen is likely to occur.
However, if the reading from the memory 30 is accelerated and the ratio of the vertical blanking period to the vertical effective scanning period is increased, such a difference can be alleviated and the occurrence of the display unevenness can be suppressed.

  In the first embodiment, in the unit circuit 170 of each row, the logic level of the output signal of the T-FF 1710 is inverted every time the scanning signal falls for the first field or the second field. One of the TFTs 1724 and 1734 is turned on. The present invention is not limited to this configuration, and as a configuration for supplying a signal for discriminating between the first field and the second field from outside the unit circuit 170, for example, from the control circuit 20, the TFT 1724, 1734 may be exclusively turned on.

In the first embodiment, the surface inversion method is used in which all the pixels 110 are driven to have positive polarity in the first field and negative polarity in the second field. However, the lines that invert the polarity for each row of the scanning lines 112 are used. An inversion method may be used, or a dot inversion method in which the polarity is inverted for each row of the scanning lines 112 and each column of the data lines 114 may be used.
Here, for example, in the first field, one line of odd-numbered pixels is driven to have a positive polarity, and one pixel of even-numbered rows is driven to have a negative polarity, and the line inversion method for inverting the writing polarity in the second field; In this case, the logic level of the polarity designation signal Pol is changed in accordance with the respective polarities, and the unit circuit 170 of the odd-numbered row is made the same as that of the first embodiment in the capacitor line driving circuit 160. The selection signal supplied to the gate electrode of the TFT 1724 and the gate electrode of the TFT 1734 may be replaced.
Further, when the dot line inversion method is used, the following configuration may be used. That is, first, a total of two first and second capacitance lines are provided for one scanning line 112, and a unit circuit 170 is provided for each of the first and second capacitance lines. Provide separately. Second, the first capacitance lines are associated with the odd-numbered and odd-numbered columns and the even-numbered and even-numbered columns of pixels 110, and the odd-numbered and even-numbered columns and the even-numbered and odd-numbered columns of pixels 110 are associated with the second capacitance lines. Third, in the first field, the odd-numbered and odd-numbered columns and pixels in the even-numbered and even-numbered columns are driven to positive polarity, and the odd-numbered and even-numbered columns and pixels in the even-numbered and odd-numbered columns are driven to negative polarity. In the case of inverting the input polarity, the logic level of the polarity designation signal Pol is changed in accordance with each polarity, and each row is determined by the unit circuit of the odd row when the line inversion method is used for the first capacitance line. A configuration may be adopted in which the capacitance signal is supplied and the capacitance signal is supplied to the second capacitance line by the unit circuit in the even-numbered row when the line inversion method is used.
In this configuration, the direction of voltage change with respect to the first capacitance line is an ascending direction in the first field, and the direction of voltage change with respect to the second capacitor line is reversed in the first field. Direction, going up in the second field. Here, for example, the voltage change direction with respect to the first capacitance line is fixed in the rising direction in the first field and the second field, respectively, and the voltage change direction with respect to the second capacitance line is set in the downward direction in each of the first field and the second field In addition, a switch (or a selector) that selects one of the capacitor lines in accordance with the polarity may be provided for each pixel 110.

Second Embodiment
Next, an electro-optical device according to a second embodiment of the invention will be described. FIG. 12 is a block diagram illustrating an overall configuration of the electro-optical device 10b according to the second embodiment. The electro-optical device 10b shown in this figure is different from the electro-optical device 10a according to the first embodiment shown in FIG. 1 mainly in the following points.
That is, in order to cancel the holding voltage change of the liquid crystal capacitor 120, the electro-optical device 10a according to the first embodiment has a configuration in which the voltage of the capacitor line 132 provided for each row is changed during the non-selection period. On the other hand, in the electro-optical device 10b according to the second embodiment, the second embodiment is different from the first embodiment in that the common common electrode 108 is changed in voltage during the vertical blanking period of each field over each row. Is different.

  Due to this difference, in the second embodiment, a common electrode driving circuit 200 is provided instead of the capacitor line driving circuit 160 in the first embodiment. The common electrode driving circuit 200 supplies a common signal Vcn to the common electrode 108. Details will be described later.

In the second embodiment, while the circuit configuration of the pixels 110 is changed, the control lines 134 are provided along the row direction so as to be paired with the scanning lines 112, and the control lines 134 are controlled. An auxiliary capacitance control circuit 180 is provided.
Among these, the auxiliary capacitance control circuit 180 supplies auxiliary capacitance control signals Shz1, Shz2, Shz3,..., Shz480 to the control lines 134 provided corresponding to the 1, 2, 3,. Is. In the second embodiment, the auxiliary capacitance control circuit 180 has only a function of buffering and outputting the set signal Set supplied from the control circuit 20. Further, in the second embodiment, the capacitance line 132 in the first to 480th rows is configured to be applied with a constant temporally voltage Vcom from the outside. Further, the dummy scanning signal Y481 that is not used in the first embodiment is supplied to the common electrode driving circuit 200 in the second embodiment.

Here, for convenience of explanation, the configuration of the pixel 110 in the second embodiment will be described with reference to FIG. FIG. 13 is a diagram illustrating an equivalent circuit of the pixel 110 according to the second embodiment. Like FIG. 2, the intersection of the i-th row and the (i + 1) -th row with the j-th column and the (j + 1) -th column is illustrated. A corresponding 2 × 2 configuration of a total of four pixels is shown.
The pixel 110 shown in FIG. 13 is different from the configuration shown in FIG. 2 in that a TFT 136 is electrically interposed between the other end of the auxiliary capacitor 130 and the capacitor line 132. Here, as a representative example, what is located in the i row and j column, in the pixel 110 in the i row and j column, the gate electrode of the n-channel TFT 136 is connected to the control line 134 in the i row. The one end electrode (either the source electrode or the drain electrode) is connected to the other end of the auxiliary capacitor 130, and the other end electrode (the other one of the source electrode or the drain electrode) is connected to the i-th capacitor line 132. It is connected.
Accordingly, in the second embodiment, the other end of the auxiliary capacitor 130 is connected to the capacitor line 132 when the TFT 136 is on, and is not electrically connected to any part when the TFT 136 is off. become.
In FIG. 13, Shz (i) and Shz (i + 1) indicate auxiliary capacitance control signals supplied to the capacitance lines 132 in the i and (i + 1) th rows, respectively.

Next, the common electrode drive circuit 200 in the second embodiment will be described. FIG. 14 is a circuit diagram showing the configuration of the common electrode driving circuit 200, and FIG. 15 is a voltage waveform diagram for explaining the operation of the common electrode driving circuit 200.
In the first embodiment, the unit circuit 170 is provided for each capacitor line 132. However, since the common electrode 108 is common to the pixels 110 in each row in the second embodiment, only one common electrode driving circuit 200 is provided. Is provided.
Therefore, in FIGS. 14 and 15, unlike the unit circuit 170, the symbol “(i)” for specifying a row is not given to the selection signal.

As shown in FIG. 14, the scanning signal Y480 for the final 480th row and the scanning signal Y481 for the dummy 481st row are supplied from the scanning line driving circuit 140 to the common electrode driving circuit 200. A reset signal Rst similar to that in the first embodiment and a new set signal Set are supplied from the control circuit 20.
Here, the common electrode driving circuit 200 is different from the unit circuit 170 shown in FIG. 6 in that a scanning signal Y480 is supplied to the inverted clock input terminal of the T-FF 1710, and secondly, A delay signal D480 obtained by delaying the scanning signal Y480 by the amount of time Ta by the delay circuit 1702 is supplied to the gate electrodes of the TFTs 1722 and 1732. Third, a selection signal for each of the gate electrodes of the TFTs 1726 and 1736. The fourth circuit is a RS-FF (Reset Set Flip-Flop) 1750 and a fourth point is that the voltage LCcom is supplied to the terminal Nr.

Therefore, these differences will be mainly described.
First, the scanning signal Y480 is supplied to the inverted clock input terminal of the T-FF 1710. Therefore, the selection signal Sel output from the normal output terminal Q of the T-FF 1710 is, as shown in FIG. 15, when the scanning signal Y480 falls to the L level in the first field, that is, the last 480th row. When the selection of the scanning line 112 is completed and the vertical blanking period F1b starts, it changes to the H level, and thereafter, when the scanning signal Y480 falls again to the L level in the next second field, that is, the vertical level. When the blanking period F2b starts, the level changes to L level. Conversely, the selection signal / Sel output from the inverting output terminal / Q of the T-FF 1710 changes to the L level when the scanning signal Y480 falls to the L level in the first field, and then the next second When the scanning signal Y480 falls to L level again in two fields, it changes to H level.
If the delay signal D480 is H level in the first field and the second field, the TFTs 1722 and 1732 are turned on, and the terminals Np and Nm are set to the voltage LCcom, respectively.

Next, the delay circuit 1740 delays the scanning signal Y481 by the amount of time Ta and supplies it as a delay signal D481 to the reset input terminal (R) of the RS-FF 1750. The inverter 1742 inverts the logic level of the set signal Set and supplies the inverted signal / Set to the set input terminal (S) of the RS-FF 1750. The RS-FF 1750 supplies the output signal from the normal output terminal Q to the gate electrode of the TFT 1736 as the selection signal R, and supplies the output signal from the inverted output terminal / Q to the gate electrode of the TFT 1726 as the selection signal L.
The RS-FF 1750 resets the normal output terminal Q to L level (inverted output terminal / Q to H level) when the delay signal D481 supplied to the reset input terminal (R) changes from L to H level. When the signal / Set supplied to the set input terminal (S) changes from L to H level, the normal output terminal Q is set to H level (inverted output terminal / Q is set to L level).
Here, as shown in FIG. 16, the control circuit 20 outputs the set signal Set as an L level pulse immediately before the start of the first field and the second field. Therefore, as shown in FIG. 15, the inversion signal / Set becomes an H level pulse immediately before the end of the vertical blanking periods F1b and F2b.

Therefore, the selection signal R is generated from the timing at which the inverted signal / Set becomes H level immediately before the scanning signal Y1 becomes H level as the first field (X timing in the drawing). It changes to H level and becomes H level over the period until time amount Ta passes. In a period in which the selection signal R is at the H level, the TFT 1726 is turned off and the TFT 1736 is turned on. As a result, the common electrode 108 is connected to the terminal Nr, so that the common signal Vcn is fixed to the voltage LCcom.
Next, the selection signal L becomes the H level over the period from when the scanning signal Y480 changes from H to the level in the first field and the time Ta passes, until the inversion signal / Set becomes the H level. Therefore, the TFT 1726 is turned on. Further, when the scanning signal Y480 falls in the first field, the selection signal Sel becomes H level. Therefore, the TFT 1724 is turned on. Therefore, as a result of connecting the common electrode 108 to the terminal Np, the common signal Vcn gradually rises with time from the set voltage LCcom.

Subsequently, the selection signal R is the second field after the inversion signal / Set becomes H level immediately before the scanning signal Y1 becomes H level, and the scanning signal Y480 changes from H to level in the second field. It becomes the H level over the period until the amount Ta passes. For this reason, the common signal Vcn is fixed to the voltage LCcom again.
Next, the selection signal L is at the H level over the period from the time when the scanning signal Y480 changes from H to the level in the second field and the time Ta passes, until the inversion signal / Set becomes the H level. become. Therefore, the TFT 1726 is turned on. Further, when the scanning signal Y480 falls in the second field, the selection signal / Sel becomes H level. Therefore, this time, the TFT 1734 is turned on. Therefore, as a result of the common electrode 108 being connected to the terminal Nm, the common signal Vcn gradually decreases with time from the voltage LCcom.

For this reason, as shown in FIG. 16, the common signal Vcn is fixed to the voltage LCcom in the vertical effective scanning period F1a of the first field, and gradually rises with time from the voltage LCcom in the vertical blanking period F1b. The voltage waveform is fixed to the voltage LCcom again in the vertical effective scanning period F2a of the second field, and gradually decreases from the voltage LCcom over time in the vertical blanking period F2b.
Since the amount of time Ta is negligibly small, in FIG. 16 (and FIG. 17), the common signal Vcn is described as changing from the voltage LCcom when the scanning signal Y480 becomes L level.

Next, the effect of changing the voltage of the common electrode 108 during the vertical blanking period will be described with reference to FIG. FIG. 17 shows the pixel electrode Pix (1, j) corresponding to the first row and the jth column and the pixel electrode Pix (480, j) corresponding to the last 480th row and the jth column. It is a figure which shows a voltage change in the relationship with the scanning signals Y1 and Y480 corresponding to each.
When the scanning signal Y1 corresponding to the first row in the first field becomes H level, the positive voltage Vj of the data signal Xj is applied to the pixel electrode Pix (1, j) in the 1st row and jth column by turning on the TFT 116. Is applied. When the scanning signal Y1 changes from H to L level, the pixel electrode Pix (1, j) is lowered by the voltage Vf due to field through when the TFT 116 changes from on to off.
Such a positive voltage writing operation is performed for the pixels 110 in the second, third, fourth,..., 479th rows when the scanning signals Y2, Y3, Y4,.
However, in the second embodiment, the capacitance line 132 of each row is constant at the voltage Vcom, and the voltage of the pixel electrode does not change unless the common electrode 108 reaches the vertical blanking period. In other words, after the corresponding scanning signal has changed to L level, it gradually decreases due to off-leakage.
When the scanning signal Y480 corresponding to the last row in the first field becomes H level, the pixel electrode Pix (480, j) becomes the positive voltage of the data signal Xj by turning on the TFT. When the scanning signal Y480 changes from H to L level, the pixel electrode Pix (480, j) drops by the voltage Vf due to field through.

Here, when the scanning signal Y480 becomes L level and the time Ta passes, the common signal Vcn starts to rise from the voltage LCcom.
In the second embodiment, since the capacitor line 132 is constant at the voltage Vcom, in the series connection of the liquid crystal capacitor 120 and the auxiliary capacitor 130 in each pixel 110, the other end of the auxiliary capacitor 130 is kept constant. The common electrode 108 which is the other end of the liquid crystal capacitor 120 rises from the voltage Vcom.
Let Vk be the voltage of the pixel electrode at the voltage change start timing of the common signal Vcn, that is, the timing when the scanning signal Y480 becomes L level and the time Ta passes. In addition, when the change in the common signal Vcn from the voltage Vcom is a function ΔV (t) of the elapsed time from the voltage change start timing of the common signal Vcn, the voltage of the pixel electrode 118 is
Vk + {Cpix / (Cs + Cpix)}. ΔV (t)
It can be expressed as.
For this reason, in the second embodiment, the voltage increase of the common signal Vcn is the value obtained by multiplying the voltage of the pixel electrode 118 by the voltage change ΔV (t) of the common signal by the capacitance ratio {Cpix / (Cs + Cpix)}. It will act in the direction of increasing gradually over time.
On the other hand, the off-leakage of the TFT 116 in the first field acts in a direction in which the voltage of the pixel electrode gradually decreases with time.
Eventually, in the second embodiment, the voltage increase of the common electrode 108 in the vertical blanking period F1b of the first field cancels the voltage decrease due to off-leakage. Therefore, according to the second embodiment, as shown by the solid line in FIG. 17, the voltage fluctuation of the pixel electrode is compensated so as to become substantially zero in the vertical blanking period F1b. The voltage fluctuation due to can be suppressed.

By the way, immediately before the end of the vertical blanking period F1b, that is, immediately before the scanning signal Y1 becomes H level, when the set signal Set becomes L level, the inverted signal / Set becomes H level, so the common signal Vcn becomes the voltage LCcom. Return to. At this time, in each pixel 110, since the TFT 136 is turned off, the other end of the auxiliary capacitor 130 is electrically disconnected from the capacitor line 132 to be in a high impedance state. For this reason, even if the common electrode 108 changes from the voltage increasing process to the voltage LCcom, the holding voltage of the liquid crystal capacitor 120 is not affected. However, as the common electrode 108 changes to the voltage LCcom, the voltage of the pixel electrode also decreases.
In the second field, the direction of voltage change due to off-leakage is opposite to that of the first field. In the vertical blanking period F2b of the second field, the common electrode 108 gradually decreases with the passage of time from the voltage LCcom, thereby canceling the voltage increase due to off-leakage. For this reason, even in the vertical blanking period F2b, it is possible to compensate for the voltage fluctuation of the pixel electrode to be almost zero, and to suppress the voltage fluctuation due to off-leakage.

As described above, according to the second embodiment, the decrease in the holding voltage of the liquid crystal capacitor 120 due to the off-leakage is the voltage increase of the common electrode 108 in the vertical blanking period F1b in the first field in which the positive voltage is written. In addition, in the second field in which a negative voltage is written, each is canceled by the voltage drop of the common electrode 108 in the vertical blanking period F2b. For this reason, it is possible to suppress the influence due to the off-leakage of the TFT 116.
In addition, since the voltage change of the common electrode is not pulsed but is given to change gradually with time, the capacitance component and resistance component in the pixel cause a deviation depending on the vertical and horizontal positions of the pixel. The phenomenon is also suppressed.

By the way, in the first embodiment, since the voltage of the capacitor line 132 is changed for each row in accordance with the scanning signal corresponding to the row, the period for offsetting the decrease in the holding voltage due to the off-leakage is in each row. In each of them, a period from when the selection of the scanning line is completed until the scanning line is selected again is aligned over each row.
On the other hand, in the second embodiment, since the voltage of the common electrode 108 common to all the pixels 110 is changed in the vertical blanking period, a period in which the decrease in the holding voltage is offset with respect to the non-selection period. The relative position occupied differs from line to line. For example, in the first pixel of the first row, after the selection of the first row is completed, the voltage of the common electrode changes after the selection of the second to 480th rows is completed. It occupies on the rear end side with respect to the non-selection period. On the other hand, in the last pixel in the 480th row, the voltage of the common electrode changes immediately after the selection is completed. Therefore, the period for canceling the decrease in the holding voltage occupies the front end side with respect to the non-selection period.
As described above, in the second embodiment, since the time from when the TFT 116 is turned off to when the voltage change of the common electrode starts is different for each row, a difference also occurs in the progress of off-leakage. For this reason, in the second embodiment, display unevenness in which the brightness varies depending on the scanning line position on the screen is likely to occur as compared with the first embodiment.
However, also in the second embodiment, as in the case where all the capacitance lines 132 are collectively driven, if the reading from the memory 30 is accelerated and the ratio of the vertical blanking period to the vertical effective scanning period is increased, Such display unevenness can be suppressed. Furthermore, in the second embodiment, since one common electrode driving circuit 200 drives the common electrode 108, compared with the capacitive line driving circuit 160 of the first embodiment having the unit circuit 170 for each row, The configuration is simplified.

Also in the second embodiment, the voltage change characteristics of the common electrode 108 are set individually for the positive polarity and the negative polarity so as to cancel not only the off-leak but also the variation in the holding voltage of the liquid crystal capacitor 120 due to the field through. This is desirable as in the first embodiment.
By the way, the configuration of the pixel 110 in the second embodiment (see FIG. 13) is the same as that in FIG. 5 of JP-A-2009-75300. For this reason, in order to cancel the field through of the TFT 116 and the TFT 194, the technique described in the publication can be used. On the other hand, off-leakage may be canceled by a voltage change of the common electrode. To achieve such a configuration, the auxiliary capacitance control circuit 180 is supplied with scanning signals Y1 to Y480 together with the set signal Set, and the auxiliary capacitance control signals Shz1 to Shz480 are individually generated from these logic levels. It ’s fine.

In each of the first and second embodiments described above, one frame is divided into the first field and the second field, and the positive polarity writing and the negative polarity writing are executed, respectively. Is divided into an even number of fields of 4 or more, for example, and positive polarity writing and negative polarity writing may be executed alternately. Further, the positive polarity writing and the negative polarity writing may be executed alternately for each of an odd frame and an even frame without dividing the field. In any case, the number of scanning line selections is counted by the T-FF 1710, and the capacity line 132 or the common electrode 108 is offset in accordance with the odd number or even number of the count result so as to cancel off-leakage after positive polarity writing. Any configuration that selects whether to increase the voltage or to decrease the voltage so as to cancel off-leakage after negative polarity writing may be used.
Further, the capacitor line driver circuit 160 and the auxiliary capacitor control circuit 180 may be provided on the side opposite to the scanning line driver circuit 140.
In any of the first and second embodiments described above, the liquid crystal capacitor 120 is not limited to the transmissive type, but may be a reflective type. Furthermore, the liquid crystal capacitor 120 is not limited to the normally black mode, but may be a normally white mode in which the liquid crystal capacitor 120 is in a white state when no voltage is applied, for example, as a TN method.

<Electronic equipment>
Next, a projector will be described as an example of an electronic apparatus to which the electro-optical devices 10a and 10b according to the above-described embodiments are applied. FIG. 18 is a plan view showing the configuration of the projector.
As shown in this figure, a projector 2100 is provided with a lamp unit 2102 made of a white light source such as a halogen lamp. The projection light emitted from the lamp unit 2102 is provided with three primary colors of R (red), G (green), and B (blue) by three mirrors 2106 and two dichroic mirrors 2108 disposed therein. And led to the light valves 100R, 100G and 100B corresponding to the respective primary colors. Note that B light has a longer optical path than other R and G colors, and therefore, in order to prevent the loss, B light passes through a relay lens system 2121 including an incident lens 2122, a relay lens 2123, and an exit lens 2124. Led.

In the projector 2100, three sets of electro-optical devices according to the embodiment are provided corresponding to each of the R color, the G color, and the B color. Then, the video data corresponding to each of the R color, G color, and B color is supplied from the upper circuit and converted into the data signal Vid corresponding to each color. The configuration of the light valves 100R, 100G, and 100B is the same as that of the liquid crystal panel 100 described above, and is driven according to video data corresponding to each of the R color, G color, and B color.
The lights modulated by the light valves 100R, 100G, and 100B are incident on the dichroic prism 2112 from three directions. In the dichroic prism 2112, the R and B light beams are refracted at 90 degrees, while the G light beam travels straight. Therefore, after the images of the respective colors are combined, a color image is projected onto the screen 2120 by the projection lens 2114.

  Since light corresponding to each of the R, G, and B colors is incident on the light valves 100R, 100G, and 100B by the dichroic mirror 2108, there is no need to provide a color filter. In addition, the transmission images of the light valves 100R and 100B are projected after being reflected by the dichroic prism 2112, whereas the transmission image of the light valve 100G is projected as it is, so the horizontal scanning direction by the light valves 100R and 100B is The image is reversed in the horizontal scanning direction by the light valve 100G and displayed in an inverted image.

  Note that examples of the electronic device include an electronic viewfinder, a rear projection type television, a head mounted display, and the like in addition to the projector described with reference to FIG.

10a, 10b ... electro-optical device, 20 ... control circuit, 30 ... memory, 40 ... D / A conversion circuit, 100 ... liquid crystal panel, 105 ... liquid crystal, 108 ... common electrode, 110 ... pixel, 112 ... scanning line, 114 ... Data line 116... TFT 118. Pixel electrode 120. Liquid crystal capacitor 130 130 Auxiliary capacitor 132 Capacitor line 140 Scan line driver circuit 160 Capacitor line driver circuit 170 Unit circuit 172 Selector 190 ... data line driving circuit, 200 ... common electrode driving circuit, 2100 ... projector

Claims (9)

Scanning lines;
A transistor electrically connected to the scan line;
A drive circuit of an electro-optical device comprising an auxiliary capacitor provided in a pixel corresponding to the transistor,
A scanning line driving circuit for selecting the scanning line;
A predetermined potential is supplied to the capacitor line electrically connected to the auxiliary capacitor during the scanning line selection period, and the gray level of the pixel is not changed during the non-selection period of the scanning line. A drive circuit for an electro-optical device, comprising: a capacitive line drive circuit that changes a potential of the capacitive line. 2. The capacitor line driving circuit according to claim 1, wherein the capacitor line drive circuit changes the potential of the capacitor line in a direction in which an absolute value of a potential difference from the predetermined potential increases in a non-selection period of the scanning line. Drive circuit for electro-optical device. The electro-optical device includes:
A second scanning line, a second transistor electrically connected to the second scanning line, and a second auxiliary capacitor provided in the second pixel corresponding to the second transistor,
The scanning line driving circuit selects the second scanning line following the scanning line,
The capacitor line driving circuit supplies a predetermined potential to the second capacitor line electrically connected to the second auxiliary capacitor during the selection period of the second scan line, and non-selects the second scan line. 3. The drive circuit of the electro-optical device according to claim 1, wherein the potential of the second capacitor line is changed so that the gradation of the second pixel does not change during the period. The capacitor line driving circuit includes:
4. The change from the predetermined potential to the capacitor line is started when a predetermined time elapses after the selection of the scanning line is finished. 5. Drive circuit for electro-optical device. The capacitor line driving circuit includes:
A selector that is provided for the capacitor line and selects either the first terminal or the second terminal;
When the first terminal is selected from the start of the selection of the scanning line until the predetermined time has elapsed after the selection of the scanning line is completed, and when a predetermined amount of time has elapsed after the selection of the scanning line is completed Select the second terminal from
The predetermined potential is applied to the first terminal,
The off-state transistor is connected to the second terminal, and the predetermined potential is set until a predetermined time elapses after selection of the scanning line is completed. Drive circuit for the electro-optical device. The capacitor line driving circuit includes:
When the potential of the electrode that is not connected to the capacitor line among the pair of electrodes of the auxiliary capacitor is higher than the predetermined potential of the capacitor line, the predetermined potential with the passage of time from the predetermined potential To rise against
When the potential of the electrode that is not connected to the capacitor line among the pair of electrodes of the auxiliary capacitor is lower than the predetermined potential of the capacitor line, the predetermined potential with the passage of time from the predetermined potential The drive circuit of the electro-optical device according to claim 1, wherein the drive circuit is changed so as to be lowered with respect to the drive circuit. Scanning lines;
A transistor electrically connected to the scan line;
A drive circuit for an electro-optical device, comprising: an auxiliary capacitor provided in a pixel corresponding to the transistor; and a pixel capacitor provided in parallel with the auxiliary capacitor and having a pixel electrode and a common electrode,
A scanning line driving circuit for selecting the scanning line;
A common electrode that supplies a predetermined potential to the common electrode during a selection period of the scanning line and changes a potential of the common electrode so that a gradation of the pixel does not change during a non-selection period of the scanning line. A drive circuit for an electro-optical device, comprising: a drive circuit; Scanning lines;
A transistor electrically connected to the scan line;
An auxiliary capacitor provided in the pixel corresponding to the transistor;
A scanning line driving circuit for selecting the scanning line;
A predetermined potential is supplied to the capacitor line electrically connected to the auxiliary capacitor during the scanning line selection period, and the gray level of the pixel is not changed during the non-selection period of the scanning line. An electro-optical device comprising: a capacitor line driving circuit that changes a potential of the capacitor line. An electronic apparatus comprising the electro-optical device according to claim 8.

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