JP2008233283A - Liquid crystal display device and driving method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a liquid crystal display device capable of suppressing application of a DC component to liquid crystal, thereby suppressing generation of flicker on a picture by simple configuration. <P>SOLUTION: First and second scanning signal line drive circuits 410, 420 are arranged on both sides of a display part 500. Scanning signal lines GL(1) to GL(N) on the display part 500 are alternately driven one by one in each horizontal scanning period by the first and second scanning signal line drive circuits 410, 420, and each scanning signal line GL(i) is alternately driven in each one-frame period by the first and second scanning signal line drive circuits 410, 420 (i =1, 2, ..., N). In this case, the potential Vcom of a common electrode is set to a value lowered from source center potential VSdc by (ΔVβp+ΔVβn)/2 corresponding to a pull-in voltage on the center of a screen for instance. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to an active matrix liquid crystal display device using a switching element such as a thin film transistor and a driving method thereof.

  Since the active matrix liquid crystal display device can obtain an excellent display image without crosstalk between adjacent display pixels even when the number of display pixels is increased, a display such as a television receiver, a computer, a cellular phone, etc. Widely used as a device.

  Such an active matrix type liquid crystal display device includes a liquid crystal panel as a display unit including a plurality of pixel formation units arranged in a matrix and a driving circuit thereof. In the liquid crystal panel, a plurality of data signal lines and a plurality of scanning signal lines are formed in a lattice shape so as to cross each other, and a plurality of auxiliary capacitance lines are extended so as to extend in parallel with the plurality of scanning signal lines. Is formed. One pixel formation portion corresponds to each of intersections of the plurality of data signal lines and the scanning signal lines. In addition, the liquid crystal panel includes a common electrode that is provided in common to the plurality of pixel formation portions arranged in a matrix and is opposed to the pixel electrode included in each pixel formation portion with the liquid crystal interposed therebetween. ing.

  The active matrix liquid crystal display device includes a scanning signal line driving circuit connected to the plurality of scanning signal lines and a data signal line driving circuit connected to the plurality of data signal lines as driving circuits for the liquid crystal panel having the above-described configuration. And an auxiliary capacitance line driving circuit connected to the plurality of auxiliary capacitance lines, and a common electrode driving circuit connected to the common electrode.

  FIG. 3 is an equivalent circuit diagram showing an electrical configuration of one pixel formation portion in the liquid crystal panel of the liquid crystal display device as described above. Each pixel forming portion P (n, m) has a source electrode connected to the data signal line SL (m) passing through the corresponding intersection and a gate electrode on the scanning signal line GL (n) passing through the intersection. It includes a thin film transistor (hereinafter abbreviated as “TFT”) 10 as a connected switch element, and a pixel electrode Epix connected to the drain electrode of the TFT 10, and a liquid crystal capacitance Clc by the pixel electrode Epix and the common electrode Ecom. The auxiliary capacitance Ccs is formed by the pixel electrode Epix and the auxiliary capacitance line CsL provided along the scanning signal line GL (n). The liquid crystal capacitance Clc and the auxiliary capacitance Ccs constitute a pixel capacitance for holding a voltage indicating the value of the pixel to be formed by each pixel formation portion. A parasitic capacitance Cgd is formed between the pixel electrode Epix and the scanning signal line GL (n).

Since a parasitic capacitance Cgd exists between the scanning signal line GL (n) and the pixel electrode Epix in each pixel formation portion P (n, m), the data signal S (m) shown in FIG. Assuming that the voltage is applied to the signal line SL (m), when the voltage of the scanning signal G (n) falls from the gate-on voltage Vgh to the gate-off voltage Vgl as shown in FIG. ), The level shift ΔVd caused by the parasitic capacitance Cgd occurs in the pixel electrode potential (pixel potential) Vd. This level shift ΔVd is referred to as “field-through voltage” or “pull-in voltage”. This pull-in voltage ΔVd is expressed by the following equation.
ΔVd = (Vgh−Vgl) · Cgd / (Clc + Ccs + Cgd) (1)
Such a pull-in voltage ΔVd causes flicker, display deterioration, and the like in the display image. On the other hand, a method of applying a bias to the potential of the common electrode so as to reduce the influence of the pull-in voltage ΔVd caused by the parasitic capacitance Cgd is conventionally known.

  However, it is difficult to form an ideal signal line without a signal propagation delay in a liquid crystal panel used in an active matrix liquid crystal display device, and it is inevitable that a signal propagation delay occurs to some extent. For this reason, the scanning signal line formed on the liquid crystal panel needs to be handled as a distributed constant line having wiring resistance and wiring capacitance. Accordingly, the voltage waveform of the scanning signal G (n) in the scanning signal line is increased as the distance from the position where the scanning signal G (n) is applied by the scanning signal line driving circuit (that is, the input end of the scanning signal G (n)). Slowing down (that is, the fall time of the scanning signal G (n) increases). When the fall time of the scanning signal G (n) increases, the TFT 10 is not completely turned off during the fall period, and charge transfer (pixels) between the data signal line SL (m) and the pixel capacitor is performed. (Capacity recharging) occurs. Therefore, the pull-in voltage ΔVd (> 0) generated in the pixel potential Vd due to the parasitic capacitance Cgd becomes smaller as the distance from the input end of the scanning signal G (n) in the scanning signal line increases.

  As described above, the pull-in voltage ΔVd varies depending on the position in the liquid crystal panel, and is not uniform in the screen. Therefore, when a method of applying a bias to the potential Vcom of the common electrode Ecom so that the influence of the pull-in voltage ΔVd of the pixel potential Vd is reduced, the pull-in voltage ΔVd can be obtained only by applying a uniform bias to the common electrode. It is not possible to sufficiently eliminate flicker, display deterioration, and the like that occur in the display image due to the above. In other words, if the non-uniformity of the pull-in voltage ΔVd in the screen cannot be ignored due to the increase in size and definition of the screen, the above method cannot eliminate the non-uniformity, and the liquid crystal corresponding to each pixel is preferably switched to AC. Since it cannot be driven, problems such as generation of flicker in a display image and a burn-in afterimage due to application of a direct current component to the liquid crystal are caused.

On the other hand, in order to suppress the rounding of the waveform of the scanning signal, a configuration in which scanning signal line driving circuits are provided on the left and right sides of the liquid crystal panel (both ends in the direction in which the scanning signal lines extend) is considered. Further, in order to make the pull-in voltage ΔVd of the pixel potential uniform, an inclination control unit for controlling the falling edge of the scanning signal so that the scanning signal falls at substantially the same inclination irrespective of the position on the scanning signal line is driven by the scanning signal line. A configuration provided in a circuit has been proposed (see Patent Document 3). Further, a gate driver is connected to one end of the gate line (scanning signal line) and a discharge circuit is connected to the other end of the gate line, so that when the applied voltage from one end of the gate line is an on-control voltage, An active matrix liquid crystal panel driving method has been proposed in which an end is opened and an off control voltage is applied from the other end when the applied voltage from one end of the gate line is an off control voltage (patent) Reference 2). Furthermore, a configuration has been proposed in which a correction voltage is obtained by adding a voltage corresponding to a pull-in voltage of the pixel potential (voltage drop of the liquid crystal cell voltage) ΔVd to the input data voltage (see Patent Document 1).
Japanese Patent Laid-Open No. 62-209418 JP-A-10-282471 JP-A-11-281957 JP 11-133930 A

  However, when scanning signal line drive circuits are provided on both sides of the liquid crystal panel and scanning signals are applied from both (left and right) ends, it becomes possible to suppress insufficient charging of the pixel capacity, but the center of the screen (left and right) ) It is difficult to make the pull-in voltage ΔVd the same at both ends, and the charge amount of the pixel capacitance is only at the center of the screen due to the delay (time shift) between the scanning signals output from the left and right scanning signal line drive circuits. Display unevenness may occur. Further, as described in Patent Document 3, in order to control the fall of the scanning signal, a special drive circuit is required, and it is necessary to reduce the time for charging the pixel capacitance. In the configuration described in Patent Document 2, the difference in display potential of the pixel potential pull-in voltage ΔVd can be reduced, but it is difficult to make the pull-in voltage ΔVd sufficiently uniform over the entire screen. Further, even when the pixel voltage pull-in voltage ΔVd is made uniform using the structure described in Patent Document 1, a structure for obtaining a correction voltage by adding a voltage corresponding to the pull-in voltage ΔVd to the input data voltage. Incurs complications.

  Accordingly, an object of the present invention is to provide a liquid crystal display device that can suppress the occurrence of flicker on a screen by suppressing application of a direct current component to a liquid crystal with a simple configuration.

According to a first aspect of the present invention, a plurality of data signal lines, a plurality of scanning signal lines intersecting with the plurality of data signal lines, and intersections of the plurality of data signal lines and the plurality of scanning signal lines are respectively provided. An active matrix type liquid crystal display device having a plurality of pixel forming portions arranged in a matrix correspondingly,
A data signal line driving unit that applies a plurality of data signals representing an image to be displayed to the plurality of data signal lines, and a scanning signal line driving unit that selectively drives the plurality of scanning signal lines;
Each pixel forming portion passes through a corresponding intersection and a switching element that is turned on when a scanning signal line passing through the corresponding intersection is in a selected state and turned off when the scanning signal line is in a non-selected state. A pixel electrode connected to the data signal line through the switching element, a common electrode commonly provided in the plurality of pixel formation portions and arranged to face the pixel electrode, and the pixel formation A liquid crystal commonly provided in a portion and sandwiched between the pixel electrode and the common electrode,
The data signal line driving unit generates the plurality of data signals such that the polarity of a voltage applied between each pixel electrode and the common electrode is inverted every frame period,
The scanning signal line driving unit generates a scanning signal to be applied to one end of the plurality of scanning signal lines in order to selectively drive the plurality of scanning signal lines. And a second scanning signal line driving circuit for generating a scanning signal to be applied to the other end of the plurality of scanning signal lines in order to selectively drive the plurality of scanning signal lines, Application of the scanning signal from the first scanning signal line driving circuit to the one end and application of the scanning signal from the second scanning signal line driving circuit to the other end of the signal line Are alternately switched every frame period.

According to a second aspect of the present invention, in the first aspect of the present invention,
The scanning signal line driving unit includes a scanning signal line to which the scanning signal is applied from the first scanning signal line driving circuit, and a scanning signal line to which the scanning signal is applied from the second scanning signal line driving circuit. The plurality of scanning signal lines are selectively driven so as to be alternately arranged in each frame period.

According to a third aspect of the present invention, in the first aspect of the present invention,
The scanning signal line driving unit is configured to scan the plurality of scanning signals so that the scanning signal is applied to the plurality of scanning signal lines from only one of the first and second scanning signal line driving circuits in each frame period. The signal line is selectively driven.

  Other aspects of the present invention will be apparent from the description of the above aspects of the present invention and the following embodiments, and thus description thereof will be omitted.

  According to the first aspect of the present invention, one end of each scanning signal line from the first scanning signal line driving circuit under inversion driving for inverting the polarity of the voltage applied to the liquid crystal every frame period. The application of the scanning signal to the part and the application of the scanning signal from the second scanning signal line driving circuit to the other end part are alternately switched every frame period. As a result, the variation in the pull-in voltage when the positive voltage is applied to the pixel electrode and the variation in the pull-in voltage when the negative voltage is applied are offset in the adjacent two frame periods, and the positive pixels in the adjacent two frame periods The average value of the electrode potential and the negative pixel electrode potential is substantially the same value in the entire region of the display unit (screen). Therefore, by setting one fixed value as the potential of the common electrode, it is possible to suppress the direct current component of the voltage applied to the liquid crystal and suppress the occurrence of flicker over the entire screen.

  According to the second aspect of the present invention, the scanning signal line to which the scanning signal is applied from the first scanning signal line driving circuit and the scanning signal line to which the scanning signal is applied from the second scanning signal line driving circuit are provided. The scanning signal lines of the display unit are selectively driven so as to be alternately arranged in each frame period, and for each scanning signal line, the scanning signal is applied to one end from the first scanning signal line driving circuit. Application of the scanning signal from the second scanning signal line driver circuit to the other end is alternately switched every frame period. Thereby, the direct current component of the voltage applied to the liquid crystal can be suppressed over the entire screen, and the occurrence of flicker can be suppressed.

  According to the third aspect of the present invention, the scanning signal is applied to the scanning signal line of the display unit from only one of the first and second scanning signal line driving circuits in each frame period, and each scanning signal For each line, the application of the scanning signal from the first scanning signal line driving circuit to one end and the application of the scanning signal from the second scanning signal line driving circuit to the other end are alternated every frame period. Switch to. Thereby, the direct current component of the voltage applied to the liquid crystal can be suppressed over the entire screen, and the occurrence of flicker can be suppressed.

Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.
<1. First Embodiment>
<1.1 Overall configuration>
FIG. 1 is a block diagram showing the overall configuration of an active matrix liquid crystal display device according to a first embodiment of the present invention. This liquid crystal display device includes a display control circuit 200, a data signal line driving circuit 300, first and second scanning signal line driving circuits 410 and 420, a common electrode driving circuit 600, and a display unit 500. . The display unit 500 includes a plurality (M) of data signal lines SL (1) to SL (M), a plurality (N) of scanning signal lines GL (1) to GL (N), and a plurality of these. A plurality of (M × N) pixels provided corresponding to the intersections of the data signal lines SL (1) to SL (M) and the plurality of scanning signal lines GL (1) to GL (N), respectively. The formation part is included and it becomes a structure as shown in FIG.2 and FIG.3. Here, FIG. 2 schematically shows a configuration of the display unit 500 in the present embodiment, and FIG. 3 shows an equivalent circuit of a pixel formation unit in the display unit 500, and the scanning signal line GL (n) and A pixel formation portion corresponding to an intersection with the data signal line SL (m) is denoted by a reference symbol “P (n, m)”. In the present embodiment, the display unit 500 corresponds to a liquid crystal panel, but in addition to the display unit 500, part or all of the data signal line driving circuit 300 and the first and second scanning signal line driving circuits 410 and 420 are included. The structure integrated with the liquid crystal panel may be sufficient.

  As shown in FIGS. 2 and 3, each pixel forming portion P (n, m) has a gate electrode connected to the scanning signal line GL (n) passing through the corresponding intersection and a data signal passing through the intersection. The TFT 10 which is a switching element having a source electrode connected to the line SL (m), the pixel electrode Epix connected to the drain electrode of the TFT 10, and the plurality of pixel formation portions P (i, j) (i = 1) ˜N, j = 1 to M) and the common electrode Ecom, and the plurality of pixel formation portions P (i, j) (i = 1 to N, j = 1 to M). And a liquid crystal layer sandwiched between the pixel electrode Epix and the common electrode Ecom.

  In each pixel formation portion P (n, m), a liquid crystal capacitance Clc is formed by the pixel electrode Epix and the common electrode Ecom facing each other with the liquid crystal layer interposed therebetween. Further, an auxiliary capacitance line CsL is formed in parallel with each scanning signal line GL (n), and in each pixel formation portion P (n, m), an auxiliary capacitance Ccs is provided between the pixel electrode Epix and the auxiliary capacitance line CsL. Is formed. Further, a parasitic capacitance Cgd is formed between the pixel electrode Epix and the scanning signal line GL (n). In this specification, it is assumed that the pixel capacitor Cpix is configured by the liquid crystal capacitor Clc and the auxiliary capacitor Ccs. The capacitance values of these capacitors Clc, Ccs, Cpix, and Cgd are also indicated by the same symbols “Clc”, “Ccs”, “Cpix”, and “Cgd”, respectively.

  The display control circuit 200 receives a data signal DAT and a timing control signal TS sent from the outside, and receives a digital image signal DV, a data start pulse signal SSP for controlling the timing for displaying an image on the display unit 500, and a data clock. The signal SCK, the latch strobe signal LS, the odd row gate start pulse signal GSPa, the even row gate start pulse signal GSPb, the odd row gate clock signal GCKa, and the even row gate clock signal GCKb are output. The data clock signal SCK is a clock signal including a pulse corresponding to each pixel of the image represented by the digital image signal DV, and the data start pulse signal SSP is a signal including one pulse at the beginning of each horizontal scanning period. The latch strobe signal LS is a signal including one pulse for each horizontal scanning period. The odd-numbered gate clock signal GCKa is a clock signal having a pulse corresponding to the odd-numbered scanning signal line with a period of two horizontal scanning periods, and the even-numbered gate clock signal GCCKb is an even number with a period of two horizontal scanning periods. This is a clock signal having a pulse corresponding to the second scanning signal line. Furthermore, the odd-numbered gate start pulse signal GSPa is a signal having one pulse including the selection start time of the first scanning signal line GL (1) in the duration in each frame period every two frame periods. The row gate start pulse signal GSPb is a signal having one pulse including the selection start time of the second scanning signal line GL (2) in each frame period every two frame periods. However, the pulse of the odd-numbered gate start pulse signal GSPa and the pulse of the even-numbered pulse signal GSPb appear in the same frame period.

  The data signal line driving circuit 300 receives the digital image signal DV, the data start pulse signal SSP, the data clock signal SCK, and the latch strobe signal LS output from the display control circuit 200 and receives each pixel forming unit P in the display unit 500. Data signals S (1) to S (M) are applied to the data signal lines SL (1) to SL (M) in order to charge the pixel capacitance Cpix (liquid crystal capacitance Clc and auxiliary capacitance Ccs) of (n, m), respectively. To do. At this time, in the data signal line driving circuit 300, the digital image signal DV indicating the voltage to be applied to each of the data signal lines SL (1) to SL (M) is sequentially supplied at the timing when the pulse of the data clock signal SCK is generated. Retained. At the timing when the pulse of the latch strobe signal LS is generated, the held digital image signal DV is converted into an analog voltage, and all the data signal lines SL (1) are converted into data signals S (1) to S (M). To SL (M) simultaneously. That is, in this embodiment, the line sequential driving method is adopted as the driving method of the data signal lines SL (1) to SL (M).

  The first scanning signal line driving circuit 410 is disposed on one side (left side in FIG. 1) of the display unit 500, and the second scanning signal line driving circuit 420 is disposed on the other side (right side in FIG. 1). One end (left end in FIG. 1) of the scanning signal lines SL (1) to SL (N) in the unit 500 is connected to the first scanning signal line driving circuit 410, and in addition to the scanning signal lines SL (1) to SL (N). The end (the right end in FIG. 1) is connected to the second scanning signal line drive circuit 420. Of the signals output from the display control circuit 200, the odd-numbered gate start pulse signal GSPa is input to the first scanning signal line driving circuit 410, and the even-numbered gate start pulse signal GSPb is input to the second scanning signal line driving circuit 420. The odd-numbered and even-numbered gate clock signals GCKa and GCKb are input to both the first and second scanning signal line driving circuits 410 and 420.

  The first and second scanning signal line driving circuits 410 and 420 both have a first input terminal Tia for inputting the odd-numbered gate start pulse signal GSPa and a second input for inputting the even-numbered gate start pulse signal GSPb. N / 2-stage shift registers each having flip-flops corresponding to odd-numbered scanning signal lines GL (1), GL (3),..., GL (N−1). (Hereinafter referred to as “odd row shift register”) and N / 2-stage shift registers (hereinafter referred to as flip-flops) corresponding to the even-numbered scanning signal lines GL (2), GL (4),. (Referred to herein as N being an even number).

  When the pulse of the odd-numbered gate start pulse signal GSPa is input from the display control circuit 200 to the first scanning signal line driving circuit 410 via the first input terminal Tia, this pulse (hereinafter referred to as “odd-numbered row start pulse”) is The odd row shift registers in the first scanning signal line driving circuit 410 are sequentially transferred based on the odd row gate clock signal GCKa. In accordance with this transfer, in one frame period, scanning signals G (1), G (3),..., G (N−1) that are sequentially activated every other horizontal scanning period are driven by the first scanning signal line. The circuit 410 applies the odd-numbered scanning signal lines GL (1), GL (3),. The odd-numbered row start pulse is then output from the output terminal Toa of the first scanning signal line driving circuit 410 and input to the second scanning signal line driving circuit 420 via the first input terminal Tia. In the second scanning signal line driving circuit 420, the odd row start pulse is sequentially transferred to the odd row shift register based on the odd row gate clock signal GCKa. In accordance with this transfer, in the next one frame period, scanning signals G (1), G (3),..., G (N−1) that are sequentially activated every other horizontal scanning period for each horizontal scanning period are the second scanning signal. It is applied from the line drive circuit 420 to odd-numbered scanning signal lines GL (1), GL (3),... GL (N−1), respectively.

  On the other hand, when the pulse of the even-numbered gate start pulse signal GSPb is input from the display control circuit 200 to the second scanning signal line driving circuit 420 via the second input terminal Tib, this pulse (hereinafter referred to as “even-numbered row start pulse”). ) Are sequentially transferred to the even-numbered row shift register in the second scanning signal line driving circuit 420 based on the even-numbered gate clock signal GCKb. In accordance with this transfer, in one frame period, scanning signals G (2), G (4),..., G (N) that are sequentially activated every other horizontal scanning period for each horizontal scanning period are the second scanning signal line drive circuit 420. To the even-numbered scanning signal lines GL (2), GL (4),..., GL (N). The even-numbered row start pulse is then output from the output terminal Tob of the second scanning signal line driving circuit 420 and input to the first scanning signal line driving circuit 410 via the second input terminal Tib. In the first scanning signal line driving circuit 410, the even row start pulse is sequentially transferred to the even row shift register based on the even row gate clock signal GCKb. In accordance with this transfer, in the next one frame period, scanning signals G (2), G (4),..., G (N) that are sequentially activated every other horizontal scanning period are driven by the first scanning signal line. The circuit 410 applies the even-numbered scanning signal lines GL (2), GL (4),..., GL (N).

  As described above, the scanning signal lines GL (1) to GL (N) of the display unit 500 are alternately driven one by one for each horizontal scanning period by the first and second scanning signal line driving circuits 410 and 420. In addition, each scanning signal line GL (i) is alternately driven every frame period by the first and second scanning signal line driving circuits 410 and 420 (i = 1, 2,..., N). The first scanning signal line driving circuit 410 supplies the scanning signals G (1), G (3),... To the odd-numbered scanning signal lines GL (1), GL (3),. , G (N−1) is applied, the output to the even-numbered scanning signal lines GL (2), GL (4),. While the scanning signals G (2), G (4),..., G (N) are applied to the scanning signal lines GL (2), GL (4),. .., GL (N−1) are output in a high impedance state (OFF state). The same applies to the second scanning signal line drive circuit 420. That is, each of the first and second scanning signal line driving circuits 410 and 420 sets the output to the scanning signal line that is not driven among the odd-numbered scanning signal line and the even-numbered scanning signal line to the high impedance state (OFF state). Each output is switched on / off in response to switching of the non-driven scanning signal line between the odd-numbered scanning signal line and the even-numbered scanning signal line every frame period.

  The common electrode drive circuit 600 applies a predetermined fixed potential (hereinafter referred to as “common potential”) Vcom to the common electrode Ecom and each auxiliary capacitance line CsL in the display unit 500. The common potential Vcom will be described later.

  As described above, in the display unit 500, the data signals S (1) to S (M) are applied to the data signal lines SL (1) to SL (M), respectively, and the scanning signal lines GL (1) to GL are applied. (N) is applied with scanning signals G (1) to G (M), respectively, and a common potential Vcom is applied to the common electrode Ecom and the auxiliary capacitance line CsL, so that each pixel electrode Epix has a common electrode. A voltage corresponding to a pixel value based on the digital image signal DV is given with the potential Vcom of Ecom as a reference, and is held in the pixel capacitor Cpix. Thus, a voltage corresponding to the potential difference between each pixel electrode Epix and the common electrode Ecom is applied to the liquid crystal layer of the display unit 500, and the display unit 500 controls the light transmittance of the liquid crystal layer by this applied voltage. Thus, the image represented by the digital image signal DV is displayed.

<1.2 Action and effect>
Next, for comparison, the operation of the conventional liquid crystal display device in which the scanning signal line driving circuit is provided only on one side of the display unit will be described, and then the operation of the liquid crystal display device according to the present embodiment will be described. . In the following description, portions of the conventional liquid crystal display device that are the same as or correspond to those of the liquid crystal display device according to the embodiment (FIGS. 1 to 3) are denoted by the same reference numerals. In the following, the polarity of the voltage applied to the pixel capacitor (the voltage applied to the liquid crystal layer) is inverted every frame period and also every line (every scanning signal line), that is, one line. The following description assumes that the inversion driving method (1H inversion driving method) is employed.

  FIG. 4 is a voltage waveform diagram showing changes in the data signal S (m), the scanning signal G (n), and the potential Vd of the pixel electrode Epix of the pixel formation portion P (n, m) in the conventional liquid crystal display device ( As will be described later, the same voltage waveform is obtained in this embodiment. The voltage waveform of the data signal S (m) varies depending on the image to be displayed, but for the sake of convenience of explanation, the data signal S (m) that maximizes the voltage applied to the liquid crystal is given below (others). The same applies to the embodiments and the modified examples.

In the display unit 500, the data signal S (m) shown in FIG. 4A is applied to the data signal line SL (m), and the scanning signal G (n) shown in FIG. 4B is applied to the scanning signal line GL (n). ) Is applied, the potential (hereinafter also simply referred to as “pixel potential”) Vd of the pixel electrode Epix in the pixel formation portion P (n, m) in the n-th row and m-th column is shown in FIG. (1 ≦ n ≦ N, 1 ≦ m ≦ M). That is, when the voltage of the scanning signal G (n) becomes the gate-on voltage Vgh (the scanning signal G (n) is active), the data signal S (m) is transmitted to the pixel electrode via the TFT 10 of the pixel formation portion P (n, m). The pixel capacitance Cpix (Clc and Ccs) is charged. Thereafter, when the voltage of the scanning signal G (n) becomes the gate-off voltage Vgl (the scanning signal G (n) is inactive), the TFT 10 is turned off, and the pixel electrode Epix of the pixel formation portion P (n, m) It is electrically disconnected from the data signal line SL (m). At this time, the pixel potential Vd is affected by the voltage change of the scanning signal G (n) from the gate-on voltage Vgh to the gate-off voltage Vgl, and decreases by the pull-in voltage ΔVd expressed by the following equation (1).
ΔVd = (Vgh−Vgl) · Cgd / (Clc + Ccs + Cgd) (1)
Here, Cgd indicates a parasitic capacitance between the pixel electrode Epix and the scanning signal line GL (n). After the voltage of the scanning signal G (n) changes from the gate-on voltage Vgh to the gate-off voltage Vgl, the pixel potential Vd is maintained while the voltage of the scanning signal G (n) is the gate-off voltage Vgl.

  As can be seen from FIG. 4C, the voltage VLC (> 0) applied to the liquid crystal is charged to the pixel capacitor Cpix with a positive voltage with respect to the common electrode Ecom due to the influence of the pull-in voltage ΔVd. Sometimes, it becomes smaller than the original charging voltage (voltage of the data signal S (m)) by ΔVd, and when a negative voltage is charged to the pixel capacitor Cpix with respect to the common electrode Ecom, ΔVd is higher than the original charging voltage. Only get bigger. Therefore, the potential Vcom of the common electrode Ecom is set to the center value of the data signal S (m), that is, the source center potential (the average value of the maximum value and the minimum value or the value indicating the DC level of the data signal S (m)) VSdc. If the luminance to be displayed is fixed, the applied voltage VLC to the liquid crystal is different for each frame period, and this is visually recognized as flicker (flicker). As a countermeasure against this, there is conventionally known a method in which the common electrode potential (common potential) Vcom is set lower than the source center potential VSdc by the pull-in voltage ΔVd.

  However, since each scanning signal line GL (n) has wiring resistance and wiring capacitance, the scanning signal G (n) is applied to the voltage waveform of each scanning signal G (n) by the scanning signal line driving circuit. As you move away from the location, When the waveform of the scanning signal G (n) is rounded, the pull-in voltage ΔVd (> 0) decreases, so the pull-in voltage ΔVd in each pixel formation portion P (n, m) is a position on the scan signal line GL (n). (Distance from the input end to which the scanning signal G (n) is applied by the scanning signal line driving circuit).

  For example, as shown in FIGS. 5A and 5B, in the case of the conventional example in which the scanning signal line driving circuit 400 is provided only on one side of the display unit 500, the scanning signal line driving circuit 400 is close to the position A. The drawing voltages ΔVαp and ΔVαn are as shown in FIG. 5C, and the drawing voltages ΔVγp and ΔVγn at the position C far from the scanning signal line driving circuit 400 are as shown in FIG. 5E, corresponding to the center of the screen. The drawing voltages ΔVβp and ΔVβn at the position B are as shown in FIG. 5D (ΔVαp> 0, ΔVαn> 0, ΔVβp> 0, ΔVβn> 0, ΔVγp> 0, ΔVγn> 0). In FIG. 5, it is assumed that a positive voltage is held in the pixel capacitor Cpix in the k frame and a negative voltage is held in the pixel capacitor Cpix in the k + 1 frame. 5C, 5D, and 5E are enlarged waveform diagrams of the pixel potential Vd when the pixel capacitor Cpix is charged with the data signal S (m) corresponding to the pixel value, that is, the scanning signal G (n). ) Is an enlarged waveform diagram of the pixel potential Vd near the time point when the gate-on voltage Vgh changes to the gate-off voltage Vgl.

Now, in order to prevent flicker from occurring at the center of the screen (position B), the common potential Vcom is set to a value represented by the following equation (see FIG. 5D).
Vcom = {(X1−ΔVβp) + (X2−ΔVβn)} / 2
= (X1 + X2) / 2- (ΔVβp + ΔVβn) / 2
= VSdc- (ΔVβp + ΔVβn) / 2 (2)
Here, X1 represents the value of the data signal S (m) in the case of positive polarity, and X2 represents the value of the data signal S (m) in the case of negative polarity. The common potential Vcom in this case is compared with the common potential for preventing flicker from occurring at the position A.
(ΔVαp + ΔVαn) / 2− (ΔVβp + ΔVβn) / 2
It is only shifted. In this case, the common potential Vcom is compared with the common potential for preventing flicker from occurring at the position C.
(ΔVβp + ΔVβn) / 2− (ΔVγp + ΔVγn) / 2
It is only shifted. Therefore, even if the common potential Vcom is set so that flicker does not occur at the center of the screen, the applied voltage (absolute value) to the liquid crystal is slightly different for each frame period in other areas in the screen, The voltage contains a direct current component. This is visually recognized as flicker on the screen.

  On the other hand, in the present embodiment, the first scanning signal line driving circuit 410 and the second scanning signal line driving circuit 420 are respectively provided on one side and the other side of the display unit 500 (see FIGS. 1 and 6). As described above, the scanning signal lines GL (1) to GL (N) of the display unit 500 are alternately arranged by the first and second scanning signal line driving circuits 410 and 420 every one horizontal scanning period. The scanning signal lines GL (n) are driven alternately by the first and second scanning signal line driving circuits 410 and 420 every frame period (n = 1, 2,..., N). . Now, as shown in FIGS. 6A and 6B, in a certain frame period (Kth frame), the scanning signal from the first scanning signal line driving circuit 410 to the i-th scanning signal line GL (i). Assuming that G (i) is applied and the pixel capacitance Cpix of the pixel formation portion P (i, m) is charged with a positive polarity, in the next frame period (K + 1 frame), the scanning signal line GL (i ) Is applied from the second scanning signal line driving circuit 420 to charge the pixel capacitor Cpix of the pixel formation portion P (i, m) with a negative polarity.

  6A and 6B, an arrow written on the display unit 500 indicates that one of the first and second scanning signal line driving circuits 410 and 420 with respect to the scanning signal line GL (n) of the display unit 500. It shows from which the scanning signal G (n) is applied (the same applies to FIG. 8 described later). That is, the arrow in FIG. 6A indicates that the scanning signal G (i) is applied from the first scanning signal line driving circuit 410 to the i-th scanning signal line GL (i), and the i + 1-th scanning signal line GL ( It shows that the scanning signal G (i + 1) is applied from the second scanning signal line driving circuit 420 to i + 1). Further, an arrow in FIG. 6B indicates that the scanning signal G (i) is applied from the second scanning signal line driving circuit 420 to the i-th scanning signal line GL (i), and the i + 1-th scanning signal line GL ( This shows that the scanning signal G (i + 1) is applied from the first scanning signal line driving circuit 410 to i + 1).

  As shown in FIGS. 6 (a) and 6 (b), in the present embodiment, focusing on the i-th scanning signal line GL (i), the first and second scanning signal line driving circuits 410 and 420 receive every frame period. Since the scanning signal G (i) is alternately applied to the first scanning signal line driving circuit 410, the pull-in voltage ΔVd at the position A close to the first scanning signal line driving circuit 410 is a large value ΔVαp at the k-th frame as shown in FIG. (Same as the pull-in voltage at the position A in the conventional example (FIG. 5C)), and a small value ΔVγn (same as the pull-in voltage at the position C in the conventional example (FIG. 5E)) in the (k + 1) th frame. ) On the other hand, the pull-in voltage ΔVd at the position C close to the second scanning signal line drive circuit 420 is a small value ΔVγp (similar to the pull-in voltage at the position C in the conventional example) at the k-th frame, as shown in FIG. ) And becomes a large value ΔVαn (about the same as the pull-in voltage at the position A in the conventional example) in the (k + 1) th frame. Further, the pull-in voltage ΔVd at a position that is equally distant from both the first scanning signal line driving circuit 410 and the second scanning signal line driving circuit 420, that is, at the position B corresponding to the center of the screen, is as shown in FIG. In addition, the value ΔVβp is an intermediate value in the kth frame (similar to the pull-in voltage at the position B in the conventional example (FIG. 5D)), and the intermediate value ΔVβn also in the k + 1th frame.

Therefore, the value of the common potential Vcom for preventing flicker from occurring at the center of the screen (position B) is given by the following equation as in the conventional example.
Vcom = (X1 + X2) / 2− (ΔVβp + ΔVβn) / 2
= VSdc- (ΔVβp + ΔVβn) / 2 (3)
Further, the value of the common potential Vcom for preventing flicker from occurring at the position A is given by the following equation.
Vcom = (X1 + X2) / 2− (ΔVαp + ΔVγn) / 2
= VSdc- (ΔVαp + ΔVγn) / 2 (4)
A value of the common potential Vcom for preventing flicker from occurring at the position C is given by the following equation.
Vcom = (X1 + X2) / 2− (ΔVγp + ΔVαn) / 2
= VSdc- (ΔVγp + ΔVαn) / 2 (5)
Here, in consideration of the above-described magnitude relationship regarding ΔVαp, ΔVαn, ΔVβp, ΔVβn, ΔVγp, and ΔVγn, the following equation is established.
ΔVαp + ΔVγn≈ΔVβp + ΔVβn≈ΔVγp + ΔVαn (6)
Therefore, the variation in the pull-in voltage ΔVd when a positive voltage is applied to the pixel electrode Epix and the variation in the pull-in voltage ΔVd when a negative voltage is applied are offset in two adjacent frame periods (kth frame and k + 1th frame). In addition, the average value of the positive pixel potential Vd and the negative pixel potential Vd in the adjacent two frame periods is substantially the same value in the entire region of the display unit 500 (screen). Therefore, by setting one fixed value (for example, the value given by the above equation (3)) as the value of the common potential Vcom, the DC component of the voltage applied to the liquid crystal can be suppressed in any region of the display unit 500. The occurrence of flicker can be suppressed over the entire screen.

  As described above, according to the present embodiment, the first and second scanning signal line driving circuits 410 and 420 respectively arranged on the left and right sides of the display unit 500 alternate the scanning signal lines GL (n) every frame period. Driving to suppress the direct current component of the voltage applied to the liquid crystal over the entire display unit 500. Therefore, it is possible to suppress the occurrence of flicker due to non-uniformity of the pull-in voltage ΔVd with a simple configuration without requiring a circuit for controlling the falling edge of the scanning signal, a circuit for correcting the input voltage, or the like. be able to. Further, by suppressing the direct current component of the voltage applied to the liquid crystal, it is possible to prevent image burn-in and deterioration of the liquid crystal.

<2. Second Embodiment>
FIG. 7 is a block diagram showing the overall configuration of an active matrix liquid crystal display device according to the second embodiment of the present invention. Since the basic configuration of the liquid crystal display device is the same as that of the first embodiment, the same reference numerals are given to the same or corresponding parts, and hereinafter, the first embodiment of the configuration of the present embodiment will be described below. Different parts will be explained.

  In the present embodiment, the display control circuit 200 generates a gate clock signal GCK having a period of one horizontal scanning period instead of the odd-numbered gate clock signal GCKa and the even-numbered gate clock signal GCKb in the first embodiment. In addition, the display control circuit 200 in the present embodiment generates the first gate start pulse signal GSP1 instead of the odd row gate start pulse signal GSPa and the even row gate start pulse signal GSPb in the first embodiment. The first gate start pulse signal GSP1 is a signal including one pulse every two frame periods. In the present embodiment, the first gate start pulse signal GSP1 includes one pulse at the beginning of each odd-numbered frame period. The first gate start pulse signal GSP1 is input only to the first scanning signal line driving circuit 410.

  The first and second scanning signal line drive circuits 410 and 420 in this embodiment are the same as those in the first embodiment with respect to the arrangement relationship and connection relationship with the display unit 500, but the internal configuration is the first embodiment. It differs from the form. That is, the first scanning signal line drive circuit 410 has an N-stage shift register, and the shift register sequentially transfers the first gate start pulse signal GSP1 based on the gate clock signal GCK. Scan signals G (1) to G (N) that are sequentially active in the horizontal scanning period are output. These scanning signals G (1) to G (N) are applied to one end (left end in FIG. 7) of the scanning signal lines GL (1) to GL (N) in each odd-numbered frame period.

  When one pulse in the first gate start pulse signal GSP1 is transferred to the output terminal of the shift register in the first scanning signal line driver circuit 410, the first gate signal is output from the first scanning signal line driver circuit 410. The signal is input to the second scanning signal line driver circuit 420 as a pulse of the gate start pulse signal GSP2. The second scanning signal line drive circuit 420 also includes an N-stage shift register, and the second gate start pulse signal GSP2 is sequentially transferred based on the gate clock signal GCK by this shift register, and one horizontal scan is performed according to this transfer. The scanning signals G (1) to G (N) that are active for each period are sequentially output. These scanning signals G (1) to G (N) are applied to the other end (right end in FIG. 7) of the scanning signal lines GL (1) to GL (N) in each even-numbered frame period.

  In this way, the scan signals G (1) to G (N) are applied to the scan signal lines GL (1) to GL (N) from the first scan signal line driving circuit 410 in each odd-numbered frame period. In each even-numbered frame period, the scanning signals G (1) to G (N) are applied from the second scanning signal line driving circuit 420 to the scanning signal lines GL (1) to GL (N), respectively. That is, the scanning signal G (n) is alternately applied to one end and the other end of each scanning signal line GL (n) every frame period (n = 1, 2,..., N). The first scanning signal line driving circuit 410 scans the scanning signals G (1) to G (N) from the second scanning signal line driving circuit 420 (even-numbered frame period). The outputs for the lines GL (1) to GL (N) are configured to be in a high impedance state (OFF state). The second scanning signal line driving circuit 420 also scans the scanning signal G (1) to G (N) from the first scanning signal line driving circuit 410 (odd-numbered frame period). The outputs for the lines GL (1) to GL (N) are configured to be in a high impedance state (OFF state).

  Also in the present embodiment as described above, each scanning signal line GL (n) is alternately driven every frame period by the first and second scanning signal line driving circuits 410 and 420 (n = 1, 2,..., N), as in the first embodiment, the pull-in voltages at positions A, B, and C in the extending direction (horizontal direction) of the scanning signal line GL (n) are shown in FIGS. As shown in (e). Therefore, by setting one fixed value (for example, the value given by the above equation (3)) as the value of the common potential Vcom, the DC component of the voltage applied to the liquid crystal is suppressed in any region of the display unit 500. be able to. Therefore, also in the present embodiment, a circuit for controlling the falling edge of the scanning signal, a circuit for correcting the input voltage, and the like are not required, and this is caused by non-uniformity of the pull-in voltage with a simple configuration. The occurrence of flicker can be suppressed.

Next, the influence of the pull-in voltage on the display brightness in this embodiment will be described.
As shown in FIGS. 8A and 8B, in the present embodiment, each scanning signal line GL (n) of the display unit 500 is sent by the first and second scanning signal line driving circuits 410 and 420 every frame period. Driven alternately (n = 1, 2,..., N), and in each frame period, only one of the first and second scanning signal line driving circuits 410 and 420 scans the scanning signal lines GL (1) ˜ GL (N) is driven. FIG. 8C is a voltage waveform diagram showing a change in the pixel potential Vd in the present embodiment. When such a driving method is employed, the pull-in voltages ΔVd and i + 1 at the positions A and C on the i-th line are used. The drawing voltage ΔVd at positions A and C on the line is shown.

  As shown in FIG. 8C, at the position A of the i-th line, a large pull-in voltage ΔVαp is generated in the k-th frame where a positive voltage is applied to the pixel electrode Epix, and a negative voltage is applied to the pixel electrode Epix. A small pull-in voltage ΔVγn is generated in the applied (k + 1) th frame, whereas a small pull-in voltage ΔVγp is generated in the kth frame in which a positive voltage is applied to the pixel electrode Epix at the position C of the i-th line. A large pull-in voltage ΔVαn is generated in the (k + 1) th frame in which a negative voltage is applied to Epix. Accordingly, the voltage VLC (absolute value) applied to the liquid crystal at the i-th line is larger at the position C than at the position A. On the other hand, at the position A of the (i + 1) th line, a small pull-in voltage ΔVγp is generated in the (k + 1) th frame when the positive voltage is applied to the pixel electrode Epix, and is large in the kth frame when the negative voltage is applied to the pixel electrode Epix. While the pull-in voltage ΔVαn is generated, at the position C of the (i + 1) th line, a large pull-in voltage ΔVαp is generated in the (k + 1) th frame where the positive voltage is applied to the pixel electrode Epix, and the negative voltage is applied to the pixel electrode Epix. A small pull-in voltage ΔVγn is generated at the kth frame. Accordingly, the voltage VLC (absolute value) applied to the liquid crystal in the (i + 1) th line is smaller at the position C than at the position A.

  Therefore, when the driving method according to the present embodiment is adopted, even when an image having the same gradation is displayed on the entire surface, the liquid crystal is changed depending on the position of the display unit 500 in the left-right direction (the direction in which the scanning signal lines extend). Since the applied voltage VLC is different and the luminance is different for each display line, the luminance unevenness can be visually recognized. However, if the resolution in the vertical direction is increased to increase the number of horizontal scanning lines per frame, the luminance unevenness is spatially averaged and becomes difficult to be visually recognized.

<3. Modification>
In the first and second embodiments described above, the 1H inversion driving method is adopted. However, the present invention is not limited to this, and the nH inversion driving method (n ≧ 2) or the frame inversion driving in which line inversion is not performed. The present invention can also be applied when the method is adopted. That is, even in such a case, the scanning signal lines GL (n) are alternately driven every frame period by the first and second scanning signal line driving circuits respectively disposed on the left and right of the display unit 500. Thus, the occurrence of flicker due to non-uniformity of the pull-in voltage can be suppressed over the entire screen.

  In the first embodiment, the scanning signal lines GL (1) to GL (N) of the display unit 500 are alternately arranged by the first and second scanning signal line driving circuits 410 and 420 for each horizontal scanning period. The scanning signal lines GL (1) to GL (N) are alternately driven by the first and second scanning signal line driving circuits 410 and 420 every n horizontal scanning periods. Good (n ≧ 2).

1 is a block diagram showing an overall configuration of an active matrix liquid crystal display device according to a first embodiment of the present invention. It is a figure which shows typically the structure of the display part of the liquid crystal display device which concerns on the said 1st Embodiment. It is a circuit diagram which shows the equivalent circuit of the pixel formation part in the liquid crystal display device which concerns on the said 1st Embodiment, and the conventional liquid crystal display device. It is a voltage waveform diagram for demonstrating operation | movement of the liquid crystal display device which concerns on the said 1st Embodiment, and the conventional liquid crystal display device. Schematic diagrams (a) and (b) showing driving of scanning signal lines in a conventional liquid crystal display device, and voltage waveform diagrams (c) to (e) for explaining generation of flicker due to non-uniformity of a pull-in voltage ). Schematic diagrams (a) and (b) showing driving of scanning signal lines in the liquid crystal display device according to the first embodiment, and a principle for suppressing occurrence of flicker in the first embodiment. It is figure (c)-(e). It is a block diagram which shows the whole structure of the active matrix type liquid crystal display device which concerns on the 2nd Embodiment of this invention. In the schematic diagrams (a) and (b) showing the driving method in the second embodiment, and the voltage waveform diagram (c) for explaining the influence of the pull-in voltage on the display luminance when the driving method is adopted. is there.

Explanation of symbols

10 ... TFT (switching element)
200: Display control circuit 300: Data signal line drive circuit (data signal line drive unit)
410: first scanning signal line driving circuit 420 ... second scanning signal line driving circuit 450 ... auxiliary capacitance line driving circuit 500 ... display section Clc ... liquid crystal capacitance Ccs ... auxiliary capacitance Cgd ... parasitic capacitance Cpix ... pixel capacitance Epix ... pixel electrode Ecom ... Common electrode GL (i) ... Scanning signal line (i = 1, 2, ..., N)
SL (j) Data signal line (j = 1, 2,..., M)
CsL ... storage capacitor line P (i, j) ... pixel formation part (i = 1, 2, ..., N; j = 1, 2, ..., M)
DA ... Digital image signal SSP ... Data start pulse signal SCK ... Data clock signal GSP1 ... First gate start pulse signal GSPa ... Odd row gate start pulse signal GSPb ... Even row gate start pulse signal GCK ... Gate clock signal GCKa ... Odd row Gate clock signal GCKb ... Even-numbered gate clock signal G (i) ... Scanning signal (i = 1, 2, ..., N)
S (j): Data signal (j = 1, 2,..., M)
Vcom: Common potential

Claims (5)

The plurality of data signal lines, the plurality of scanning signal lines intersecting with the plurality of data signal lines, and the intersections of the plurality of data signal lines and the plurality of scanning signal lines are arranged in a matrix. An active matrix type liquid crystal display device having a plurality of pixel forming portions,
A data signal line driver that applies a plurality of data signals representing an image to be displayed to the plurality of data signal lines;
A scanning signal line driving unit that selectively drives the plurality of scanning signal lines,
Each pixel forming portion passes through a corresponding intersection and a switching element that is turned on when a scanning signal line passing through the corresponding intersection is in a selected state and turned off when the scanning signal line is in a non-selected state. A pixel electrode connected to the data signal line through the switching element, a common electrode commonly provided in the plurality of pixel formation portions and arranged to face the pixel electrode, and the pixel formation A liquid crystal commonly provided in a portion and sandwiched between the pixel electrode and the common electrode,
The data signal line driving unit generates the plurality of data signals such that the polarity of a voltage applied between each pixel electrode and the common electrode is inverted every frame period,
The scanning signal line driving unit generates a scanning signal to be applied to one end of the plurality of scanning signal lines in order to selectively drive the plurality of scanning signal lines. And a second scanning signal line driving circuit for generating a scanning signal to be applied to the other end of the plurality of scanning signal lines in order to selectively drive the plurality of scanning signal lines, Application of the scanning signal from the first scanning signal line driving circuit to the one end and application of the scanning signal from the second scanning signal line driving circuit to the other end of the signal line Are alternately switched every frame period. A matrix type liquid crystal display device.   The scanning signal line driving unit includes a scanning signal line to which the scanning signal is applied from the first scanning signal line driving circuit, and a scanning signal line to which the scanning signal is applied from the second scanning signal line driving circuit. 2. The active matrix liquid crystal display device according to claim 1, wherein the plurality of scanning signal lines are selectively driven so as to be alternately arranged in each frame period.   The scanning signal line driving unit is configured to scan the plurality of scanning signals so that the scanning signal is applied to the plurality of scanning signal lines from only one of the first and second scanning signal line driving circuits in each frame period. 2. The active matrix liquid crystal display device according to claim 1, wherein the signal lines are selectively driven. The plurality of data signal lines, the plurality of scanning signal lines intersecting with the plurality of data signal lines, and the intersections of the plurality of data signal lines and the plurality of scanning signal lines are arranged in a matrix. A drive circuit for an active matrix type liquid crystal display device having a plurality of pixel formation portions,
A data signal line driver that applies a plurality of data signals representing an image to be displayed to the plurality of data signal lines;
A scanning signal line driving unit that selectively drives the plurality of scanning signal lines,
Each pixel forming portion passes through a corresponding intersection and a switching element that is turned on when a scanning signal line passing through the corresponding intersection is in a selected state and turned off when the scanning signal line is in a non-selected state. A pixel electrode connected to the data signal line through the switching element, a common electrode commonly provided in the plurality of pixel formation portions and arranged to face the pixel electrode, and the pixel formation A liquid crystal commonly provided in a portion and sandwiched between the pixel electrode and the common electrode,
The data signal line driving unit generates the plurality of data signals such that the polarity of a voltage applied between each pixel electrode and the common electrode is inverted every frame period,
The scanning signal line driving unit generates a scanning signal to be applied to one end of the plurality of scanning signal lines in order to selectively drive the plurality of scanning signal lines. And a second scanning signal line driving circuit for generating a scanning signal to be applied to the other end of the plurality of scanning signal lines in order to selectively drive the plurality of scanning signal lines, Application of the scanning signal from the first scanning signal line driving circuit to the one end and application of the scanning signal from the second scanning signal line driving circuit to the other end of the signal line Are alternately switched every frame period. The plurality of data signal lines, the plurality of scanning signal lines intersecting with the plurality of data signal lines, and the intersections of the plurality of data signal lines and the plurality of scanning signal lines are arranged in a matrix. A driving method of an active matrix type liquid crystal display device having a plurality of pixel forming portions,
A data signal line driving step of applying a plurality of data signals representing an image to be displayed to the plurality of data signal lines;
A scanning signal line driving step for selectively driving the plurality of scanning signal lines,
Each pixel forming portion passes through a corresponding intersection and a switching element that is turned on when a scanning signal line passing through the corresponding intersection is in a selected state and turned off when the scanning signal line is in a non-selected state. A pixel electrode connected to the data signal line through the switching element, a common electrode commonly provided in the plurality of pixel formation portions and arranged to face the pixel electrode, and the pixel formation A liquid crystal commonly provided in a portion and sandwiched between the pixel electrode and the common electrode,
In the data signal line driving step, the plurality of data signals are generated such that the polarity of a voltage applied between each pixel electrode and the common electrode is inverted every frame period,
The scanning signal line driving step includes a first driving step for generating a scanning signal to be applied to one end of the plurality of scanning signal lines in order to selectively drive the plurality of scanning signal lines; Generating a scanning signal to be applied to the other end of the plurality of scanning signal lines in order to selectively drive the scanning signal lines,
In the scanning signal line driving step, for each scanning signal line, application of the scanning signal generated in the first driving step to the one end and the scanning signal generated in the second driving step are performed. The driving method, wherein the application to the other end is alternately switched every frame period.

Images