JP2011043791A - Liquid crystal display device and method for driving liquid crystal display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To display a high-quality image suppressed in image noise by reducing horizontal line-shaped noise which is generated sometimes when a display device is driven with time division multiplexing by dividing an entire pixel region into a plurality of groups of divided pixel regions where a plurality of rows are treated as one group. <P>SOLUTION: As shown in (G) of the figure, a crosstalk generated when a load characteristic control signal B(2) is changed to a high level at a time t27 (a constant current load transistor of each of a plurality of pixels of an adjacent divided pixel region changes to on-states) and a crosstalk generated when the transistor is changed to an off-state at a time t29 is generated in different, positive and negative directions. As a result, those crosstalks cancel each other out, and a potential variation caused by the crosstalk of a liquid crystal drive voltage VPE(1') of each of a plurality of pixels of a lowermost line in a divided pixel region adjacent to respective pixels of an uppermost line of the adjacent divided pixel region becomes nearly 0 as shown by a dotted line in (H). <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a liquid crystal display device and a driving method of the liquid crystal display device, and more particularly to an active matrix type liquid crystal display device and a driving method of the liquid crystal display device.

  In recent years, a liquid crystal display device of LCOS (Liquid Crystal on Silicon) type is often used as a central part for projecting images in projector devices and projection televisions. This LCOS liquid crystal display device has a structure in which a transparent electrode, a liquid crystal layer, a reflective electrode arranged in a matrix, a liquid crystal driving element in which a liquid crystal driving circuit is formed on a silicon substrate, and the like overlap.

  In this liquid crystal display device, pixels are arranged at intersections of a plurality of data lines (column signal lines) and a plurality of gate lines (row scanning lines). As shown in FIG. 15, each pixel includes a pixel selection transistor Q, a signal holding capacitor Cs, and a reflective electrode PE. The pixel selection transistor Q has a gate connected to a gate line (row scanning line) G and a drain connected to a data line (column signal line) D. As shown in FIG. 15, the liquid crystal element LC has a configuration in which a liquid crystal display (liquid crystal layer) LCM is sandwiched between a reflective electrode (pixel drive electrode) PE and a counter electrode (common electrode) CE facing each other. Has been.

  In the liquid crystal element LC, the fixed voltage Vcom is applied to the common electrode CE, and various voltages according to the video signal are supplied to the reflective electrode (pixel drive electrode) PE, thereby controlling the light modulation rate of the liquid crystal display LCM. Display as video. Normally, since the liquid crystal element can be AC driven for long-term reliability, the reflection electrode (pixel drive electrode) PE modulates light according to the video signal with respect to the fixed voltage Vcom of the common electrode CE. AC driving is performed by alternately applying positive and negative voltages that have the same rate.

  In some cases, there is an application example where the voltage of the counter electrode is switched according to the timing of driving with the positive and negative voltages for the purpose of reducing the dynamic range of the video signal, but the basic idea is the same It is.

  In the conventional liquid crystal display device, the video signal is normally written to each pixel once per frame, and the video signal on the positive side and the negative side is signaled alternately with respect to the common electrode CE every frame. After writing into the storage capacitor Cs, the storage voltage is applied to the reflective electrode (pixel drive electrode) PE to drive the liquid crystal element LC with alternating current. In this case, there is an example of double speed driving in which the liquid crystal is AC driven at a frequency twice as high as the writing frequency, but the frequency is about 60 Hz to 120 Hz, and is not a high frequency in any case.

  On the other hand, if the liquid crystal element is driven with alternating current at a higher frequency so that the direct current component between the reflective electrode (pixel drive electrode) PE and the common electrode CE can be reduced to zero, it is possible to improve reliability such as prevention of burn-in. Connection and image display quality are also improved.

  Until now, prevention of deterioration of written signals such as countermeasures against feedthrough caused by parasitic capacitance of the pixel selection transistor (for example, refer to Patent Document 1) and countermeasures for leakage of a storage capacitor (for example, refer to Patent Document 2). A method is disclosed. However, it seems that efforts to drive alternating current at higher frequencies have not been studied much.

  For each of a plurality of pixels connected to the same scanning line, the storage capacitor of each pixel is alternately connected to the storage capacitor line corresponding to the scanning line and another storage capacitor line corresponding to the adjacent scanning line. The compensation voltage for compensating the direct current component between the pixel drive electrode and the counter electrode is inverted for each storage capacitor line, so that the image quality deterioration caused by the potential fluctuation of the common electrode line or the common electrode is reduced. A liquid crystal display device that prevents generation thereof has been conventionally known (see, for example, Patent Document 3).

JP 2006-10897 A JP 2002-250938 A JP 2004-354742 A

  As described above, it is desirable to drive the liquid crystal element with an alternating current at a high frequency as a means for improving reliability such as prevention of burn-in of the liquid crystal element, but it is positive with respect to the counter electrode voltage due to restrictions such as writing time to the pixel. It is difficult to alternately write video signals on the negative side and the negative side at high speed, and conventionally, the frequency of AC drive is only performed at a frame rate or about twice that frequency.

  Further, in the liquid crystal display device described in Patent Document 3, the polarity of the compensation voltage can be reversed only for each frame, and the image signal voltage has two types of voltages, positive and negative, with respect to the common electrode voltage Vcom. is necessary.

  The present invention has been made in view of the above points. The liquid crystal element is AC-driven at a higher speed than before, and the entire pixel portion is divided into a plurality of divided pixel portions each having a plurality of rows as one group. An object of the present invention is to provide a liquid crystal display device and a liquid crystal display device driving method capable of reducing a horizontal line noise that may occur when the image is driven and displaying a high-quality image with little image noise.

In order to achieve the above object, a liquid crystal display device according to the present invention includes a liquid crystal element in which a liquid crystal layer is sandwiched between an opposing pixel drive electrode and a common electrode, and a positive video signal sampled and held for a certain period. 1 sampling and holding means, a second sampling and holding means for sampling and holding a negative video signal for a certain period, and a positive electrode held by the first sampling and holding means when the first gate control signal is input The negative video signal is impedance-converted and applied to the pixel driving electrode, and when the second gate control signal is input, the negative video signal held by the second sampling and holding means is impedance-converted and applied to the pixel driving electrode. Impedance connected between the switching means and the connection point between the output terminal of the switching means and the pixel drive electrode and the ground potential or the power supply potential. A constant current load element for dancing transform, a pixel having, two data lines and a plurality of sets of data lines and a plurality of gate lines and a set is provided at the intersection of intersecting, respectively,
Provided for each of a plurality of sets of data lines, supplying a positive video signal to one of a set of two data lines and supplying a negative video signal to the other data line; A plurality of switches sequentially performed in units of a plurality of sets of data lines, a horizontal driving in which the plurality of switches are driven in units within a horizontal scanning period, and a plurality of gate lines are selected for each horizontal scanning period. The horizontal direction and vertical direction driving means for performing vertical direction driving, and the entire pixel portion composed of a plurality of pixels are grouped into h groups (h is a natural number of 2 or more), each pixel of a plurality of consecutive rows as one group. When divided into the divided pixel portions, the first gate control signal is supplied in a time-sharing manner to each divided pixel portion of the h divided pixel portions, and then the second gate control signal is supplied to the h divided pixel portions. Supplying in a time-sharing manner for each divided pixel portion, Gate control signal supply means that alternately repeats every predetermined vertical scanning period corresponding to the number of rows of the divided pixel portion, and the nth (n = 1, 2,... h-1) constant current loads in the divided pixel units so that the active periods of the constant current load elements in the divided pixel units do not overlap with the active periods of the constant current load elements in the (n + 1) th divided pixel unit. Load element control signal supply means for supplying a control signal to the element in a time-sharing manner for each of the divided pixel portions of the h divided pixel portions.

  In the liquid crystal display device of the present invention, the gate control signal supply unit includes the active period of the switching unit in the nth divided pixel unit and the n + 1th divided pixel unit among the h divided pixel units. The first and second gate control signals are supplied to the switching means in the h divided pixel portions in a time-sharing manner for each divided pixel portion so that the active periods of the switching means do not overlap with each other. .

In order to achieve the above object, the liquid crystal display device according to the present invention samples a liquid crystal element in which a liquid crystal layer is sandwiched between a pixel drive electrode and a common electrode facing each other, and a positive video signal for a predetermined period. First sampling and holding means for holding, second sampling and holding means for sampling and holding a negative video signal for a certain period, and holding by the first sampling and holding means when the first gate control signal is input The positive polarity video signal is impedance-converted and applied to the pixel driving electrode, and when the second gate control signal is input, the negative polarity video signal held by the second sampling and holding means is impedance-converted to the pixel driving electrode. Switching means to be applied to, and a connection point between the output terminal of the switching means and the pixel drive electrode and a ground potential or a power supply potential. A constant current load element for impedance conversion, a pixel having the two sets of data lines and a set of data lines and a plurality of gate lines are provided at the intersection of intersecting, respectively,
Provided for each of a plurality of sets of data lines, supplying a positive video signal to one of a set of two data lines and supplying a negative video signal to the other data line; A plurality of switches sequentially performed in units of a plurality of sets of data lines, a horizontal driving in which the plurality of switches are driven in units within a horizontal scanning period, and a plurality of gate lines are selected for each horizontal scanning period. The horizontal direction and vertical direction driving means for performing vertical direction driving, and the entire pixel portion composed of a plurality of pixels are grouped into h groups (h is a natural number of 2 or more), each pixel of a plurality of consecutive rows as one group. When dividing into the divided pixel portions, the divided pixels are supplied in a time division manner to all of the divided pixel portions arranged in every other order among the h divided pixel portions. Predetermined vertical run corresponding to the number of multiple lines After the first gate control signal supply means that repeats every period and the first gate control signal are supplied to all of the divided pixel portions arranged in every other order, h second gate control signals are supplied. Among the divided pixel portions, the supply of the divided pixel portions to all of the remaining divided pixel portions arranged in every other order to which the first gate control signal is not supplied is repeated for each predetermined vertical scanning cycle. And a second gate control signal supply means.

In order to achieve the above object, the driving method of the liquid crystal display device of the present invention is such that a plurality of sets of data lines and a plurality of gate lines intersect each other. Provided for each of a plurality of provided pixels and a plurality of sets of data lines, and supplies a positive video signal to one of a set of two data lines, and a negative polarity to the other data line A plurality of switches for sequentially supplying video signals in units of sets to a plurality of sets of data lines, horizontal driving for driving the plurality of switches in units within a horizontal scanning period, and a plurality of gate lines Horizontal direction and vertical direction driving means for performing vertical direction driving for selecting each horizontal scanning period, each of the plurality of pixels,
A liquid crystal element in which a liquid crystal layer is sandwiched between an opposing pixel drive electrode and a common electrode, a first sampling and holding means for sampling a positive video signal and holding it for a certain period, and sampling a negative video signal Second sampling and holding means for holding for a certain period of time, and when the first gate control signal is input, the positive polarity video signal held by the first sampling and holding means is impedance-converted and applied to the pixel drive electrode, When the second gate control signal is input, the switching means for impedance-converting the negative video signal held by the second sampling and holding means and applying it to the pixel drive electrode, and the output terminal of the switching means and the pixel drive electrode A constant current load element for impedance conversion, connected between the connection point and the ground potential or the power supply potential. To the liquid crystal display device,
When the entire pixel portion composed of a plurality of pixels is divided into divided pixel portions of h groups (h is a natural number of 2 or more), each pixel of a plurality of consecutive rows being one group, the first gate control signal is supplying the second gate control signal in a time-sharing manner for each of the divided pixel portions of the h divided pixel portions, after being supplied in a time-sharing manner for each of the divided pixel portions of the h divided pixel portions, It repeats alternately every predetermined vertical scanning period corresponding to the number of rows of the divided pixel portion, and among the h divided pixel portions, the nth (n = 1, 2,..., H−1). A control signal is sent to the constant current load elements in the h divided pixel sections so that the active period of the constant current load elements in the divided pixel section and the active period of the constant current load elements in the (n + 1) th divided pixel section do not overlap. supply in a time-sharing manner for each divided pixel portion of the h divided pixel portions. And butterflies.

  Further, the driving method of the liquid crystal display device according to the present invention includes an active period of the switching unit in the nth (n is a natural number) divided pixel portion among the plurality of divided pixel portions of the plurality of groups, and the (n + 1) th divided pixel portion. The first and second gate control signals are supplied in a time-sharing manner to the switching means in the divided pixel portions of a plurality of groups so that the active periods of the switching means in the divided pixel portion do not overlap.

In order to achieve the above object, the driving method of the liquid crystal display device of the present invention is such that a plurality of sets of data lines and a plurality of gate lines intersect each other. Provided for each of a plurality of provided pixels and a plurality of sets of data lines, and supplies a positive video signal to one of a set of two data lines, and a negative polarity to the other data line A plurality of switches for sequentially supplying video signals in units of sets to a plurality of sets of data lines, horizontal driving for driving the plurality of switches in units within a horizontal scanning period, and a plurality of gate lines Horizontal direction and vertical direction driving means for performing vertical direction driving for selecting each horizontal scanning period, each of the plurality of pixels,
A liquid crystal element in which a liquid crystal layer is sandwiched between an opposing pixel drive electrode and a common electrode, a first sampling and holding means for sampling a positive video signal and holding it for a certain period, and sampling a negative video signal Second sampling and holding means for holding for a certain period of time, and when the first gate control signal is input, the positive polarity video signal held by the first sampling and holding means is impedance-converted and applied to the pixel drive electrode, When the second gate control signal is input, the switching means for impedance-converting the negative video signal held by the second sampling and holding means and applying it to the pixel drive electrode, and the output terminal of the switching means and the pixel drive electrode A constant current load element for impedance conversion, connected between the connection point and the ground potential or the power supply potential. To the liquid crystal display device,
When the entire pixel portion composed of a plurality of pixels is divided into divided pixel portions of h groups (h is a natural number of 2 or more), each pixel of a plurality of consecutive rows being one group, the first gate control signal is For every predetermined vertical scanning period corresponding to the number of rows of the divided pixel units, the time divisional supply to all of the divided pixel units arranged in every other order among the h divided pixel units is performed. After the first gate control signal is repeatedly supplied to all of the divided pixel portions arranged in every other order, the second gate control signal is supplied to the first gate control among the h divided pixel portions. It is characterized in that the supply in a time-sharing manner to all of the remaining divided pixel portions arranged in every other order where no signal is supplied is repeated every predetermined vertical scanning period.

  According to the present invention, it occurs when the liquid crystal element is AC driven at a higher speed than before and the entire pixel portion is divided into a plurality of divided pixel portions each having a plurality of rows as one group and is driven in a time division manner. It is possible to reduce horizontal line noise and to display a high quality image with little image noise.

1 is a basic configuration diagram of an embodiment of a liquid crystal display device of the present invention. It is a circuit diagram of an example of the pixel circuit of the liquid crystal display device of this invention. It is a timing chart for demonstrating the outline | summary of the alternating current drive control of the liquid crystal display device of this invention. It is a figure which shows the relationship from the black level of a positive polarity video signal written in the pixel of a liquid crystal display device, and a negative polarity video signal to a white level. It is a block diagram of 1st Embodiment of the principal part of the liquid crystal display device of this invention. It is a timing chart of the signal of each part of FIG. It is a timing chart for demonstrating generation | occurrence | production of horizontal linear noise. It is a figure which shows an example of horizontal linear noise. It is a timing chart for demonstrating the method to suppress horizontal linear noise by one Embodiment of this invention apparatus. It is a circuit diagram of one embodiment of a driving circuit of a main part of the device of the present invention. It is a block diagram of 2nd Embodiment of the principal part of the liquid crystal display device of this invention. It is a timing chart of the signal of each part of Drawing 11. It is a block diagram of 3rd Embodiment of the principal part of the liquid crystal display device of this invention. It is a timing chart of the signal of each part of FIG. It is a block diagram of an example of one pixel of the conventional liquid crystal display device.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  FIG. 1 shows a basic configuration diagram of an embodiment of a liquid crystal display device according to the present invention. As shown in FIG. 1, the liquid crystal display device 100 according to the present embodiment includes a horizontal direction driving circuit 10, a vertical direction driving circuit 20, a pixel unit 30, a video signal 71a on the positive side with respect to the common electrode voltage, and a negative side. The two horizontal signal lines 5a and 5b for supplying the video signal 71b to the two video switches 1-1a and 1-1b, 1-2a and 1-2b,. Lines 6-1a and 6-1b, 6-2a and 6-2b,..., And gate lines 8-1, 8-2,. In the drawing, the suffix number after the hyphen of each symbol indicates that the same type of component is in a different position. Also, the lowercase letter a following the suffix number indicates the first system of the two systems, and b indicates the second system. FIG. 1 shows a part of the entire component. FIG. 1 shows a basic configuration of a liquid crystal display device according to the present invention. Specifically, in the liquid crystal display device of this embodiment, as will be described later, a plurality of rows are arranged in one group. The liquid crystal display device is divided into a plurality of groups of divided pixel portions in the vertical direction and driven in a time division manner.

  The pixel unit 30 is arranged in a matrix at intersections of two lines of data lines (6-1a and 6-1b,...) And gate lines (8-1, 8-2,...). It consists of pixels 41, 42, 51, 52, etc. The horizontal driving circuit 10 includes pixel selection transistors for the pixels 41, 51,... In the first column via two systems of switches 1-1a, 1-1b and two systems of data lines 6-1a, 6-1b. The drains of Q1 and Q2 are connected respectively.

  Similarly, the horizontal driving circuit 10 includes pixels 42, 52,... In the second column via two systems of switches 1-2a and 1-2b and two systems of data lines 6-2a and 6-2b. Are connected to the drains of the pixel selection transistors of the second column and the drains of the two pixel selection transistors of the pixels in the third and subsequent columns in the same manner via two systems of switches and two systems of data lines, respectively.

  The vertical driving circuit 20 is commonly connected to the gates of the two pixel selection transistors Q1 and Q2 of the pixels 41, 42,... In the first row in the pixel unit 30 through the gate line 8-1. Yes. Similarly, the vertical driving circuit 20 is commonly connected to the gates of two pixel selection transistors of each pixel in the same row in the pixel unit 30 through each gate line.

  Further, the controller 60 supplies various clock signals generated so as to be synchronized with the input video signals 71a and 71b to the horizontal direction driving circuit 10 and the vertical direction driving circuit 20 (paths are not shown), and the input video signal 71a, Each of the horizontal and vertical scans is driven by driving the data lines (6-1a, 6-1b,...) And the gate lines (8-1, 8-2,...) In synchronization with 71b. The pixel selection accompanied by is performed.

  Next, an outline of the operation of the embodiment shown in FIG. 1 will be described. The data line 6-1a supplies a video signal 71a on the positive side with respect to the common electrode voltage of the liquid crystal. At the same time, the data line 6-1b supplies the video signal 71b on the negative side with respect to the common electrode voltage. The pixel selection transistors Q1 and Q2 are simultaneously turned on by a voltage applied to the gate via the gate line 8-1. As a result, the positive video signal 71a supplied from the data line 6-1a is written into the storage capacitor C1 via the drain and source of the pixel selection transistor Q1. At the same time, the negative video signal 71b supplied from the data line 6-1b is written into the storage capacitor C2 via the drain and source of the pixel selection transistor Q2.

  Subsequently, the pixel selection transistors Q1 and Q2 are simultaneously turned off by a voltage applied to the gate via the gate line 8-1. As a result, the positive and negative video signals 71a and 71b are held in the holding capacitors C1 and C2, respectively, until the next video signals 71a and 71b for which the pixel selection transistors Q1 and Q2 are next turned on are written.

  The positive and negative video signals 71a and 71b held in the holding capacitors C1 and C2, respectively, are read out through buffer amplifiers A1 and A2 which are impedance conversion circuits having high input resistances, respectively, and changeover switches S1 and S2 Are alternately selected, and the liquid crystal is AC driven by changing the voltage of the reflective electrode 4 (pixel drive electrode PE).

  FIG. 2 is a pixel circuit diagram showing in more detail one pixel constituting the liquid crystal display device 100 of the present embodiment shown in FIG. As shown in FIG. 2, one pixel of the liquid crystal display device 100 holds pixel selection transistors Q1 and Q2 for writing positive and negative pixel signals in parallel and image signal voltages of respective polarities. The same as the conventional liquid crystal element shown in FIG. 15 comprising two independent storage capacitors Cs1 and Cs2 (corresponding to C1 and C2 in FIG. 1), transistors Q3 to Q6 and Q9, pixel drive electrodes (reflection electrodes) PE, and the like. The liquid crystal element LC is configured.

  The transistor Q1 and the holding capacitor Cs1 constitute a first sampling and holding unit that samples a positive video signal and holds it for a certain period. The transistor Q2 and the holding capacitor Cs2 constitute a second sampling and holding unit that samples the negative video signal and holds it for a certain period.

  The impedance conversion source follower circuit including the transistors Q3, Q5, and Q9 constitutes the buffer amplifier A1 of FIG. The impedance conversion source follower circuit including the transistors Q4, Q6, and Q9 constitutes the buffer amplifier A2 of FIG. A transistor Q5 having a drain connected to the source of the transistor Q3 and a transistor Q6 having a drain connected to the source of the transistor Q4 are switching transistors corresponding to the changeover switches S1 and S2 in FIG. 1, respectively. The sources of the transistors Q5 and Q6 are connected to the reflective electrode (pixel drive electrode) PE of the liquid crystal element LC.

  Note that the storage capacitor C3 in FIG. 1 is not shown in FIG. This is because the holding capacitor C3 can be substituted by the parasitic capacitances of the transistors Q5 and Q6 and the parasitic capacitance of the liquid crystal, and may not be formed if the leakage current of the node of the reflective electrode PE is sufficiently small. .

  The pixel portion data line is composed of a pair of positive data line Di + and negative data line Di− for each pixel circuit, and video signals having different polarities sampled by a data line driving circuit (not shown) are provided. Supplied. The drain terminals of the pixel selection transistors Q1 and Q2 are respectively connected to a positive data line Di + (corresponding to, for example, 6-1a in FIG. 1) and a negative data line Di− (corresponding to, for example, 6-1b in FIG. 1). Each gate terminal is connected to a row scanning line Gj (corresponding to, for example, the gate line 8-1 in FIG. 1) for the same row.

  The transistors Q3 and Q5 constitute switching means for impedance-converting the positive video signal held in the holding capacitor Cs1 and applying it to the pixel drive electrode PE when the first gate control signal is inputted via the wiring S +. Also, the transistors Q4 and Q6 impedance-convert the negative video signal held in the holding capacitor Cs2 when the second gate control signal is input via the wiring S-, and apply it to the pixel drive electrode PE. The switching means is configured. The transistor Q9 is a constant current load transistor.

  Next, an outline of AC drive control of the liquid crystal display device 100 of the present embodiment will be described with reference to the timing chart of FIG. FIG. 3 is a timing chart for explaining an outline of AC drive control of the liquid crystal display device according to the present invention. 3A shows the vertical synchronization signal VD, and FIG. 3B shows a control signal for the wiring B applied to the gate of the transistor Q9 in the pixel circuit of FIG. Since the transistor Q9 is a constant current load element of the source follower buffer circuit, the control signal for the wiring B is a load element control signal (hereinafter also referred to as a load characteristic control signal). FIG. 3C shows a gate control signal of the wiring S + applied to the gate of the switching transistor Q5 that transfers the positive drive voltage in the pixel circuit, and FIG. 3D shows the negative electrode in the pixel circuit. 4 shows each signal waveform of a gate control signal of the wiring S− applied to the gate of the switching transistor Q6 that transfers the active drive voltage.

  FIG. 4 shows the relationship from the black level to the white level of the positive video signal I and the negative video signal II written to the pixel. The positive video signal I has a black level when the level is minimum and a white level when the level is maximum, whereas the negative video signal II has a white level when the level is minimum and a black level when the level is maximum. The inversion center of the positive video signal I and the negative video signal II is indicated by III.

  In FIG. 4, the positive polarity video signal I indicates the black level when the level is minimum and the white level when the level is maximum, and the negative polarity video signal II indicates the white level when the level is minimum and the black level when the level is maximum. However, in the pixel circuit of the liquid crystal display device of the present invention, the positive video signal I is a white level when the level is minimum, a black level when the level is maximum, and the negative video signal II is black when the level is minimum. The level may be a white level at the maximum.

  In the pixel circuit shown in FIG. 2, when a scanning pulse is supplied from the vertical driving circuit (20 in FIG. 1), the pixel selection transistors Q1 and Q2 are simultaneously turned on, and the holding capacitors Cs1 and Cs2 have a positive polarity and a negative polarity, respectively. Video signal voltage is stored. As described above, the circuit section including the transistors Q3, Q5, and Q9 and the circuit section including the transistors Q4, Q6, and Q9 are impedance conversion source follower circuits (so-called source follower buffers). The input transistor, the transistors Q5 and Q6 function as a polarity switching switching transistor, and the transistor Q9 functions as a constant current source load.

  The input resistance of the source follower buffer is almost infinite. For this reason, as in the conventional active matrix liquid crystal display device, the charges accumulated in the holding capacitors Cs1 and Cs2 are held without leakage until a signal is newly written after one frame.

  The switching transistors Q5 and Q6 switch and send the output signal of the source follower buffer to a liquid crystal element LC composed of a reflective electrode (pixel drive electrode) PE, a liquid crystal display (hereinafter also referred to as a liquid crystal layer) LCM, and a common electrode CE. To do. The gate terminals of the transistor Q5 for switching the positive video signal and the transistor Q6 for switching the negative video signal are independent, and each is connected to the wirings S + and S- in the row direction for the same row pixel. Has been.

  When the gate control signal of the wiring S + shown in FIG. 3C is at a high level, the positive side switching transistor Q5 is turned on, and the load characteristic control signal supplied to the wiring B in this period is shown in FIG. As shown in the figure, when the level is high, the source follower buffer circuit is activated, and the pixel drive electrode PE node is charged to the positive video signal level. When the positive drive voltage of the pixel drive electrode PE is fully charged, the load characteristic control signal of the wiring B is set to low level, and the gate control signal of the wiring S + is also switched to low level at that time. Then, the pixel drive electrode PE is in a floating state, and the positive drive voltage is held in the liquid crystal capacitor.

  On the other hand, when the gate control signal of the wiring S− shown in FIG. 3D is at a high level, the negative polarity side switching transistor Q6 is turned on, and the load characteristic control signal supplied to the wiring B during this period is shown in FIG. ), The source follower buffer circuit becomes active and the pixel drive electrode PE node is charged to the negative video signal level. When the negative polarity drive voltage of the pixel drive electrode PE is completely charged, the load characteristic control signal of the wiring B is set to the low level, and the gate control signal of the wiring S− is also switched to the low level at that time. Then, the pixel drive electrode PE is in a floating state, and the negative drive voltage is held in the liquid crystal capacitor.

  Hereinafter, the pixel drive electrode PE of the liquid crystal element has positive polarity by repeating the operation of intermittently activating the constant current load transistor Q9 in synchronization with the switching in which the switching transistors Q5 and Q6 are alternately turned on. A drive voltage VPE converted into an alternating current with each negative video signal is applied as shown in FIG.

  In the present embodiment, the held charge is not directly transferred to the pixel driver, but is supplied with a voltage via the source follower buffer circuit. There is no problem of neutralization, and driving without voltage level attenuation can be realized even if polarity switching is performed many times.

  Further, Vcom shown in FIG. 3F represents a voltage applied to the common electrode CE formed on the counter substrate of the liquid crystal display device. The substantial AC drive voltage of the liquid crystal display LCM is a difference voltage between the applied voltage Vcom of the common electrode CE and the applied voltage of the pixel drive electrode PE. In the present embodiment, as shown in FIG. 3F, the applied voltage Vcom of the common electrode CE is synchronized with pixel polarity switching with respect to a reference level substantially equal to the inversion reference level Vc of the pixel drive electrode potential. Inverted. As a result, the absolute value of the potential difference between the applied voltage Vcom of the common electrode CE and the applied voltage of the pixel drive electrode PE is always the same, and the liquid crystal display LCM has an AC voltage having no DC component as shown in FIG. VLC is applied. The applied voltage Vcom of the common electrode CE is output from the controller 60 shown in FIG.

  As described above, in this embodiment, once the video signals 71a and 71b on the positive side and the negative side are written into the holding capacitors C1 (Cs1) and C2 (Cs2) once per frame, the video of the next frame is obtained. The liquid crystal element can be AC driven by alternately switching the changeover switches S1 (Q5) and S2 (Q6) any number of times during one frame period until the signal is written.

  That is, according to the pixels of FIGS. 1 and 2, the AC driving frequency of the liquid crystal element can be freely set by the switching cycle of the positive and negative driving voltages regardless of the vertical scanning frequency. The liquid crystal driving frequency can be dramatically increased as compared with the above. Thereby, the present embodiment can realize burn-in prevention and reliability improvement.

  In the present embodiment, the amplitude of the drive voltage on the pixel (PE) side can be reduced to about ½ or less by switching the applied voltage of the common electrode CE in a phase opposite to the applied drive voltage of the pixel drive electrode PE. . As a result, the required withstand voltage of the transistors constituting the pixel circuit and the peripheral scanning circuit is greatly reduced, the application of a special high withstand voltage structure and process is not required, and the device cost can be reduced.

  Further, in this embodiment mode, a driver unit such as a pixel circuit can be configured with a low withstand voltage and small transistor as described above, so that a higher pixel density liquid crystal display device can be realized, and the per unit channel width can be reduced by reducing the transistor withstand voltage. Therefore, it is possible to employ a transistor having a high driving capability, and thus it is possible to easily cope with a high-speed driving operation.

  Further, in this embodiment, as shown in FIG. 3A, the load characteristic control signal of the wiring B is used as a pulse train, and the constant current load transistor (Q9 in FIG. 2) of the source follower buffer circuit is not always active. The polarity switching switching transistors (Q5 and Q6 in FIG. 2) are controlled so as to be active only during a limited period within the conduction period. This is because a reduction in current consumption in the liquid crystal display device is taken into consideration. For example, even if the current of the steady source follower buffer circuit per pixel circuit is a very small current of 1 μA, the current consumption becomes large under the condition that all the pixels of the liquid crystal display device constantly consume the current. There is a problem that. For example, in a full high-definition (2 million pixels) liquid crystal display device, the current consumption reaches 2 A.

  Therefore, in the present embodiment, as shown in FIGS. 3A to 3C, the polarity switching switching transistor (Q5) in which the gate control signal supplied through the wirings S + and S- is at a high level. , Q6) only during the conduction period, the load characteristic control signal supplied via the wiring B is set to the high level to limit the driving period of the constant current load transistor (Q9 in FIG. 2) of the source follower buffer circuit. As a result, immediately after the electrode voltage VPE of the liquid crystal element is charged and discharged to the target level as shown in FIG. 3E, the constant current load transistor (Q9) is immediately turned off by setting the load characteristic control signal to the low level. The current of the source follower buffer circuit is stopped. Therefore, according to the present embodiment, it is possible to suppress a substantial current consumption even though all the pixels are provided with the source follower buffer circuit (buffer amplifier).

  Further, according to the present embodiment, when the liquid crystal element LC is AC driven by switching the positive / negative driving voltage by the switching means, the signal voltage held in the holding capacitors C1, C2 (Cs1, Cs2) is directly applied to the pixel. Instead of transmitting to the drive electrode PE, the pixel drive electrode PE is driven through the buffer amplifiers A1 (Q3) and A2 (Q4). Therefore, even when the switching transistors Q5 and Q6 are alternately switched at a high speed several times, the signal is output. There is an advantage that more ideal AC driving can be realized without lowering the voltage level.

  Furthermore, according to the present embodiment, as shown in FIG. 2, the transistor Q9 is connected as a common load element of the two buffer amplifiers between the output terminals of the switching transistors Q5 and Q6 and the ground potential, thereby 1 The number of transistors per pixel can be reduced, and higher pixel density can be realized. Further, by reducing the number of transistors, features such as high yield and low cost of the pixel circuit can be obtained.

  Incidentally, in the above-described embodiment described with the timing chart of FIG. 3, the example in which intermittent active control is performed so that current does not flow constantly to the source follower buffer circuit has been described. The embodiment described below is further characterized in that control means is provided so that all the pixels are not turned on at the same time.

  FIG. 5 shows a configuration diagram of a first embodiment of a main part of a liquid crystal display device according to the present invention. In this embodiment, polarity inversion control and active control of the source follower buffer circuit are realized with a time difference in the vertical direction of the screen.

  As shown in FIG. 5, in the present embodiment, divided pixel units 90-1, 90-2,..., In which the pixel unit 30 in FIG. 1 is divided into h in the vertical direction (h is a natural number of 2 or more). 90-h, a shift of h stages for shifting the polarity switching gate control signal of the wiring S +, the polarity switching gate control signal of the wiring S-, and the load characteristic control signal of the wiring B in synchronization with the same shift clock SCK. This is a configuration having registers 91a, 91b and 91c. The shift registers 91a, 91b, and 91c correspond to the vertical driving circuit 20 shown in FIG. FIG. 5 shows only circuit portions necessary for active control of the source follower buffer circuit, and illustration of the horizontal driving circuit 10 and the like is omitted.

  Each of the divided pixel portions 90-1, 90-2,..., And 90-h includes groups # 1, # 2,. This is a divided pixel portion. The shift register 91a is connected to the input terminals S + (1), S + (2),..., And S + (h) of the divided pixel portions 90-1, 90-2,. Are supplied from the output terminals of the first stage, the second stage,..., The h stage. Further, the shift register 91b includes input terminals S- (1), S- (2),..., And S- (h) of the divided pixel units 90-1, 90-2,. In addition, the gate control signal for switching the polarity of the wiring S- is supplied from the output terminals of the first stage, the second stage,. Further, the shift register 91c is connected to the input terminals B (1), B (2),..., And B (h) of the divided pixel portions 90-1, 90-2,. The B load characteristic control signal is supplied from the output terminals of the first stage, the second stage,.

  FIG. 6 shows a timing chart of signals of the respective parts in FIG. FIG. 6A shows the shift clock SCK supplied to the shift registers 91a, 91b and 91c. In synchronism with this shift clock SCK, the shift register 91a shifts the polarity switching gate control signal of the wiring S + shown in FIG. 6 (B) from the output terminals of the first, second and h stages. 6 (C), (D), and (E) are output, and the input terminals S + (1), S + (2), and S + of the divided pixel units 90-1, 90-2, and 90-h are output. Supply to (h). Subsequently, the shift register 91b shifts the polarity switching gate control signal of the wiring S− shown in FIG. 6F, and outputs the output signals from the first, second, and h-stage output terminals in FIG. The gate control signals shown in (H) and (I) are output, and the input terminals S- (1), S- (2), and S- (h) of the divided pixel units 90-1, 90-2, and 90-h are output. ).

  On the other hand, the shift register 91c shifts the load characteristic control signal of the wiring B shown in FIG. 6 (J), and the output terminals of the first stage, the second stage, and the h stage from FIG. 6 (K), (L), The load characteristic control signal shown in (M) is output and supplied to the input terminals B (1), B (2), and B (h) of the divided pixel units 90-1, 90-2, and 90-h.

  According to this embodiment, it is possible to perform polarity inversion and buffer active control with a time difference for the divided group in the vertical direction of the screen, and the current value is dispersed and averaged in time, so that the instantaneous overcurrent is caused. Malfunctions and failures can be avoided. In order to prevent the influence of the control time difference from affecting the display characteristics, the frequency of the shift clock SCK may be selected to be sufficiently higher than the polarity inversion frequency.

  As described above, in the embodiment shown in FIG. 5, the entire pixel unit 30 composed of a plurality of pixels constituting the display screen is divided into a plurality of groups of divided pixel units 90 − each pixel of a plurality of consecutive rows as one group. When divided into 1 to 90-h, the plurality of constant current load transistors Q9 in the plurality of divided pixel portions are controlled in an active manner in a time-division manner with a predetermined time difference for each divided pixel portion. Prevent pixel buffer amplifiers from becoming active at the same time.

  As a result, in this embodiment, it is possible to prevent the current consumed by the buffer amplifier from flowing in a concentrated manner in all the pixels, and to ensure the reliability of the power supply wiring pattern and the like and to stabilize the operation. However, there are also side effects. This phenomenon will be described below with reference to FIG.

  FIG. 7 is an enlarged view of a part of the timing chart of FIG. 6. In particular, gate control signals and load characteristics of the divided pixel unit 90-1 of group # 1 and the divided pixel unit 90-2 of group # 2 in FIG. The control signal and the waveform of the liquid crystal drive voltage VPE applied to the liquid crystal layer LCM are also shown. Compared to the timing chart of FIG. 3, the timing chart of FIG. 7 shows the time axis in an enlarged manner.

  In synchronization with the shift clock SCK shown in FIG. 7 (A), as shown in FIG. 7 (B) at time t1, the polarity switching gate control signal (hereinafter referred to as the following) is input to the input terminal S + (1). When the positive polarity switch control signal S + (1)) becomes high level, the transistor Q5 shown in FIG. 2 of each of the plurality of pixels of the divided pixel unit 90-1 of the group # 1 is turned on. As shown in FIG. 7D, since the load characteristic control signal B (1) input to the input terminal B (1) described above is at a low level, it is in the same OFF state as before. For this reason, the liquid crystal drive voltage VPE temporarily rises as shown in FIG. 7H due to the parasitic capacitance of the gate of the transistor Q5. Note that the liquid crystal drive voltage VPE (1 ′) indicated by a dotted line in FIG. 7H is the pixel of the line closest to the divided pixel unit 90-2 among the pixels of the plurality of lines in the divided pixel unit 90-1. The liquid crystal drive voltage VPE indicates the liquid crystal drive voltage VPE, and the liquid crystal drive voltage VPE (1) indicated by the solid line indicates the liquid crystal drive voltage VPE of each pixel in the divided pixel portion 90-1 of the other lines.

  Subsequently, during the period from the next rise time t2 of the shift clock SCK to the next rise time t4, as shown in FIG. 7D, the load characteristic control signal B (1) becomes high level, As a result, the transistor Q9 shown in FIG. 2 of each of the plurality of pixels in the divided pixel section 90-1 of the group # 1 is turned on, so that the source follower buffer circuit including the transistors Q5 and Q9 is activated. During the period from time t2 to time t4, each pixel of the divided pixel unit 90-1 is always driven by the source follower buffer circuit, and the positive video signal from the storage capacitor Cs1 is applied to the pixel drive electrode PE. Thus, the liquid crystal driving voltage changes as shown in FIG.

  Subsequently, at time t4, the load characteristic control signal B (1) becomes low level, and the transistors Q9 of each of the plurality of pixels of the divided pixel unit 90-1 are turned off, but the positive polarity switch control signal S + (1). Since the transistor Q5 is still on and the transistor Q5 is in the on state, the liquid crystal driving voltage changes in a direction to return to the off potential of the transistor Q9 as shown in FIG. When the positive polarity switch control signal S + (1) also becomes low level at time t5, the transistor Q5 is also turned off in the same manner as the transistor Q9, so that the pixel drive electrode PE is in a floating state, and the positive polarity drive voltage is applied to the liquid crystal capacitance. The liquid crystal driving voltage of each pixel in the divided pixel portion 90-1 is changed as shown in FIG.

  As shown in FIG. 7C, the polarity switching input to the above-described input terminal S- (1) at time t7 after the elapse of the vertical scanning period corresponding to the number of lines of the divided pixel unit 90-1 from time t1. When the gate control signal for use (hereinafter referred to as negative polarity switch control signal) S- (1) becomes high level, the transistor Q6 shown in FIG. 2 of each of the plurality of pixels of the divided pixel section 90-1 of the group # 1 is turned on. However, at this point in time, as shown in FIG. 7D, the load characteristic control signal B (1) is at a low level, so that the transistor Q9 is in the same OFF state as before. For this reason, the liquid crystal drive voltage VPE temporarily rises as shown in FIG. 7H due to the parasitic capacitance of the gate of the transistor Q6.

  Hereinafter, during a period when the load characteristic control signal B (1) is at a high level from time t8 to t10, the source follower buffer circuit composed of the transistors Q6 and Q9 becomes active, and the negative video signal from the holding capacitor Cs2 is the pixel. Applied to the drive electrode PE, the liquid crystal drive voltage of each pixel in the divided pixel portion 90-1 changes to a lower level than when a positive video signal is applied, as shown in FIG.

  Thereafter, when the load characteristic control signal B (1) becomes low level at time t10 and the negative polarity switch control signal S- (1) becomes low level at time t11, the liquid crystal drive of each pixel in the divided pixel unit 90-1 is performed. The voltage changes as shown in FIG.

  Note that the positive polarity switch control signal S + (2) applied to the input terminal S + (2) of the divided pixel portion 90-2 of the group # 2 and the negative polarity switch control inputted to the input terminal S- (2). The load characteristic control signal B (2) input to the signal S- (2) and the input terminal B (2) is the above positive polarity switch as shown in FIGS. Since the control signal S + (1), the negative polarity switch control signal S- (1), and the load characteristic control signal B (1) change with a delay of one clock cycle of the shift clock SCK, The liquid crystal driving voltage of each pixel changes as shown in FIG.

  Here, among the pixels of the plurality of lines in the divided pixel unit 90-1, each pixel of the lowermost line closest to the divided pixel unit 90-2 is the uppermost line of the divided pixel unit 90-2. Since it is adjacent to each pixel, it is easy to crosstalk the potential fluctuation through the pixel drive electrode PE, and as shown by the dotted line in FIG. 7H, the lowermost line in the divided pixel portion 90-1 The liquid crystal drive voltage VPE (1 ′) of each pixel is relative to the liquid crystal drive voltage VPE (1) of each pixel in a line other than the lowest stage in the divided pixel portion 90-1 indicated by a solid line in FIG. In other words, the crosstalk amount is superposed.

  That is, each pixel of the divided pixel unit 90-1 is always driven by the source follower buffer circuit during the period from time t2 to t4 and t8 to t10 shown in FIG. This is not affected by the period of time t3 to t5 and t9 to t11 when each of the pixels is driven. However, when the load characteristic control signal B (1) is at a low level, the source follower buffer circuit is not driven and is in an electrically floating state. Each pixel in the line is also cross-talked with a slight potential change of each pixel in the uppermost line of the adjacent divided pixel unit 90-2. As a result, during the period when the load characteristic control signal B (1) is low and the transistor Q9 is off, the cross-talked potential fluctuation is held as the pixel potential.

  The effect of the above crosstalk is the same in the other divided pixel units 90-2 to 90-h, and the liquid crystal driving voltage VPE of each pixel in the lowermost line of each divided pixel unit is the same in the adjacent divided pixel units. The potential change of each pixel in the uppermost line becomes a potential superimposed as crosstalk.

  Since the potential fluctuation superimposed by the crosstalk becomes the luminance difference of the display image as it is, the divided pixel portions 90-1 to 90- (h-1) are displayed on the screen as indicated by N1 to Nh-1 in FIG. The luminance of each pixel in the lowermost line is lower than the luminance of each pixel in the other lines, and is displayed as horizontal line noise, leading to a significant reduction in quality of the display image.

  Therefore, the horizontal line noise is reduced by the driving method of the liquid crystal display device of the present invention described below.

  FIG. 9 shows a timing chart of the first embodiment of the driving method of the liquid crystal display device according to the present invention. In the present embodiment, a liquid crystal display device in which a pixel unit including a plurality of pixels as illustrated in FIG. 5 is divided in a vertical direction into a plurality of divided pixel units each having a plurality of rows as one group and is driven in a time division manner. In this case, each divided drive unit is driven according to the timing chart shown in FIG.

  The timing chart shown in FIG. 9 is obtained by enlarging the time axis of the timing chart of FIG. 6, and in particular, the positive polarity of the divided pixel unit 90-1 of group # 1 and the divided pixel unit 90-2 of group # 2 in FIG. 5 shows waveforms of a switch control signal, a negative polarity switch control signal, a load characteristic control signal, and a liquid crystal driving voltage VPE applied to the liquid crystal layer LCM.

  Each pixel of the divided pixel portion 90-1 of the group # 1 has a positive polarity as shown in FIG. 9B at time t21 in synchronization with the shift clock SCK shown in FIG. The switch control signal S + (1) becomes high level, the transistor Q5 shown in FIG. 2 is turned on, and the liquid crystal driving voltage VPE (1) is shown by a solid line in FIG. 9 (H) due to the parasitic capacitance of the gate of the transistor Q5. As shown, it rises once.

  Subsequently, during the period from the next rise time t22 of the shift clock SCK to the next rise time t24, as shown in FIG. 9D, the load characteristic control signal B (1) becomes high level, As a result, the transistor Q9 shown in FIG. 2 of each of the plurality of pixels in the divided pixel section 90-1 of the group # 1 is turned on, so that the source follower buffer circuit including the transistors Q5 and Q9 is activated. During the period from time t22 to time t24, each pixel of the divided pixel unit 90-1 is always driven by the source follower buffer circuit, and the positive video signal from the storage capacitor Cs1 is applied to the pixel drive electrode PE. Thus, the liquid crystal driving voltage VPE (1) changes as shown by the solid line in FIG.

  Subsequently, at time t24, the load characteristic control signal B (1) becomes low level, and the transistors Q9 of each of the plurality of pixels of the divided pixel unit 90-1 are turned off. On the other hand, since the positive polarity switch control signal S + (1) is still at the high level at the time t24, the transistor Q5 is in the on state, so that the liquid crystal drive voltage VPE (1) is as shown by a solid line in FIG. It changes in a direction to return to the off potential of the transistor Q9. When the positive polarity switch control signal S + (1) also becomes low level at time t25, the transistor Q5 is also turned off similarly to the transistor Q9, so that the pixel drive electrode PE is in a floating state, and the positive polarity drive voltage is applied to the liquid crystal capacitance. The liquid crystal driving voltage VPE (1) of each pixel of the divided pixel portion 90-1 changes as shown by a solid line in FIG.

  Here, in the case of FIG. 7, a positive polarity switch control signal S + (2), a negative polarity switch control signal S- (2) applied to each pixel of the divided pixel portion 90-2 of the group # 2, and load characteristics. The control signal B (2) is delayed by one clock cycle of the shift clock SCK from the positive polarity switch control signal S + (1), the negative polarity switch control signal S- (1), and the load characteristic control signal B (1). I was trying to change. Therefore, a period (t2 to t4, t8 to t10) in which the constant current load transistor Q9 of each pixel of the divided pixel unit 90-1 is actively controlled, and the constant current load transistor Q9 of each pixel of the divided pixel unit 90-2. Are partially overlapped with periods (t3 to t5, t9 to t11), and the liquid crystal drive voltage VPE of each pixel in the lowermost line of the divided pixel unit 90-1 is affected by crosstalk. It was happening.

  On the other hand, in this embodiment, as shown in FIG. 9E, at time t26 after time t25 when both the transistors Q5 and Q9 of each pixel of the divided pixel portion 90-1 are turned off. The switch control signal S + (2) is set to high level. Then, during the period from time t27 to time t29 after one shift clock cycle, as shown in FIG. 9G, the load characteristic control signal B (2) is set to the high level, and each pixel of the divided pixel unit 90-2 The constant current load transistor Q9 is actively controlled.

  That is, in the present embodiment, the period (t22 to t24 and t32 to t34 described later) during which the constant current load transistor Q9 of each pixel of the divided pixel unit 90-1 is actively controlled, and the divided pixel unit 90-2 The period (t27 to t29 and later-described t37 to t39) during which the constant current load transistor Q9 of each pixel is actively controlled does not overlap (overlap).

  As shown in FIG. 9E, the positive polarity switch control signal S + (2) is set to the high level during a period from time t26 to time t30 after four shift clock cycles, thereby dividing the pixel unit 90-2. The transistor Q5 shown in FIG. 2 of each of the plurality of pixels is turned on. Within a period from time t27 to time t29 during the on-period of the transistor Q5, a plurality of pixels of the divided pixel unit 90-2 are generated by the high level load characteristic control signal B (2) shown in FIG. The transistor Q9 shown in FIG. 2 is also turned on. As a result, the source follower buffer circuit including the transistors Q5 and Q9 of each of the plurality of pixels of the divided pixel unit 90-2 is activated.

  The period from time t27 to time t29 is always driven by the source follower buffer circuit, and the positive video signal from the storage capacitor Cs1 of each of the plurality of pixels of the divided pixel unit 90-2 is the pixel drive electrode. When applied to PE, the liquid crystal drive voltage VPE (2) changes as shown in FIG.

  Subsequently, as shown in FIG. 9G, the load characteristic control signal B (2) becomes low level at time t29, and the transistors Q9 of each of the plurality of pixels in the divided pixel portion 90-2 are turned off. On the other hand, at time t29, since the positive polarity switch control signal S + (2) is still at the high level and the transistor Q5 is in the on state, the liquid crystal drive voltage VPE (2) of each pixel in the divided pixel unit 90-2. Changes in a direction to return to the off-state potential of the transistor Q9 as shown in FIG. When the positive polarity switch control signal S + (2) becomes low level at time t30, the transistor Q5 is turned off in the same manner as the transistor Q9 in each pixel in the divided pixel section 90-2.

  Here, even during a period (time t27 to t29) in which the source follower buffer circuit including the transistors Q5 and Q9 of each of the plurality of pixels of the divided pixel unit 90-2 is actively controlled (time t27 to t29), the maximum of the divided pixel unit 90-1 is obtained. Crosstalk from a plurality of pixels in the lowermost line of the divided pixel unit 90-1 occurs in the plurality of pixels in the lower line through the pixel drive electrode PE.

  However, during the period from time t27 to t29, as shown in FIGS. 9B and 9D, the positive polarity switch control signal S + (1) and the load characteristic control signal B (1) are always low. At the level, the transistors Q5 and Q9 of each of the plurality of pixels in the divided pixel unit 90-1 are turned off, and the source follower buffer circuit composed of them is in an electrically floating state.

  For this reason, as shown in FIG. 9G, the load characteristic control signal B (2) changes to the high level at time t27 (the transistors Q9 of the plurality of pixels of the divided pixel unit 90-2 change to ON. ) And the crosstalk at the time of changing to a low level at time t29 (transistor Q9 of each of the plurality of pixels of the divided pixel unit 90-2 is turned off) are generated in different directions. As a result, the crosstalk is canceled out, and the liquid crystal driving voltage VPE (1 ′) of each of the plurality of pixels in the lowermost line in the divided pixel portion 90-1 is as shown by a dotted line in FIG. In the period from time t27 to time t29, the potential fluctuation due to the above crosstalk becomes almost zero.

  Similarly to the above phenomenon, the pixel electrode accompanying the on / off of the transistor Q5 of each of the plurality of pixels in the divided pixel portion 90-2 by the positive polarity switch control signal S + (2) shown in FIG. The potential fluctuation may also affect the liquid crystal driving voltage VPE of each of the plurality of pixels on the lowermost line in the divided pixel unit 90-1.

  However, in this embodiment, the positive polarity switch control signals S + (1) and S + (2) are in a high level period during which the transistor Q5 is turned on, as shown in FIGS. (That is, the active period of the switching means composed of the transistors Q3 and Q5 applied to the pixel drive electrode PE by converting the impedance of the positive video signal) does not overlap at all. For this reason, in the present embodiment, pixel electrode potential fluctuations associated with on / off of the transistors Q5 of each of the plurality of pixels in the divided pixel unit 90-2 are affected by the lowermost line in the divided pixel unit 90-1. The influence on the liquid crystal driving voltage VPE of each of the plurality of pixels can be eliminated.

  Thereafter, at time t31 after the vertical scanning period corresponding to the number of lines of the divided pixel portion 90-1 from time t21, as shown in FIG. 9C, the negative polarity switch control signal S- (1) is at the high level. become. Further, at time t36 after the vertical scanning period corresponding to the number of lines of the divided pixel portion 90-1 from time t26, as shown in FIG. 9F, the negative polarity switch control signal S- (2) is at the high level. become.

  These negative polarity switch control signals S- (1) and S- (2) are used in the high level period during which the transistor Q6 is turned on as shown in FIGS. The active period of the switching means composed of the transistors Q4 and Q5 applied to the pixel drive electrode PE after impedance conversion does not overlap. For this reason, according to the present embodiment, pixel electrode potential fluctuations associated with on / off of the transistors Q5 of the plurality of pixels in the divided pixel unit 90-2 are the lowest level in the divided pixel unit 90-1. The influence on the liquid crystal drive voltage VPE of each pixel in the line can be eliminated.

  Further, even during the period after the time t31 when the negative video signal is held and applied to the pixel drive electrode PE, the load characteristic control signals B (1) and B (2) are shown in FIGS. As shown in (G), the high-level period is not overlapped, and the constant current load transistor Q9 of each pixel of the divided pixel unit 90-1 is actively controlled (time t32 to t34) and divided The period (time t37 to t39) in which the constant current load transistor Q9 of each pixel of the pixel unit 90-2 is actively controlled is prevented from overlapping (overlapping).

  For this reason, the crosstalk when the load characteristic control signal B (2) changes to the high level at time t37 (the transistors Q9 of the plurality of pixels of the divided pixel unit 90-2 change to ON), and at time t39. It occurs in a direction different from the positive and negative crosstalk when changing to the low level (transistor Q9 of each of the plurality of pixels of the divided pixel unit 90-2 is turned off), and as a result, the crosstalk is canceled, The liquid crystal driving voltage VPE (1 ′) of each of the plurality of pixels in the lowermost line in the divided pixel portion 90-1 is the above-mentioned even during the period from time t37 to t39, as indicated by a dotted line in FIG. The potential fluctuation due to crosstalk becomes almost zero.

  FIG. 10 shows a circuit diagram of an embodiment of a drive circuit that outputs each signal of the timing chart shown in FIG. The drive circuit 110 is a circuit used in place of the shift registers 91a to 91c shown in FIG. 5, and includes shift registers 111 and 112, and logic circuits 113-1 to 113-h and 114-1 to 114-h. Composed.

  The shift register 111 shifts the positive polarity switch control signal S + described above in synchronization with the shift clock SCK, and sequentially supplies output signals to the logic circuits 113-1 to 113-h. The shift register 112 shifts the negative polarity switch control signal S− described above in synchronization with the shift clock SCK and outputs an output signal to the logic circuits 114-1 to 114-h. Each of the logic circuits 113-1 to 113-h has the same configuration, and includes three OR circuits 151 to 153 and two inverters 154 and 155.

  The OR circuit 151 outputs a logical sum signal of the first positive polarity switch control signal and the fourth positive polarity switch control signal input after three shift clock cycles. The OR circuit 152 includes a second positive polarity switch control signal input after one shift clock cycle from the time of input of the first positive polarity switch control signal, and two shift clocks from the time of input of the first positive polarity switch control signal. A logical sum signal with the third positive polarity switch control signal input after the cycle is output.

  The OR circuit 153 performs a logical sum operation on the logical sum signals output from the OR circuits 151 and 152, respectively. Inverter 154 inverts the signal output from OR circuit 153 and outputs load characteristic control signal B. Inverter 155 inverts the signal output from OR circuit 152 and outputs positive polarity switch control signal S +.

  The logic circuits 113-1 to 113-h receive the load characteristic control signals B (1) to B (h) in FIG. 9 by sequentially supplying the positive polarity switch control signal S + supplied from the shift register 111. As shown in (D) and (G), time-division output is performed so that the high level periods do not overlap, and the positive polarity switch control signals S + (1) to S + (h) are shown in FIG. As shown in B) and (E), output is performed in a time-sharing manner so that the high level periods do not overlap.

  The logic circuits 114-1 to 114-h have the same circuit configuration as the logic circuits 113-1 to 113-h, and are sequentially supplied with the negative polarity switch control signal S- supplied from the shift register 112. As shown in FIGS. 9D and 9G, the load characteristic control signals B (1) to B (h) are output in a time division manner so that the high level periods do not overlap, and the negative polarity switch As shown in FIGS. 9C and 9F, the control signals S- (1) to S- (h) are output in a time division manner so that the high level periods do not overlap.

  Next, a second embodiment of the present invention for reducing the above-described horizontal linear noise will be described.

  FIG. 11 shows a block diagram of a second embodiment of the main part of the liquid crystal display device according to the present invention. In this embodiment, polarity inversion control and active control of the source follower buffer circuit are realized with a time difference in the vertical direction of the screen. In the figure, the same components as those in FIG.

  As shown in FIG. 11, in the present embodiment, divided pixel units 90-1, 90-2,..., In which the pixel unit 30 in FIG. 1 is divided into h in the vertical direction (h is a natural number of 2 or more). 90-h, a positive polarity switch control signal for the wiring S +, a negative polarity switch control signal for the wiring S-, and a load characteristic control signal for the wiring B are respectively shifted in synchronization with the same shift clock SCK. , 94 and 95. The shift registers 93, 94, and 95 correspond to the vertical driving circuit 20 shown in FIG. FIG. 5 shows only circuit portions necessary for active control of the source follower buffer circuit, and illustration of the horizontal driving circuit 10 and the like is omitted. Each of the divided pixel portions 90-1, 90-2,..., And 90-h is a group # 1, # 2 in which a plurality of rows of the pixel portion 30 in FIG. ,... And #h. In the present embodiment, h is an arbitrary even number.

  This embodiment differs from the first embodiment shown in FIG. 5 in the following points. In FIG. 11, the shift register 93 shifts the positive polarity switch control signal of the wiring S + and outputs it from the first stage, second stage,..., H / 2 stage output terminals, (H / 2) +1 stage, (h / 2) +2 stage,..., And the latter half portion 93b output from the h stage output terminal. As for the connection between each output terminal and the divided pixel portion, in the first half 93a of the shift register, the first stage output terminal is the input terminal S + (2) of the divided pixel portion 90-2, and the second stage output terminal is the divided pixel. The input terminal S + (4) of the unit 90-4, the output terminal of the third stage is the input terminal S + (6),... Of the divided pixel unit 90-6, and the output terminal of the h / 2 stage is divided. The pixel unit 90-h is connected to the input terminal S + (h). In the second half portion 93b of the shift register, the output terminal of the (h / 2) +1 stage is divided into the input terminal S + (1) of the divided pixel portion 90-1, and the output terminal of the (h / 2) +2 stage is divided. The input terminal S + (3), (h / 2) + third stage output terminal of the pixel portion 90-3 is the input terminal S + (5),..., And (h / 2) of the divided pixel portion 90-5. ) + (H / 2) stage (= h stage) output terminals are respectively connected to the input terminals S + (h−1) of the divided pixel section 90- (h−1).

  Similarly, the shift register 94 and the shift register 95 are also divided into the first half portions 94a and 95a and the second half portions 94b and 95b, and the divided pixel portions 90-1 to 90-1 are similar to the first half portion 93a and the second half portion 93b of the shift register 93. 90-h. That is, each stage output terminal of the first half portion 94a of the shift register is the negative electrode of the even-numbered divided pixel portions 90-2, 90-4,..., 90-h among the divided pixel portions 90-1 to 90-h. Connected to the input terminal of the directional switch control signal S-, and each stage output terminal of the first half portion 95a of the shift register controls the load characteristics of the even-numbered divided pixel portions 90-2, 90-4,. It is connected to the input terminal of signal B.

  Further, each stage output terminal of the shift register latter half portion 94b has odd-numbered divided pixel portions 90-1, 90-3,..., 90- (h−) of the divided pixel portions 90-1 to 90-h. 1) is connected to the input terminal of the negative polarity switch control signal S−, and each stage output terminal of the shift register latter half portion 95b is connected to the odd-numbered divided pixel portions 90-1, 90-3,. h-1) is connected to the input terminal of the load characteristic control signal B.

  Next, the operation of the present embodiment will be described with reference to the timing chart of FIG. FIG. 12A shows the shift clock SCK supplied to the shift registers 93, 94 and 95. In synchronism with this shift clock SCK, the shift register 93 shifts the positive polarity switch control signal S + shown in FIG. 12 (B) to change the first stage, the second stage,... Positive polarity switch control signals are sequentially output from the output terminals. At this time, the positive polarity switch control signals output from the output terminals of the first, second, third,..., H / 2 stages of the first half portion 93a of the shift register 93 are shown in FIG. D), (F), (H),..., (J), the input terminals S + (2) and 90-4 of the even-numbered divided pixel section 90-2 are input terminals S + ( 4), 90-6 input terminal S + (6),..., 90-h input terminal S + (h).

  Subsequently, (h / 2) +1 stage of the shift register 93 (1st stage of the second half portion 93b), (h / 2) +2 stage, (h / 2) +3 stage,..., H stage The positive polarity switch control signals sequentially output from the respective output terminals (the h / 2 stage of the second half portion 93b) are shown in FIGS. 12 (C), (E), (G),..., (I). As shown, the input terminal S + (1) of the odd-numbered divided pixel section 90-1, the input terminal S + (3) of 90-3, the input terminal S + (5) of 90-5,. The signals are sequentially supplied to the input terminal S + (h-1) of 90- (h-1).

  After a positive polarity switch control signal is output from the output terminal h at the final stage of the shift register 93, after a predetermined period corresponding to a plurality of lines of each of the divided pixel portions 90-1 to 90-h, the shift register 94 is transferred to FIG. As shown in K), the negative polarity switch control signal S- is input. The shift register 94 shifts the negative polarity switch control signal S− in synchronization with the shift clock SCK, and sequentially positive polarity from the output terminals of the first, second,. Outputs a switch control signal.

  At this time, the first, second, third,..., H / 2 stage output terminals of the first half portion 94a of the shift register 94 are shown in FIGS. 12 (M), (O), (Q). ,... (S), the negative polarity switch control signals sequentially output are input terminals S- (2) and 90-4 of the even-numbered divided pixel section 90-2. (4), 90-6 input terminal S- (6),..., 90-h input terminal S- (h).

  Subsequently, (h / 2) +1 stage of the shift register 94 (1st stage of the second half 94b), (h / 2) +2 stage, (h / 2) +3 stage,..., H stage Negative polarity switch control sequentially output as shown in FIGS. 12 (L), (N), (P),..., (R) from each output terminal (h / 2 stage of the second half 94b). The signals are input terminals S + (1) of the odd-numbered divided pixel section 90-1, input terminals S + (3) of 90-3, input terminals S + (5) of 90-5,. -Is supplied to the input terminal S + (h-1) of (h-1).

  On the other hand, the shift register 95 shifts the input load characteristic control signal B shown in FIG. 12 (T) in synchronization with the shift clock SCK to shift the first stage, the second stage, the third stage,. Load characteristic control signals are sequentially output from the output terminals of the respective stages. At this time, the load characteristic control signals output from the first, second, third,..., H / 2 stage output terminals of the first half portion 95a of the shift register 95 are shown in FIG. ), (X), (Z),..., (B), the input terminals B (2) of the even-numbered divided pixel section 90-2, the input terminals B (4) of 90-4, , 90-h input terminal B (6),..., 90-h input terminal B (h).

  Subsequently, (h / 2) +1 stage of the shift register 95 (first stage of the second half 95b), (h / 2) +2 stage, (h / 2) +3 stage,..., H stage The load characteristic control signals sequentially output from the respective output terminals (h / 2 stage of the second half portion 95b) are shown in FIGS. 12 (U), (W), (Y),. As described above, the input terminal B (1) of the odd-numbered divided pixel section 90-1, the input terminal B (3) of 90-3, the input terminal B (5) of 90-5,..., 90- (h -1) are sequentially supplied to the input terminal B (h-1).

  As described above, in the present embodiment, even-numbered divided pixel units among the divided pixel units 90-1 to 90-h are driven first by the first half portions 93a, 94a, and 95a of the shift registers 93, 94, and 95, respectively. Subsequently, the configuration is such that the odd-numbered divided pixel portions of the divided pixel portions 90-1 to 90-h are driven by the latter half portions 93b, 94b and 95b of the shift registers 93, 94 and 95, respectively.

  Next, the effect of this embodiment will be described.

  As already described with reference to FIGS. 7 and 8, when two adjacent divided pixel portions are continuously driven, the liquid crystal driving voltage VPE of each pixel in the lowermost line of the divided pixel portion is adjacent to each other. This results in a potential in which the crosstalk for driving the divided pixel portion to be superimposed is superimposed. However, in the present embodiment, the order of driving is changed so that the divided pixel units 90-1 to 90-h are driven one by one, so that crosstalk from adjacent divided pixel units is avoided. can do. As a result, there is no luminance difference between the displayed images, and it is possible to suppress horizontal linear noise as shown in FIG.

  Next, a third embodiment of the present invention for reducing the above-described horizontal linear noise will be described.

  FIG. 13 shows a block diagram of a third embodiment of the main part of the liquid crystal display device according to the present invention. In the present embodiment, as in the first and second embodiments, the polarity inversion control and the active control of the source follower buffer circuit are realized with a time difference in the vertical direction of the screen. In the figure, the same components as those in FIG.

  As shown in FIG. 13, in the present embodiment, divided pixel units 90-1, 90-2,..., In which the pixel unit 30 of FIG. 90-h, the h-stage shift register 97 for shifting the positive polarity switch control signal for the wiring S +, the negative polarity switch control signal for the wiring S-, and the load characteristic control signal for the wiring B in synchronization with the same shift clock SCK. 98 and 99. The shift registers 97, 98, and 99 correspond to the vertical driving circuit 20 shown in FIG. FIG. 5 shows only circuit portions necessary for active control of the source follower buffer circuit, and illustration of the horizontal driving circuit 10 and the like is omitted. Each of the divided pixel portions 90-1, 90-2,..., And 90-h is a group # 1, # 2 in which a plurality of rows of the pixel portion 30 in FIG. ,... And #h. In the present embodiment, h is an arbitrary even number.

This embodiment is different from the first and second embodiments shown in FIGS. 5 and 11 in the following points. In FIG. 13, each of the shift registers 97, 98 and 99 has three stage output terminals, and a total of k (k = h / 3) blocks 97 _{1 to} 97 connected in series with each other. _k , 98 _{1 to} 98 _k and 99 _{1 to} 99 _k .

For example, a shift register 97 for shifting in synchronization with the positive switch control signal to the shift clock SCK is the first stage, a first block 97 ₁ having an output terminal of the second and third stages, the fourth stage , first with a second block 97 ₂ having an output terminal of the fifth stage and the sixth stage, in the same repetition, h-5-stage, the output terminal of the h-4 stage and h-3 stage a k-1th block 97 _k-1 and a kth (= h / 3) th block 97 _k having output terminals of h-2, h-1 and h stages, They are connected in series. The same applies to the other shift registers 98 and 99.

Connections between the output terminals of the blocks 97 _{1 to} 97 _k , 98 _{1 to} 98 _k , and 99 _{1 to} 99 _k and the divided pixel units 90-1 to 90-h are as follows. In the first block 97 ₁ , 98 ₁ , 99 _1, the first stage output terminal is the divided pixel unit 90-2, the second stage output terminal is the divided pixel unit 90-4, and the third stage output terminal is the divided pixel. Connected to the unit 90-6. Second block 97 _2, 98 _2, 99 ₂ each stage to the (throughout the shift register 4 stage) output terminal of the divided pixel section 90-1, second-stage (5-stage the entire shift register) Are connected to the divided pixel unit 90-3, and the output terminal of the third stage (sixth stage in the entire shift register) is connected to the divided pixel unit 90-5.

In the same manner, the k-1th blocks 97 _k-1 , 98 _k-1 , and 99 _k-1 have the output terminals of the first stage (h-5th stage in the whole shift register) as the divided pixel unit 90-. In (h-4), the output terminal of the second stage (h-4th stage in the whole shift register) is connected to the divided pixel unit 90- (h-2), and the third stage (h-3 stage in the whole shift register). ) Is connected to the divided pixel portion 90-h. Furthermore, the k-th block 97 _k, 98 _k, 99 _k in the first stage output terminal divided pixel unit (the entire shift register is h-2 stage) 90- (h -5), 2-stage ( The output terminal of the h-1 stage in the entire shift register is the divided pixel section 90- (h-3), and the output terminal of the third stage (the h stage in the entire shift register) is the divided pixel section 90- (h- 1).

Next, the operation of the present embodiment will be described with reference to the timing chart of FIG. FIG. 14A shows the shift clock SCK supplied to the shift registers 97, 98 and 99. The shift clock SCK is also supplied to the blocks 97 _{2 to} 97 _k , 98 _{2 to} 98 _k , and 99 _{2 to} 99 _k , but the illustration thereof is omitted in FIG.

In synchronization with the shift clock SCK, the shift register 97 shifts the positive polarity switch control signal S + shown in FIG. 14B, and outputs the first stage, the second stage,... Positive polarity switch control signals are output sequentially from the terminals. At this time, the first-stage block 97 ₁ of the shift register 97, the second stage, the positive switch control signal outputted from the output terminals of the third stage, FIG. 14 (D), (F) , (H) As shown in FIG. 5, the input terminals S + (2), the input terminal S + (4) of 90-4, and the input terminal S + (6) of 90-6 are sequentially supplied to the even-numbered divided pixel section 90-2. Is done. Subsequently, the first-stage block 97 ₂ of the shift register 97, the second stage, the positive switch control signal outputted from the output terminals of the third stage, FIG. 14 (C), (E) , (G) As shown in FIG. 4, the input terminals S + (1), the input terminals S + (3) of 90-3 and the input terminal S + (5) of 90-5 are sequentially supplied to the odd-numbered divided pixel section 90-1. Is done.

Hereinafter, similarly, the positive polarity switch control signals output from the output terminals of the first stage, the second stage, and the third stage of the block 97 _k-1 of the shift register 97 are shown in FIGS. , (N), the input terminal S + (h-4) of the even-numbered divided pixel section 90- (h-4), the input terminal S + (h-2) of 90- (h-2). , 90-h are sequentially supplied to the input terminal S + (h). The positive polarity switch control signals output from the output terminals of the first stage, the second stage, and the third stage of the block 97 _k of the shift register 97 are shown in FIGS. 14 (I), (K), and (M). As shown, the input terminals S + (h-5) of the odd-numbered divided pixel section 90- (h-5), the input terminals S + (h-3) of 90- (h-3), 90- (h -1) are sequentially supplied to the input terminal S + (h-1).

After the positive polarity switch control signal is output from the output terminal h of the third stage (h stage in the whole shift register) of the block 97 _k of the final stage of the shift register 97, each divided pixel unit 90-1 to 90-h. After a predetermined period corresponding to the plurality of lines, the negative polarity switch control signal S− is input to the shift register 98 as shown in FIG. Similarly to the shift register 97, the shift register 98 outputs the negative polarity switch control signals sequentially shifted from the blocks 98 _{1 to} 98 _k and supplies the divided pixels 90-1 to 90-h with the same predetermined register as the shift register 97. Supply in order. FIGS. 14P to 14U show negative polarity switch control signals supplied to the divided pixel portions 90-1 to 90-6. 14 (V) to 14 (a) show negative switch control signals supplied to the divided pixel units 90- (h-5) to 90-h.

Similarly to the shift registers 97 and 98, the shift register 99 sequentially shifts the input load characteristic control signal B from the blocks 99 _{1 to} 99 _k in synchronization with the shift clock SCK as shown in FIG. The obtained load characteristic control signal is output and supplied to the divided pixels 90-1 to 90-h in a predetermined order similar to the shift registers 97 and 98. FIGS. 14C to 14H show load characteristic control signals supplied to the divided pixel units 90-1 to 90-6. FIGS. 14L to 14F show load characteristic control signals supplied to the divided pixel units 90- (h-5) to 90-h.

In this way, the present embodiment includes three shift stage blocks 97 _{1 to} 97 _k , 98 _{1 to} 98 _k , and 99 _{1 to} 99 _k each having three stage output terminals and connected in series to each other. The divided pixel units 90-1 to 90-h are grouped by six adjacent divided pixel units and sequentially driven in units of groups, and the even-numbered divided pixels are provided in the six divided pixel units of each group. This is characterized in that the first part is driven first, and then the odd-numbered divided pixel part is driven.

  Next, the effect of this embodiment will be described.

  As already described with reference to FIGS. 7 and 8, when two adjacent divided pixel portions are continuously driven, the liquid crystal driving voltage VPE of each pixel in the lowermost line of the divided pixel portion is adjacent to each other. This results in a potential in which the crosstalk at the time of driving the divided pixel portion to be superimposed is superimposed. However, in the present embodiment, the driving order is changed, and the driving of the divided pixel portions in the six divided pixel portions of each set is skipped one by one. Crosstalk from the divided pixel portion can be avoided. As a result, there is no luminance difference between the displayed images, and it is possible to suppress horizontal linear noise as shown in FIG.

  In the third embodiment described above, each block has a configuration of three stages. However, it is also possible to have a configuration of two stages or more and h / 2 stages or less. In this case as well, horizontal line noise is suppressed. A similar effect can be expected. Note that if there are many stages in each block, there will be a large time difference in the timing at which the adjacent divided pixel units are driven. Therefore, there is a possibility that a difference in the decrease in the holding potential due to the liquid crystal capacitance will occur, resulting in a light / dark difference in image display. There is. However, by reducing the number of stages in each block, the difference in liquid crystal holding potential in adjacent divided pixel portions can be reduced, and high-quality image display can be realized.

  The present invention is not limited to the above embodiment. For example, the polarity relationship between the polarity of the common electrode voltage Vcom and the positive polarity switch control signal S + and the negative polarity switch control signal S- is shown in FIG. It may be the reverse of the example of 3. In the second and third embodiments, the even-numbered divided pixel unit is driven first and then the odd-numbered divided pixel unit is driven. However, the reverse order may be used. Furthermore, in the second and third embodiments, it has been described that h, which is the total number of divided pixel portions, is an even number, but the desired effect can be obtained even if h is an odd number.

1-1a, 1-1b, 1-2a, 1-2b Video switch 4, PE reflective electrode (pixel drive electrode)
5a, 5b Horizontal signal lines 6-1a, 6-1b, 6-2a, 6-2b, Di +, Di- data lines (column signal lines)
7 Common electrode lines 8-1 and 8-2 Gate lines (row scanning lines)
DESCRIPTION OF SYMBOLS 10 Horizontal direction drive circuit 20 Vertical direction drive circuit 30 Pixel part 41, 42, 51, 52 Pixel 60 Controller 71a Positive side video signal (positive polarity video signal)
71b Negative video signal (negative video signal)
90-1 to 90-h Divided pixel portions 91a, 91b, 91c, 93 to 95, 97 to 99 Shift registers 93a, 94a, 95a Shift register first half 93b, 94b, 95b Shift register second half 97 _{1 to} 97 _k , 98 _{1 to} 98 _k , 99 _{1 to} 99 _k shift register block 100 liquid crystal display device S1, S2 changeover switch C1, C2, C3, Cs1, Cs2 signal holding capacitor A1, A2 buffer amplifier Q1, Q2 pixel selection transistor Q3, Q4 buffer Amplifier transistors Q5, Q6 Switching transistor Q9 Constant current source load transistor CE Common electrode (counter electrode)
LCM liquid crystal display (liquid crystal layer)
LC liquid crystal element

Claims (6)

A liquid crystal element in which a liquid crystal layer is sandwiched between an opposing pixel drive electrode and a common electrode;
First sampling and holding means for sampling and holding a positive video signal for a certain period;
A second sampling and holding means for sampling a negative video signal and holding it for a predetermined period;
When the first gate control signal is input, the positive video signal held by the first sampling and holding means is impedance-converted and applied to the pixel driving electrode, and when the second gate control signal is input, the first gate control signal is input. Switching means for impedance-converting the negative-polarity video signal held by the sampling and holding means and applying it to the pixel drive electrode;
A constant current load element for impedance conversion connected between a connection point between the output terminal of the switching means and the pixel drive electrode and a ground potential or a power supply potential;
Are provided at intersections where a plurality of sets of data lines and a plurality of gate lines intersect each other, each having two data lines as a set,
Provided for each of the plurality of sets of data lines, supplying the positive video signal to one of the two data lines and supplying the negative video signal to the other data line A plurality of switches for sequentially performing a set unit for the plurality of sets of data lines;
Horizontal and vertical direction drive means for performing horizontal direction driving for driving the plurality of switches in the set unit within a horizontal scanning period and vertical direction driving for selecting the plurality of gate lines for each horizontal scanning period;
When the entire pixel portion composed of the plurality of pixels is divided into divided pixel portions of h groups (h is a natural number of 2 or more), each pixel of a plurality of consecutive rows being one group, the first gate control After the signal is supplied in a time division manner for each of the divided pixel portions of the h divided pixel portions, the second gate control signal is supplied in a time division manner for each of the divided pixel portions of the h divided pixel portions. Gate control signal supply means that alternately repeats the supply every predetermined vertical scanning period corresponding to the number of rows of the divided pixel portion;
Among the h divided pixel portions, the active period of the constant current load element in the nth (n = 1, 2,..., H−1) divided pixel portion and the (n + 1) th divided portion. In order not to overlap the active period of the constant current load element in the pixel unit, a control signal is sent to the constant current load element in the h divided pixel units for each divided pixel unit of the h divided pixel units. A load element control signal supply means for supplying in a divided manner. The gate control signal supply means includes
Among the h divided pixel portions, an active period of the switching means in the nth divided pixel portion and an active period of the switching means in the (n + 1) th divided pixel portion do not overlap. 2. The liquid crystal display device according to claim 1, wherein the first and second gate control signals are supplied to the switching means in the h divided pixel portions in a time division manner for each divided pixel portion. A liquid crystal element in which a liquid crystal layer is sandwiched between an opposing pixel drive electrode and a common electrode;
First sampling and holding means for sampling and holding a positive video signal for a certain period;
A second sampling and holding means for sampling a negative video signal and holding it for a predetermined period;
When the first gate control signal is input, the positive video signal held by the first sampling and holding means is impedance-converted and applied to the pixel driving electrode, and when the second gate control signal is input, the first gate control signal is input. Switching means for impedance-converting the negative-polarity video signal held by the sampling and holding means and applying it to the pixel drive electrode;
A constant current load element for impedance conversion connected between a connection point between the output terminal of the switching means and the pixel drive electrode and a ground potential or a power supply potential;
Are provided at intersections where a plurality of sets of data lines and a plurality of gate lines intersect each other, each having two data lines as a set,
Provided for each of the plurality of sets of data lines, supplying the positive video signal to one of the two data lines and supplying the negative video signal to the other data line A plurality of switches for sequentially performing a set unit for the plurality of sets of data lines;
Horizontal and vertical direction drive means for performing horizontal direction driving for driving the plurality of switches in the set unit within a horizontal scanning period and vertical direction driving for selecting the plurality of gate lines for each horizontal scanning period;
When the entire pixel portion composed of the plurality of pixels is divided into divided pixel portions of h groups (h is a natural number of 2 or more), each pixel of a plurality of consecutive rows being one group, the first gate control A signal corresponding to the number of the plurality of rows of the divided pixel portions is supplied in a time division manner to all of the divided pixel portions arranged in every other order among the h divided pixel portions. First gate control signal supply means that repeats every vertical scanning period;
After the first gate control signal is supplied to all of the divided pixel units arranged in every other order, the second gate control signal is sent to the second of the h divided pixel units. A second gate control signal that repeats the time-division supply to all of the divided pixel units arranged in every other order, to which one gate control signal is not supplied, every predetermined vertical scanning period. A liquid crystal display device. A plurality of pixels provided at intersections where a plurality of sets of data lines and a plurality of gate lines intersect each other, each of which includes two data lines;
Provided for each of the plurality of sets of data lines, supplying a positive video signal to one of the two data lines and supplying a negative video signal to the other data line A plurality of switches for sequentially performing a set unit for the plurality of sets of data lines;
Horizontal and vertical direction drive means for performing horizontal direction driving for driving the plurality of switches in the set unit within a horizontal scanning period and vertical direction driving for selecting the plurality of gate lines for each horizontal scanning period;
Each of the plurality of pixels includes:
A liquid crystal element in which a liquid crystal layer is sandwiched between an opposing pixel drive electrode and a common electrode;
First sampling and holding means for sampling and holding the positive video signal for a certain period;
Second sampling and holding means for sampling and holding the negative video signal for the predetermined period;
When the first gate control signal is input, the positive video signal held by the first sampling and holding means is impedance-converted and applied to the pixel driving electrode, and when the second gate control signal is input, the first gate control signal is input. Switching means for impedance-converting the negative-polarity video signal held by the sampling and holding means and applying it to the pixel drive electrode;
A constant current load element for impedance conversion connected between a connection point between the output terminal of the switching means and the pixel drive electrode and a ground potential or a power supply potential;
For a liquid crystal display device having a configuration
When the entire pixel portion composed of the plurality of pixels is divided into divided pixel portions of h groups (h is a natural number of 2 or more), each pixel of a plurality of consecutive rows being one group, the first gate control After the signal is supplied in a time division manner for each of the divided pixel portions of the h divided pixel portions, the second gate control signal is supplied in a time division manner for each of the divided pixel portions of the h divided pixel portions. And alternately repeating the supply every predetermined vertical scanning period corresponding to the number of rows of the divided pixel portion,
Among the h divided pixel portions, the active period of the constant current load element in the nth (n = 1, 2,..., H−1) divided pixel portion and the (n + 1) th divided portion. In order not to overlap the active period of the constant current load element in the pixel unit, a control signal is sent to the constant current load element in the h divided pixel units for each divided pixel unit of the h divided pixel units. A method for driving a liquid crystal display device, characterized by being dividedly supplied.   Among the h divided pixel portions, an active period of the switching means in the nth divided pixel portion and an active period of the switching means in the (n + 1) th divided pixel portion do not overlap. 5. The liquid crystal display device according to claim 4, wherein the first and second gate control signals are supplied to the switching means in the h divided pixel portions in a time division manner for each divided pixel portion. Driving method. A plurality of pixels provided at intersections where a plurality of sets of data lines and a plurality of gate lines intersect each other, each of which includes two data lines;
Provided for each of the plurality of sets of data lines, supplying a positive video signal to one of the two data lines and supplying a negative video signal to the other data line A plurality of switches for sequentially performing a set unit for the plurality of sets of data lines;
Horizontal and vertical direction drive means for performing horizontal direction driving for driving the plurality of switches in the set unit within a horizontal scanning period and vertical direction driving for selecting the plurality of gate lines for each horizontal scanning period;
Each of the plurality of pixels includes:
A liquid crystal element in which a liquid crystal layer is sandwiched between an opposing pixel drive electrode and a common electrode;
First sampling and holding means for sampling and holding the positive video signal for a certain period;
Second sampling and holding means for sampling and holding the negative video signal for the predetermined period;
When the first gate control signal is input, the positive video signal held by the first sampling and holding means is impedance-converted and applied to the pixel driving electrode, and when the second gate control signal is input, the first gate control signal is input. Switching means for impedance-converting the negative-polarity video signal held by the sampling and holding means and applying it to the pixel drive electrode;
A constant current load element for impedance conversion connected between a connection point between the output terminal of the switching means and the pixel drive electrode and a ground potential or a power supply potential;
For a liquid crystal display device having a configuration
When the entire pixel portion composed of the plurality of pixels is divided into divided pixel portions of h groups (h is a natural number of 2 or more), each pixel of a plurality of consecutive rows being one group, the first gate control A signal corresponding to the number of the plurality of rows of the divided pixel portions is supplied in a time division manner to all of the divided pixel portions arranged in every other order among the h divided pixel portions. Repeated every vertical scanning period of
After the first gate control signal is supplied to all of the divided pixel units arranged in every other order, the second gate control signal is sent to the second of the h divided pixel units. A liquid crystal characterized in that supply in a time-sharing manner to all of the divided pixel portions arranged in every other order in which one gate control signal is not supplied is repeated for each predetermined vertical scanning period. A driving method of a display device.

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