JP3203835B2 - Liquid crystal display - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a thin film transistor (T
hin Film Transister. A so-called active matrix type liquid crystal display panel using a TFT (hereinafter referred to as TFT) or the like is provided, and an AC drive method is employed in which a common voltage to be applied to a common electrode provided commonly to all pixels is fixed. The present invention relates to a liquid crystal display device.

In recent years, a liquid crystal display device provided with a liquid crystal display panel has been highly expected as a display device which replaces a display device provided with a cathode ray tube (CRT), and its technical development has been actively carried out. I have.

[0003] Among such liquid crystal display devices, an AC drive type liquid crystal display device having an active matrix type liquid crystal display panel is particularly promising because of its high display speed and excellent display quality. .

[0004]

2. Description of the Related Art Conventionally, as an AC drive type liquid crystal display device having an active matrix type liquid crystal display panel, there is known a device schematically shown in FIG.

In FIG. 1, reference numeral 1 denotes an active matrix type liquid crystal display panel in which the number of pixels as a minimum unit of image display is 4 (horizontal: horizontal direction) × 4 (vertical: vertical direction).
_{11-2 44} respectively represent pixels.

In an actual liquid crystal display panel, the number of pixels is, for example, 64 for monochrome (monocolor) display.
0 (horizontal) × 480 (vertical), and for color display, each pixel for R (red), G (green), and B (blue) is required. For example, 640 × 3 ( (Horizontal) × 480 (vertical).

Here, the arrangement of pixels in the horizontal direction is generally called a line, and writing of a display signal composed of an analog signal for one screen, that is, a so-called analog display signal, is sequentially performed for each line, and the analog display for one screen is performed. By writing a signal at a rate of about 60 times per second, an image without flicker is shown to human eyes.

[0008] Figure 7 is a configuration of a liquid crystal display panel 1 of the active matrix type is a diagram schematically showing, in FIG, 3 _{11-3 44} TFT, 4 ₁₁ forming a switching element
To 4 ₄₄ liquid crystal capacitance of each pixel 2 _{11-2 44,} 5 _{11-5 44} pixel electrodes analog display signal is provided for each pixel 2 _{11-2 44} is applied, 6 all the pixels 2 ₁₁ a common electrode provided in common to to 2 _44.

X _{1 to} X ₄ are data lines (signal lines) for supplying analog display signals to the pixel electrodes 5 _{11 to} 5 ₄₄ ,
₁ to Y ₄ is TFT 3 ₁₁ to 3 ₄₄ ON of the gate lines (scanning lines) for controlling the OFF, bias voltage to the common electrode 6 is 7, as a so-called common voltage Vcom, for example, 7.0
It is a common voltage source that supplies [V].

In FIG. 6, reference numeral 8 denotes a control circuit for controlling the entire apparatus, HS denotes a horizontal synchronizing signal, VS denotes a vertical synchronizing signal, and CLK denotes a timing signal for giving a write timing of a display signal. Note that this timing signal CL
K can be generated inside the apparatus by measuring the cycle of the horizontal synchronization signal HS, and is not essentially required.

D _IN is a display signal (display data) composed of a digital signal supplied from the outside, that is, a so-called digital display signal. In this example, [D 2, D 1, D 0, ] Has a 3-bit configuration.

Reference numeral 9 denotes an inverting / non-inverting circuit which operates as an inverting circuit or a non-inverting circuit under the control of an inverting / non-inverting instruction signal AP output from the control circuit 8. In the case of "H", the non-inverting circuit
When the non-inversion instruction signal AP = “L”, the circuit operates as an inversion circuit.

The inversion / non-inversion instruction signal AP is synchronized with the horizontal synchronizing signal HS, for example, in an odd-numbered frame, “H” (first horizontal period) → “L” (second horizontal period) → The inversion is repeated as “H” (third horizontal period) → “L” (fourth horizontal period). In even frames, “L” (first horizontal period) → “H” (second horizontal period)
The inversion is repeated in the order of “L” (third horizontal period) → “H” (third horizontal period).

Reference numeral 10 denotes a data driver formed as an LSI for driving the data lines X _{1 to} X _4.
Is the start signal T1 output line by line from the control circuit 8 and the clock signal C output from the control circuit 8
K1 in synchronization with the shifting bit by bit, a shift register of the serial input-parallel output type timing signal SP ₁ to SP ₄ to sequentially output 4-bit configuration.

Further, 12 _{1 to} 12 ₄ are inverting / non-inverting circuits 9
The digital display signal D _IN for each pixel or the digital inversion display signal / D _IN obtained by inverting the digital display signal D _IN is synchronized with the timing signals SP _{1 to} SP ₄ output from the shift register 10. This is a 3-bit memory circuit that holds and outputs simultaneously with holding.

Further, 13 _{1 to} 13 ₄ are memory circuits 12 ₁ to 13 ₁
Decodes the digital display signal D _IN or digital highlight signal / D _IN outputted from the 12 _4, a decoder for outputting a logic level of the selection signal for selecting a reference voltage to be described later.

[0017] Here, the decoder _131-134 is the same circuit configuration, if Shimese on behalf of the decoder 13 ₁ is configured as shown in FIG. In the figure, 14-1
6 is a digital display signal D _IN or a digital inversion display signal /
This is an input terminal to which signals D2 to D0 or / D2 to / D0 of each bit of D _IN are input.

Reference numerals 17 to 19 denote inverters and 20 to 2
3 NAND circuit, 24 to 31 is a NOR circuit, in the decoder 13 _1, the digital display signal D _IN or digital highlight signal / D _IN and NOR circuit 24 to 31 is input via a memory circuit 12 ₁ The relationship with the output is as shown in Table 1.

[0019]

[Table 1]

In FIG. 6, reference numerals 32 _{1 to} 32 ₄ denote logical level selection signals output from the decoders 13 _{1 to} 13 ₄ as analog switch Os of an analog switch which will be described later.
N, a level conversion circuit unit (LC) in which a level conversion circuit for converting to a level at which OFF control can be performed is arranged.
Part).

Here, the level conversion circuit sections 32 _{1 to} 32 _1
4 is the same circuit configuration, if Shimese on behalf of the level converting circuit 32 _1, is configured as shown in FIG. In the figure, reference numerals 33 to 40 denote level conversion circuits.

The level conversion circuits 33 to 40 have the same circuit configuration, and as a representative of the level conversion circuit 33, are configured as shown in FIG. In the figure, 4
1 is a VH voltage line for supplying a high voltage VH, for example, 15 [V], 42 and 43 are pMOS transistors, 44 and 45
NMOS transistor 46 is an inverter, 47 denotes an input terminal to which the output of the NOR circuit 24 of the decoder 13 ₁ is input, 48 an output terminal.

In the level conversion circuit 33, NO
When the output of the R circuit 24 is 0 [V] (L level), nM
OS transistor 44 = OFF, nMOS transistor 45 = ON, pMOS transistor 42 = ON, pM
The OS transistor 43 is turned off, and the output of the level conversion circuit 33 becomes 0 [V].

On the other hand, the output of the NOR circuit 24 = 5
In the case of [V] (H level), the nMOS transistor 44
= ON, nMOS transistor 45 = OFF, pMO
S transistor 42 = OFF, pMOS transistor 4
3 = ON, output of the level conversion circuit 33 = 15
[V].

In FIG. 6, reference numeral 49 denotes a reference voltage V0.
To V15, T2 is a reference voltage source 49
Is a control signal for controlling the type of reference voltage output from the controller, and is a signal that repeats inversion similarly to the inversion / non-inversion instruction signal AP.

Here, the reference voltage source 49 is configured as shown in FIG.
A reference voltage source for generating 0 to V15, 66 to 81 are analog switches, and 82 is an inverter.
To V15 are voltage values as shown in Table 2.

[0027]

[Table 2]

In the reference voltage source 49, the control signal T2 =
In the case of "H", the analog switches 66 to 73 = ON,
The analog switches 74 to 81 are turned off, and the reference voltages V0 (2.0 [V]) to V7 (4.8 [V]) can be selected.

When the control signal T2 is "L", the analog switches 66 to 73 are turned off, the analog switches 74 to 81 are turned on, and the reference voltage V8 (9.2) is set.
[V]) to V15 (12.0 [V]) can be selected.

In FIG. 6, reference numerals 83 _{1 to} 83 ₄ denote selectable reference voltages V0 to V7 or V8 to V8 output from the reference voltage source 49 in accordance with the selection signals output from the level conversion circuit sections 32 _{1 to} 32 _4. A selector for selecting one reference voltage from V15.

[0031] These selectors 83 ₁ to 83 ₄ are the same circuit configuration, if Shimese on behalf of the selector 83 _1,
It is configured as shown in FIG. 8, and is connected to the reference voltage source 49 as shown in FIG.

In the figure, 84 to 91 are analog switches whose ON and OFF are controlled by the outputs of the level conversion circuits 33 to 40, respectively. These analog switches 84 to 91 correspond to the corresponding level conversion circuits, respectively. The output is OFF when the output = 0 [V], and ON when the output of the corresponding level conversion circuit is 15 [V].

[0033] Thus, digital display signal D _IN or digital inverted display signal is input to the decoder 13 ₁ / D _IN
When the relationship between the selectors 83 ₁ of the output voltage (reference voltage selector 83 ₁ selects) are as shown in Table 3.

[0034]

[Table 3]

Therefore, a digital display signal D _IN inputted from the outside, an inversion / non-inversion instruction signal AP for controlling the inversion / non-inversion circuit 9, a control signal T2 for controlling the reference voltage source 49, and a selector relationship with 83 ₁ of the output voltage (reference voltage selector 83 ₁ selects) are as indicated in Table 4.

[0036]

[Table 4]

Further, in FIG. 6, 92 ₁ to 92 ₄ are analog switches, 93 a control signal T3 of the logic level output from the control circuit 8 and the level conversion, the analog switches 92 ₁ to 92 ₄ to ON, This is a level conversion circuit that controls OFF.

Also, 94 _{1 to} 94 ₄ are analog
The selector is supplied via the switch 92 ₁ to 92 ₄ 83
_{1-83 4} capacitor for storing the reference voltage selected is 9
5 _{1-95 4} is an operational amplifier constituting the buffer.

Reference numeral 96 denotes an LSI gate driver for driving the gate lines Y _{1 to} Y _4. T 4 denotes a start signal having the same cycle as the vertical synchronizing signal VS outputted from the control circuit 8, and CK 2. Is a clock signal having the same cycle as the horizontal synchronizing signal HS output from the control circuit 8.

Further, 97 is a start signal T4 shifted by one bit in synchronism with the clock signal CK2, the gate drive signal DV ₁ ～DV ₄ shift register serial input-parallel output type of the output 4 bits constituting the is there.

Also, 98 _{1 to} 98 ₄ are shift registers 97
Gate drive signal DV ₁ ~DV ₄ ON the TFT 3 ₁₁ to 3 ₄₄ of the liquid crystal display panel 1 that is output from a level conversion circuit for converting a level capable OFF control.

FIGS. 11 and 12 are time charts for explaining the operation of such a conventional liquid crystal display device. FIG. 11 shows an odd frame (2n-1 vertical period).
FIG. 12 shows a first horizontal period and a second horizontal period in an even-numbered frame (2n vertical periods).

In the figure, D _{11 to} D ₁₄ are pixels 2 _{11 on} the first line.
Digital display signal for to 2 _14, D ₂₁ to D ₂₄ is a digital display signal to the pixel 2 _{21-2 24} of the second line, in this _{example, D 11 = D 21 = [} D2, D1, D0] =
[0, 0, 0], D ₁₂ = D ₂₂ = [D2, D1, D0] =
_{[0,1,1], D 13 = D} 23 = [D2, D1, D0] =
[1, 0, 1], D ₁₄ = D ₂₄ = [D2, D1, D0] =
[1, 1, 1].

As shown in FIG. 11, the first of the odd-numbered frames
In the horizontal period, the inversion / non-inversion instruction signal AP =
At "H", the inverting / non-inverting circuit 9 is maintained to operate as a non-inverting circuit, the control signal T2 is set to "H", and in the reference voltage source 49, the analog switches 66 to 73 are turned on. , Analog switches 74-81 = O
The reference voltages V0 (2.0 [V]) to V7 (4.
8 [V]) can be selected (see FIG. 10).

Therefore, in this example, the digital display signal D
_{11, D 12, D 13,} D 14 is not inverted, respectively, D ₁₁
= [D2, D1, D0] = [0,0,0], D 12 = [D
2, D1, D0] = [0, 1, 1], D ₁₃ = [D2, D
1, D0] = [1, 0, 1], D ₁₄ = [D2, D1, D
0] = [1,1,1] and the timing signals SP ₁ to SP ₁
Sequentially in synchronization with the SP ₄ are written into the memory circuit 12 ₁ to 12 _4.

In this case, as is apparent from Table 3,
Output voltage of selector 83 ₁ = 2.0 [V], selector 83
_Second output voltage = 3.2 [V], the selector 83 _third output voltage = 4.0 [V], the output voltage = 4.8 selectors 83 ₄
[V].

[0047] Here, the control signal T3 = "H", when the analog switches 92 ₁ to 92 ₄ = ON, the output voltage of the selector 83 ₁ to 83 _4, respectively, the capacitor 94
Held in _{1-94 4,} the voltage held in the capacitors 94 _{1-94 4,} as an analog display signal, the operational amplifier 95 _{1-95 4,} the data line X ₁ to X ₄ and TFT 3 ₁₁
Through to 3 ₁₄ is applied to the pixel electrode 5 _{11-5 14.}

The voltage between this result, in the pixel _211, the pixel electrode 5 ₁₁ and the common electrode 6 is 2.0-7.0 = -
5.0 [V], and the digital display signal D ₁₁ = [D2,
D1, D0] = [0, 0, 0].

In the pixel 2 ₁₂ , the pixel electrode 5 ₁₂
And the voltage between the common electrode 6 is 3.2-7.0 = −3.8.
[V], and the digital display signal D ₁₂ = [D2, D1,.
D0] = [0,1,1] is performed.

In the pixel 2 ₁₃ , the pixel electrode 5 ₁₃
And the voltage between the common electrode 6 is 4.0−7.0 = −3.0.
[V], and the digital display signal D ₁₃ = [D2, D1,.
D0] = [1, 0, 1].

In the pixel 2 ₁₄ , the pixel electrode 5 ₁₄
And the voltage between the common electrode 6 is 4.8-7.0 = −2.2.
[V], and the digital display signal D ₁₄ = [D2, D1,.
D0] = [1, 1, 1].

That is, in the first horizontal period in the odd-numbered frame, the display of each of the pixels 2 ₁₁ to 2 ₁₄ is performed by the pixel electrode 5 ₁₁
5 ₁₄ voltage <carried out under the relation of the voltage of the common electrode 6. The same applies to the third horizontal period. FIG.
Reference numeral 3 indicates the relationship between the voltage applied to the pixel electrode, the voltage between the pixel electrode and the common electrode (the voltage applied to the liquid crystal), and the transmittance of the liquid crystal.

Next, in the second horizontal period, the inversion / non-inversion instruction signal AP = “L”, and the inversion / non-inversion circuit 9
Is set to operate as an inverting circuit, and
The control signal T2 is set to "L", and in the reference voltage source 49, the analog switches 66 to 73 are turned off, the analog switches 74 to 81 are turned on, and the reference voltage V8 is set.
(9.2 [V]) to V15 (12.0 [V]) can be selected (see FIG. 10).

Therefore, in this example, the display data D ₂₁ , D
₂₂ , D ₂₃ , and D ₂₄ are respectively inverted, and / D ₂₁ = [/ D
2, / D1, / D0] = [1, 1, 1], / D ₂₂ = [/
D2, / D1, / D0] = [1,0,0], / D 23 =
[/ D2, / D1, / D0] = [0,1,0], / D 24
= [/ D2, / D1, / D0] is the = [0,0,0], sequentially written into the memory circuit 12 ₁ to 12 ₄ in synchronism with the timing signal SP ₁ to SP _4.

In this case, as is apparent from Table 3,
Output voltage of selector 83 ₁ = 12.0 [V], selector 8
3 ₂ of the output voltage = 10.8 [V], the selector 83 _third output voltage = 10.0 [V], the output voltage = 9 of the selector 83 _4.
2 [V].

[0056] Here, the control signal T3 = "H", when the analog switches 92 ₁ to 92 ₄ = ON, the output voltage of the selector 83 ₁ to 83 _4, respectively, the capacitor 94
Held in _{1-94 4,} the voltage held in the capacitors 94 _{1-94 4,} as an analog display signal, the operational amplifier 95 _{1-95 4,} the data line X ₁ to X ₄ and TFT 3 ₂₁
Through to 3 ₂₄ is applied to the pixel electrode 5 _{21-5 24.}

[0057] voltage between this result, in the pixel 2 _21, and the pixel electrode 5 ₂₁ and the common electrode 6, 12.0-7.0 =
5.0 [V], and the digital display signal D ₂₁ = [D2,
D1, D0] = [0, 0, 0].

In the pixel 2 ₂₂ , the pixel electrode 5 ₂₂
And the voltage between the common electrode 6 is 10.8-7.0 = 3.8.
[V], and the digital display signal D ₂₂ = [D2, D1,.
D0] = [0,1,1] is performed.

In the pixel 2 ₂₃ , the pixel electrode 5 ₂₃
And the voltage between the common electrode 6 is 10.0-7.0 = 3.0.
[V], and the digital display signal D ₂₃ = [D2, D1,.
D0] = [1, 0, 1].

In the pixel 2 ₂₄ , the pixel electrode 5 ₂₄
And the voltage between the common electrode 6 is 9.2-7.0 = 2.2
[V], and the digital display signal D ₂₄ = [D2, D1,.
D0] = [1, 1, 1].

That is, in the second horizontal period in the odd-numbered frame, the display of each of the pixels 2 ₂₁ to 2 ₂₄ is performed by the pixel electrode 5 ₂₁
5 ₂₄ voltage> performed under the relationship between the voltage of the common electrode 6. The same applies to the fourth horizontal period.

Next, as shown in FIG. 12, in the first horizontal period of the even frame, the inversion / non-inversion instruction signal AP =
At “L”, the inverting / non-inverting circuit 9 is maintained to operate as _an inverting circuit, and the control signal T2 = “L”
In the reference voltage source 49, the analog switch 6
6-73 = OFF, analog switches 74-81 = O
N, and the reference voltages V8 (9.2 [V]) to V15 (1
2.0 [V]) can be selected (see FIG. 10).

Therefore, in this example, the display data D ₁₁ , D
₁₂ , D ₁₃ , and D ₁₄ are respectively inverted, and / D ₁₁ = [/ D
2, / D1, / D0] = [1, 1, 1], / D ₁₂ = [/
D2, / D1, / D0] = [1,0,0], / D 13 =
[/ D2, / D1, / D0] = [0,1,0], / D 14
= [/ D2, / D1, / D0] is the = [0,0,0], sequentially written into the memory circuit 12 ₁ to 12 ₄ in synchronism with the timing signal SP ₁ to SP _4.

In this case, as is apparent from Table 3,
Output voltage of selector 83 ₁ = 12.0 [V], selector 8
3 ₂ of the output voltage = 10.8 [V], the selector 83 _third output voltage = 10.0 [V], the output voltage = 9 of the selector 83 _4.
2 [V].

[0065] Here, the control signal T3 = "H", when the analog switches 92 ₁ to 92 ₄ = ON, the output voltage of the selector 83 ₁ to 83 _4, respectively, the capacitor 94
Held in _{1-94 4,} the voltage held in the capacitors 94 _{1-94 4,} as an analog display signal, the operational amplifier 95 _{1-95 4,} the data line X ₁ to X ₄ and TFT 3 ₁₁
Through to 3 ₁₄ is applied to the pixel electrode 5 _{11-5 14.}

[0066] voltage between this result, in the pixel _211, the pixel electrode 5 ₁₁ and the common electrode 6, 12.0-7.0 =
5.0 [V], and the digital display signal D ₁₁ = [D2,
D1, D0] = [0, 0, 0].

In the pixel 2 ₁₂ , the pixel electrode 5 ₁₂
And the voltage between the common electrode 6 is 10.8-7.0 = 3.8.
[V], and the digital display signal D ₁₂ = [D2, D1,.
D0] = [0,1,1] is performed.

In the pixel 2 ₁₃ , the pixel electrode 5 ₁₃
And the voltage between the common electrode 6 is 10.0-7.0 = 3.0.
[V], and the digital display signal D ₁₃ = [D2, D1,.
D0] = [1, 0, 1].

In the pixel 2 ₁₄ , the pixel electrode 5 ₁₄
And the voltage between the common electrode 6 is 9.2-7.0 = 2.2
[V], and the digital display signal D ₁₄ = [D2, D1,.
D0] = [1, 1, 1].

That is, in the first horizontal period in the even-numbered frame, the display of each pixel 2 ₁₁ to 2 ₁₄ is performed by the pixel electrode 5 ₁₁
5 ₁₄ voltage> performed under the relationship between the voltage of the common electrode 6. The same applies to the third horizontal period.

Next, in the second horizontal period, the inversion / non-inversion circuit 9 is set to operate as a non-inversion circuit with the inversion / non-inversion instruction signal AP = “H”, and the control signal T2 = It is set to “H”, and in the reference voltage source 49, the analog switches 66 to 73 are turned on, the analog switches 74 to 81 are turned off, and the reference voltage V0 (2.0) is set.
[V]) to V7 (4.8 [V]) can be selected (see FIG. 10).

Therefore, in this example, the digital display signal D
_{21, D 22, D 23,} D 24 is not inverted, respectively, D ₂₁
= [D2, D1, D0] = [0,0,0], D 22 = [D
2, D1, D0] = [0, 1, 1], D ₂₃ = [D2, D
1, D0] = [1, 0, 1], D ₂₄ = [D2, D1, D
0] = [1,1,1] and the timing signals SP ₁ to SP ₁
Sequentially in synchronization with the SP ₄ are written into the memory circuit 12 ₁ to 12 _4.

In this case, as is apparent from Table 3,
Output voltage of selector 83 ₁ = 2.0 [V], selector 83
_Second output voltage = 3.2 [V], the selector 83 _third output voltage = 4.0 [V], the output voltage = 4.8 selectors 83 ₄
[V].

[0074] Here, the control signal T3 = "H", when the analog switches 92 ₁ to 92 ₄ = ON, the output voltage of the selector 83 ₁ to 83 _4, respectively, the capacitor 94
Held in _{1-94 4,} the voltage held in the capacitors 94 _{1-94 4,} as an analog display signal, the operational amplifier 95 _{1-95 4,} the data line X ₁ to X ₄ and TFT 3 ₂₁
Through to 3 ₂₄ is applied to the pixel electrode 5 _{21-5 24.}

[0075] voltage between this result, in the pixel 2 _21, and the pixel electrode 5 ₂₁ and the common electrode 6 is 2.0-7.0 = -
5.0 [V], and the digital display signal D ₂₁ = [D2,
D1, D0] = [0, 0, 0].

In the pixel 2 ₂₂ , the pixel electrode 5 ₂₂
And the voltage between the common electrode 6 is 3.2-7.0 = −3.8.
[V], and the digital display signal D ₂₂ = [D2, D1,.
D0] = [0,1,1] is performed.

In the pixel 2 ₂₃ , the pixel electrode 5 ₂₃
And the voltage between the common electrode 6 is 4.0−7.0 = −3.0.
[V], and the digital display signal D ₂₃ = [D2, D1,.
D0] = [1, 0, 1].

In the pixel 2 ₂₄ , the pixel electrode 5 ₂₄
And the voltage between the common electrode 6 is 4.8-7.0 = −2.2.
[V], and the digital display signal D ₂₄ = [D2, D1,.
D0] = [1, 1, 1].

That is, in the second horizontal period in the even-numbered frame, the display of each of the pixels 2 ₂₁ to 2 ₂₄ is performed by the pixel electrode 5 ₂₁
5 ₂₄ voltage <carried out under the relation of the voltage of the common electrode 6. The same applies to the fourth horizontal period.

As described above, in the liquid crystal display device, in the first and third horizontal periods of the odd frame, the voltages of the pixel electrodes 5 _{11 to} 5 ₁₄ and 5 _{31 to} 5 ₃₄ <the voltage of the common electrode 6, and the odd number the second frame, in the fourth horizontal period, a voltage> the voltage of the common electrode 6 of the pixel electrode 5 _{21-5 24,} 5 _{41-5 44,} the first even frame, the third horizontal period, the pixel electrode 5 ₁₁ 5 _14, 5 ₃₁ and 5 ₃₄ voltage> the voltage of the common electrode 6 of the second even frame, in the fourth horizontal period, the voltage of the pixel electrode 5 ₂₂ 5 _24, 5 ₄₂ to 5 ₄₄ <common electrode 6 , And AC drive is performed.

In other words, for the same line, the AC drive is performed such that the voltage polarity between the pixel electrode and the common electrode is inverted every frame. The reason why the voltage polarity between the pixel electrode and the common electrode is inverted every line in one frame is to reduce crosstalk.

[0082]

In such a conventional liquid crystal display device, V0 (2.0 [V]) is used as a reference voltage.
To V7 (4.8 [V]) and high voltage V8 (9.2 [V]).
[V] to V15 (12.0 [V]), an operational amplifier having a high withstand voltage and a large current must be used as the operational amplifier constituting the reference voltage source 49. For this reason, there has been a problem that the cost is increased and the power consumption is increased.

Similarly, V0 (2.
0 [V]) to V7 (4.8 [V]), and a high voltage V7
Since in need of (9.2 [V]) ~V15 ( 12.0 [V]), with a high breakdown voltage that is needed as the analog switches constituting the selector 83 ₁ to 83 _4, the selector 83 _{1-83 4} analog switches oN constituting the decoder 13 ₁ to 1 in order to control the OFF
3 ₄ logic level of the select signal of a high voltage output from, for example, the level conversion circuit unit 3 for level conversion to 15 [V]
Would it require a 2 _{1-32 4.}

Therefore, the LSI of the data driver 10
In such a case, the chip area is increased, the cost of the data driver 10 is increased, and the cost of the liquid crystal display device itself is increased.

[0085] Here, the reference voltage is an analog which requires twice as many number of gradations, constituting the selector 83 ₁ to 83 ₄
The number of the level conversion circuit constituting the switching number and the level conversion circuit unit 321 _to 323 _4, respectively, shall be the same as the number of gradations. Therefore, the above-mentioned problem becomes a very serious problem when an attempt is made to increase the number of gradations and improve the display quality.

In view of the above, the present invention has a structure in which the number of reference voltages is the same as the number of gradations and does not require a high voltage as the reference voltage, so that the cost can be reduced.
It is an object of the present invention to provide an AC driving type liquid crystal display device including an active matrix type liquid crystal display panel, which can reduce power consumption.

[0087]

FIG. 1 is a diagram showing in principle the circuit configuration of the present invention. In the figure, reference numeral 100 denotes an active matrix type which is driven by an alternating current with a constant common voltage to be applied to a common electrode. The liquid crystal display panel 101 is a reference voltage source that outputs a reference voltage having a voltage lower than the common voltage and a different value equal to the number of gradations.

The reference numeral 102 designates a digital display signal supplied from the outside in accordance with a predetermined rule, for example, for the same line, inverting the voltage polarity between the pixel electrode and the common electrode every frame, and changing the polarity within one frame. In 1
This is a reference voltage selection circuit that decodes with or without inversion according to the rule of inverting the voltage polarity between the pixel electrode and the common electrode for each line, and selects a corresponding reference voltage from the reference voltage source 101.

Reference numeral 103 denotes a reference voltage holding circuit that holds the reference voltage selected by the reference voltage selection circuit 102. Reference numeral 104 denotes a case where an analog display signal higher than the common voltage is to be supplied to the pixel electrode. This is an addition voltage generation circuit that generates an addition voltage to be added to the reference voltage held in the reference voltage holding circuit 103.

When an analog display signal having a voltage lower than the common voltage is to be supplied to the pixel electrode 105, the reference voltage held in the reference voltage holding circuit 103 is supplied to the pixel electrode, and the reference voltage 105 is supplied to the pixel electrode. When an analog display signal higher than the voltage is to be supplied, the reference voltage holding circuit 1
This is an analog display signal supply circuit that supplies a voltage obtained by adding the addition voltage generated from the addition voltage generation circuit 104 to the reference voltage held at 03 to the pixel electrode.

[0091]

In the present invention, when an analog display signal lower than the common voltage is to be supplied to the pixel electrode, the reference voltage held in the reference voltage holding circuit 103 is supplied to the pixel electrode, and the pixel electrode is supplied to the pixel electrode. If an analog display signal higher than the common voltage is to be supplied, the reference voltage holding circuit 1
AC driving is performed by supplying a voltage obtained by adding the addition voltage generated from the addition voltage generation circuit 104 to the reference voltage held at 03 to the pixel electrode.

As a result, since the reference voltage to be output from the reference voltage source 101 is lower than the common voltage, an operational amplifier having a high withstand voltage and a high current is not required as the operational amplifier constituting the reference voltage source 101. It is sufficient to provide a low-voltage, low-current operational amplifier.

Further, the number of reference voltages is sufficient to be the same as the number of gradations, and can be reduced to half of the conventional case. Further, the added voltage generated from the added voltage generating circuit 104 is one voltage value. And the added voltage generation circuit 104 can be constituted by a simple circuit.

As described above, since the reference voltage to be output from the reference voltage source 101 is lower than the common voltage, an analog switch constituting a selector for selecting a reference voltage in the reference voltage selection circuit 102 is used. As a result, a high-breakdown-voltage analog switch is not required, and a low-breakdown-voltage analog switch is sufficient. As a result, a level conversion circuit necessary for operating the high-breakdown-voltage analog switch is not required.

In addition, the addition of the additional voltage is performed by forming the reference voltage holding circuit 103 with a capacitor and using the reference voltage selection circuit 10.
Holding the reference voltage selected by 2 on the capacitor;
The addition voltage generation circuit 104 is connected to the low voltage side electrode of the capacitor.
Can be performed by applying an additional voltage generated from.

[0096]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS. 2 to 5, taking an improved version of the conventional liquid crystal display device shown in FIG. In FIGS. 2 and 3, parts corresponding to those in FIGS. 6 and 8 are denoted by the same reference numerals, and redundant description is omitted.

FIG. 2 is a diagram schematically showing a circuit configuration of a main part of one embodiment of the present invention. In this embodiment, an active matrix type liquid crystal display panel 1, an inversion / non-inversion circuit 9, a level Conversion circuit 93 and gate driver 96
Is configured similarly to the conventional liquid crystal display device shown in FIG.

This embodiment is different from the conventional liquid crystal display shown in FIG. 6 in that the control circuit 8, reference voltage source 49 and data driver 10 provided in the conventional liquid crystal display shown in FIG. A different point is that a control circuit 106, a reference voltage source 107 and a data driver 108 having different configurations are provided, and an additional voltage generating circuit 109 which is not provided in the conventional liquid crystal display device shown in FIG. 6 is provided.

The difference between the control circuit 106 and the control circuit 8 provided in the conventional liquid crystal display device shown in FIG.
A point that the control signal T2 for controlling the selectable reference voltage is not outputted to the reference voltage source 107, and a point that the control signal TD for controlling the addition voltage generation circuit 109 is outputted.
Otherwise, the configuration is the same as that of the control circuit 8 provided in the conventional liquid crystal display device shown in FIG.

Here, the reference voltage source 107 is configured as shown in FIG. 3, and this reference voltage source 107 is different from the reference voltage source 49 provided in the conventional liquid crystal display device shown in FIG. , Reference voltages V0 (2.0 [V]) to V7 (4.
8 [V]) are provided, and only reference voltage sources 50 to 57 for outputting reference voltages V8 (9.2 [V]) to V15 are provided.
(12.0 [V]), reference voltage sources 58 to 65,
The point is that the analog switches 66 to 81 and the inverter 82 are not provided (see FIG. 10).

The data driver 108 is the data driver 1 provided in the conventional liquid crystal display device shown in FIG.
0 differs, not providing the level conversion circuit unit 321 _to 323 ₄ and the selector 83 ₁ to 83 _4, alternatively, the reference voltage is selected according to the selection signal output from the decoder _131-134 that it is provided with a selector _{1101 4,} and connection of the capacitor 94 _{1-94 4,} i.e., the capacitor 94 _{1-94 4} operational amplifiers 95 ₁ to 95 ₄
Electrodes 94A ₁ electrodes opposed to being connected to the non-inverting input terminal of ～94A ₄ is a point of being commonly connected, other memory circuits 12 ₁ to 12 _4, the decoder _131-134,
The operational amplifiers 95 _{1 to} 95 ₄ have the same configuration as the data driver 10 provided in the conventional liquid crystal display device shown in FIG.

Here, the selectors 110 _{1 to} 110 ₄ have the same circuit configuration. If the selector 110 ₁ is shown as a representative, it is configured as shown in FIG.
10 ₁ is different from the selector 83 ₁ provided in the conventional liquid crystal display device shown in FIG. 6, in place of the analog switches 84-91 of the high withstand voltage selector 83 ₁ is provided, ON at the logical level of the signal, OFF Are provided with analog switches 111 to 118 having a low withstand voltage.

[0103] In this embodiment, these analog switches 111 to 118, respectively, ON, OFF is controlled by the output of the decoder 13 ₁ of the NOR circuit 24 to 31, the output = 0 of the corresponding NOR circuit [V] (L level) OFF, output of corresponding NOR circuit = 5
In the case of [V] (H level), it is turned ON.

[0104] Thus, digital display signal D _IN or digital inverted display signal is input to the decoder 13 ₁ / D _IN
When the relationship between the selector 110 ₁ of the output voltage (reference voltage selector 110 ₁ selects) is as shown in Table 5.

[0105]

[Table 5]

[0106] Thus, also, a digital display signal D _IN inputted from outside, and inversion and non-inversion command signal AP which controls the inversion and non-inversion circuit 9, the selector 110 _first output voltage (selector 110 ₁ selects Table 6 shows the relationship with the reference voltage.

[0107]

[Table 6]

The addition voltage generation circuit 109 includes an inverter 119 for inverting the control signal and a voltage VA, for example,
A VA voltage source 120 that outputs 2.0 [V];
B, for example, a VB voltage source 121 that outputs 9.2 [V]
An analog switch 122 whose ON / OFF is controlled by the control signal TD, and an analog switch 123 whose ON / OFF is controlled by the output of the inverter 119
Are provided.

Here, these analog switches 12
Fixed contacts 2,123 is connected to the electrode 94A ₁ ~94A ₄ of the capacitor 94 _{1-94 4,} the control signal TD =
In the case of “H”, the analog switch 122 is turned on, the analog switch 123 is turned off, and the control signal TD =
In the case of “L”, the analog switch 122 is turned off and the analog switch 123 is turned on.

The control signal TD is a signal that alternates between an H level and an L level. The control signal TD includes a first horizontal period, a third horizontal period of an odd-numbered frame, a second horizontal period of an even-numbered frame,
In the fourth horizontal period, the common voltage Vcom is applied to the pixel electrode.
Assuming that it should provide an analog display signal voltage lower than, in this case, the control signal T3 = "H", the analog switch 92 ₁ ~92 ₄ = ON, the selector 11
The reference voltages selected by O _{1 to} 110 ₄ are stored in the capacitors 94 ₁ to 94 ₁
Before to be held in 94 _4, it is set to "L" → "H".

Further, the control signal TD indicates the second horizontal period and the fourth horizontal period of the odd frame and the first horizontal period of the even frame.
In the horizontal period and the third horizontal period, it is assumed that an analog display signal having a voltage higher than the common voltage Vcom should be supplied to the pixel electrode. In this case, the control signal T3 =
"H", the analog switches 92 _{1 to} 92 ₄ = ON,
After the reference voltages selected by the selectors 110 _{1 to} 110 ₄ are held in the capacitors 94 _{1 to} 94 ₄ , “H” is changed to “L”.

FIGS. 4 and 5 are time charts for explaining the operation of the present embodiment. FIG. 4 shows the first horizontal period and the second horizontal period in an odd-numbered frame (2n-1 vertical period). Indicates a first horizontal period and a second horizontal period in an even-numbered frame (2n vertical periods).

In the figure, D _{11 to} D ₁₄ are pixels 2 _{11 on} the first line.
Digital display signal for to 2 _14, D ₂₁ to D ₂₄ is a digital display signal to the pixel 2 _{21-2 24} of the second line, also in this embodiment, as in the conventional example shown in FIGS. 11 and 12 D ₁₁ = D ₂₁ = [D2, D1, D0]
= [0,0,0], D ₁₂ = D ₂₂ = [D2, D1, D0]
_{= [0,1,1], D 13 =} D 23 = [D2, D1, D0]
= [1, 0, 1], D ₁₄ = D ₂₄ = [D2, D1, D0]
= [1,1,1].

As shown in FIG. 4, in the first horizontal period of the odd frame, the inversion / non-inversion instruction signal AP = “H”
Thus, the inverting / non-inverting circuit 9 is maintained so as to operate as a non-inverting circuit.

Therefore, in this example, the digital display signal D
_{11, D 12, D 13,} D 14 is not inverted, respectively, D ₁₁
= [D2, D1, D0] = [0,0,0], D 12 = [D
2, D1, D0] = [0, 1, 1], D ₁₃ = [D2, D
1, D0] = [1, 0, 1], D ₁₄ = [D2, D1, D
0] = [1,1,1] and the timing signals SP ₁ to SP ₁
Sequentially in synchronization with the SP ₄ are written into the memory circuit 12 ₁ to 12 _4.

In this case, as apparent from Table 5,
Output voltage of selector 110 ₁ = 2.0 [V], selector 1
10 _second output voltage = 3.2 [V], the output voltage = 4.0 selectors 110 ₃ [V], the selector 110 ₄ of the output voltage =
It becomes 4.8 [V].

[0117] Here, the control signal TD, when to be supplied to an analog display signal voltage lower than the common voltage Vcom to the pixel electrodes, the control signal T3 = "H", the analog switch 92 _{1-92 4} = Set to ON and selectors 110 _{1 to} 11
0 ₄ reference voltage selected is prior to held in the capacitor 94 _{1-94 4} is "L" → "H".

[0118] Consequently, before the reference voltage corresponding to the digital display signal D ₁₁ to D ₁₄ from the selector _{1101 4} has been selected is held in the capacitor 94 _{1-94 4,} the sum voltage generating circuit 109, Analog switch 122
= ON, and the analog switch 123 = OFF.

[0119] Accordingly, the capacitors 94 _{1-94 4} electrodes _{94A 1 ~94A 4 = 2 [V} ], the capacitor 94
₁ voltage to 94 ₄ of the operational amplifier 95 _{1-95 4} side electrode,
Before the addition voltage is added in the fourth horizontal period of the previous even frame, the reference voltage value is selected by the selectors 110 _{1 to} 110 ₄ (in FIG. 4, Z _{1 to} Z ₄ indicate this reference voltage value). There).

[0120] Thereafter, the control signal T3 = "H", the analog switch 92 ₁ ~92 ₄ = ON, the selector 110
Reference _{voltage 1-110 4} corresponds to the digital display signal D ₁₁ to D ₁₄ selected will be held in the capacitor 94 _{1-94 4,}
Subsequently, the control signal T3 is set to "L", and the control signal TD is maintained at "H".

Therefore, in this case, the voltages held in these capacitors 94 _{1 to} 94 ₄ are used as analog display signals as operational amplifiers 95 _{1 to} 95 ₄ and data lines X _{1 to} X ₄
And it is applied to the pixel electrode 5 _{11-5 14} via the TFT 3 ₁₁ to 3 _14.

As a result, in the pixel 2 ₁₁ , the voltage between the pixel electrode 5 ₁₁ and the common electrode 6 becomes 2.0−7.0 = −
5.0 [V], and the digital display signal D ₁₁ = [D2,
D1, D0] = [0, 0, 0].

In the pixel 2 ₁₂ , the pixel electrode 5 ₁₂
And the voltage between the common electrode 6 is 3.2-7.0 = −3.8.
[V], and the digital display signal D ₁₂ = [D2, D1,.
D0] = [0,1,1] is performed.

In the pixel 2 ₁₃ , the pixel electrode 5 ₁₃
And the voltage between the common electrode 6 is 4.0−7.0 = −3.0.
[V], and the digital display signal D ₁₃ = [D2, D1,.
D0] = [1, 0, 1].

In the pixel 2 ₁₄ , the pixel electrode 5 ₁₄
And the voltage between the common electrode 6 is 4.8-7.0 = −2.2.
[V], and the digital display signal D ₁₄ = [D2, D1,.
D0] = [1, 1, 1].

That is, in the first horizontal period in the odd-numbered frame, the display of each of the pixels 2 ₁₁ to 2 ₁₄ is performed by the pixel electrode 5 ₁₁
5 ₁₄ voltage <carried out under the relation of the voltage of the common electrode 6. The same applies to the third horizontal period.

Next, in the second horizontal period, the inversion / non-inversion instruction signal AP = “L”, and the inversion / non-inversion circuit 9
Are set to operate as an inverting circuit.

Therefore, in this example, the digital display signal D
₂₁ , D ₂₂ , D ₂₃ , and D ₂₄ are respectively inverted, and / D ₂₁ =
[/ D2, / D1, / D0] = [1,1,1], / D 22
= [/ D2, / D1, / D0] = [1, 0, 0], / D
₂₃ = [/ D2, / D1, / D0] = [0,1,0], /
_{D 24 = [/ D2, /} D1, / D0] is the = [0,0,0], sequentially written into the memory circuit 12 ₁ to 12 ₄ in synchronism with the timing signal SP ₁ to SP _4.

In this case, as apparent from Table 5,
Output voltage of selector 110 ₁ = 4.8 [V], selector 1
Output voltage of 10 ₂ = 3.6 [V], output voltage of selector 110 ₃ = 2.8 [V], output voltage of selector 110 ₄ =
2.0 [V].

[0130] Here, the control signal TD, when to be supplied to an analog display signal voltage higher than the common voltage Vcom to the pixel electrodes, the control signal T3 = "H", the analog switch 92 _{1-92 4} = Set to ON and selectors 110 _{1 to} 11
0 ₄ reference voltage selected is the after holding the capacitor 94 _{1-94 4,} is the "H" → "L".

As a result, in this case, control signal TD =
"H", analog switch 122 = ON, analog
The switch 123 = OFF, the state where there is a capacitor 94 _{1-94 4} electrodes _{94A 1 ~94A 4 = 2 [V} ], the control signal T3 = "H", the analog switch 92
Is a ₁ to 92 ₄ = ON, the reference voltage corresponding to the digital highlight signal / D ₂₁ ~ / D ₂₄ to the selector _{1101 4} has been selected is held in the capacitor 94 _{1-94 4} respectively.

[0132] Then, control signal T3 = is "L", the analog switch 92 ₁ to 92 ₄ = OFF, followed by the control signal TD = is "L", the analog switch 122 =
OFF, the analog switch 123 = ON, the electrode 94A ₁ ~94A ₄ of the capacitor 94 _{1-94 4} 9.2
[V] (voltage VB) is applied.

[0133] In this case, the electrode 94A ₁ ~94A ₄ of the capacitor 94 _{1-94 4,} 9.2 [V] (voltage VB) -2.0
This means that the voltage has been increased by [V] (voltage VA) = 7.2 [V].

[0134] As a result, the voltage of the operational amplifier 95 ₁ side electrode of the capacitor _{94 1 = 4.8 + 7.2 = 12.0} [V],
Voltage of the electrode of the capacitor 94 _{2 on} the side of the operational amplifier 95 ₂
3.6 + 7.2 = 10.8 [V] , the voltage of the operational amplifier 95 ₃ side electrode of the capacitor 94 ₃ = 2.8 + 7.2 = 10.0
[V], the voltage of the operational amplifier 95 ₄ side electrode of the capacitor 94 ₄ = 2.0 + 7.2 = 9.2 becomes [V].

Therefore, in this case, the capacitor 9
4 _1-94 voltage that is added to 7.2 [V] at the reference voltage held in the _4, as an analog display signal, the operational amplifier 9
5 _{1-95 4,} the data line X ₁ to X ₂ and TFT 3 ₂₁ to 3
Through _24, it is applied to the pixel electrode 5 _{21-5 24.}

[0136] voltage between this result, in the pixel 2 _21, and the pixel electrode 5 ₂₁ and the common electrode 6, 12.0-7.0 =
5.0 [V], and the digital display signal D ₂₁ = [D2,
D1, D0] = [0, 0, 0].

In the pixel 2 ₂₂ , the pixel electrode 5 ₂₂
And the voltage between the common electrode 6 is 10.8-7.0 = 3.8.
[V], and the digital display signal D ₂₂ = [D2, D1,.
D0] = [0,1,1] is performed.

In the pixel 2 ₂₃ , the pixel electrode 5 ₂₃
And the voltage between the common electrode 6 is 10.0-7.0 = 3.0.
[V], and the digital display signal D ₂₃ = [D2, D1,.
D0] = [1, 0, 1].

In the pixel 2 ₂₄ , the pixel electrode 5 ₂₄
And the voltage between the common electrode 6 is 9.2-7.0 = 2.2
[V], and the digital display signal D ₂₄ = [D2, D1,.
D0] = [1, 1, 1].

That is, in the second horizontal period in the odd-numbered frame, display of each of the pixels 2 ₂₁ to 2 ₂₄ is performed by the pixel electrode 5 ₂₁
5 ₂₄ voltage> performed under the relationship between the voltage of the common electrode 6. The same applies to the fourth horizontal period.

Next, as shown in FIG. 5, in the first horizontal period of the even-numbered frame, the inversion / non-inversion instruction signal AP =
At "L", the inverting / non-inverting circuit 9 is maintained to operate as an inverting circuit.

Therefore, in this example, the digital display signal D
₁₁ , D ₁₂ , D ₁₃ , and D ₁₄ are respectively inverted, and / D ₁₁ =
[/ D2, / D1, / D0] = [1,1,1], / D 12
= [/ D2, / D1, / D0] = [1, 0, 0], / D
₁₃ = [/ D2, / D1, / D0] = [0,1,0], /
_{D 14 = [/ D2, /} D1, / D0] is the = [0,0,0], sequentially written into the memory circuit 12 ₁ to 12 ₄ in synchronism with the timing signal SP ₁ to SP _4.

In this case, as apparent from Table 5,
Output voltage of selector 110 ₁ = 4.8 [V], selector 1
Output voltage of 10 ₂ = 3.6 [V], output voltage of selector 110 ₃ = 2.8 [V], output voltage of selector 110 ₄ =
2.0 [V].

[0144] Here, the control signal TD, when to be supplied to an analog display signal voltage higher than the common voltage Vcom to the pixel electrodes, the control signal T3 = "H", the analog switch 92 _{1-92 4} = Set to ON and selectors 110 _{1 to} 11
0 ₄ reference voltage selected is the after holding the capacitor 94 _{1-94 4,} is the "H" → "L".

Thus, in this case, control signal TD =
"H", analog switch 122 = ON, analog
The switch 123 = OFF, the state where there is a capacitor 94 _{1-94 4} electrodes _{94A 1 ~94A 4 = 2 [V} ], the control signal T3 = "H", the analog switch 92
Is a ₁ to 92 ₄ = ON, the reference voltage corresponding to the digital inverted signal / D ₁₁ ~ / D ₁₄ to the selector _{1101 4} has been selected is held in the capacitor 94 _{1-94 4} respectively.

[0146] Then, control signal T3 = is "L", the analog switch 92 ₁ to 92 ₄ = OFF, followed by the control signal TD = is "L", the analog switch 122 =
OFF, the analog switch 123 = ON, the electrode 94A ₁ ~94A ₄ of the capacitor 94 _{1-94 4} 9.2
[V] (voltage VB) is applied.

[0147] In this case, the electrode 94A ₁ ~94A ₄ of the capacitor 94 _{1-94 4,} 9.2 [V] (voltage VB) -2.0
This means that the voltage has been increased by [V] (voltage VA) = 7.2 [V].

[0148] As a result, the voltage of the operational amplifier 95 ₁ side electrode of the capacitor _{94 1 = 4.8 + 7.2 = 12.0} [V],
Voltage of the electrode of the capacitor 94 _{2 on} the side of the operational amplifier 95 ₂
3.6 + 7.2 = 10.8 [V] , the voltage of the operational amplifier 95 ₃ side electrode of the capacitor 94 ₃ = 2.8 + 7.2 = 10.0
[V], the voltage of the operational amplifier 95 ₄ side electrode of the capacitor 94 ₄ = 2.0 + 7.2 = 9.2 becomes [V].

Therefore, in this case, the capacitor 9
4 _{1-94 4} the reference voltage held in 7.2 voltage obtained by adding a [V] is the operational amplifier 95 ₁ to an analog display signal
95 _4, via the data line X ₁ to X ₂ and TFT 3 ₁₁ to 3 _14, is applied to the pixel electrode 5 _{11-5 14.}

[0150] voltage between this result, in the pixel _211, the pixel electrode 5 ₁₁ and the common electrode 6, 12.0-7.0 =
5.0 [V], and the digital display signal D ₁₁ = [D2,
D1, D0] = [0, 0, 0].

In the pixel 2 ₁₂ , the pixel electrode 5 ₁₂
And the voltage between the common electrode 6 is 10.8-7.0 = 3.8.
[V], and the digital display signal D ₁₂ = [D2, D1,.
D0] = [0,1,1] is performed.

In the pixel 2 ₁₃ , the pixel electrode 5 ₁₃
And the voltage between the common electrode 6 is 10.0-7.0 = 3.0.
[V], and the digital display signal D ₁₃ = [D2, D1,.
D0] = [1, 0, 1].

In the pixel 2 ₁₄ , the pixel electrode 5 ₁₄
And the voltage between the common electrode 6 is 9.2-7.0 = 2.2
[V], and the digital display signal D ₁₄ = [D2, D1,.
D0] = [1, 1, 1].

That is, in the first horizontal period in the even-numbered frame, the display of each of the pixels 2 ₁₁ to 2 ₁₄ is performed by the pixel electrode 5 ₁₁
5 ₁₄ voltage> performed under the relationship between the voltage of the common electrode 6. The same applies to the third horizontal period.

Next, in the second horizontal period, the inversion / non-inversion instruction signal AP = “H”, and the inversion / non-inversion circuit 9
Are set to operate as a non-inverting circuit.

Therefore, in this example, the digital display signal D
_{21, D 22, D 23,} D 24 is not inverted, respectively, D ₂₁
= [D2, D1, D0] = [0,0,0], D 22 = [D
2, D1, D0] = [0, 1, 1], D ₂₃ = [D2, D
1, D0] = [1, 0, 1], D ₂₄ = [D2, D1, D
0] = [1,1,1] and the timing signals SP ₁ to SP ₁
Sequentially in synchronization with the SP ₄ are written into the memory circuit 12 ₁ to 12 _4.

In this case, as is apparent from Table 5,
Output voltage of selector 110 ₁ = 2.0 [V], selector 1
10 _second output voltage = 3.2 [V], the output voltage = 4.0 selectors 110 ₃ [V], the selector 110 ₄ of the output voltage =
It becomes 4.8 [V].

[0158] Here, the control signal TD, when to be supplied to an analog display signal voltage lower than the common voltage Vcom to the pixel electrodes, the control signal T3 = "H", the analog switch 92 _{1-92 4} = Set to ON and selectors 110 _{1 to} 11
0 ₄ reference voltage selected is prior to held in the capacitor 94 _{1-94 4} is "L" → "H".

[0159] Consequently, before the reference voltage corresponding to the digital display signal D ₁₁ to D ₁₄ from the selector _{1101 4} has been selected is held in the capacitor 94 _{1-94 4,} the sum voltage generating circuit 109, Analog switch 122
= ON, and the analog switch 123 = OFF.

[0160] Accordingly, the capacitors 94 _{1-94 4} electrodes _{94A 1 ~94A 4 = 2 [V} ], the capacitor 94
₁ voltage to 94 ₄ of the operational amplifier 95 _{1-95 4} side electrode,
Before the added voltage 7.2 [V] is added in the first horizontal period, the reference voltage value is selected by the selectors 110 _{1 to} 110 ₄ (in FIG. 5, W _{1 to} W ₄ represent this reference voltage value). Shown).

[0161] Then, control signal T3 = "H", is the analog switches 92 ₁ ~92 ₄ = ON, the reference voltage from 2.0 to 4.8 corresponding to the digital display signal D ₁₁ ~D ₁₄ [V] is The capacitors 94 _{1 to} 94 ₄ are held. Subsequently, the control signal T3 is set to “L” and the control signal TD is maintained at “H”.

Therefore, in this case, the voltages held in these capacitors 94 _{1 to} 94 ₄ are used as analog display signals as operational amplifiers 95 _{1 to} 95 ₄ and data lines X _{1 to} X ₄
And it is applied to the pixel electrode 5 _{21-5 24} via the TFT 3 ₂₁ to 3 _24.

[0163] voltage between this result, in the pixel 2 _21, and the pixel electrode 5 ₂₁ and the common electrode 6 is 2.0-7.0 = -
5.0 [V], and the digital display signal D ₂₁ = [D2,
D1, D0] = [0, 0, 0].

In the pixel 2 ₂₂ , the pixel electrode 5 ₂₂
And the voltage between the common electrode 6 is 3.2-7.0 = −3.8.
[V], and the digital display signal D ₂₂ = [D2, D1,.
D0] = [0,1,1] is performed.

In the pixel 2 ₂₃ , the pixel electrode 5 ₂₃
And the voltage between the common electrode 6 is 4.0−7.0 = −3.0.
[V], and the digital display signal D ₂₃ = [D2, D1,.
D0] = [1, 0, 1].

In the pixel 2 ₂₄ , the pixel electrode 5 ₂₄
And the voltage between the common electrode 6 is 4.8-7.0 = −2.2.
[V], and the digital display signal D ₂₄ = [D2, D1,.
D0] = [1, 1, 1].

That is, in the second horizontal period in the even-numbered frame, the display of each of the pixels 2 ₂₁ to 2 ₂₄ is performed by the pixel electrode 5 ₂₁
5 ₂₄ voltage <carried out under the relation of the voltage of the common electrode 6. The same applies to the fourth horizontal period.

As described above, also in the present embodiment, in the first and third horizontal periods of the odd-numbered frame, the pixel electrodes 5 ₁₁ to 5 11-
5 ₁₄ , 5 _{31 to} 5 ₃₄ <voltage of the common electrode 6, and in the second and fourth horizontal periods of the odd-numbered frame, the pixel electrodes 5 _{21 to} 5 5
₂₄ , 5 _{41 to} 5 ₄₄ > the voltage of the common electrode 6, and in the first and third horizontal periods of the even frame, the pixel electrodes 5 ₁₁ to 5 ₄₄
In the second and fourth horizontal periods of the even-numbered frame, the pixel electrodes 5 _{21 to} 5 ₂₁ are set to the voltages of 5 ₁₄ and 5 _{31 to} 5 ₃₄ > the voltage of the common electrode 6.
_The AC drive is performed with the voltage of ₂₄ , 5 _{41 to} 5 ₄₄ <the voltage of the common electrode 6.

In other words, for the same line, the polarity of the voltage between the pixel electrode and the common electrode is inverted for each frame, and AC driving is performed. It is to be noted that the polarity of the voltage between the pixel electrode and the common electrode is inverted every line in one frame, as in the conventional liquid crystal display device shown in FIG. It is for planning.

In this embodiment, since the reference voltages V0 to V7 to be output from the reference voltage source 107 need only be lower than the common voltage Vcom, the reference voltage source 1
As the operational amplifier constituting the 07, an operational amplifier with a high withstand voltage and a large current is not required, and an operational amplifier with a low withstand voltage and a small current is sufficient. In this case, the addition voltage generated from the addition voltage generation circuit 109 needs only one voltage value, and the addition voltage generation circuit 109 can be configured by a simple circuit. Since the movement of the current is not accompanied, the cost can be reduced and the power consumption can be reduced.

As described above, the reference voltages V0 to V7 to be output from the reference voltage source 107 are equal to the common voltage V
Since sufficient at lower voltage than com, as analog switches constituting the selector _{1101 4} for selecting a reference voltage V0-V7, without the need for analog switches of a high breakdown voltage, sufficient in the analog switch of the low-voltage Further, this result does not require also the level conversion circuit unit 321 _to 323 ₄ required to operate the high-voltage analog switch as in the prior art, the data driver 108 LSI
In this case, the chip area can be reduced, and the cost of the data driver 108 can be reduced. In this regard, the cost of the liquid crystal display device itself can be reduced.

[0172]

As described above, according to the present invention, the reference voltage to be output from the reference voltage source is lower than the common voltage, so that the operational amplifier constituting the reference voltage source has a high withstand voltage and high voltage. There is no need for a current operational amplifier, and the number of reference voltages is the same as the number of gradations.
2, and only one voltage value is required for the addition voltage, and the addition voltage generation circuit can be constituted by a simple circuit. Therefore, the circuit configuration can be simplified, cost can be reduced, and power consumption can be reduced.

As described above, since the reference voltage to be output from the reference voltage source is lower than the common voltage, the reference voltage selection circuit can be used as an analog switch constituting a selector for selecting the reference voltage. No high voltage analog switches are required, and as a result,
Unlike the prior art, there is no need for a level conversion circuit for converting a logic level selection signal to a level required to operate a high withstand voltage analog switch. Therefore, when the data driver is formed into an LSI, the chip area can be reduced, and the cost of the data driver can be reduced. In this regard, the cost of the liquid crystal display device itself can be reduced. Can be.

[Brief description of the drawings]

FIG. 1 is a diagram showing in principle the circuit configuration of the present invention.

FIG. 2 is a diagram schematically showing a circuit configuration of a main part of one embodiment of the present invention.

FIG. 3 is a diagram showing a decoder, a reference voltage source, and a selector which constitute one embodiment of the present invention.

FIG. 4 is a time chart for explaining the operation of the embodiment of the present invention (the operation in the first horizontal period and the second horizontal period in an odd-numbered frame).

FIG. 5 is a time chart for explaining the operation of the embodiment of the present invention (the operation in the first horizontal period and the second horizontal period in an even frame).

FIG. 6 is a diagram schematically showing a circuit configuration of a main part of a conventional liquid crystal display device of an AC drive system including an active matrix type liquid crystal display panel.

FIG. 7 is a diagram schematically showing a configuration of an active matrix type liquid crystal display panel constituting the liquid crystal display device shown in FIG. 6;

8 shows a decoder constituting the liquid crystal display device shown in FIG. 6,
FIG. 3 is a diagram illustrating a level conversion circuit unit and a selector.

FIG. 9 is a circuit diagram illustrating a level conversion circuit arranged in a level conversion circuit unit included in the liquid crystal display device illustrated in FIG. 6;

10 is a diagram illustrating a reference voltage source and a selector included in the liquid crystal display device illustrated in FIG.

FIG. 11 is a time chart for explaining the operation of the conventional liquid crystal display device shown in FIG. 6 (operation in a first horizontal period and a second horizontal period in an odd frame).

FIG. 12 is a time chart for explaining the operation of the conventional liquid crystal display device shown in FIG. 6 (operation in a first horizontal period and a second horizontal period in an even frame).

FIG. 13 is a diagram showing a relationship between a voltage applied to a pixel electrode, a voltage between the pixel electrode and a common electrode, and a transmittance of liquid crystal.

[Explanation of symbols]

 Reference Signs List 100 liquid crystal display panel 101 reference voltage source 102 reference voltage selection circuit 103 reference voltage holding circuit 104 addition voltage generation circuit 105 analog display signal supply circuit

Continued on the front page (58) Investigated field (Int.Cl. ⁷ , DB name) G09G 3/36 G02F 1/133 520 G02F 1/133 550 G02G 1/133 575

Claims (3)

(57) [Claims] 1. A pixel electrode provided for each pixel, a common electrode provided commonly to all pixels, and a switching element provided for each pixel electrode for supplying an analog display signal to the pixel electrode. A liquid crystal display device comprising a liquid crystal display panel (100) driven by alternating current with a constant common voltage to be applied to the common electrode, wherein the voltage is lower than the common voltage and the number of gradations A reference voltage source (101) for outputting a reference voltage having the same number of different values as above, decoding an externally supplied digital display signal with or without inversion according to a predetermined rule, and converting a corresponding reference voltage to the reference voltage A reference voltage selection circuit (102) selected from a source (101);
A reference voltage holding circuit (103) for holding the reference voltage selected in 2); and a reference voltage holding circuit (103) when an analog display signal higher than the common voltage is to be supplied to the pixel electrode. Voltage generation circuit (10) for generating an additional voltage to be added to the reference voltage held in
4) When the analog display signal having a voltage lower than the common voltage is to be supplied to the pixel electrode, the reference voltage held in the reference voltage holding circuit (103) is supplied to the pixel electrode; When an analog display signal higher than the common voltage is to be supplied to the pixel electrode, a voltage obtained by adding the additional voltage to the reference voltage held in the reference voltage holding circuit (103) is supplied to the pixel electrode. A liquid crystal display device comprising: an analog display signal supply circuit (105). 2. The predetermined rule is that, for the same line, the voltage polarity between the pixel electrode and the common electrode is inverted every frame, and in one frame, the voltage polarity is inverted every line. 2. The liquid crystal display device according to claim 1, wherein the voltage polarity between the pixel electrode and the common electrode is inverted. 3. The addition of the addition voltage is performed by forming the reference voltage holding circuit (103) by a capacitor, holding the reference voltage selected by the reference voltage selection circuit (102) on the capacitor, 3. The liquid crystal display device according to claim 1, wherein the operation is performed by applying the additional voltage to a low-voltage side electrode.