JP2003058118A - Method for precharge driving of liquid crystal panel and electronic equipment - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress the flicker of a projector. SOLUTION: A positive precharge voltage +Vp and a negative precharge voltage -Vp are generated with a power supply circuit 300 and supplied to a precharge signal supplying circuit 40. In an R system processing circuit 100R, precharge signals NRS1 are generated with the circuit 40 on the basis of first polarity inverting signals PS1 and the resultant signals NRS1 are supplied to a liquid crystal display panel 10R. On the other hand, in a G system processing circuit 100G and a B system processing circuit 100B, precharge signals are generated on the basis of second polarity inverting signals PS2. The signals PS2 are obtained by inverting the signals PS1. Thus, the load imposed on the circuit 300 is properly distributed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal panel precharge driving method suitable for use in, for example, a projector, and an electronic device.

[0002]

2. Description of the Related Art A projector comprises a light source, a liquid crystal display panel and a lens. The light from the light source is displayed on the screen through the liquid crystal display panel and the lens whose transmittance is adjusted for each pixel according to the input image signal. When the projector displays in color, three liquid crystal display panels corresponding to RGB colors are used.

Here, the liquid crystal display panel is formed by adhering an element substrate and a counter substrate with a gap, and the gap is filled with liquid crystal. A common electrode is formed on the counter substrate, while a plurality of scanning lines, a plurality of data lines, and pixel electrodes and switching elements are formed at the intersections of the scanning lines and the data lines on the element substrate. It Then, scanning lines are sequentially selected for each horizontal period, and a data signal is supplied to each data line during a period in which one scanning line is selected, and this is written to the pixel electrode.

When the pixel pitch is narrowed, the number of pixels increases, and the number of data lines also increases. Therefore, the period for writing the data signal to the pixel electrode becomes shorter. Since the data line is accompanied by parasitic capacitance, if the writing period is short, the data signal cannot be written sufficiently.

In order to solve this, a driving method called precharge driving is known. In the precharge driving method, a precharge voltage is applied to each data line at the same time in the horizontal blanking period, and then a data signal is applied to each data line. This allows each data line to be charged with a precharge voltage, which facilitates writing of a data signal.

[0006]

However, when each liquid crystal display panel is driven by the precharge driving method, a phenomenon called flicker may occur. Flicker is a phenomenon in which the brightness of each pixel changes between fields and is recognized as flicker by the human eye.

The present invention has been made in view of the above points, and an object thereof is to improve flicker associated with precharge driving and improve the quality of a displayed image.

[0008]

In order to achieve the above object, a precharge driving method of the present invention is a precharge driving method used in an electronic device having a plurality of liquid crystal panels, wherein It is characterized in that a precharge voltage is applied to a panel for driving, and at least one liquid crystal panel is supplied with a precharge voltage having a polarity opposite to the polarity of the precharge voltage applied to another liquid crystal panel.

According to the present invention, the precharge voltage applied to at least one liquid crystal panel has a polarity opposite to the polarity of the precharge voltage applied to the other liquid crystal panels, so that the load seen from the power supply circuit is dispersed. Will be done. Therefore, even if the driving capability of the power supply circuit is low, it is possible to perform precharge close to ideal. The polarity of the precharge voltage refers to a high potential as a positive polarity and a low potential as a negative polarity with reference to the center potential of the positive precharge voltage and the negative precharge voltage.

Next, the electronic apparatus of the present invention comprises a plurality of scanning lines, a plurality of data lines, a precharge signal line, a plurality of first transistors connected to the scanning lines and the data lines. A plurality of liquid crystal panels each having a plurality of pixel electrodes connected to the respective first transistors, and a plurality of second transistors connected to the respective data lines and the precharge signal lines, and the respective liquid crystal panels And a precharge circuit for supplying a precharge voltage to each of the precharge signal lines and supplying a precharge voltage having a polarity opposite to the polarity of the precharge voltage applied to another liquid crystal panel to at least one liquid crystal panel. It is characterized by being provided. The data line seen by the power supply circuit is a capacitive load.
According to the present invention, the precharge voltage applied to at least one liquid crystal panel has a polarity opposite to the polarity of the precharge voltage applied to the other liquid crystal panels, so that the load of the power supply circuit can be dispersed.

Here, the liquid crystal panel includes control lines respectively connected to the control terminals of the plurality of second transistors, and the precharge circuit connects the control lines of the respective liquid crystal panels to a horizontal blanking period. It is preferable to supply a precharge control signal for turning on each of the second transistors during all or part of the period. Accordingly, the potential of the data line can be precharged to a predetermined potential before the data signal is supplied to each data line.

Further, the above-mentioned electronic equipment is provided with a power supply circuit for generating a positive precharge voltage which is a high potential with respect to a reference potential and a negative precharge voltage which is a high potential with respect to the reference potential. It is preferable that the charge circuit is provided corresponding to each liquid crystal panel, and selects the positive precharge voltage and the negative precharge voltage to generate the precharge voltage.

Further, in the above-mentioned electronic apparatus, each of the liquid crystal panels corresponds to each of RGB colors, and a light source for irradiating light and a light source for guiding the light from the light source to the respective liquid crystal panels to connect the respective liquid crystal panels. An optical mechanism for synthesizing the transmitted light and irradiating it to the outside is preferable. A projector corresponds to such an electronic device.

[0014]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. In this embodiment, as an example of the electro-optical device, a projector using an active matrix type liquid crystal display panel will be described.

<1: Mechanical Configuration of Projector> First, the mechanical configuration of the projector according to this embodiment will be described. FIG. 1 is a plan view showing a configuration example of this projector. As shown in this figure, the projector 1
Inside 100, a lamp unit 1102 including a white light source such as a halogen lamp is provided. The projection light emitted from the lamp unit 1102 is separated into three primary colors of RGB by the four mirrors 1106 and two dichroic mirrors 1108 arranged in the light guide 1104, and serves as a light valve corresponding to each primary color. It is incident on the liquid crystal display panels 10R, 10G and 10B. Liquid crystal display panels 10R, 10G and 10B are supplied with R, G and B supplied from an image processing circuit (not shown).
Driven by the image signals of. The light modulated by these liquid crystal display panels enters the dichroic prism 1112 from three directions. In the dichroic prism 1112, the R and B lights are refracted by 90 degrees, while the G light goes straight. Therefore, as a result of combining the images of the respective colors, the projection lens 1114
A color image is projected on a screen or the like via the. The liquid crystal display panels 10R, 10B, 10G include
Light corresponding to each of the primary colors of R, G, and B is incident on the dichroic mirror 1108, so that it is not necessary to provide a color filter on the counter substrate.

<2: Electrical Configuration of Projector> FIG. 2
FIG. 3 is a block diagram showing an electrical configuration of a projector. As shown in this figure, the projector 1100 has an RG
R, G, B system processing circuits 100R, 1 corresponding to each B color
00G, 100B, a timing circuit 200, and a power supply circuit 300. Of these, the timing circuit 2
00 generates various timing signals and supplies them to the R, G, B system processing circuits 100R, 100G, 100B, and the power supply circuit 300 generates various voltages to generate R, G, B system processing circuit 100R, 100G, 1
00B. In particular, the power supply circuit 300
Includes a first constant voltage source 301 that generates a positive precharge voltage + Vp and a second constant voltage source 302 that generates a negative precharge voltage -Vp.

R, G, B system processing circuits 100R, 100
G and 100B are similarly configured. Here, the R system processing circuit 100R will be described on behalf of the circuits of the respective systems. The R system processing circuit 100R includes the liquid crystal display panel 1
0R, an image processing circuit 30, and a precharge signal supply circuit 40.

The image signal processing circuit 30 includes a phase expansion circuit 31.
And an amplification and inversion circuit 32. The phase expansion circuit 31 performs well-known phase expansion processing on the input image signal VID and outputs it to N
A phase (N = 6 in the figure) image signal is output. By this phase expansion processing, the input image signal is divided into 6 phases, and the time axis of the input image signal VID is expanded 6 times. Here, the reason for expanding the image signal to the N phase is that the TFT in the sampling circuit described later is used.
This is for prolonging the application time of the image signal supplied to, to sufficiently secure the sampling time and the charging / discharging time.

The amplification / inversion circuit 32 amplifies the phase-developed image signal and inverts the polarity of each image signal based on the first polarity inversion signal PS1 to generate an image signal VID1.
~ VID6 is generated. Here, the polarity inversion means that the voltage level is alternately inverted with reference to the amplitude center potential of the image signal. Regarding whether to invert, whether the data signal application method is polarity inversion in scanning line units or polarity inversion in data signal lines,
It is determined depending on whether the polarity is inverted in pixel units, and the inversion period is set to one horizontal scanning period or dot clock period. In this example, the polarity of the image signal is inverted every horizontal scanning period. Therefore, one cycle of the first polarity inversion signal PS1 is two horizontal scanning periods.

Next, the precharge signal supply circuit 40
Based on the first polarity inversion signal PS1, either the positive precharge voltage + Vp or the negative precharge voltage -Vp is selected to generate the precharge signal NRS1.
Specifically, when the first polarity inversion signal PS1 is at H level, the precharge signal supply circuit 40 selects the positive precharge voltage + Vp, while the first polarity inversion signal PS1 is L level.
At the level, the precharge signal supply circuit 40 selects the negative precharge voltage -Vp. Positive precharge voltage +
Vp is a potential higher than the amplitude center potential of the image signals VID1 to VID6 by ΔV, while the negative precharge voltage −Vp
Is ΔV from the image signals VID1 to VID6 and the amplitude center potential.
Only low potential.

The timing circuit 200 generates a second polarity inversion signal PS2 in addition to the first polarity inversion signal PS1. FIG. 3 is a timing chart of the first polarity inversion signal PS1 and the second polarity inversion signal PS2. R system processing circuit 1
While the first polarity inversion signal PS1 is supplied to 00R,
The second polarity inversion signal PS2 is supplied to the G and B system processing circuits 100G and 100B. Second polarity inversion signal PS2
Indicates that the polarity of the first polarity inversion signal PS1 is inverted. Therefore, when the R color liquid crystal display panel 10R is driven with a positive polarity, the G color and B color liquid crystal display panels 10G and 10B are driven with a negative polarity. Further, as shown in FIG. 3, the precharge signal NRS2 supplied to the liquid crystal display panels 10G and 10B is
Precharge signal N supplied to the liquid crystal display panel 10R
It is the reverse of RS1.

Next, the liquid crystal display panel 10R has a liquid crystal sandwiched between an element substrate and a counter substrate, and in addition to the display area, a data line driving circuit and a scanning line driving circuit are provided in the peripheral portion of the element substrate. Has been formed. Here, the element substrate and the counter substrate are made of a quartz substrate, hard glass, or the like.

FIG. 4 is a block diagram showing a circuit configuration formed on the element substrate of the liquid crystal display panel 10R. As shown in this figure, in the element substrate, a plurality of scanning lines 112 are arranged in parallel along the X direction, and a plurality of data lines are arranged in parallel along the Y direction orthogonal thereto. Line 1
14 is formed. Here, each data line 114 has 6
The book is divided into blocks.

At each intersection of the scanning line 112 and the data line 114, for example, a thin film transistor (Thin Film Transistor) is used as a switching element.
or: hereinafter referred to as “TFT”) 116 is connected to the scanning line 112 while the source electrode of the TFT 116 is connected to the data line 114, and the TFT 1
The 16 drain electrodes are connected to the pixel electrode 118. Each pixel is composed of a pixel electrode 118, a common electrode formed on the counter substrate, and a liquid crystal sandwiched between these electrodes, and the scanning line 112 and the data line 11 are formed.
4 will be arranged in a matrix at each intersection. In addition to this, a storage capacitor (not shown) is formed in a state of being connected to each pixel electrode 118.

The scanning line drive circuit 120 is formed on the element substrate and generates a pulsed scanning signal based on the clock signal CLY from the timing circuit 200, its inverted clock signal CLYINV, the transfer start pulse DY, and the like. The data is sequentially output to each scanning line 112. Specifically, the scanning line driving circuit 120 sequentially shifts the transfer start pulse DY supplied at the beginning of the vertical scanning period in accordance with the clock signal CLY and its inverted clock signal CLYINV, and outputs it as a scanning line signal. The scanning lines 112 are sequentially selected.

On the other hand, the sampling circuit 130 has a sampling switch 131 at one end of each data line 114 for each data line 114. This switch 131 is a TF that is also formed on the element substrate.
Image signals VID1 to VID6 are input to the source electrode of the switch 131. And
The gate electrodes of the six switches 131 connected to the data lines 114a to 114f of the block B1 are connected to the signal line to which the sampling signal S1 is supplied, and the block B2
The gate electrodes of the six switches 131 connected to the data lines 114a to 114f are connected to the signal line to which the sampling signal S2 is supplied.
The gate electrodes of the six switches 131 connected to the data lines 114a to 114f are connected to the signal line to which the sampling signal Sn is supplied. Here, the sampling signals S1 to Sn are signals for sampling the image signals VID1 to VID6 for each block during the horizontal effective display period.

The shift register circuit 140 is also formed on the element substrate, and the clock signal CLX from the timing circuit 200 and its inverted clock signal CLXIN.
The sampling signals S1 to Sn are sequentially output based on V, the transfer start pulse DX, and the like. Specifically, the shift register circuit 140 sequentially shifts the transfer start pulse DX supplied at the beginning of the horizontal scanning period according to the clock signal CLX and its inverted clock signal CLXINV, and the pulse widths of these shifted signals are adjacent to each other. The signals are narrowed so that they do not overlap with each other, and are sequentially output as sampling signals S1 to Sn.

In such a structure, when the sampling signal S1 is output, the image signal VI is supplied to the six data lines 114a to 114f belonging to the block B1.
D1 to VID6 are sampled so that these image signals VID1 to VID6 are 6 in the current selected scan line.
The pixel is written in each pixel by the TFT 116.

Thereafter, when the sampling signal S2 is output, this time, the six data lines 1 belonging to the block B2 are output.
14a to 114f respectively include image signals VID1 to VID.
ID6 is sampled and these image signals VID1
.About.VID6 is written in the six pixels in the selected scanning line at that time by the TFT 116.

Similarly, the sampling signals S3,
When S4, ..., Sn are sequentially output, block B3,
Six data lines 114a to 1 belonging to B4, ..., Bn
Image signals VID1 to VID6 are sampled in 14f, and these image signals VID1 to VID6 are sampled.
Will be written in each of the six pixels in the selected scanning line at that time. Then, after that, the next scanning line is selected, and similar writing is repeatedly executed in the blocks B1 to Bn.

In this driving method, the sampling circuit 13
The number of stages of the shift register circuit 140 that drives and controls the switch 131 at 0 is reduced to 1/6 as compared with the method of driving each data line in a dot-sequential manner. Further, since the frequency of the clock signal CLX to be supplied to the shift register circuit 140 and its inverted clock signal CLXINV is only 1/6, the number of stages can be reduced and the power consumption can be reduced.

On the other hand, in the above display device, since each data line 114 has a capacitive component, the time required to write the image signals VID1 to VID6 sampled by the switch 131 into the pixel by the TFT 116 tends to be prolonged. . To eliminate this, a precharge circuit 160 is provided. The precharge circuit 160 includes a switch 165 for each data line 114 at the other end of each data line 114. The switch 165 is composed of an N-channel (or P-channel) TFT similarly formed on the element substrate, its drain electrode (or source electrode) is connected to the data line 114, and its source electrode (or drain electrode) is a signal. It is connected to the line 162. The gate electrode of each switch 165 is connected to the control line 161. The precharge control signal NRG is supplied to the control line 161, while the precharge signal NRS1 is supplied to the signal line 162.

The precharge control signal NRG is applied to the data line at the timing preceding the sampling signals S1 to Sn, that is, after the selection of a certain scanning line is completed, the next scanning line is selected. It is a pulse-like signal which becomes H level in the horizontal retrace line period until it is turned on. Therefore, the precharge signal NRS1 is applied to the data line 114 in the period, and the potential of the data line 114 is precharged to one of the positive precharge voltage + Vp or the negative precharge voltage −Vp.

In such a configuration, the timing circuit 200 includes the R, G, B system processing circuits 100R, 100
The same clock signal CLY, inverted clock signal CLYINV, transfer start pulse DY, clock signal CLX, inverted clock signal CLXINV, transfer start pulse DX, and precharge control signal NRG are supplied to G and 100B. Therefore, each of the liquid crystal display panels 10R, 10
G and 10B will operate in synchronization.

On the other hand, the timing circuit 200 supplies the first polarity inversion signal PS1 to the R system processing circuit 100R, while the G system processing circuit 100G and the B system processing circuit 10 are provided.
The second polarity inversion signal PS2 is supplied to 0B. As a result, the liquid crystal display panel 10R displays the precharge signal NRS.
1, while liquid crystal display panels 10G and 10 are supplied.
A precharge signal NRS2 is supplied to B.

This point will be described in detail with reference to FIG. FIG. 5 is a timing chart showing the operation of each liquid crystal display panel. As shown in the figure, during the nth horizontal running period, the precharge signal NRS1 is the positive precharge voltage + Vp, while the precharge signal N is
RS2 has a negative precharge voltage -Vp. Therefore, when the precharge control signal NRG becomes active in the period from time t1 to time t2 within the horizontal blanking period, the liquid crystal display panels 10R, 10G, 10B are activated.
The TFTs 165 are simultaneously turned on. Therefore,
A positive precharge voltage + Vp is applied to each data line 114 of the liquid crystal display panel 10R, while a negative precharge voltage -Vp is applied to the liquid crystal display panels 10G and 10B.

This is considered as a load fluctuation as seen from the power supply circuit 300. As described above, since the data line 114 faces the common electrode across the liquid crystal, the data line 114
Has a capacitive component. Therefore, when the precharge control signal NRG becomes active, the load suddenly increases. Then, a large current flows into each liquid crystal display panel 10R, 10G, 10B from the first constant voltage source 301 of the power supply circuit 300, but there is a certain limit in an actual circuit. Therefore, at time t2, the liquid crystal display panel 10
The voltage of the R data line 114 is the positive precharge voltage + V
It does not reach p and has a constant error voltage ΔV1.

The same applies to the negative precharge voltage -Vp. Specifically, in the (n + 1) th horizontal scanning period, in the period from time t3 to time t4 within the horizontal blanking period, the precharge control signal NR
When G becomes active, a negative precharge voltage -Vp is applied to each data line 114 of the liquid crystal display panel 10R. At this time, the voltage of the data line 114 does not reach the negative precharge voltage −Vp and has a constant error voltage ΔV2.

Here, the values of ΔV1 and ΔV2 are different.
This is the switch 1 that constitutes the precharge circuit 160.
Due to the characteristics of 65. That is, in this example, since the switch 165 is an N-channel TFT, the on-resistance increases as the voltage applied to the source electrode approaches the voltage of the gate electrode, while the voltage applied to the source electrode changes to the voltage of the gate electrode. There is a property that the on-resistance decreases when the distance from Therefore, the precharge signal NR
The ON resistance is large when S1 is the positive precharge voltage + Vp, and is small when the precharge signal NRS1 is the negative precharge voltage -Vp. As a result, when the data line 114 is viewed as a capacitive load, the time constant becomes large when the positive precharge voltage + Vp, and therefore the error voltage ΔV1 becomes large, while the precharge signal NRS becomes the negative precharge voltage −. V
When p, the time constant becomes small, so the error voltage ΔV
2 becomes smaller.

The difference between the error voltage ΔV1 and the error voltage ΔV2 is that the image signals VID1 to VID are transmitted to the data line 114.
This means that there is a difference in the initial potential of the data line 114 when 6 is written. If there is a difference in the initial potential, even if the same voltage is applied to the data line 114, there is a difference in the voltage finally written in the pixel electrode 118. Therefore, the effective voltage value applied to the liquid crystal of each pixel is different between the odd field and the even field. Since the brightness of each pixel is determined by the effective voltage value of the liquid crystal, people perceive the brightness change as flicker.

As in the conventional projector, by supplying the same first polarity inversion signal PS1 to all the liquid crystal display panels 10R, 10G and 10B,
If the same precharge signal NRS1 is supplied,
The load of each constant voltage source 301, 302 in the power supply circuit 300 becomes very heavy. Therefore, the error voltage ΔV1 and the error voltage ΔV2 increase, and the initial potential of the data line 114 largely deviates from the ideal value. As a result, in a conventional projector, people perceived a flicker of a change in luminance between fields.

On the other hand, in this embodiment, R
In the liquid crystal display panel 10R for G and the liquid crystal display panels 10G and 10B for G and B, the polarities of the precharge voltages supplied are opposite to each other. As described above, the positive precharge voltage + Vp and the negative precharge voltage -Vp are generated by the independent first and second constant voltage sources 301 and 302. That is, the load viewed from the power supply circuit 300 is dispersed.

Now, the effect of load distribution will be examined using an equivalent circuit. FIG. 6 is an equivalent circuit in the case where the output voltage of the first constant voltage source 301 in the conventional projector is input and the voltage of the data line of the liquid crystal display panel 10R is output, and FIG. 7 is the second circuit in the conventional projector. This is an equivalent circuit when the output voltage of the constant voltage source 302 is input and the voltage of the data line of the liquid crystal display panel 10R is output. Further, FIG. 8 is an equivalent circuit in the case where the output voltage of the first constant voltage source 301 in this embodiment is input and the voltage of the data line of the liquid crystal display panel 10R is output, and FIG. 9 is in this embodiment. This is an equivalent circuit when the output voltage of the second constant voltage source 302 is input and the voltage of the data line of the liquid crystal display panel 10R is output.

In these figures, "Ra" represents the resistance value from the first constant voltage source to the data line 114, and the ON resistance value of the switch 165 when the positive precharge voltage + Vp is applied. Is included.
“Rb” represents the resistance value from the second constant voltage source to the data line 114, and includes the on resistance value of the switch 165 when the negative precharge voltage −Vp is applied. Further, “C” represents the total capacitance value of the capacitance components of all the data lines 114 extending in one liquid crystal display panel.

First, in the conventional projector, since the same precharge signal NRS1 is supplied to each liquid crystal display panel 10R, 10G, 10B, the first constant voltage source 3
01 and the second constant voltage source 302 have a capacitance component of 3C.
Becomes On the other hand, in the present embodiment, the first constant voltage source 30
The capacitance component viewed from the first and second constant voltage sources 302 is C.

It is assumed that a step signal of amplitude V is input to such an equivalent circuit. In this case, the error voltage ΔV1 ′ shown in FIG. 6 and the error voltages ΔV2 ′ and ΔV1′− shown in FIG.
ΔV2 ′ is given by the following equation. ΔV1 '= V * EXP [-1 / 3CRa] ... Equation 1 ΔV2' = V * EXP [-1 / 3CRb] ... Equation 2 ΔV1'-ΔV2 '= V * EXP [-t / 3C] * (EXP [1 /Ra]-EXP[1/Rb])...Equation 3 On the other hand, the error voltage ΔV1 shown in FIG. 6 and the error voltages ΔV2 and ΔV1-ΔV2 shown in FIG. 8 are given by the following equations. ΔV1 = V * EXP [-1 / CRa] ... Equation 4 ΔV2 = V * EXP [-1 / CRb] ... Equation 5 ΔV1-ΔV2 = V * EXP [-t / C] * (EXP [1 / Ra]- EXP [1 / Rb]) …… Equation 6

Comparing equations 1 and 2 with equations 4 and 5, it can be seen that ΔV1 and ΔV2 are smaller than ΔV1 ′ and ΔV2 ′. Therefore, the projector according to the present embodiment can charge the data line 114 with the positive precharge voltage + Vp and the negative precharge voltage −Vp more nearly ideally as compared with the conventional projector. Further, comparing Equation 3 and Equation 6, ΔV1-ΔV2
It can be seen that is smaller than ΔV1′−ΔV2 ′. That is, this embodiment is different from the conventional one in that the error voltage ΔV1 with respect to the positive precharge voltage + Vp is increased.
And the error voltage ΔV2 with respect to the negative precharge voltage −Vp can be reduced. Since flicker occurs according to the difference in error voltage, according to this embodiment, flicker can be reduced.

<3: Application Example> (1) In the above-described embodiment, the blocks B1 to Bm are sequentially selected, and the six phases are set for the six data lines 114a to 114f belonging to the selected one block. The expanded phase expanded image signals VID1 to VID6 are sampled and supplied at the same time. The number of phase expanded and the number of data lines supplied simultaneously (that is, the number of data lines forming one block) are as follows. It is not limited to "6". For example, assuming that the number of data lines forming one block is 3, 12, 12, 24, ...
It is also possible to simultaneously supply image signals that have been subjected to 3-phase expansion, 12-phase expansion, 24-phase expansion, etc. to the data lines and supplied in parallel. Further, it may not be phase-developed.

(2) In the above-described embodiment, the projector has been described as an example of the electronic apparatus, but the present invention is not limited to this.
Any electronic device that drives a plurality of liquid crystal display panels in synchronization can be applied. For example, the present invention can be applied to a multi-vision system in which a plurality of liquid crystal display panels are combined to form one large screen.

[0050]

As described above, according to the present invention, it is possible to improve the display image quality when driving by a plurality of liquid crystal panel precharge driving methods, and particularly it is possible to suppress flicker. .

[Brief description of drawings]

FIG. 1 is a plan view showing a mechanical configuration of a projector according to an embodiment of the invention.

FIG. 2 is a block diagram showing an electrical configuration of the projector.

FIG. 3 is a timing chart showing the operation of the liquid crystal display panel.

FIG. 4 is a block diagram showing a configuration of the liquid crystal display panel used in the projector.

FIG. 5 is a timing chart showing the operation of each liquid crystal display panel used in the projector.

FIG. 6 is an equivalent circuit diagram when an output voltage of a first constant voltage source in a conventional projector is input and a voltage of a data line of a liquid crystal display panel 10R is output.

FIG. 7 is an equivalent circuit diagram in the case where the output voltage of the second constant voltage source in the conventional projector is input and the voltage of the data line of the liquid crystal display panel 10R is output.

FIG. 8 is an equivalent circuit diagram when the output voltage of the first constant voltage source is input and the voltage of the data line of the liquid crystal display panel 10R is output in the present embodiment.

FIG. 9 is an equivalent circuit diagram in the case where the output voltage of the second constant voltage source is input and the voltage of the data line of the liquid crystal display panel 10R is output in the present embodiment.

[Explanation of symbols]

10R: Liquid crystal display panel 112 ... Scan line 114a to 114f ... Data line 116 ... TFT 118 ... Pixel electrode 161 ... control line 162 ... Signal line 200 ... Timing circuit 300 ... Power supply circuit

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) G09G 3/20 623 G09G 3/20 623B 680 680C F term (reference) 2H093 NA36 NC04 ND10 5C006 AA11 AA22 AC11 AC21 AC22 AC23 AF43 BB16 BC03 BC06 BC11 BC16 BF34 BF42 FA23 FA47 5C080 AA10 BB05 CC03 DD06 FF11 JJ02 JJ03 JJ04 JJ05 JJ06

Claims (5)

[Claims] 1. A precharge driving method for a liquid crystal panel used in an electronic device having a plurality of liquid crystal panels, wherein a precharge voltage is applied to each of the liquid crystal panels to drive the liquid crystal panel, and at least one liquid crystal panel is A precharge driving method for a liquid crystal panel, characterized in that a precharge voltage having a polarity opposite to that of the precharge voltage applied to the liquid crystal panel is supplied. 2. A plurality of scanning lines, a plurality of data lines, a precharge signal line, a plurality of first transistors connected to each of the scanning lines and each of the data lines, and a connection of each of the first transistors. A plurality of stored pixel electrodes, and a plurality of second electrodes connected to the data lines and the precharge signal line.
A plurality of liquid crystal panels each having a transistor, and a precharge voltage supplied to a precharge signal line of each liquid crystal panel, and a polarity of the precharge voltage applied to at least one liquid crystal panel to another liquid crystal panel. And a precharge circuit for supplying a precharge voltage of opposite polarity. 3. The liquid crystal panel includes control lines connected to the control terminals of the plurality of second transistors, respectively, and the precharge circuit is connected to the control lines of the liquid crystal panels during a horizontal blanking period. The electronic device according to claim 2, wherein a precharge control signal for turning on each of the second transistors is supplied for all or a part of the period. 4. A power supply circuit for generating a positive precharge voltage that is a high potential with respect to a reference potential and a negative precharge voltage that is a high potential with respect to the reference potential, wherein the precharge circuit includes each liquid crystal. The electronic device according to claim 2, wherein the electronic device is provided corresponding to a panel, and selects the positive precharge voltage and the negative precharge voltage to generate the precharge voltage. 5. Each of the liquid crystal panels corresponds to each of RGB colors, and a light source for irradiating light and a light from the light source are guided to each of the liquid crystal panels to synthesize light transmitted through the liquid crystal panels. The electronic device according to claim 2, further comprising: an optical mechanism that irradiates the light to the outside.