JP2002169520A - Electro-optical device, pattern generating circuit, and electronic equipment - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce an unevenness of luminance generated on the boundaries between blocks when a plurality of data lines is driven in collected blocks. SOLUTION: A correction amount output part 340 outputs a correction amount Cmp corresponding to an image signal to a 2nd data line varying in voltage due to selection of blocks. An adder 324 adds the correction amount Cmp to an image signal Dd to a 1st data line varying in voltage due to the variation in the voltage of the 2nd data line, and outputs the image signal as an image signal D'. To easily set the correction amount Cmp, a pattern generating circuit 34a outputs an image signal of such a display pattern as intermediate density pixels and specific density pixels form a checkered pattern.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electro-optical device such as a liquid crystal display device, which enables high-quality display by suppressing the occurrence of luminance unevenness occurring at the boundary of a block in which a plurality of data lines are put together. The present invention relates to an electro-optical device, a pattern generation circuit for easily setting a correction amount thereof, and an electronic apparatus.

[0002]

2. Description of the Related Art A conventional electro-optical device, for example, an active matrix type liquid crystal display device will be described with reference to FIGS. First, as shown in FIG. 13, the conventional liquid crystal display device mainly includes a liquid crystal display panel 100, a timing signal generation circuit 200, and an image signal processing circuit 30. Among them, the timing signal generating circuit 200 outputs a clock signal and a control signal (described later as necessary) used for controlling each unit. In addition, S constituting the image signal processing circuit 30
The / P conversion circuit 302 serially inputs one system image signal VID, and converts it into N systems (N = 6 in the figure).
, And is expanded N times on the time axis and output in parallel. Here, the reason for outputting the image signals in parallel is to secure a sufficient time for applying the sampled image signals to the data lines, as described later.

On the other hand, an inverting circuit 304 constituting the image signal processing circuit 30 inverts the polarity of the image signal output in parallel to the N systems in accordance with the following criteria, and amplifies the image signal appropriately to obtain the image signal VID1. To VID6 to the liquid crystal display panel 100. In other words, the inversion circuit 304 determines whether the method of applying the image signal to the data line is A: polarity inversion in scan line units, B: polarity inversion in data line units,
C: Determined according to the polarity inversion in pixel units, and set the polarity inversion cycle to one horizontal scanning period or dot clock cycle. However, in this example, for convenience of explanation, a case where A: polarity inversion in scanning line units will be described as an example. Here, the polarity inversion of the image signal is referred to as
This means that the voltage level of the image signal immediately after the conversion is alternately inverted with reference to the voltage applied to the counter electrode or a voltage substantially equal thereto.

Next, the liquid crystal display panel 100 will be described. The liquid crystal display panel 100 has a configuration in which an element substrate and a counter substrate face each other with a certain gap, and a TN (Twisted Nematic) liquid crystal is sealed in the gap. Among them, the element substrate is made of a quartz substrate, hard glass, or the like. On this element substrate, m scanning lines 112 are formed in parallel along the X (row) direction in FIG.
(6n) data lines 11 in parallel along the (column) direction
4 are formed (m and n are integers, respectively). Here, the data lines 114 are divided into blocks in units of six, and these are referred to as block B for convenience.
1, B2, B3,..., Bn. In the following description, when a data line is generally pointed out, the reference numeral is indicated as 114. However, when a data line in a block is specified and indicated, the reference numeral is 114a, 11a.
4b, 114c, 114d, 114e, and 114f.

Subsequently, near a portion where the scanning line 112 and the data line 114 intersect via an insulating film (not shown), a thin film transistor (hereinafter, “TFT”) as an example of a switching element is provided. ) 116 are provided. The gate of the TFT 116 is connected to the scanning line 112 while the source of the TFT 116 is connected to the data line 114 and
The drain 116 is connected to the pixel electrode 118.
The pixel electrode 118 is a transparent electrode made of ITO (Indium Tin Oxide: indium tin oxide) or the like, and faces the counter electrode (common electrode) 108 formed on the counter substrate. Here, the pixel electrode 118 and the counter electrode 10
8, the liquid crystal capacitance sandwiching the liquid crystal 105 corresponds to the intersection of the scanning line 112 and the data line 114, with one end serving as the pixel electrode 118 and the other end serving as the counter electrode 108. Thus, they are arranged in a matrix of m rows × (6n) columns. Note that a voltage LCcom that is constant over time is applied to the counter electrode 108. At the intersection of the scanning line 112 and the data line 114, another storage capacitor (not shown) is provided, one end of which is connected to the pixel electrode 118 (the drain of the TFT 116), and the other end is connected in common. Then, a constant voltage is applied over time.

Here, an alignment film (not shown) rubbed on the opposing surfaces of the element substrate and the opposing substrate so that the major axis direction of the molecules of the liquid crystal 105 is continuously twisted by about 90 degrees between the two substrates. ) Are provided, while polarizers (not shown) each having an absorption axis set in a direction along the alignment direction are provided on the rear surface side of the substrate. Thus, if the effective voltage value applied to the liquid crystal capacitor is zero, the transmittance of light passing through the liquid crystal capacitor becomes maximum (white), while the transmittance gradually increases as the effective voltage value increases. It is configured so that the transmittance decreases to a minimum (black) finally (normally white mode).

Next, the scanning line driving circuit 120 is formed on the element substrate, and receives the clock signal CLY from the timing signal generating circuit 200 and the inverted clock signal CLYin.
v, scanning signal G1, based on transfer start pulse DY, etc.
Gm are generated and output to each of the scanning lines 112. More specifically, as shown in FIG. 15, the scanning line driving circuit 120 changes the logic level of the clock signal CLY (and the inverted clock signal CLYinv) to the transfer start pulse DY supplied at the beginning of the vertical scanning period. The scanning signals G1, G2,..., Gm, which are shifted every time and become H level sequentially and exclusively, are supplied to the first, second,. .

Subsequently, the shift register circuit 130 outputs the sampling control signals S1, S2,..., Sn within one horizontal scanning period. More specifically, as shown in FIG. 15, the shift register circuit 130 supplies the transfer start pulse DX supplied at the beginning of one horizontal effective scanning period.
With the clock signal CLX (and the inverted clock signal CL
Xinv) are shifted each time the logic level changes, and the sampling control signals S1, S2,. Output.

On the other hand, the image signals VID1 to VID6 converted into six systems by the image signal processing circuit 30 are supplied via six image signal lines 171 and are subjected to data control in accordance with sampling control signals S1, S2,. Line 114
Is sampled by each of the. More specifically, the data lines 114 are divided into blocks every six lines, and j (j is 1, 2,
.., N) of the six data lines 114 belonging to the n-th block, the sampling switch 141 connected to one end of the leftmost data line 114a outputs the image signal line when the sampling control signal Sj goes high. The image signal VID1 supplied through the 171 is sampled and supplied to the data line 114a.

A sampling switch 14 connected to one end of a data line 114b located in a second column among six data lines 114 also belonging to the j-th block.
1 indicates that when the sampling control signal Sj goes high,
The image signal VID2 is sampled and the data line 1 is sampled.
14b. Hereinafter, similarly, j
Of the six data lines 114 belonging to the th block,
Data lines 114c, 11 located in the third, fourth, fifth, and sixth columns
Each of the sampling switches 141 connected to one end of each of the sampling control signals S
When j becomes H level, the image signals VID3, VID4,
Each of VID5 and VID6 is sampled, and the corresponding data line 114c, 114d, 114e,
114f. That is, the shift register circuit 130 and the 6n sampling switches 141 constitute a data line driving circuit. Each of the sampling switches 141 is a TFT similar to a switching element inserted between the data line 114 and the pixel electrode 118.

In such a configuration, when the sampling control signal S1 goes to the H level, the image signals VID1 to VID6 are sampled on the six data lines 114a to 114f belonging to the block B1, respectively. The charges corresponding to the voltages of VID1 to VID6 correspond to the intersections of the currently selected scanning line 112 (the scanning signal is at the H level) and the six data lines 114a to 114f belonging to the block B1. Each of the liquid crystal capacitors is written by turning on the TFT 116.

Thereafter, when the sampling control signal S2 goes high, the image signals VID are respectively applied to the six data lines 114a to 114f belonging to the block B2.
1 to VID6 are sampled, and charges corresponding to the voltages of the sampled image signals VID1 to VID6 are:
The currently selected scan line 112 and block B2
Are written to the six liquid crystal capacitances corresponding to the intersections with the six data lines 114a to 114f belonging to.

Hereinafter, sampling control signals S3, S4,
,..., Sn sequentially become H level, blocks B3, B
,..., Bn, six data lines 114 a to 114
At f, the image signals VID1 to VID6 are sampled, and writing to the liquid crystal capacitance is performed in the same manner. Thereafter, the next scanning line is selected, and similar writing is repeatedly executed in the blocks B1, B2,..., Bn.

In this driving method, the number of stages of the shift register circuit 130 for controlling the sampling switch 141 is
This is reduced to 1/6 compared to the method of driving the data lines in a dot sequence. Further, the clock signal CLX to be supplied to the shift register circuit 130 and its inverted clock signal C
Since the frequency of LXinv is also reduced to 1/6, the power consumption can be reduced as well as the number of stages is reduced.

Incidentally, the counter substrate 108 is provided with the pixel electrode 1.
In addition to the liquid crystal 18, the liquid crystal also faces the data line 114 via the liquid crystal 105. In addition, since the data line 114 extends in the Y direction, adjacent data lines are particularly likely to be capacitively coupled to each other. Further, the data line 114 itself is formed of a low-resistance wiring layer of aluminum or the like. However, since the line width is narrowed by high definition, it is inevitable to have a certain wiring resistance. Due to these factors, even if the image signal is sampled on the data line 114, the data line 1
The voltage at 14 does not immediately match the voltage of the image signal, but gradually approaches the voltage of the image signal according to a time constant determined by parasitic capacitance, wiring resistance, and the like.

Further, in this example, since the polarity of the image signal is inverted for each scanning line, the data line 11 is switched every horizontal scanning cycle.
It is necessary to invert the polarity of the voltage of No. 4 with reference to the applied voltage (or near voltage) of the counter electrode. Therefore, in a certain horizontal scanning period, the voltage of the data line 114 immediately before the application of the image signal and the voltage of the image signal to be actually applied have a polarity inversion relationship. There is a tendency that the time it takes for the voltage to match the voltage of the original image signal becomes longer.

Therefore, in order to make the data line 114 reach the original voltage in a short time, as shown in FIG.
A precharge circuit 160 is provided. The precharge circuit 160 includes a precharging switch 165 provided for each data line 114. Each precharging switch 165 is supplied with the other end of the corresponding data line 114 and a precharge signal NRS. A precharge control signal NR is inserted between the
When G becomes an active level (H level), it is turned on. This precharge control signal NR
G is at H level at a timing preceding the sampling control signals S1, S2,..., Sn, that is, during a horizontal flyback period from the end of selection of one scanning line to the selection of the next scanning line. It is a signal that becomes

For this reason, each of the data lines 114 is once precharged to the voltage of the precharge signal NRS during the horizontal retrace period, and thereafter the image signals VID1 to VID
6 is sampled. Therefore, the data lines 114 based on the image signals VID1 to VID6
And the amount of charge / discharge of the data line 114 becomes small, and the voltage of the data line 114 reaches the original voltage in a short time. As a result, the time required for writing is reduced.

[0019]

However, if the data lines 114 are driven in blocks or used in combination with precharge, the blocks B1, B2,.
Brightness unevenness at the boundary of Bn, particularly, intermediate density (gray)
The problem arises when a certain type of rule pattern is displayed against a background.

The principle of the occurrence of the luminance unevenness will now be described by focusing on the blocks B1 and B2 and displaying a gray pattern of the same density over one surface as a rule pattern. FIG. 16 is a voltage waveform diagram for explaining luminance unevenness occurring in this case. Here, in the example shown in FIG. 16, the voltage that can be taken by the precharge signal NRS corresponds to the voltage Vpre (+) corresponding to the black level during positive polarity writing or the black level during negative polarity writing. It is one of the voltages Vpre (-), and is alternately inverted with one horizontal scanning period as one cycle in accordance with inversion of the write polarity for each scanning line. In addition, the voltage Vpre (+) and the image signals VID1 to VID6 (however, in FIG.
(Only ID1 and VID6 are shown.) The difference between the center voltage when the polarity is inverted and the difference between the voltage Vpre (−) and the center voltage are equal to each other in terms of absolute value.

[0021] Now, in FIG. 16, reaching the timing t ₁₁ in one horizontal retrace period, the precharge control signal NRG becomes to the H level. As a result, the precharging switch 165 is turned on, so that all the data lines 11
4 is a precharge voltage Vpre (+) corresponding to positive polarity writing
Precharged. Thereafter, the precharge control signal NRG goes low, but all the data lines 114
Maintain the precharge voltage Vpre (+) due to its parasitic capacitance.

Next, reaches the timing t ₁₂ in one horizontal effective period, the sampling control signal S1 rises to the H level, the data line 114f of the block B1, the image signal VID6 are sampled by the sampling switch 141. Therefore, the voltage of the data line 114f changes from the voltage Vpre (+) maintained up to that time to a voltage corresponding to the sampled image signal VID6. The data is written to the liquid crystal capacitance corresponding to the intersection with 112. Thereafter, the sampling control signal S1 falls to the L level.

[0023] Subsequently, reaches the timing t _13, the sampling control signal S2 rises to H level, the data line 114a of the block B2, the sampling switch 1
The image signal VID1 is sampled by 41.
Therefore, the data line 114a of the block B2 transitions from the precharge voltage Vpre (+) maintained up to that point to the voltage of the sampled image signal VID1, and
This is written to the liquid crystal capacitance corresponding to the intersection of the data line 114a belonging to the block B2 and the selected scanning line 112.

At this time, the data line 1 belonging to the block B1
14, the data line 114f adjacent to the block B2
Is capacitively coupled to the data line 114a of the block B2, so that the data line 114a belonging to the block B2 transitions from the precharge voltage Vpre (+) to the voltage of the image signal VID1, thereby causing a voltage change. Become.
More specifically, the data line 114f of the block B1 changes from the original voltage to a voltage by a change due to the capacitive coupling due to the transition of the voltage of the data line 114a belonging to the block B2.

Here, if gray of the same density is to be displayed over one surface, the sampling control signal S1 becomes H
When the level becomes the level, the data line 1 belonging to the block B1
The voltage of the image signal VID6 applied to 14f should be equal to the voltage of the image signal VID1 applied to the data line 114f belonging to the block B2 when the sampling control signal S2 goes to H level.

However, since the data line 114f belonging to the block B1 changes from the original voltage to the voltage, finally, the liquid crystal corresponding to the intersection between the data line 114f belonging to the block B1 and the selected scanning line 112. The density of the capacitor (pixel) and the density of the pixel corresponding to the intersection of the data line 114a belonging to the block B2 and the selected scanning line 112 will be different from each other. On the other hand, the other data lines 114a-1114 belonging to the block B1
Since the pixel 14e is not affected by the voltage transition of the data line 114a belonging to the adjacent block B2 (it is unlikely), the pixel corresponding to the intersection between these data lines and the currently selected scanning line is inherently used. , The density difference hardly occurs. Such a difference in density is caused by the timing t ₂₁ corresponding to the negative polarity writing,
Also in t _22, t _23, As for the other blocks, furthermore, it occurs similarly even if you select another scan line. Therefore, even if an attempt is made to display the same density for all pixels, the data lines 114f
And the other data lines 114
Since there is a difference between the density of the pixels connected to a to 114e, luminance unevenness occurs vertically at the boundaries between the blocks B1, B2,..., Bn.

Such luminance unevenness is caused by the difference between the voltage / center voltage corresponding to the positive polarity writing and the voltage / center voltage corresponding to the negative polarity writing as the voltage of the precharge signal NRS. If the values are set to be different levels in terms of the values, for example, it is known that if the voltage is set to a voltage corresponding to white in positive polarity writing and to a voltage corresponding to black in negative polarity writing, respectively, the problem can be solved to some extent. Have been. However,
Even with this setting, it is not possible to suppress luminance unevenness to such an extent that it is inconspicuous. Further, although it is a short period from the application of the precharge signal NRS to the writing of the original image signal, the DC Since the component is applied, it also causes deterioration of the liquid crystal.

The present invention has been made in view of the above-described circumstances, and an object of the present invention is to provide an electro-optical device and an electronic apparatus capable of performing high-quality display by making luminance unevenness occurring at a boundary between blocks inconspicuous. The purpose is.

[0029]

In order to achieve the above object, in the electro-optical device according to the first aspect of the present invention, a plurality of scanning lines, a plurality of data lines, the scanning lines and the data lines are provided. And a switching element interposed between the pixel electrode and the data line and turned on / off in accordance with a scanning signal supplied to the scanning line. Selecting one of the scanning lines and an electro-optical capacitor whose density changes according to an effective value of a voltage applied to the pixel electrode and the counter electrode; A scanning line driving circuit for supplying a scanning signal for turning on the element, and a block in which the data lines are grouped into a plurality of data lines sequentially during a period in which one of the scanning lines is selected, and belonging to the selected block. Day A data line driving circuit for supplying an image signal to a line, and a small amount of electro-optical capacitance located on a first data line adjacent to a block selected next to the block among data lines belonging to one block. Part of the data lines belonging to the next selected block, and at least a part of the electro-optical capacitance located on the second data line adjacent to the first data line is specified. , And at least part of the electro-optical capacitance located on the second data line, or at least part of the electro-optical capacitance located on a third data line different from the first and second data lines. Partly, a pattern generating circuit that supplies an image signal of the pattern having the intermediate density, and an image signal by the pattern generating circuit, or one of an external image signal and When selecting an image signal by the pattern generation circuit, a selector that supplies the selected image signal to the data line driving circuit; and when the image signal by the pattern generation circuit is selected by the selector, The electro-optical capacitance of the electro-optical capacitance positioned at the first data line is the intermediate density, and the electro-optical capacitance of the electro-optical capacitance positioned at the second or the third data line is the intermediate density. A storage unit for storing an amount required to correct the density of the capacity as a correction amount; and a case where an external image signal is selected by the selector, and when a certain block is selected, If the image signal to the second data line belonging to the block to be selected next to the block among the image signals corresponds to the specific density, the Of the image signals, the first one belonging to the selected block
And an adder for adding the correction amount to the image signal corresponding to the data line and outputting the image signal as an image signal to the data line drive circuit.

According to this configuration, it is not specified where the boundaries of the blocks are located in the actual display. However, when a pattern generated by the pattern generation circuit is used, the intermediate density located at the end of each block in the block selection direction is reduced. Before the adjustment, since it is different from the other intermediate densities, the boundary of the block can be immediately specified. Furthermore, since the amount required to correct the intermediate density located at the end in the block selection direction to another intermediate density is used as the correction amount,
The correction amount can be set very easily.

According to another aspect of the present invention, there is provided an electro-optical device including a plurality of scanning lines, a plurality of data lines, and an intersection between the scanning lines and the data lines. A switching element that is interposed between the pixel electrode and the data line and that is turned on and off in accordance with a scan signal supplied to the scan line; An electro-optical capacitor whose density changes according to an effective voltage value applied to the pixel electrode and the counter electrode, and one of the scanning lines is selected to turn on the switching element. A scanning line driving circuit for supplying a scanning signal, and a block in which one of the scanning lines is selected, and a block in which the plurality of data lines are grouped is sequentially selected, and a data line belonging to the selected block is Picture A data line driving circuit for supplying a signal, an image signal having the electro-optical capacitance at an intermediate density, an image signal having the electro-optical capacitance at a specific density, or an external image signal; A control unit for controlling selection by the selector, wherein in the first case in which the image signal of the intermediate density or the specific density is selected, of the data lines belonging to one block, At least a part of the electro-optical capacitance located on the first data line adjacent to the selected block has an intermediate density, and among the data lines belonging to the next selected block, adjacent to the first data line Second
At least a part of the electro-optical capacitance located on the data line is set to a specific density, and the remaining or a part of the electro-optical capacitance located on the second data line, or the first, second,
Control means for controlling the selector so that at least a part of the electro-optical capacitance located on the third data line different from the data line becomes a pattern having the intermediate density;
In the first case, the density of the electro-optical capacitance that is the intermediate density among the electro-optical capacitances located on the first data line is changed to the intermediate density of the electro-optical capacitance that is positioned on the second data line. A storage unit that stores a correction amount required for correction up to the density of the electro-optical capacitor, and a control unit that causes the selector to select an external image signal. When one block is selected, if an image signal to a second data line belonging to a block to be selected next to the block among the image signals corresponds to the specific density, an external image signal is output. An adder for adding the correction amount to an image signal corresponding to a first data line belonging to a selected block among the signals, and outputting the added signal as an image signal to the data line driving circuit. Characteristic It is. According to this configuration, similarly to the first aspect, the boundary of the block can be immediately specified, and the correction amount can be set very easily.

According to a third aspect of the present invention, there is provided a pattern generating circuit, comprising: a plurality of scanning lines, a plurality of data lines, and an intersection between the scanning lines and the data lines. A switching element that is interposed between the pixel electrode and the data line and that is turned on and off in accordance with a scan signal supplied to the scan line; An optical capacitance whose density changes according to an effective value of a voltage applied to the pixel electrode and the counter electrode;
A scanning line driving circuit that supplies a scanning signal for selecting a book and turning on the switching element; and sequentially selecting a block in which the data lines are grouped into a plurality of lines during a period in which one of the scanning lines is selected. A data line driving circuit for supplying an image signal to a data line belonging to the selected block, and a data line driving circuit for supplying a data line belonging to the selected block to a first data line adjacent to the next selected block. Adding a correction amount according to an image signal to be supplied to a second data line adjacent to the first data line, which belongs to a block to be selected next, and
An image signal processing circuit that supplies an image signal to the data line driving circuit;
At least a part of the electro-optical capacitance located at the data line of the second data line is set to the intermediate density, and at least a part of the electro-optical capacitance located at the second data line is set to the specific density; Or a portion of the electro-optical capacitor located at the third data line different from the first and second data lines, or at least a portion of the electro-optical capacitor located at the third data line. It is characterized in that an image signal is supplied to the image signal processing circuit. With this configuration, similarly to the first and second aspects, the boundary between blocks can be immediately specified, the correction amount can be set extremely easily, and the configuration can be simplified. .

Here, the patterns in the first, second and third aspects of the present invention include the intermediate-density electro-optical capacitance and the specific-density electro-optical capacitance in the extending direction of the scanning lines and the data lines. Are preferably alternately arranged one by one over the extending direction of the two. When this pattern is used, the row arrangement in which the boundary of the block is located between the intermediate density and the specific density adjacent thereto in the block selection direction appears with a probability of 1/2. There is no need to correspond to the electro-optical capacity.

The pattern is such that the electro-optical capacitors of the intermediate density and the electro-optical capacitors of the specific density are alternately arranged at two or more periods in the extending direction of the data lines. Is preferred. When this pattern is used, the target density region is visually expanded,
The correction amount can be set more easily. Therefore, considering only this point, the pattern is obtained by arranging the electro-optical capacitor of the intermediate density and the electro-optical capacitor of the specific density continuously in the extending direction of the data line. It is desirable that

Further, in any of the patterns, the electro-optical capacitors having the specific density may be arranged so as to change the density in the extending direction of the scanning line or the extending direction of the data line. desirable. In such a pattern, all necessary correction amounts can be set in one display pattern, so that efficiency can be improved.

The electronic apparatus according to the present invention includes the electro-optical device according to the first or second aspect as a display unit.
As a result of suppressing luminance unevenness at the boundary between blocks, high-quality display becomes possible.

[0037]

Embodiments of the present invention will be described below with reference to the drawings.

<Embodiment> First, an active matrix type liquid crystal display device according to an embodiment of the present invention will be described. FIG. 1 is a block diagram showing the overall configuration of the liquid crystal display device. It should be noted that the configuration of the liquid crystal display panel 100 in this figure is not different from the configuration in FIG.

In FIG. 1, a pattern generation circuit 34a
At the time of adjustment, an image signal for displaying a pattern described later is digitally generated and supplied to the input terminal B of the selector 36. Selector 36
Selects the digital image signal D supplied to the input terminal A when the signal Sel1 for controlling the selection is at the H level, and is supplied to the input terminal B when the signal Sel1 is at the L level. The image signal is selected by the pattern generating circuit 34a, and the selected image signal is supplied to the image signal processing circuit 32. Here, the image signal D is
It is supplied from an external circuit (not shown) to cause the liquid crystal display panel 100 to perform a normal display. On the other hand, the image signal from the pattern generation circuit 34a is used for setting a correction amount of a correction table described later at the time of adjustment, for example, at the time of factory shipment.

Next, the image signal processing circuit 32 firstly
A second method in which a correction process is performed on the image signal D, and secondly, the corrected image signal is converted into an analog signal. It is. Here, when the blocks B1, B2,..., Bn are sequentially selected from right to left in FIG.
This occurs at a pixel corresponding to the intersection of the rightmost data line 114f in n. Then, the data line 114
What affects f is the voltage displacement of the data line 114a adjacent to the block in the block selection direction and belonging to the next block. Therefore, the image processing circuit 32 adds an image signal to be applied to the data line 114f belonging to a certain block Bj to the next block B (j + 1).
Signal VID applied to the data line 114a belonging to
In this configuration, a correction process of adding a correction amount corresponding to the voltage displacement of 1 is performed.

First, a configuration for executing this correction processing will be described. First, the latch circuit 330
Is the data line 1 of the image signal D supplied in time series.
Extract only those corresponding to the image signal to 14a,
This is latched as the image signal Da. Next, the correction amount output section 340 outputs a correction amount Cmp corresponding to the latched image signal Da, for example, with characteristics as shown in FIG. Here, the correction amount Cmp is such that when the pixel corresponding to the intersection with the data line 114a belonging to a certain block has any density from white to black, the voltage of the data line 114a is selected by selecting the block. By the transition, the data line 114f adjacent to the left side (the data line 114f belonging to the previous block)
This is for canceling the fluctuation of the voltage of. Therefore, the correction amount output unit 340 includes an address generation circuit 342, a correction table 344, and an interpolation circuit 346.

As shown in FIG. 4, the correction table 344 includes specific levels Vg1, Vg2, Vg3, and Vg among the density levels indicated by the image signal D (Da).
correction amounts Cmp1 corresponding to the five points g4 and Vg5,
Cmp2, Cmp3, Cmp4, and Cmp5 are stored in advance, and a correction amount specified by an address is read and output. The specific levels Vg1, Vg2, Vg3, Vg4 and Vg5 are selected so as to be substantially equally spaced in a range from white to black where the density level can be taken. In addition,
In the present embodiment, the correction table 344 is formed of a memory that can be electrically erased, and enables the correction amounts Cmp1, Cmp2, Cmp3, and Cmp4 to be set to arbitrary values during adjustment, and to store the set values. It is configured to keep the contents.

Here, the correction amount Cmp1 stored in the correction table 344 corresponds to the data line 114 belonging to a certain block.
When the pixel corresponding to the intersection with a is set to the specific level Vg1 corresponding to white, the voltage of the data line 114a changes by the selection of the block, so that the voltage of the adjacent data line 114f on the left side is changed. Has a magnitude corresponding to the variation, and the sign thereof is opposite to the above-mentioned variation direction. Similarly, the correction amounts Cmp2 and Cmp3
And Cmp4 are data lines 114 belonging to a certain block.
The pixels corresponding to the intersection with a are designated as specific levels Vg2,
When Vg3 and Vg4 are set, the voltage of the data line 114 is changed by the selection of the block,
The left side has a magnitude corresponding to the fluctuation of the voltage of the adjacent data line 114f, and the sign thereof is opposite to the fluctuation direction. Then, when the pixel corresponding to the intersection with the data line 114a belonging to a certain block is set to the specific level Vg5 corresponding to black, the correction amount Cmp5 causes the voltage of the data line 114 to transit by selecting the block. Has a magnitude corresponding to the amount by which the voltage of the adjacent data line 114f fluctuates to the left, and its sign is opposite to the direction of the fluctuation. The correction amounts Cmp1, Cm
How p2, Cmp3, Cmp4 and Cmp5 are defined in the present embodiment will be described later.

Next, the address generation circuit 342 determines the density level indicated by the image signal Da, classifies the following as the result of the determination, and divides the case into the address ad1 for reading the correction amount from the correction table 344 as follows. , Ad2.

First, the density levels specified by the image signal Da are the specific levels Vg1, Vg2, Vg3, Vg4, and Vg.
If any of the five points of g5, the address generation circuit 342
Outputs one address ad1 for reading out the corresponding correction amount from the correction table 344. On the other hand, if the density level specified by the image signal Da is not any of the above five points, the address generation circuit 342 outputs the specific level Vg
Two addresses ad1 and ad2 for reading out the correction amounts corresponding to the specific levels located before and after the image signal Da among the five points of 1, Vg2, Vg3, Vg4 and Vg5 are output. For example, the density level indicated by the image signal Da is on the black side of the specific level Vg2 and the specific level V
If it is whiter than g3, the address generation circuit 342 supplies an address ad1 for reading out the correction amount Cmp2 corresponding to the specific level Vg2 and a correction amount Cmp corresponding to the specific level Vg3.
The address ad2 for reading mp3 is output.

Subsequently, the interpolation circuit 346 outputs the image signal Da.
Are specified specific levels Vg1, Vg
g2, Vg3, Vg4 and Vg5
While the correction amount read from the correction table 344 is output as it is as the correction amount Cmp, if it is not any of the five points, the correction amount read from the correction table 344 is interpolated as follows. The interpolation result is used as the correction amount C
Output as mp. Specifically, the image signal Da
If the density level specified by the above is not one of the above five points, the interpolation circuit 346 calculates the two correction amounts read from the correction table 344 by the density specified by the image signal Da within the two points. Calculate internally by level.

The interpolation operation is not limited to this, and multipoint interpolation processing of three or more points may be executed.
External interpolation may be used. In the present embodiment, the correction amounts corresponding to the five specific levels are stored, but the present invention is not limited to this.

Next, the selector 350 selects the correction amount Cmp supplied to the input terminal A when the signal Sel2 for controlling the selection is at the H level, and selects the correction amount Cmp when the signal Sel2 is at the L level. The zero data NULL supplied to the terminal B is selected and supplied to one of the input terminals of the adder 324 as a selection result SelOut. On the other hand, the delay circuit 322 delays the image signal selected by the selector 36 by the time dly ′ so that the timing matches the selection result SelOut supplied to one of the input terminals of the adder 324, as the image signal Dd. Output. Subsequently, the adder 324 adds the image signal Dd and the selection result SelOut, and outputs the addition result as an image signal D ′.

Then, the D / A converter 326 converts the digital image signal D 'into an analog signal and outputs the image signal VID.
Is output as S /
The P-conversion circuit 302 and the inversion circuit 304 have exactly the same configuration as that shown in FIG. Further, the timing signal generation circuit 202 in the present embodiment includes a pattern generation circuit 34a,
The selector 36, each unit in the image signal processing circuit 32, and the liquid crystal display panel 100 are controlled by a clock signal, a control signal, and the like.

Next, the operation of the correction processing by the image signal processing circuit 32 having such a configuration will be described. When the correction processing is performed by the image signal processing circuit 32, the timing signal generation circuit 202 controls the signal Sel1 to the H level so that the selector 36 selects the input terminal A. Here, FIG. 2 is a timing chart for explaining the operation of the correction processing. As shown in this figure, one row of digital image signals D
Are supplied in chronological order corresponding to the pixels in the first, second, third,..., (6n) columns.

At this time, the timing signal generation circuit 202
Sets the signal SWP to the H level at the timing when the image signal D corresponding to the pixels in the first, seventh, thirteenth,..., (6n-5) th columns is supplied. As a result, the image signal Da latched by the latch circuit 330 is the image signal D supplied in time series corresponding to the pixels in the first, second, third,..., (6n) columns. Data line 1
Only the image signal D to the pixel corresponding to the intersection with 14a is extracted and latched.

The correction amount output section 340 reads out the correction amount Cmp corresponding to the image signal Da latched by the latch circuit 330 from the correction table 344 as described above, or outputs the correction amount Cmp by performing an interpolation operation. . Here, the first column, the seventh column, the thirteenth column,..., (6n−
5) For the sake of convenience, the correction amounts output for the image signal Da corresponding to the pixels in the column are represented by Cmp (1), Cmp (7), Cmp
(13),..., Cmp (6n−5), these correction amounts are calculated based on the time dly with respect to the image signal Da for reading out from the correction table 344 and performing interpolation calculation.
Is output with a delay.

Next, the timing signal generation circuit 202
The signal SWP is supplied to the selector 350 as the signal Sel2 with a delay of the time dly. Therefore, the selection result SelOut by the selector 350 becomes the correction amount Cmp (1) when the signal Sel2 goes to the H level for the first time, and the correction amount Cmp (7) when the signal Sel2 goes to the H level for the second time. ), And becomes the correction amount Cmp (13) when the signal Sel2 goes to the H level for the third time. Similarly, when the signal Sel2 goes to the H level for the nth time, the correction amount Cmp (6n−5) is obtained. ), And otherwise, zero data NULL.

On the other hand, the image signal Dd is delayed from the image signal D by the delay circuit 322 for a time dly 'which is longer than the time dly by one pixel of the image signal. Therefore, of the image signal Dd, the data line 1
Since only zero data NULL is added to the image signal to the pixel corresponding to the intersection with 14a, 114b, 114c, 114d, 114e, the content is not changed at all. On the other hand, in the image signal Dd, the image signal to the pixel corresponding to the intersection with the data line 114f includes the correction corresponding to the image signal to the data line 114a adjacent to the data line 114f in the block selection direction. Quantity C
mp will be added by the adder 324. However, since there is no data line 114a adjacent to the data line 114f of the last block Bn in the block selection direction, zero data NULL is added in this case so that the content is not changed. Also, the selector 350
In the period in which the selection result is the correction amount Cmp (1), the image signal Dd to be added is not yet supplied due to the delay by the delay circuit 322, and in this case, the image signal D 'in this period is invalidated.

The image signal D ', which is the result of the addition by the adder 324, is analog-converted by the D / A converter 324 and output as the image signal VID.
The signal is distributed to six systems by the conversion circuit 302,
The image signal is expanded six times in the time axis, inverted in polarity by the inversion circuit 304, and supplied as image signals VID1 to VID6. Here, the correction processing for the image signal corresponding to the pixels of one row has been described.
Such an operation is repeatedly performed for each of rows from 1 to m.

Subsequently, in the present embodiment, for the purpose of suppressing the occurrence of luminance unevenness, attention is paid to blocks B1 and B2 for comparison with the related art (see FIG. 16). Is described as an example. FIG. 3 is a voltage waveform diagram for explaining the point where the occurrence of luminance unevenness is suppressed in this case.

[0057] First, in FIG. 3, reaching the timing t ₁₁ in one horizontal retrace period, the precharge control signal N
RG becomes H level. For this reason, the precharging switch 165 is turned on, so that all the data lines 114
Are precharged to a precharge voltage Vpre (+) corresponding to positive polarity writing. Thereafter, the precharge control signal N
RG goes low, but all data lines 114
The precharge voltage Vpre (+) is maintained by the parasitic capacitance.

Next, reaches the timing t ₁₂ in one horizontal effective period, the sampling control signal S1 rises to the H level, the data line 114f of the block B1, the image signal VID6 are sampled by the sampling switch 141. This image signal VID6 is a voltage obtained by adding a voltage corresponding to the correction amount Cmp (7) to an original voltage. For this reason, the voltage of the data line 114f changes from the voltage Vpre (+) maintained up to that time to a voltage corresponding to the sampled image signal VID6. The data is written to the liquid crystal capacitor corresponding to the intersection with the pixel 112. Thereafter, the sampling control signal S1 falls to the L level.

[0059] Subsequently, reaches the timing t _13, the sampling control signal S2 rises to H level, the data line 114a of the block B2, the sampling switch 1
The image signal VID1 is sampled by 41.
Here, since nothing is added to the image signal to the data line 114a, the image signal VID1 remains at the original voltage. Therefore, the data line 114a of the block B2
Transitions from the precharge voltage Vpre (+) maintained up to that point to the voltage of the sampled image signal VID1, and this transitions to the data line 114 belonging to the block B2.
The data is written to the liquid crystal capacitance corresponding to the intersection of a with the selected scanning line 112.

At this time, data line 1 belonging to block B1
14, the data line 114f adjacent to the block B2
Is capacitively coupled to the data line 114a of the block B2, so that the data line 1 belonging to the block B2
When the voltage of 14a changes from the precharge voltage Vpre (+) to the voltage of the image signal VID1, the voltage fluctuates. However, in the present embodiment, since the voltage obtained by adding the voltage corresponding to the variation to the original voltage in advance is applied, the effect of the variation is canceled, so that the voltage substantially matches the original voltage. become.

Accordingly, the voltage of the data line 114f belonging to the block B1 changes from a voltage to a voltage. Finally, the liquid crystal capacitance (pixel) corresponding to the intersection of the data line 114f belonging to the block B1 and the selected scanning line 112 is changed. The density and the density of the pixel located at the intersection of the data line 114a belonging to the block B2 and the selected scanning line 112 are substantially equal to each other. Nothing is added to the other data lines 114a to 114e belonging to the block B1, so that the pixels corresponding to the intersections of these data lines and the currently selected scanning line maintain the original gray. Will be. Such writing is the same at the timings t ₂₁ , t ₂₂ , and t ₂₃ corresponding to the negative polarity writing, the other blocks, and the case where another scanning line is selected. Therefore, in the present embodiment, for example, even when all pixels are displayed at the same density, blocks B1, B2,.
Since the data line 114f located at the right end of the data line eventually becomes the original voltage, the other data lines 114a, 114b, 1
Since they are almost equal to 14c, 114d, and 114e, there is almost no difference in density between pixels. As a result, the occurrence of luminance unevenness at the boundary between blocks is suppressed.

Next, the precharge voltages Vpre (+), Vpre (+)
Consider (-). As described above, the voltage of the data line 114f located at the right end of a certain block fluctuates due to the voltage change of the data line 114a adjacent thereto.
It depends on the amount of voltage change of the data line 114a. Among them, the coupling capacitance with the data line 114 can be regarded as constant during operation. The voltage change amount of the data line 114a is a difference voltage between the precharge voltage Vpre and the image signal VID1 by sampling.

If the above-described correction processing is not performed, the precharge voltage Vpre (+) or Vpre (−) is used to reduce the luminance unevenness at the boundary between blocks.
It is necessary to reduce the difference voltage from the image signal VID1.
Here, the voltage of the image signal VID1 changes according to the content of the image to be displayed, but the average value is the center voltage when the polarity is inverted. Therefore, the precharge voltage Vpr
If e (+) and Vpre (-) are the central voltages, the data line 114
Since the amount of voltage change of “a” should be small, it is possible to reduce luminance unevenness.

However, the precharge voltage Vpre
Assuming that (+) and Vpre (-) are the center voltages, the image signal VID1 corresponding to black in the normally white mode
Is sampled on the data line 114a, which is a capacitive load, a large voltage change is involved, so that writing cannot be completed in a short time, and it is difficult to obtain sufficient contrast. On the other hand, in the configuration in which the correction operation is performed as in the present embodiment, it is not necessary to consider the amount of voltage change.
(+) And Vpre (-) can be set to voltages corresponding to black in a normally white mode. Therefore, according to the present embodiment, it is possible to suppress the occurrence of luminance unevenness and obtain a large contrast.

Subsequently, in the present embodiment, the correction amounts Cmp1, Cmp2, Cmp3, Cm stored in the correction table 344.
How to set p4 and Cmp5 will be described. Note that, for convenience of explanation, the correction amounts Cmp1, Cmp2, Cmp
3, Cmp4 and Cmp5 are initially in a state of zero, that is, in a state where no correction is made.
When setting the correction amount from this state, the timing signal generation circuit 202 controls the signal Sel1 to be at the L level to cause the selector 36 to select the input terminal B.

Further, the timing signal generation circuit 202
Controls the pattern generating circuit 34a to output an image signal for displaying a pattern as shown in FIG. 6A. Specifically, the pattern generation circuit 3
4a is a white pixel corresponding to a specific level Vg1 (FIG. 4) as a specific color, and an arbitrary intermediate density (gray) as an intermediate color
And an image signal for displaying a checkerboard pattern in which pixels are alternately arranged in the row direction and the column direction. In this display pattern, as shown in FIG. 6A, a row array in which a boundary of a block is located between a pixel of an intermediate color and a pixel of a specific color (white) adjacent to the pixel in the block selection direction. Will always appear.

Here, in the state where the correction amount Cmp1 is zero, no correction is performed on the image signal.
As shown in FIG. 5A, the density of the pixel f corresponding to the intersection of the data lines 114f (the pixel f located at the right end in each block) is different from the density of the gray pixels b and d which should be the same. Will be. Therefore, the correction amount Cmp1 is increased or decreased to make the density of the pixel f coincide with the density of the pixels b and d, as shown in FIG. Then, the correction amount Cmp1 at the coincident stage is set so as to be used in the above-described correction processing. Note that the adjustment of the density may be automatically performed by image processing of capturing a display image, or may be manually performed by an adjuster relying on the visual sense.

Next, the pattern generation circuit 34a
The specific color in (a) is set to a density corresponding to the specific level Vg2 (FIG. 4). When the correction amount Cmp2 is zero,
Since no correction is performed on the image signal, the density of the pixel f is different from the density of the pixels b and d, as shown in FIG. Therefore, by increasing or decreasing the correction amount Cmp2,
As shown in FIG. 5B, the density of the pixel f is made to match the density of the pixels b and d, and the correction amount Cmp at the time when they match is made.
2 is set to be used in the above-described correction processing. Hereinafter, similarly, the specific colors are set as specific levels Vg3, Vg4, and Vg5.
The correction amounts Cmp3, Cmp4, and Cmp5 at the stage when the density of the pixel f matches the density of the pixels b and d are set to be used in the above-described correction processing. With these settings, the correction amounts Cmp1, Cmp2, Cmp3, Cmp4, Cmp5 respectively corresponding to the specific levels Vg1, Vg2, Vg3, Vg4, Vg5 are set.

Here, in the actual display, where the boundary of the block is located is not specified, so that in a normal display, which pixel corresponds to which data line,
Cannot be determined. On the other hand, in the display pattern shown in FIG. 6A, when the selection direction of the block is from left to right, the density of the gray pixel located at the right end of the block is different from that before adjustment. Since the density is different from that of the gray pixels, the boundary of the block can be immediately specified. Moreover, in the display pattern in FIG. 6A, the row arrangement in which the boundary of the block is located between the pixel of the intermediate color and the pixel of the specific color adjacent to the pixel in the block selection direction has a probability of 1/2. Appears in. Therefore, it is not necessary to associate a display pattern with a pixel. For example, it is not always necessary to associate the pixel f with an intermediate color and the pixel a with a specific color. Therefore, if a pattern as shown in FIG. 6A is used, the correction amounts Cmp1, Cmp2, Cmp3, Cmp4 and Cmp5 can be set very easily with a simple configuration.

In the present embodiment, the display patterns suitable for setting the correction amount include, in addition to FIG.
6 (b) and the pattern shown in FIG. 6 (c). Among these, as shown in FIG. 6B, two or more pixels of the intermediate color and pixels of the specific color continue in the column direction,
When the pattern arranged alternately is used, the pixel to be adjusted and the pixel whose density does not change are both continuous, so that the visual display area is increased and the adjustment becomes easier. Therefore, in an extreme case, as shown in FIG. 6C, a pattern in which pixels of the intermediate color and pixels of the specific color are continuously arranged over the entire area in the column direction may be used. However, if the number of data lines 114 constituting one block is an even number as in the present embodiment, it is necessary to associate the pixel f with an intermediate color and the pixel a with a specific color. If the number of data lines 114 constituting one block is odd, this association is not necessary.

Further, in this embodiment, the correction amounts of the five points are individually set. However, as shown in FIG. 7, a pattern in which a specific color is gray-scaled in the column direction may be used. When such a pattern is used, if the density of the pixel to be adjusted is adjusted over the entire display pattern so as to match the density of the pixel located in the row direction, the correction amounts Cmp1, Cmp2, Cmp3, Cmp4, Cm
p5 can be set in one display. Therefore, the setting of the correction amount can be made more efficient. In the pattern shown in FIG. 7, the gray scale direction may be the row direction.

According to such an embodiment, it is possible to suppress the occurrence of luminance unevenness at the boundary between blocks, and to easily set the correction amount used for the correction processing.

<Second Embodiment> In the first embodiment described above, the pattern is displayed by the image signal generated by the pattern generation circuit 34a, and the correction amount used for the image signal correction processing is set. The thing is,
Since it has only a simple regularity, an image signal corresponding to one of the densities may be selected according to the display pattern. Therefore, a second embodiment having such a configuration will be described. FIG. 8 is a block diagram showing the configuration of the liquid crystal display device according to the second embodiment. In the figure, a selector 38 is provided at an input stage of the image signal processing circuit 32. The input terminal A receives an external image signal D, and the input terminal B receives an image signal Dg corresponding to an intermediate color.
However, an image signal Ds corresponding to a specific color is supplied to the input terminal C. The timing signal generation circuit 204 includes the liquid crystal display panel 100 and the image signal processing circuit 3.
In addition to the signal 2, the signal Sel11 for controlling the selection by the selector 38 is output. Therefore, the timing signal generation circuit 204 functions as a control unit that controls the selection by the selector 38.

In this configuration, the liquid crystal display panel 100
When the normal display is performed (ie, when the display is performed according to the image signal D), the timing signal generation circuit 204 controls the selector 38 to select the input terminal A by the signal Sel11. On the other hand, when setting the correction amount, the timing signal generation circuit 204 sends the signals Bel and C to the selector 38 in response to the signal Sel11.
Is set to A according to the density in the display pattern.
Control to select. For example, if the patterns shown in FIG. 6A, FIG. 6B, and FIG. 6C are to be displayed, the timing signal generation circuit 204 is provided at every interval when one pixel of the image signal is supplied. The selector 38 is controlled so that the input terminals B and C are alternately switched. As shown in FIG. 7, when displaying a grayscale pattern, the density indicated by the image signal Ds may be increased or decreased in accordance with vertical scanning or horizontal scanning.

<Third Embodiment> Next, a liquid crystal display device according to a third embodiment of the present invention will be described. Although the image signal D or the image signal for pattern display is switched by the selector 36 in the first embodiment and by the selector 38 in the second embodiment, the correction amount is set once. It doesn't have the character of resetting frequently. Therefore, when defining the correction amount,
As in the third embodiment shown in FIG. 9, a pattern generation circuit 34b may be directly connected to the input of the image signal processing circuit 32 to supply an image signal corresponding to a display pattern. Here, the pattern generation circuit 34b displays the patterns as shown in FIGS. 6A, 6B, 6C, and 7 described above, and the correction amount is set. Is performed using this pattern.

<Applications and Modifications of the Embodiments> The present invention is not limited to the above-described first, second and third embodiments, and various applications and modifications are possible.

<Application Modification: Part 1> As described later, a liquid crystal display device is sometimes used for image formation of a video projector. In a video projector, two use states are assumed: a case where the device is placed on the floor and a case where the device is suspended from the ceiling. In these two usage states,
Since the positional relationship of the liquid crystal panel with respect to the screen is reversed up, down, left and right, it is necessary to be able to reverse the scanning direction in the liquid crystal panel both vertically and horizontally in order to cope with both use states.

In the above embodiment, since the block selection direction is from left to right as shown in FIG. 10A, the data located at the right end of blocks B1, B2,. Line 114f was affected by the voltage shift on the adjacent data line 114a. However, when the scanning direction of the data line 114 is reversed, the block selection direction changes from right to left as shown in FIG. 10B, so that the data line 114a located at the left end of each block becomes
It will be affected by voltage displacement on the adjacent data line 114f.

Here, in order to switch the block selection direction, two frame memories capable of storing one frame of image signal are provided at the front stage of the liquid crystal display device, and the image signal is written to one of the frame memories. In the period, an image signal is read from the other frame memory, and the image signal is supplied to the image signal processing circuit 32.
Further, when the image signal is read from the frame memory, the image signal is read in a reverse order to the writing order.
With this configuration, when the selection direction of the block is reversed, the image signal to the data line 114a is supplied to the image signal processing circuit 32 prior to the image signal to the data line 114f that exerts an influence. Therefore, the supply order of the image signals does not change even if the block selection direction is reversed.

Therefore, the forward rotation in the block selection direction
In order to cope with the inversion, a control signal indicating the distribution direction is supplied to the S / P conversion circuit 302 in the embodiment, and the image signals VID1 to VID6 are supplied in accordance with the control signal.
What is necessary is just to change the correspondence between the image signal lines. Specifically, when the control signal indicates the normal rotation, the image signal VID1 is applied to the first image signal line 171, the image signal VID2 is applied to the second image signal line 171,. The image signal VID6 is supplied to each of the image signal lines 171 of the first image signal line 171. When the control signal indicates inversion, the image signal VID6 is supplied to the first image signal line 171 and the image signal VID6 is supplied to the second image signal line 171. The image signal VID5,..., And the image signal VID1 may be supplied to the sixth image signal line 171. Note that the scanning line driving circuit 120
It is a matter of course that the shift register circuit 130 and the shift register circuit 130 are configured to be capable of both forward and reverse transfer.

<Application Modification: Part 2> In the above-described embodiment, the six data lines 114 are combined into one block, and the six data lines 114 belonging to one block are converted into six systems. Although the image signals VID1 to VID6 are sampled, the number of conversions and the number of data lines to be sampled (that is, the number of data lines constituting one block) are not limited to “6”. For example, if the response speed of the sampling switch 141 is sufficiently high, the image signal is serially transmitted to one image signal line 171 without being converted in parallel, and sampling is sequentially performed for each data line 114. May be.

Further, assuming that the number of conversions and the number of data lines to be applied simultaneously are “3”, “12”, “24”, etc., three, 12, or 24 data lines are converted into three systems Alternatively, a configuration may be adopted in which image signals subjected to 12-system conversion, 24-system conversion, and the like are simultaneously supplied. In addition, as the conversion number,
In view of the fact that a color image signal is composed of signals related to three primary colors, a multiple of 3 is preferable in terms of simplifying control and circuits. However, in the case of a simple light modulation application such as a projector to be described later, the number need not be a multiple of three. Further, in the embodiment, the correction circuit 300 performs the conversion before the serial-parallel conversion of the image signal.
Although the correction is performed, the correction may be performed after the serial-parallel conversion.

<Application Modification: Part 3> In the above-described embodiment, the description has been made on the premise that the precharge is performed in the horizontal retrace period before the block is selected. However, in the present invention, when blocks are sequentially selected, In addition, by adding a correction amount in advance to an image signal to a data line that fluctuates in voltage due to a voltage displacement in another data line so as to offset the fluctuation, luminance unevenness occurring at the boundary between blocks is suppressed. Therefore, it is a matter of course that a configuration without pre-charging may be used. In short, the present invention can be applied to all configurations in which a correction amount that cancels out the fluctuation is previously added to the image signal to the data line whose voltage fluctuates due to the voltage displacement in the other data line. For this reason, the image signal correction processing can be applied not only to a configuration for processing digitally but also to a configuration for performing analog processing, and to a configuration in which the correction amount is changed corresponding to each of positive polarity writing and negative polarity writing. But it is applicable.

In addition, in the embodiment, the normally white mode in which white display is performed when the effective voltage value applied to the liquid crystal capacitance is zero has been described. However, the effective voltage value applied to the liquid crystal capacitance has been described. May be a normally black mode in which black display is performed when is zero. Further, in the above-described embodiment, the TN type is used as the liquid crystal.
Further, a dye (guest) having anisotropy in visible light absorption in the major axis direction and the minor axis direction of the molecule is dissolved in a liquid crystal (host) having a fixed molecular arrangement, and the dye molecule is parallel to the liquid crystal molecule. A liquid crystal of GH (guest host) type or the like may be used.

In addition, when no voltage is applied, the liquid crystal molecules are aligned vertically with respect to both substrates, while when the voltage is applied, the liquid crystal molecules are aligned with both substrates in a vertical direction (homeotropic alignment). It may be configured,
When a voltage is not applied, the liquid crystal molecules are arranged in a horizontal direction with respect to both substrates, while when a voltage is applied, the liquid crystal molecules are arranged in a direction perpendicular to both substrates. good. As described above, the present invention can be applied to various types of liquid crystal and alignment methods.

In addition to the liquid crystal display device, the present invention can be applied to various electro-optical devices which perform display by the electro-optical effect using electroluminescence (EL), fluorescence by plasma emission or electron emission, or the like. . At this time, the electro-optical material is an EL, a mirror device, a gas, a phosphor, or the like. In addition, EL as an electro-optical material
When EL is used, the EL is interposed between the pixel electrode 118 and the opposing electrode of the transparent conductive film on the element substrate 101, so that the opposing substrate, which is necessary for a liquid crystal display device, becomes unnecessary. Thus, the present invention is applicable to all electro-optical devices having a configuration similar to the above-described configuration.

<Electronic Apparatus> Next, some electronic apparatuses using the liquid crystal display device according to the above-described embodiment will be described.

<Part 1: Projector> First, a projector using the above-described liquid crystal display device as a light valve will be described. FIG. 11 is a plan view showing the configuration of this projector. As shown in this figure, a lamp unit 1102 including a white light source such as a halogen lamp is provided inside the projector 1100. The projection light emitted from the lamp unit 1102 is R (red) and G by three mirrors 1106 and two dichroic mirrors 1108 disposed inside.
The light is separated into three primary colors (green) and B (blue), and guided to light valves 100R, 100G, and 100B corresponding to the respective primary colors.

Here, the light valves 100R, 100G
And 100B are basically the same as the liquid crystal display panel 100 according to the above-described embodiment. That is, the light valves 100R, 100G, and 100B
It functions as an optical modulator for generating each primary color image of B. The B light has a longer optical path compared to the other R and G lights, so that the incident lens 1122, the relay lens 1123, and the outgoing lens 1
It is guided through a relay lens system 1121 consisting of.

Now, the light valves 100R, 100G,
The lights modulated by 100B respectively enter dichroic prism 1112 from three directions. And
In the dichroic prism 1112, the R and B lights are refracted at 90 degrees, while the G light travels straight.
As a result, a color image obtained by combining the primary color images is projected onto the screen 1120 via the projection lens 1114.

<Part 2: Personal Computer> Next, an example in which the above-described liquid crystal display device is applied to a multimedia-compatible personal computer will be described.
FIG. 21 is a perspective view showing the configuration of the personal computer. As shown in FIG.
The liquid crystal display panel 100 used as a display unit, the optical disk read / write drive 1212, and the magnetic disk read / write drive 12
14, a stereo speaker 1216 and the like.
A keyboard 1222 and a pointing device (mouse) 1224 are connected to the
The transmission and reception of control signals and the like are performed wirelessly via infrared rays or the like. Since the liquid crystal display panel 100 is used as a direct-view type, one dot is formed by three pixels of RGB and a color filter is provided for each pixel. A backlight unit (not shown) for ensuring visibility in a dark place is provided on the back surface of the liquid crystal display panel 100.

<Summary of Electronic Equipment> In addition to the electronic equipment described with reference to FIG. 11 and FIG.
LCD TVs, viewfinder / monitor direct-view video tape recorders, car navigation systems, pagers, electronic organizers, calculators, word processors, workstations, videophones, POS terminals, digital still cameras, devices with touch panels, etc. No.
Needless to say, the liquid crystal display device according to the embodiment, the application, and the modification can be applied to these various electronic devices.

[0093]

As described above, according to the present invention, it is possible to suppress the occurrence of luminance unevenness at the boundary between blocks and to easily set the correction amount used for the correction processing.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a liquid crystal display device according to a first embodiment of the present invention.

FIG. 2 is a timing chart for explaining an operation of an image signal processing circuit in the liquid crystal display device.

FIG. 3 is a voltage waveform chart for explaining the operation of the liquid crystal display device.

FIG. 4 is a diagram illustrating a relationship between an input image signal and an output correction amount in the correction circuit.

FIGS. 5A and 5B are diagrams for explaining an operation of setting a correction amount in a correction circuit of the same image signal processing circuit.

FIGS. 6A, 6B, and 6C are diagrams illustrating examples of patterns by a pattern generator in the same liquid crystal display device.

FIG. 7 is a diagram showing an example of a pattern by a pattern generator.

FIG. 8 is a block diagram illustrating a configuration of a liquid crystal display device according to a second embodiment of the present invention.

FIG. 9 is a block diagram illustrating a configuration of a liquid crystal display device according to a third embodiment of the present invention.

FIG. 10 (a) shows affected data lines when the block selection direction goes from left to right, and FIG. 10 (b) shows the case where the block selection direction goes from right to left. FIG. 3 is a diagram showing data lines affected by

FIG. 11 is a cross-sectional view illustrating a configuration of a projector as an example of an electronic apparatus to which the liquid crystal display device according to the embodiment is applied.

FIG. 12 is a front view illustrating a configuration of a personal computer as an example of an electronic apparatus to which the liquid crystal display device is applied.

FIG. 13 is a block diagram showing an overall configuration of a conventional liquid crystal display device.

FIG. 14 is a block diagram illustrating an electrical configuration of a liquid crystal display panel in a conventional liquid crystal display device.

FIG. 15 is a timing chart illustrating the operation of a conventional liquid crystal display device.

FIG. 16 is a voltage waveform diagram for explaining an operation of a conventional liquid crystal display device.

[Explanation of symbols]

 32 image signal processing circuit 34a, 34b pattern generation circuit 36, 38 selector 100 liquid crystal display panel 108 pixel electrode 112 scanning line 114a-114f data line 116 TFT 118 pixel electrode 120 scanning line driving circuit 130 shift register 141 sampling switch 324 adder 344 correction table (storage means)

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 2H093 NA16 NA22 NA43 NA53 NA80 NC13 NC22 NC34 ND06 5C006 AA11 AC21 AF43 AF46 AF51 AF52 AF81 AF82 BB16 BC16 BF04 BF28 FA22 5C080 AA10 BB05 DD05 EE29 FF11 JJ01 JJ04 JJ04 JJ04 JJ04 JJ04 JJ04 JJ04 JJ04 JJ04 JJ04

Claims (12)

[Claims] A plurality of scanning lines; a plurality of data lines; and an intersection between the scanning lines and the data lines, interposed between a pixel electrode and the data lines, and A switching element that is turned on and off in accordance with the supplied scanning signal; and an electro-optical capacitor having the pixel electrode at one end and a counter electrode at the other end, and a voltage effective value applied to the pixel electrode and the counter electrode. An electro-optical capacitor whose density changes in response to the current, a scanning line driving circuit for selecting one of the scanning lines and supplying a scanning signal for turning on the switching element, and a period during which one of the scanning lines is selected Next, while sequentially selecting a block in which the data lines are grouped into a plurality of lines,
A data line driving circuit for supplying an image signal to a data line belonging to a selected block; and a data line belonging to a certain block being located at a first data line adjacent to a block selected next to the block. At least a part of the electro-optical capacitance to be used is set to the intermediate density, and among the data lines belonging to the block selected next, the electro-optical capacitance located at the second data line adjacent to the first data line is reduced. Even if a part of the electro-optical capacitance is located at a specific density, the remaining part or a part of the electro-optical capacitance located at the second data line or a third data line different from the first and second data lines is located. A pattern generating circuit that supplies an image signal of a pattern having at least a part of the electro-optical capacitance to have the intermediate density, an image signal by the pattern generating circuit, or an external image signal. When selecting either one, and when selecting an image signal by the pattern generation circuit,
A selector for supplying the selected image signal to the data line driving circuit; and an intermediate portion of the electro-optical capacitors located on the first data line when the selector selects an image signal from the pattern generation circuit. The amount required to correct the density of the electro-optical capacitor as the density to the density of the electro-optical capacitor as the intermediate density among the electro-optical capacitors located on the second or third data line is a correction amount. When an image signal from the outside is selected by the selector, and when one block is selected, the block should be selected next to the block among the image signals. If the image signal to the second data line belonging to the block corresponds to the specific density, the first image signal belonging to the selected block among the external image signals. An image signal corresponding to the over data lines, wherein by adding the correction amount, the electro-optical device characterized by comprising an adder for outputting an image signal to the data line driving circuit. 2. A plurality of scanning lines, a plurality of data lines, and intersecting the scanning lines and the data lines, interposed between a pixel electrode and the data lines, and A switching element that is turned on and off in accordance with the supplied scanning signal; and an electro-optical capacitor having the pixel electrode at one end and a counter electrode at the other end, and a voltage effective value applied to the pixel electrode and the counter electrode. An electro-optical capacitor whose density changes in response to the current, a scanning line driving circuit for selecting one of the scanning lines and supplying a scanning signal for turning on the switching element, and a period during which one of the scanning lines is selected In addition, while sequentially selecting a block in which the data lines are grouped into a plurality of lines,
A data line driving circuit for supplying an image signal to a data line belonging to the selected block; an image signal having the electro-optical capacitance at an intermediate density; an image signal having the electro-optical capacitance at a specific density; A selector for selecting one of the image signals, and control means for controlling selection by the selector,
In the first case, in which the image signal having the intermediate density or the specific density is selected, among the data lines belonging to a certain block, a position is set to a first data line adjacent to a block selected next to the block. At least a part of the electro-optical capacity to be used is set to the intermediate density, and among the data lines belonging to the block to be selected next, the electro-optical capacity located on the second data line adjacent to the first data line is reduced. Even if a part of the electro-optical capacitance is located at a specific density, the remaining part or a part of the electro-optical capacitance located at the second data line or a third data line different from the first and second data lines is located. So that at least a part of the electro-optical capacitance is a pattern with the intermediate density,
Control means for controlling the selector; and, in the first case, the density of the electro-optical capacitance, which is the intermediate density, of the electro-optical capacitances positioned on the first data line is positioned on the second data line. Storage means for storing a correction amount required for correction up to the density of the electro-optical capacity which is the intermediate density among the electro-optical capacities to be performed; andthe control means causes the selector to select an external image signal. 2, when a certain block is selected, among the image signals, the image signal to the second data line belonging to the block to be selected next to the block corresponds to the specific density. , The first image signal belonging to the selected block among the external image signals
And an adder for adding the correction amount to an image signal corresponding to the data line and outputting the same as an image signal to the data line driving circuit. 3. The pattern according to claim 1, wherein the electro-optical capacitance of the intermediate density and the electro-optical capacitance of the specific density are alternately arranged one by one over the extending direction of the scanning line and the extending direction of the data line. 3. The electro-optical device according to claim 1, wherein the electro-optical device is arranged. 4. The pattern is arranged such that the electro-optical capacitors of the intermediate density and the electro-optical capacitors of the specific density are alternately arranged in two or more cycles in the extending direction of the data lines. The electro-optical device according to claim 1, wherein: 5. The pattern according to claim 1, wherein the intermediate-density electro-optical capacitance and the specific-density electro-optical capacitance are arranged continuously in the extending direction of the data line. The electro-optical device according to claim 1 or 2, wherein: 6. The pattern is characterized in that the electro-optical capacitors of the specific density are arranged so that the density changes over the extending direction of the scanning line or the extending direction of the data line. The electro-optical device according to claim 1. 7. An electronic apparatus comprising the electro-optical device according to claim 1 in a display unit. 8. A plurality of scanning lines, a plurality of data lines, and intersecting between the scanning lines and the data lines, interposed between the pixel electrodes and the data lines, and connected to the scanning lines. A switching element that is turned on and off in accordance with the supplied scanning signal; and an electro-optical capacitor having the pixel electrode at one end and a counter electrode at the other end, and a voltage effective value applied to the pixel electrode and the counter electrode. An electro-optical capacitor whose density changes in response to the current, a scanning line driving circuit for selecting one of the scanning lines and supplying a scanning signal for turning on the switching element, and a period during which one of the scanning lines is selected In addition, while sequentially selecting a block in which the data lines are grouped into a plurality of lines,
A data line driving circuit for supplying an image signal to a data line belonging to the selected block; and an image to be supplied to a first data line adjacent to the next selected block among the data lines belonging to the selected block. Adding a correction amount according to an image signal to be supplied to a second data line belonging to a block to be selected next and adjacent to the first data line, to the data line driving circuit; And an image signal processing circuit for supplying an image signal to the second data line. At least a part of the located electro-optical capacitance has a specific density, and is different from the remaining or a part of the electro-optical capacitance located on the second data line, or the first and second data lines. Third Pattern generating circuit an image signal of a pattern and the intermediate concentration at least a portion of the electro-optic capacity located in the data line, and supplying the image signal processing circuit. 9. The pattern according to claim 1, wherein the intermediate-density electro-optical capacitance and the specific-density electro-optical capacitance are alternately arranged one by one over the scanning line extending direction and the data line extending direction. 9. The pattern generation circuit according to claim 8, wherein the pattern generation circuit is arranged. 10. The pattern is arranged such that the electro-optical capacitors of the intermediate density and the electro-optical capacitors of the specific density are alternately arranged in two or more cycles in the direction in which the data lines extend. The pattern generation circuit according to claim 8, wherein: 11. The pattern according to claim 1, wherein the intermediate-density electro-optical capacitor and the specific-density electro-optical capacitor are arranged continuously in the extending direction of the data line. 9. The pattern generation circuit according to claim 8, wherein: 12. The pattern is characterized in that the electro-optical capacitors having the specific density are arranged so as to change the density in the extending direction of the scanning line or the extending direction of the data line. The pattern generation circuit according to claim 8, wherein: