JP2007010946A - Optoelectronic device, driving method, and electronic apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To secure a sampling period of a data signal supplied to an image signal line 180. <P>SOLUTION: Pixels 110 are provided correspondingly to intersections between scan lines 112 and data lines 114 divided every four into blocks. Image signal lines 180 are divided into groups (a) and (b), and each group consists of four lines and has a voltage holding property. When a scan line 112 of one row is selected, data signals Vid1 to Vid4 of four channels having voltages according with gradations of pixels corresponding to the selected scan line are supplied. A selection circuit 170 alternately selects the groups (a) and (b) and distributes the data signals Vid1 to Vi4 to four image signal lines 180 belonging to the selected group. A sampling signal output circuit 140 outputs signals synchronously with group selection of the selection circuit 170 while overlapping a H level in order. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

The present invention relates to a technique for ensuring a long period for sampling a data signal supplied to an image signal line on the data line.

In recent years, projectors that form a small reduced image by using a display panel such as a liquid crystal and enlarge and project the small reduced image by an optical system are becoming widespread. The projector does not have a function of creating an image by itself, and is supplied with image data (or an image signal) from a host device such as a personal computer or a TV tuner. This image data specifies the gradation (brightness) of the pixels, and is supplied in the form of vertical and horizontal scanning of the pixels arranged in a matrix, so that the display panel used in the projector is also this It is appropriate to drive according to the format. For this reason, in a display panel used in a projector, scanning lines are selected one by one in a predetermined order, and data lines are selected one by one in order in a period in which one scanning line is selected. In general, driving is performed in a dot sequential manner in which a data signal converted to be suitable for driving a liquid crystal is supplied to a selected data line.

On the other hand, recently, high definition of a display image is progressing like high vision. High definition can be achieved by increasing the number of scanning lines and the number of data lines to increase the number of pixels. However, since the frame frequency is fixed, the increase in the number of scanning lines increases to 1
The horizontal scanning period is shortened. Further, in the dot sequential method, the data line selection period is shortened by increasing the number of data line columns. For this reason, in the dot sequential method, it becomes impossible to secure a sufficient time for supplying the data signal to the data line as the definition becomes higher, and writing to the pixels has started to be insufficient.

Therefore, a method called phase expansion drive has been devised for the purpose of eliminating the shortage of writing (see Patent Document 1). In this phase development drive, the data lines are blocked every predetermined column, for example, every four columns (in Patent Document 1, every six columns are blocked, but here, every four columns are used for comparison. ) In the horizontal scanning period, the blocks are selected one by one in a predetermined order, and the data signals expanded four times with respect to the time axis are sampled on the four columns of data lines belonging to the selected block. It is a method. In this phase development driving method, the time for sampling the data signal on the data line can be secured four times in this example as compared with the dot sequential method, so it is considered suitable for high definition. Yes.
JP 2000-112437 A

By the way, in the above example, compared with the dot sequential method, the time for sampling the data signal on the data line can be secured four times as compared with the dot sequential method, but with this method alone, high definition can be achieved. Further progress has raised the possibility that a sufficient period of sampling the data signal on the data line cannot be ensured. However, the data signal is 4 times to 8 times.
There is also a problem in that the configuration required for decompression becomes complicated if it is simply expanded to double, 16 times,.
The present invention has been made in view of the above-described circumstances, and an object of the present invention is to ensure a sufficient period for sampling a data signal on a data line and to contribute to simplification of the configuration. To provide an optical device, a driving method, and an electronic apparatus.

In order to achieve the above object, in the present invention, a plurality of scanning lines and a plurality of data lines provided corresponding to a plurality of data lines blocked for each m (m is an integer of 1 or more) are provided. It is classified into pixels, a scanning line driving circuit for selecting the plurality of scanning lines in a predetermined order, and n (n is an integer of 2 or more) groups, each group consisting of m, In addition to selecting m × n image signal lines having voltage holdability and a group in a predetermined order,
A selection circuit that distributes m-channel data signals having a voltage corresponding to the gradation of the pixel corresponding to the scanning line selected by the scanning line driving circuit to m image signal lines belonging to the selected group; A sampling signal output circuit that outputs the sampling signal for selecting the blocks in a predetermined order in synchronization with the distribution by the selection circuit, and a sampling switch provided for each of the plurality of data lines, A sampling switch that turns on the one corresponding to the block selected by the sampling signal and samples the data signal distributed to the image signal line onto the data line; According to the present invention, an m-channel image signal can be further expanded n times and held on an image signal line. Therefore, it is possible to secure a longer period for sampling the data signal supplied to the image signal line on the data line without complicating the configuration.

In the present invention, a capacitance may be parasitic on each of the image signal lines, and a voltage holding property may be provided by the capacitance. Further, a capacitor may be connected between the image signal line and a potential line having a constant potential, and the capacitor may have a voltage holding property.
Further, the voltage of the data signal is provided between each output terminal of the selection circuit and the image signal line, and the voltage of the data signal selected by the selection circuit is held. The held voltage is based on a predetermined potential. It is good also as a structure further provided with the amplifier circuit which amplifies with an amplification factor and supplies to the said image signal line. The amplifier circuit includes n and p-channel transistors connected in series, and the data signal sampled by the sampling circuit is commonly input to the gates of both transistors, and the drains of both transistors are Are preferably connected to the data line in common.
Furthermore, the present invention can be conceptualized not only as an electro-optical device but also as a driving method of an electro-optical device and an electronic apparatus having the electro-optical device.

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram illustrating the overall configuration of the electro-optical device according to the present embodiment.
As shown in this figure, the electro-optical device 10 is roughly divided into a processing circuit 50 and a display panel 100. Among these, the processing circuit 50 is a circuit that controls the operation of the display panel 100 and the like, and is a circuit module mounted on a printed circuit board. The display panel 100 is an FPC.
(Flexible Printed Circuit) Connected by a substrate or the like.

The processing circuit 50 is further divided into a scanning control circuit 52, an S / P conversion circuit 320, a D / A conversion circuit group 330, and a polarity inversion circuit 340.
The S / P conversion circuit 320 receives image data Vin supplied from a host device (not shown) in synchronization with the vertical scanning signal Vs, the horizontal scanning signal Hs, and the dot clock signal Dclk.
As shown in Fig. 4, the image data is expanded four times on the time axis, distributed to four channels of image data Vd1 to Vd4, and the phases of four pixels are aligned and output (serial-parallel conversion or phase expansion). Also called).
Here, the image data Vin is digital data for designating the gradation (brightness) of the pixel. Specifically, in a certain horizontal effective scanning period, the selected row is positioned and 1
Image data corresponding to pixels from the column to the last column is sequentially supplied in synchronization with the dot clock signal Dclk.
Among these, the image data Vin of the pixels in the first, fifth, ninth,.
2, 6, 10,..., The image data Vin of the pixels in the columns is image data Vd 2, 3, 7, 1
The image data Vin of the pixels in the 1st column is output as image data Vd3, and the image data Vin of the pixels in the 4th, 8th, 12th,... Column is output as image data Vd4.
Note that the image data Vin is not supplied in the blanking period. For this reason, in the blanking period, the S / P conversion circuit 320 replaces the pixel data with data for blackening the image data Vd.
1 to Vd4 are output.

The D / A conversion circuit group 330 is an aggregate of D / A converters provided for each channel,
The phase-developed image data Vd1 to Vd4 are converted into analog voltages corresponding to the gradation values for each channel.
In the present embodiment, the image data Vin is converted to analog after serial-parallel conversion. However, it is needless to say that analog conversion may be performed before serial-parallel conversion.

The polarity inversion circuit 340 converts the D / A converted 4-channel analog signal to the higher level than the voltage Vc by the voltage of the analog signal when the positive polarity is instructed by the scanning control circuit 52. On the other hand, when the negative polarity is instructed, it is converted to a lower side than the voltage Vc and is output as data signals Vid1 to Vid4, respectively.
Here, the voltage Vc is the amplitude center potential of the data signal as shown in FIG. This voltage Vc is a substantially intermediate value between the high voltage Vdd of the power supply and the ground potential Gnd, and is a reference for the writing polarity to the pixel. That is, in the present embodiment, for the data signal, the higher side than the voltage Vc is called positive polarity, and the lower side is called negative polarity. The voltage is based on the ground potential Gnd of the power supply unless otherwise specified.

Here, the reason why the polarity of the data signal is inverted by the polarity inverting circuit 340 is to drive the pixel by alternating current. There are various methods such as (a) every scanning line, (b) every data transmission, (c) every pixel, (d) every surface (frame), etc. In this embodiment, it is assumed that (a) polarity reversal for each scanning line is present. However, the present invention is not limited to this.

The scanning control circuit 52 has a first function for controlling the scanning of the display panel 100 and the S / S described above.
A second function for controlling the phase expansion so as to synchronize with the horizontal scanning of the display panel 100, and a third function for generating a group selection signal Gs so as to synchronize with this phase expansion; It has mainly.
Here, the first function will be described in detail. The scanning control circuit 52 is based on the dot clock signal Dclk, the vertical scanning signal Vs, and the horizontal scanning signal Hs supplied from the host device.
The transfer start pulse DY and the clock signal CLY are generated to control the vertical scan of the display panel 100, and the transfer start pulse DX and the clock signal CLX are generated to control the horizontal scan of the display panel 100.
As for the third function, the scan control circuit 52 generates a group selection signal Gs having the same phase as the clock signal CLX in the horizontal effective display period, for example, as shown in FIG.

On the other hand, the display panel 100 has a configuration in which an element substrate and a counter substrate on which a common electrode is formed are bonded together with a sealing material with a certain gap, and liquid crystal is sealed in the gap. A predetermined image is formed by the change.

FIG. 2 is a block diagram showing the configuration of the display panel 100. As shown in FIG.
As shown in this figure, in this display panel 100, 864 rows of scanning lines 112 extend in the X (horizontal) direction in the figure, while 1152 columns of data lines 114 extend in the Y (vertical) direction in the figure. Exist. Pixels 110 are provided so as to correspond to the intersections between the scanning lines 112 and the data lines 114. Therefore, in this embodiment, the pixels 110 are arranged in a matrix of 864 rows × 1152 columns in the display region 100a, but the present invention is not limited to this.
In this embodiment, 1152 columns of data lines 114 are divided into blocks every four columns. Therefore, for convenience of explanation, the first, second, third, fourth,..., 287, and 288th blocks from the left are denoted as B1, B2, B3, B4,.

FIG. 3 is a diagram showing a detailed configuration of the pixel 110 in the display panel 100, corresponding to the intersection of the i row and the (i + 1) row adjacent thereto, the j column and the (j + 1) column adjacent thereto. A 2 × 2 configuration for a total of four pixels is shown. Here, i and (i + 1) are symbols for generally indicating the row in which the pixels 110 are arranged, and are integers of 1 to 864, and j, (j
+1) is a symbol for generally indicating a column in which the pixels 110 are arranged.
The following integers.
As shown in FIG. 3, in the pixel 110, the source of an n-channel TFT (thin film transistor) 116 is connected to the data line 114 and the drain is connected to the pixel electrode 11.
8, while the gate is connected to the scanning line 112.
Further, the common electrode 108 is provided in common to all the pixels so as to face the pixel electrode 118 formed on the element substrate. A TN liquid crystal 105 is sandwiched between the pixel electrode 118 and the common electrode 108. For this reason, a liquid crystal capacitor 120 including the pixel electrode 118, the common electrode 108, and the liquid crystal 105 is formed for each pixel.
Note that a voltage LCcom that is constant in time is applied to the common electrode 108.
In this embodiment, the potential is the same as the reference voltage Vc. However, for reasons described below,
There is a case where it is set slightly lower than the reference voltage Vc.

Although not shown in particular, the opposing surfaces of both substrates are respectively provided with alignment films that have been rubbed so that the major axis direction of the liquid crystal molecules is continuously twisted between the substrates by, for example, about 90 degrees. A polarizer corresponding to the orientation direction is provided on each back side of the substrate.
If the voltage effective value applied to the liquid crystal capacitor 120 is zero, the light passing between the pixel electrode 118 and the common electrode 108 rotates about 90 degrees along the twist of the liquid crystal molecules, while the voltage effective value As is increased, the liquid crystal molecules are tilted in the direction of the electric field, and as a result, their optical rotation disappears. For this reason, for example, in the transmission type, when the polarizers are respectively arranged on the incident side and the back side so that the polarization axis coincides with the alignment direction, the light transmittance is maximum if the voltage effective value is close to zero. On the other hand, while the white display is obtained, the amount of transmitted light decreases as the effective voltage value increases, and finally the black display with the minimum transmittance is obtained (normally white mode).

In addition, in order to reduce the influence of charge leakage from the liquid crystal capacitor 120 via the TFT 116 at the off time, the storage capacitor 109 is formed for each pixel. One end of the storage capacitor 109 is connected to the pixel electrode 118 (the drain of the TFT 116), while the other end is commonly connected to the capacitor line 107 over all pixels. Although not shown in FIG. 2, the capacitor line 107 is maintained at the same voltage LCcom as the common electrode 108 in the present embodiment.
Specifically, although the capacitor line 107 is formed on the element substrate and the common electrode 108 is formed on the counter substrate, the capacitor line 107 and the common electrode 108 are electrically connected by a conductive material (not shown). ing. Therefore, the pixel electrode 118 (the drain of the TFT 116) and the common electrode 108
Is a configuration in which a liquid crystal capacitor 120 and a storage capacitor 109 are added in parallel for each pixel 110.
Note that as long as the potential of the capacitor line 107 is constant in time, it may not be LCcom, and may be, for example, the ground potential Gnd.
Further, the TFT 116 in the pixel 110 is formed by a common manufacturing process with a scanning line driving circuit 130, a sampling signal output circuit 140, a sampling circuit 150, and the like, which will be described below, and contributes to downsizing and cost reduction of the entire device. is doing.

In FIG. 2, around the display area 100a in which the pixels 110 are arranged, a scanning line driving circuit 1 is provided.
30 and a peripheral circuit such as a sampling signal output circuit 140 are provided.
Among these, the scanning line driving circuit 130 supplies the scanning signals G1, G2, G3,..., G864 to the scanning lines 112 in the first row, the second row, the third row,. is there.
The details of the scanning line driving circuit 130 are omitted because they are not directly related to the present invention. For example, as shown in FIG. 5, the scanning line driving circuit 130 is supplied at the beginning of each vertical effective display period, and the half period of the clock signal CLY. A transfer start pulse DY having a corresponding pulse width (H level) is captured at the timing when the ethical level of the clock signal CLY transitions, and this is used as the scanning signal G1, and the scanning signal G1 is half of the clock signal CLY. In this configuration, the signals are sequentially delayed and output as scanning signals G2, G3,..., G864.
In the present embodiment, the horizontal scanning period is divided into a vertical blanking period and a vertical effective display period following the blanking period. Here, as shown in FIG. 5, the vertical effective display period is a period from the timing when the scanning signal G1 becomes H level to the timing when the scanning signal G864 returns to L level, and the vertical effective display period is included in the vertical effective period. The period excluding the display period is defined as the vertical blanking period.

Next, as shown in FIG. 5, the sampling signal output circuit 140 is supplied at the beginning of each horizontal effective display period and has a transfer start pulse having a pulse width (H level) corresponding to one cycle of the clock signal CLX. DX is captured at the timing when the clock signal CLX becomes H level, and this is used as the sampling signal S1, and the sampling signal S1 is sequentially delayed by half a cycle of the clock signal CLX to obtain the sampling signals S2, S3, …,
It is configured to output as S288. For this reason, among the sampling signals S1, S2, S3,..., S288 in the present embodiment, the portions that are adjacent to each other are output in an overlapping manner.
In the present embodiment, the horizontal scanning period is divided into a horizontal blanking period and a horizontal effective display period following the blanking period. Here, as shown in FIG. 7, the horizontal effective display period starts from the timing at which the sampling signal S1 changes from L to H level.
A period from the time when 88 changes from H to L level is defined as a period during which the horizontal effective display period is excluded from the horizontal scanning period.

On the other hand, the selection circuit 170 receives the 4-channel data signal Vid supplied from the processing circuit 50.
The demultiplexer distributes 1 to Vid4 to the group a for each channel if the group selection signal Gs is H level, and to the group b for each channel if the group selection signal Gs is L level.

Here, FIG. 4A is a diagram showing a detailed configuration of the selection circuit 170.
As shown in this figure, the path of each channel in the data signals Vid1 to Vid4 is branched into two groups, group a and group b. Among these, the path branched into the group a is the image signal line 18 via the transmission gate 174 for each channel.
At 0, the data signals Vid1 to Vid4 are output as Vid1a to Vid4a. On the other hand, the path branched into the group b reaches the image signal line 180 via the transmission gate 176 for each channel, and the data signals Vid1 to Vid4 are V
Output as id1b to Vid4b.

Each of the transmission gates 174 and 176 has a configuration in which n-channel and p-channel TFTs are combined. Among these, the group selection signal Gs is supplied to the gate of the n-channel TFT in the transmission gate 174, while p A signal obtained by logically inverting the group selection signal Gs by the NOT circuit 172 is supplied to the gate of the channel type TFT. On the other hand, the n-channel TF in the transmission gate 176
A signal obtained by logically inverting the group selection signal Gs by the NOT circuit 172 is supplied to the gate of T, while the group selection signal Gs is supplied to the gate of the p-channel TFT.

Here, the eight image signal lines 180 are wires arranged on the display panel 100 so as to be arranged at the same pitch and to have the same length. For this reason, as shown in FIG. 2, the capacitance Cs is evenly parasitic on the eight image signal lines 180.

Next, the sampling circuit 150 is an aggregate of sampling switches 151 provided corresponding to each of the data lines 114. Each sampling switch 151 is, for example, an n-channel TFT, and its drain is connected to the data line 114.
Here, the sampling signals corresponding to the blocks are commonly supplied to the gates of the four sampling switches 151 corresponding to the data lines 114 belonging to the same block. For example, the sampling signal S4 corresponding to the block B4 is commonly supplied to the gates of the four sampling switches 151 corresponding to the data lines 114 in the 13th to 16th columns belonging to the block B4.

The source of the sampling switch 151 has data signals Vid1a to Vd as follows.
It is connected to one of the eight image signal lines 180 to which id4a and Vid1b to Vid4b are supplied.
That is, in the sampling switch 151 in which the drain is connected to one end of the j-th data line 114 counted from the left in FIG. 2, the j-th data line 114 has an odd block (B1,.
B3, B5,..., B287) and the remainder of dividing j by 4 is “1”.
The source is connected to the image signal line 180 to which the data signal Vid1a is supplied. Similarly, the drain is connected to the data line 114 whose remainders obtained by dividing j by 4 are “2”, “3”, and “0”. The source of the sampling switch 151 is the data signals Vid2a and Vid3
a and Vid4a are connected to the supplied image signal line 180, respectively, while the data line 114 in the jth column belongs to an even block (B2, B4, B6,..., B288), and j is divided by 4 If the remainder is “1”, the source is connected to the image signal line 180 to which the data signal Vid1b is supplied, and similarly, the remainder obtained by dividing j by 4 is “2”, “3”, “0”. The sampling switch 151 whose drain is connected to the data line 114 is connected to the image signal line 180 to which the data signals Vid2b, Vid3b, and Vid4b are supplied.

For example, in FIG. 2, the source of the sampling switch 151 whose drain is connected to the data line 114 in the eleventh column is that the data line 114 in the eleventh column belongs to an odd block, and “
Since the remainder of dividing “11” by 4 is “3”, it is connected to the third image signal line 180 to which the data signal Vid3a is supplied. In addition, for example, in FIG.
The source of the sampling switch 151 whose drain is connected to the data line 1 is the 14th column data line 1
14 belongs to the even block, and the remainder obtained by dividing “14” by 4 is “2”, so that it is connected to the sixth image signal line 180 to which the data signal Vid2b is supplied.

In such a sampling circuit 150, when a certain sampling signal becomes H level, the four sampling switches 15 belonging to the block corresponding to the sampling signal.
1 are simultaneously turned on, and the data signals Vid1a to Vid supplied to the image signal line 180
4a or data signals Vid1b to Vid4b are simultaneously sampled on four columns of data lines 114 belonging to the block.

Next, the operation of the electro-optical device 10 will be described.
First, the transfer start pulse DY is supplied to the scanning line driving circuit 130 at the beginning of one vertical scanning effective display period. By this supply, as shown in FIG. 5, the scanning signals G1, G2, G
3,..., G864 are sequentially and exclusively H level for each horizontal scanning period.
First, the horizontal effective display period in which the scanning signal G1 is at the H level will be described. In this horizontal effective display period, writing is performed with positive polarity.
In this horizontal effective display period, as shown in FIG. 6, first, image data Vin corresponding to the pixels 110 in the first row, the first column, the first row, the second column, the first row, the third column, and the first row, the fourth column, ie, the selection The image data Vin of the pixel 110 corresponding to the intersection of the scanning line 112 in the first row and the data line 114 belonging to the block B1 is sequentially supplied from the host device. This image data is S /
Latched and expanded by a factor of 4 on the time axis by the P conversion circuit 320,
Image data Vd1 to Vd over a period corresponding to the dot clock Dclk in the fourth to seventh columns.
4 is converted into an analog signal by the D / A conversion circuit group 330, and further converted into a positive voltage on the higher side by a voltage specified with the voltage Vc as a reference by the polarity inversion circuit 340, and the data signal Vid1 to Vid4 are supplied to the display panel 100.
On the other hand, the group selection signal Gs is at the H level over a period corresponding to the fourth to seventh columns of dot clocks Dclk expanded four times. Therefore, in the display panel 100, since the selection circuit 170 selects the image signal line 180 of the group a, the data signals Vid1 to Vid.
4 is supplied to the first to fourth image signal lines 180 as data signals Vid1a to Vid4b.

Next, the image data V corresponding to the pixels 110 in the first row, the fifth column, the first row, the sixth column, the first row, the seventh column, and the first row, the eighth column.
in, that is, the selected scanning line 112 of the first row and the data line 1 belonging to the block B2
The image data Vin of the pixel 110 corresponding to the intersection with 14 is sequentially supplied from the host device. Similarly, this image data is expanded four times on the time axis to become image data Vd1 to Vd4 over a period corresponding to the dot clock Dclk in the 8th to 11th columns, and the positive polarity on the higher side by the specified voltage. Voltage data signals Vid1 to Vid4 are supplied to the display panel 100, respectively.
On the other hand, the group selection signal Gs becomes L level over a period corresponding to the dot clocks Dclk in the 8th to 11th columns expanded four times. Therefore, in the display panel 100, since the selection circuit 170 selects the image signal line 180 of the group b, the data signals Vid1 to Vi
d4 is supplied to the fifth to eighth image signal lines 180 as data signals Vid1b to Vid4b.

For this reason, the image signal lines 180 of the group a are electrically disconnected from the processing circuit 50 by the selection circuit 170, but the data signals Vid1a to Vid4a immediately before being electrically disconnected by the capacitor Cs, that is, 1 row 1 Each of the pixels 110 is held at a positive voltage that specifies the gradation of the pixels 110 in the first column to the first row and the fourth column.
Accordingly, the first to fourth image signal lines 180 belonging to the group a are positive electrodes that specify the gradation of the pixels 110 in the first row, first column to first row, fourth column over a period corresponding to the dot clock Dclk in the fourth to seventh columns. Since the positive voltage is supplied and then held at the positive voltage for a period corresponding to the dot clocks Dclk in the eighth to eleventh columns, it is apparently expanded eight times on the time axis.

Subsequently, the image data Vin corresponding to the pixels 110 in the first row, the ninth column, the first row, the tenth column, the first row, the eleventh column, and the first row, the 12th column, that is, the scanning line 112 in the first row to be selected and the block B3 Image data Vin corresponding to the pixel 110 corresponding to the intersection with the data line 114 is sequentially supplied from the host device. Similarly, this image data is expanded by 4 times on the time axis,
The image data Vd1 through the period corresponding to the dot clock Dclk in the 12th to 15th columns.
Vd4, and data signals Vid1 to Vid4 having a positive voltage on the higher side by the specified voltage.
Are supplied to the display panel 100 respectively.
On the other hand, the group selection signal Gs becomes H level again over a period corresponding to the dot clocks Dclk in the 12th to 15th columns expanded four times. Therefore, in the display panel 100, since the selection circuit 170 selects the image signal line 180 of the group a, the data signal Vid1
˜Vid4 are the first to fourth image signal lines 180 as the data signals Vid1a to Vid4a.
To be supplied.
Therefore, the image signal lines 180 of the group b are electrically disconnected from the processing circuit 50 by the selection circuit 170, but the data signals Vid1b to Vid4b immediately before being electrically disconnected by the capacitor Cs, that is, one row 5 The positive voltages specifying the gradations of the pixels 110 in the first column to the first row and the eighth column are respectively held.
Therefore, the fifth to eighth image signal lines 180 belonging to the group b are positive electrodes that specify the gradation of the pixels 110 in the first row, the fifth column to the first row, and the eighth column over a period corresponding to the dot clock Dclk in the eighth to eleventh columns. Since the positive voltage is supplied and then held at the positive voltage for a period corresponding to the dot clocks Dclk in the 12th to 15th columns, it is apparently expanded eight times on the time axis.

Similarly, every time image data Vin corresponding to an even block and image data Vin corresponding to an odd block are supplied in the first row, the logic level of the group selection signal Gs is inverted, and the group data The selection of the image signal line 180 for a and the image signal line 180 for group b is alternately switched.
As a result, as shown in FIG. 6, the image data Vin corresponding to the odd-numbered block is expanded four times in time, and then the data signals Vid1a to Vi are applied to the image signal lines 180 of the group a.
As a result, d4a is supplied in a form expanded by 8 times in time, while the image data Vin corresponding to the even block following the odd block is expanded by 4 times in time, Data signals Vid1b to Vid4b are supplied to the image signal line 180 after being delayed by four periods of the dot clock Dclk (that is, for four pixels), and as a result expanded in time by eight times.

In this way, the data signal V supplied to the eight image signal lines 180 and holding the voltage is supplied.
id1a to Vid4a and Vid1b to Vid4b are connected to the data line 11 as follows.
4 is sampled respectively.
That is, the sampling signal S1 during a period in which the data signals Vid1a to Vid4a corresponding to the pixels 110 in the first row and the first column to the first row and the fourth column corresponding to the block B1 are supplied to and held in the first to fourth image signal lines 180. Becomes H level. When the sampling signal S1 becomes H level, the sampling switches 151 in the first to fourth columns belonging to the block B1 are turned on at the same time, so that the data signal Vid1a supplied to the image signal line 180 is the data line 1 in the first column.
14 and the data signals Vid2a to Vid4a are similarly sampled on the data lines 114 in the second to fourth columns.
Since the scanning signal G1 is at the H level, all the TFTs 116 whose gates are connected to the scanning line 112 in the first row are turned on. For this reason, for example, the data signal Vid1a sampled on the data line 114 in the first column is at the intersection of the scanning line 112 in the first row counted from the top and the data line 114 in the first column counted from the left in FIG. Pixel electrode 118 of the corresponding pixel in the first row and the first column
Will be applied. Similarly for the data signals Vid2a to Vid4a sampled on the data lines 114 in the second to fourth columns, the pixel electrodes 1 of the pixels in the first row and the second column to the first row and the fourth column.
18 is applied.

On the other hand, during the period in which the data signals Vid1b to Vid4b corresponding to the pixels 110 in the first row and the fifth column to the first row and the eighth column corresponding to the block B2 are supplied to and held in the fifth to eighth image signal lines 180, the sampling signal S2 Becomes H level. Note that the first half of the period in which the sampling signal S2 is at the H level coincides with the latter half of the period in which the sampling signal S1 is at the H level.
When the sampling signal S2 becomes H level, the sampling switches 151 in the fifth to eighth columns belonging to the block B2 are turned on at the same time. Therefore, the data signal Vid1b supplied to the image signal line 180 is sampled on the data line 114 in the fifth column. Similarly, the data signal Vid2
b to Vid4b are sampled on the data lines 114 in the sixth to eighth columns.
Since all TFTs 116 whose gates are connected to the scanning line 112 in the first row are on, the data signal Vid1b sampled in the data line 114 in the fifth column is counted from the top in FIG. Is applied to the pixel electrode 118 of the pixel in the first row and the fifth column corresponding to the intersection of the scanning line 112 and the data line 114 in the fifth column from the left. Similarly, the data signals Vid2b to Vid4b sampled on the data lines 114 in the sixth to eighth columns are applied to the pixel electrodes 118 of the pixels in the first row and the fifth column to the first row and the eighth column.

In the same manner, the sampling signals S3, S4,..., S288 are sequentially set to the H level while the latter half period in which the sampling signal with the younger number is output coincides with the first half period in which the subsequent sampling signal is output. Become.
Here, during the period when the sampling signal with the odd number is at the H level, the data signals Vid1a to Vid4a corresponding to the odd blocks with the same number are the first to fourth image signal lines 180.
Therefore, the data signals Vid1a to Vid4a are sampled on the four columns of data lines 114 belonging to the odd-numbered block, respectively, to the scanning line 112 in the first row and the odd-numbered block. It is applied to the pixel electrode 118 of the pixel corresponding to the intersection with the four data lines 114 to which it belongs.
On the other hand, the period in which the even numbered sampling signal is at the H level is a period in which the data signals Vid1b to Vid4b corresponding to the same even block as the number are supplied and held in the fifth to eighth image signal lines 180. Therefore, the data signals Vid1b to Vid4b are sampled on the four columns of data lines 114 belonging to the even-numbered blocks, respectively, and cross the first row scanning lines 112 and the four columns of data lines 114 belonging to the even-numbered blocks. The voltage is applied to the pixel electrode 118 of the corresponding pixel.
As a result, a voltage data signal is drawn for all the pixels in the first row in accordance with the gradation specified by the image data Vin.

Even if the scanning signal G1 becomes L level and all of the TFTs 116 in the first row are turned off, the positive voltage written in the pixel electrode 118 is not stored in the pixel capacitance or accumulated until the scanning signal G1 becomes H level again. It is held by the capacitor 109.

Since the image data Vin is not supplied in the horizontal blanking period, which is the horizontal effective display period in which the scanning signal G2 is at the H level, the S / P conversion circuit 320 designates all the image data Vd1 to Vd4 to be blackened. Replace with the data you want. Further, since the writing polarity changes from positive polarity to negative polarity during this horizontal blanking period, for example, the data signal Vid1a has a positive voltage Vb (+ that designates the black color of the pixel as shown in FIG. ) To a voltage Vb (−) that is negative and specifies the black color of the pixel.
In addition, referring to the voltage of the data signal Vid in FIG. 7, the voltages Vb (+) and Vw (+)
, Vg (+), when applied to the pixel electrode 118, the pixel is set to the lowest gradation black,
The positive voltage is white, black, and gray having an intermediate gray level of the highest gray level, and the voltage range is included in the range of the voltage Vc and the higher power supply voltage Vdd.
The voltages Vb (−), Vw (−), and Vg (−) are negative voltages that cause the pixel to be black, white, and gray, respectively, when applied to the pixel electrode 118, and each of the voltages Vb. (+), Vw (+)
, Vg (+) are symmetrical with respect to the reference voltage Vc.

In the present embodiment, as described above, since polarity inversion is performed in units of scanning lines, the scanning signal G
In the horizontal effective display period in which 2 is at the H level, the data signals Vid1a to Vid4a and Vid1b to Vid4b are negative. For this reason, the data signals Vid1 to Vid4 output from the polarity inverting circuit 340 are set to lower voltages by the voltage specified by the image data Vin with reference to the voltage Vc. FIG. 7 illustrates the voltage waveform of the data signal Vid1 among them.

In FIG. 7, the data signal Vid <b> 1 is selected by the selection circuit 170.
In addition, a state is shown in which the voltage is held by the capacitor Cs parasitic to the image signal line 180 while being distributed to Vid1b and Vid1b.
Further, in the latter half period in which the sampling signal S288 is at the H level, the data signals Vid1 to Vid4 supplied from the processing circuit 50 and the image signal line 180 belonging to the group b in the first half period in which the sampling signal S1 is at the H level. The supplied data signals Vid1b to Vid4b are not shown in FIG. 7 because the voltages are uncertain.
Other operations are the same as those in the one horizontal scanning period in which the immediately preceding scanning signal G1 is at the H level, whereby the writing of the negative voltage data signal to the pixel 110 located in the second row is completed. It will be.

In the same manner, the scanning signals G3, G4,...
Writing is performed to the pixels in the row,. As a result, positive polarity writing is performed for the pixels in the odd-numbered rows, while negative polarity writing is performed for the pixels in the even-numbered rows. In this one vertical scanning period, the pixels in the first to 864th rows are written. Writing will be completed for all of the above.
In the next one vertical scanning period, similar writing is performed. At this time, the writing polarity for the pixels in each row is switched. That is, in the next one vertical scanning period, the negative polarity signal is written to the odd-numbered pixels, while the positive polarity signal is written to the even-numbered pixels. In this way, since the writing polarity for the pixels is switched every vertical scanning period, a direct current component is not applied to the liquid crystal 105, and deterioration of the liquid crystal 105 is prevented.

Thus, according to the present embodiment, the data signals Vid1 to Vid1 supplied from the processing circuit 50 are displayed.
Vid4 is doubled by the distribution by the selection circuit 170 and the voltage holding property of the capacitance Cs parasitic to the image signal line 180. For this reason, the period for sampling the data signal supplied to the image signal line 180 to the data line 114 should be twice as long as the period expanded four times the time axis by the S / P conversion circuit 320. Can do.
Therefore, according to the present embodiment, it is possible to secure a longer double period for sampling the data signal on the data line while keeping the expansion of the time axis in the S / P conversion circuit 320 constant at four times. Become.

In the above-described embodiment, the voltage is held by the capacitance Cs parasitic to the image signal line 180. However, since the image signal line 180 is likely to vary with the parasitic capacitance alone, the image signal line 180 has one end. May be used together with the parasitic capacitance by positively providing a capacitor with the other end connected to the potential Gnd in common. Note that in the case where a capacitor is provided separately, it is preferable to form part of the manufacturing process of the TFT 116 as in the case of the storage capacitor 109.
Further, in the case where a capacitor is separately provided in this way, it is sufficient that the other end of the capacitor is kept at a constant potential with respect to time. Therefore, for example, Vdd of the power source may be used instead of the ground potential Gnd.

In the embodiment, the selection circuit 170 is configured as shown in FIG. In this configuration, a group selection signal Gs and an inverted signal of the group selection signal Gs are supplied to the transmission gates 174 and 176. The group selection signal Gs is supplied to the transmission gates 174 and 176 through the NOT circuit 172. Since the phase of the inverted signal of Gs is delayed, it is assumed that the transmission gates 174 and 176 are not ideally turned on / off.
Therefore, as shown in FIG. 4B, the NOT circuit 172 is a phase compensation type in which the group selection signal Gs and its inverted signal are connected to each other and the phases of both signals are aligned. It is good also as a structure.

In the embodiment, the data signal selected by the selection circuit 170 is directly used as the image signal line 18.
However, as shown in FIG. 8, an amplifier circuit 190 may be provided between the output terminal of the selection circuit 170 and the image signal line 180, respectively.
For example, as shown in FIG. 9, one amplifier circuit 190 includes a p-channel TFT 192 and an n-channel TFT 194 whose characteristics are complementary to each other.
The source of 2 is connected to a power supply line for supplying the power supply voltage Vdd, while the source of the TFT 194 is grounded to the potential Gnd. The gates of the TFTs 192 and 194 are commonly connected to the output terminal of the selection circuit 170, respectively, while the drains of the TFTs 192 and 194 are commonly connected to the image signal line 180, respectively.

For this reason, the amplifier circuit 190 is based on Vc, which is an intermediate value of the voltage (Vdd−Gnd).
A voltage obtained by inverting the voltage of the data signal selected by the selection circuit 170 is the image signal line 180.
It is the composition that appears in.
Here, the capacitance Cg is parasitic on the gates of the TFTs 192 and 194 as indicated by broken lines in FIG. Therefore, even if the selection circuit 170 is electrically disconnected from the processing circuit 50, the gates of the TFTs 1562 and 1564 are held at the voltage immediately before being electrically disconnected by the capacitor Cg. The inverted voltage of the data signal is continuously applied to the image signal line 180.

When the amplifier circuit 190 is provided in each image signal line 180 in this way, the data signal Vid1a˜
When the voltages of Vid4a and Vid1b to Vid4b are applied to the image signal line 180, the influence of the capacitance Cs can be reduced.
That is, the data signal selected by the selection circuit 170 is only applied to the portion up to the common gate of the TFTs 192 and 194 in the amplification circuit 190, and therefore the capacitor Cs parasitic on the image signal line 180 is charged and discharged. There is an advantage that the output impedance of the data signals Vid <b> 1 to Vid <b> 4 in the processing circuit 50 may be higher than the configuration of FIG.
In the amplifier circuit 190, a voltage obtained by inverting the voltage of the data signal selected by the selection circuit 170 with respect to Vc appears on the image signal line 180. However, the voltage of the data signal is constant. A voltage obtained by inverting the voltage multiplied by the coefficient with respect to Vc may appear on the image signal line 180.

In the embodiment, the number of phase expansion is set to “4”. However, even if the phase expansion is not performed, the data signal supplied to the image signal line 180 is distributed to the data line by distribution by the selection circuit 170 as in the phase expansion. The effect of extending the sampling period can be obtained.
In the embodiment, the selection circuit 170 receives the data signal Vid1 supplied from the processing circuit 50.
Although the number of distributing Vid4 is set to “2”, the present invention may be distributed to three or more.
Here, when the number of phase expansions is m (m is an integer of 1 or more) and the number of distributions is n (n is an integer of 2 or more), the number of image signal lines 180 is m × n, and the image signal lines 180 The period for sampling the data signal supplied to the data line can be ensured by m × n times as compared with the dot sequential method.

In embodiments, the drain voltage LCcom applied to the common electrode 108, had to match the potential V _C is a measure of the polarity inversion, due to the parasitic capacitance between the gate and drain of the TFT, when turned from on to off A phenomenon in which the potential of the (pixel electrode 118) decreases (referred to as push-down, penetration, field-through, etc.) occurs. In order to prevent deterioration of the liquid crystal, the liquid crystal capacitor 120 is basically driven by alternating current, and therefore, the same gradation is alternately written on the common electrode 108 on the higher side (positive polarity) and the lower side (negative polarity). , in a state of being matched voltage LCcom the voltage V _C, when the alternating writing, for pushdown, effective voltage of the liquid crystal capacitor 120 towards the negative writing is larger than the positive polarity writing End up. For this reason, the voltage LCcom of the common electrode 108 is the voltage V _C that is the amplitude reference of the data signal so that the effective voltage values of the liquid crystal capacitor 120 are equal to each other even when positive polarity / negative polarity writing is performed at the same gradation. May be set slightly lower.

In the embodiment, the vertical scanning direction is the downward direction of G1 → G864 and the horizontal scanning direction is the right direction of S1 → S1152. However, in order to cope with the case of a projector or a rotatable display device described later. In addition, the scanning direction may be switched.
Furthermore, instead of the normally white mode in which white display is performed when the voltage effective value of the liquid crystal capacitor 120 is small, a normally black mode in which black display is performed may be used.

In the above-described embodiment, the TN type is used as the liquid crystal, but the STN type, BTN (Bi-stable) is used.
Twisted Nematic) and ferroelectric types such as bistable types with memory properties, polymer dispersed types, and dyes that have anisotropy in visible light absorption in the major and minor axis directions of molecules ( Guest) is dissolved in a liquid crystal (host) with a certain molecular arrangement, and dye molecules are aligned parallel to the liquid crystal molecules.
A liquid crystal such as an H (guest host) type may be used.
In addition, the liquid crystal molecules are arranged in a vertical direction with respect to both substrates when no voltage is applied, while the liquid crystal molecules are arranged in a horizontal direction with respect to both substrates when a voltage is applied. The liquid crystal molecules are aligned in the horizontal direction with respect to both substrates when no voltage is applied, while the liquid crystal molecules are aligned in the vertical direction with respect to both substrates when a voltage is applied. It is good also as a structure.
Further, in the present invention, the electro-optical material is not limited to liquid crystal, and thus, the present invention can be applied to various liquid crystal and alignment methods.
The liquid crystal device has been described so far. In the present invention, image data (video signal) is used.
Is supplied via the image signal line 180 and is sampled on the data line 114, for example, an apparatus using an EL (Electronic Luminescence) element, an electron emitting element, an electrophoretic element, a digital mirror element, It can also be applied to plasma displays.

Next, as an example of an electronic apparatus using the electro-optical device according to the above-described embodiment, a projector using the above-described display panel 100 as a light valve will be described.
FIG. 10 is a plan view showing the configuration of the projector. As shown in this figure, a projector 2100 has a lamp unit 21 formed of a white light source such as a halogen lamp.
02 is provided. The projection light emitted from the lamp unit 2102 is R (by the three mirrors 2106 and two dichroic mirrors 2108 arranged inside.
The light valve 100 is divided into three primary colors of red, G (green), and B (blue), and corresponds to each primary color.
Guided to R, 100G and 100B, respectively. Note that B light has a longer optical path than other R and G colors, and therefore, in order to prevent the loss, B light passes through a relay lens system 2121 including an incident lens 2122, a relay lens 2123, and an exit lens 2124. Led.

Here, the configuration of the light valves 100R, 100G, and 100B is the same as that of the display panel 100 in the above-described embodiment, and R supplied from the processing circuit (not shown in FIG. 10).
, G, and B are driven by image signals corresponding to the respective colors. In other words, the projector 2100 has a configuration in which three sets of electro-optical devices including the display panel 100 are provided corresponding to the R, G, and B colors.
The lights modulated by the light valves 100R, 100G, and 100B are incident on the dichroic prism 2112 from three directions. In the dichroic prism 2112, the R and B light beams are refracted at 90 degrees, while the G light beam travels straight.
Therefore, after the images of the respective colors are combined, the projection lens 2114 is displayed on the screen 2120.
As a result, a color image is projected.

The light valves 100R, 100G, and 100B include a dichroic mirror 2
Since light corresponding to the primary colors of R, G, and B is incident by 108, there is no need to provide a color filter. Further, the transmission images of the light valves 100R and 100B are projected after being reflected by the dichroic mirror 2112, whereas the transmission image of the light valve 100G is projected as it is, so the horizontal scanning direction by the light valves 100R and 100B is The image is reversed in the horizontal scanning direction by the light valve 100G and displayed in an inverted image.

In addition to the electronic device described with reference to FIG. 10, the electronic device includes a television, a viewfinder type / monitor direct view type video tape recorder, a car navigation device, a pager, an electronic notebook, a calculator, a word processor, a workstation, a television. Examples include a telephone, a POS terminal, a digital still camera, a mobile phone, and a device equipped with a touch panel. Needless to say, the above-described electro-optical device can be applied to these various electronic devices.

1 is a block diagram illustrating an overall configuration of an electro-optical device according to an embodiment of the invention. 3 is a diagram showing a configuration of a display panel in the same electro-optical device. FIG. It is a figure which shows the structure of the pixel in the same electro-optical apparatus. It is a figure which shows the structure of the selection circuit in the same electro-optical apparatus. FIG. 6 is a diagram for explaining an operation of the electro-optical device. FIG. 6 is a diagram for explaining an operation of the electro-optical device. FIG. 6 is a diagram for explaining an operation of the electro-optical device. It is a figure which shows another structure of the display panel. It is a figure which shows the amplifier circuit which concerns on another structure. 1 is a diagram illustrating a configuration of a projector to which an electro-optical device according to an embodiment is applied.

Explanation of symbols

DESCRIPTION OF SYMBOLS 50 ... Processing circuit, 100 ... Display panel, 105 ... Liquid crystal, 109 ... Storage capacity, 110 ... Pixel, 112 ... Scan line, 114 ... Data line, 116 ... TFT, 118 ... Pixel electrode, 120 ...
Liquid crystal capacitor, 130 ... Scanning line drive circuit, 140 ... Sampling signal output circuit, 150 ... Sampling circuit, 151 ... Sampling switch, 170 ... Selection circuit, 180 ... Image signal line, 190 ... Amplification circuit, 192, 194 ... TFT, 320 ... S / P conversion circuit, 2100 ... Projector

Claims (7)

A plurality of pixels provided corresponding to a plurality of scanning lines and a plurality of data lines blocked for m (m is an integer of 1 or more);
A scanning line driving circuit for selecting the plurality of scanning lines in a predetermined order;
It is classified into n (n is an integer of 2 or more) groups, and each group is m
M × n image signal lines each having a voltage holding property;
In addition to selecting groups in a predetermined order, m data signals having a voltage corresponding to the gray level of the pixel corresponding to the scanning line selected by the scanning line driving circuit belong to the selected group. A selection circuit that distributes to each of the image signal lines,
A sampling signal output circuit that outputs the sampling signal for selecting the blocks in a predetermined order in synchronization with the distribution by the selection circuit;
A sampling switch provided for each of the plurality of data lines,
A sampling switch that turns on the one corresponding to the block selected by the sampling signal and samples the data signal distributed to the image signal line to the data line;
An electro-optical device comprising: The electro-optical device according to claim 1, wherein each of the image signal lines has a parasitic capacitance, and has a voltage holding property due to the capacitance. The electro-optical device according to claim 1, wherein a capacitor is connected between the image signal line and a potential line having a constant potential, and the capacitor has a voltage holding property. Provided between each output terminal of the selection circuit and the image signal line, and holds the voltage of the data signal selected by the selection circuit, and the held voltage is an amplification factor based on a predetermined potential. An amplification circuit that amplifies the image signal and supplies it to the image signal line,
The electro-optical device according to claim 1, further comprising: The amplifier circuit is
n-channel and p-channel transistors are connected in series, and the data signal sampled by the sampling circuit is commonly input to the gates of both transistors, and the drains of both transistors are commonly connected to the data line. The electro-optical device according to claim 4, wherein the electro-optical device is provided. A plurality of pixels provided corresponding to a plurality of scanning lines and a plurality of data lines blocked for m (m is an integer of 1 or more);
It is classified into n (n is an integer of 2 or more) groups, and each group is m
M × n image signal lines each having a voltage holding property;
A driving method of an electro-optical device having:
Selecting the plurality of scanning lines in a predetermined order;
A group is selected in a predetermined order, and m-channel data signals having a voltage corresponding to the gradation of the pixel corresponding to the selected scanning line are distributed to m image signal lines belonging to the selected group. And
A sampling signal for selecting the blocks in a predetermined order is output in synchronization with the distribution by the selection circuit,
A method for driving an electro-optical device, wherein the data signal distributed to the image signal line is sampled on a data line corresponding to a block selected by the sampling signal. An electronic apparatus comprising the electro-optical device according to claim 1.

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