JP2007232871A - Electrooptical device, its driving circuit, and electronic apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To suppress a display quality from being degraded when a phase expansion driving system is employed. <P>SOLUTION: A period H wherein one row of scanning lines is selected is divided into a first period Sub1 and a second period Sub2 and while odd-numbered columns of data lines are selected three by three throughout the first period Sub1, even-numbered columns of data lines are selected three by three throughout the second period Sub2. Then a data signal supplied to an image signal line is sampled to selected three columns of data lines. At this time, shift operation by a first shift register is used in the first period Sub1 and shift operation by a second shift register is used in the second period Sub2. Consequently, pixels (denoted as [1]) where writing is performed between right and left adjacent pixels in columns after writing and pixels (denoted as [2]) where no writing is performed between right and left adjacent pixels in the columns after the writing alternately appear column by column. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

The present invention relates to a technique for making a deterioration in display quality caused when sampling a so-called phase expanded data signal inconspicuous.

In recent years, projectors that form a small reduced image by using a display panel such as a liquid crystal and enlarge and project the small reduced image by an optical system are becoming widespread. The projector does not have a function of creating an image by itself, and is supplied with image data (or an image signal) from a host device such as a personal computer or a TV tuner. This image data specifies the gradation (brightness) of the pixels, and is supplied in the form of vertical and horizontal scanning of the pixels arranged in a matrix, so that the display panel used in the projector is also this It is appropriate to drive according to the format. For this reason, in the display panel used for the projector, the scanning lines are selected by selecting the scanning lines one by one in a predetermined order and selecting the data lines by one column at a time during the period in which the scanning lines of one row are selected. In general, the data lines are driven in a dot sequential manner in which a data signal obtained by converting image data so as to be suitable for driving a liquid crystal is supplied.

On the other hand, recently, high definition of a display image is progressing like high vision. High definition of the display image can be achieved by increasing the number of scanning lines and the number of data lines, but since the frame frequency is fixed, an increase in the number of scanning lines results in one horizontal scanning period. Furthermore, in the dot sequential method, the data line selection period is shortened by increasing the number of data line columns. For this reason, in the dot sequential method, it becomes impossible to secure a sufficient time for supplying the data signal to the data line as the definition becomes higher, and writing to the pixels has started to be insufficient.
Therefore, a method called phase expansion drive has been devised for the purpose of eliminating the shortage of writing (see Patent Document 1). In this phase expansion drive, the data lines are grouped in predetermined columns, for example, every 3 columns (6 columns in Patent Document 1), and selected in a predetermined order by 3 columns in one horizontal scanning period. In this method, data signals expanded three times with respect to the time axis are supplied to the three data lines. In this phase development driving method, the time for supplying the data signal to the data line can be secured three times in this example as compared with the dot sequential method, so it was considered suitable for high definition. .
JP 2000-112437 A

By the way, in such a phase development drive method, vertical streak-like unevenness occurs in which the gradation of the pixels is slightly different in the period of every three columns selected at the same time, and the deterioration of the display quality is conspicuous. became.
The present invention has been made in view of the above-described circumstances, and an object of the present invention is to provide an electro-optical device, a driving circuit thereof, and an electronic apparatus in which deterioration in display quality is not noticeable when a phase expansion driving method is employed. Is to provide.

In order to achieve the above object, the present invention is provided corresponding to the intersection of a plurality of rows of scanning lines and a plurality of columns of data lines divided into 2m (m is an integer of 2 or more) columns. , Each of which is a driving circuit of an electro-optical device having a plurality of pixels having gradations according to a data signal sampled on the data line when the scanning line is selected, and scanning the plurality of rows A scanning line driving circuit that selects lines in a predetermined order and a period in which one scanning line is selected by the scanning line driving circuit are divided into a first period and a second period. A first shift register that sequentially outputs a predetermined pulse; a second shift register that sequentially outputs a predetermined pulse during the second period; and the block according to an output from the first shift register during the first period. No., out of 2m columns of data lines belonging to the specified block, m columns of odd or even columns are selected, and in accordance with the output from the second shift register in the second period Designate the blocks in order and supply them to a data line selection circuit that selects m columns of odd-numbered or even-numbered data lines out of 2m columns of data lines belonging to the designated block, and supplies them to m image signal lines And a sampling circuit that samples the data signals that have been selected to m columns of data lines selected by the data line selection circuit. According to the present invention, m columns of data lines from which data signals are simultaneously sampled are distributed in odd columns and even columns, so that the deterioration in display quality can be made inconspicuous.

In the present invention, the first shift register outputs a signal obtained by sequentially shifting the first pulse input at the start of the first period by a predetermined clock signal, and the second shift register
A signal obtained by sequentially shifting the second pulse input at the start of the second period with the clock signal is output, and the data line selection circuit sequentially shifts the blocks in accordance with a shift signal from the first and second shift registers. It may be configured to specify, or a predetermined input pulse,
A pulse selection circuit that supplies to the first shift register at the start of the first period, and supplies to the second shift register at the start of the second period, and the first and second shift registers are supplied A signal obtained by sequentially shifting an input pulse with a predetermined clock signal may be output, and the data line selection circuit may sequentially specify the blocks in accordance with a shift signal from the first and second shift registers.
In the present invention, the first and second shift registers output a pulse signal obtained by sequentially shifting a predetermined input pulse with a predetermined clock signal in correspondence with two or more of the blocks, and the data line selection circuit May include a logic circuit that makes the pulse signals output from the first and second shift registers be mutually exclusive in the two or more blocks by a logical operation with a predetermined enable signal. The first and second
The shift register sequentially shifts a predetermined input pulse with a predetermined clock signal, and outputs pulse signals whose pulse widths overlap each other between adjacent ones, and the data line selection circuit includes the first and second shifts. The pulse signal output from the register may be configured to have a logic circuit that makes the blocks corresponding to the pulse signal mutually exclusive by a logical operation with a predetermined enable signal.
In addition to the drive circuit of the electro-optical device, the present invention can be used as an electro-optical device,
It can also be conceptualized as an electronic device having an electro-optical device.

  Embodiments of the present invention will be described below with reference to the drawings.

<First Embodiment>
FIG. 1 is a block diagram showing the overall configuration of the electro-optical device according to the first embodiment of the invention. As shown in this figure, the electro-optical device 1 is roughly divided into a display panel 10 and a processing circuit 20. Among these, the processing circuit 20 is a circuit that controls the operation of the display panel 10 and the like.
A circuit module mounted on a printed circuit board, and the display panel 10 is an FPC (Flexib
le Printed Circuit) connected by a substrate or the like.

The processing circuit 20 further includes a scanning control circuit 52, a line memory 310, and an S / P conversion circuit 3.
20, a D / A conversion circuit group 330 and a polarity inversion circuit 340.
After one line of image data Vin supplied from a host device (not shown) is stored, it is read according to an instruction from the scanning control circuit 52 and output as image data Vout. Here, the image data Vin (Vout) is digital data for designating the gradation (brightness) of the pixel.
The S / P conversion circuit 320 converts the image data Vout read from the line memory 310 into
In accordance with an instruction from the scanning control circuit 52, the time axis is expanded three times (also referred to as phase expansion or serial-parallel conversion), and distributed to channels ch1 to ch3 according to the instruction and output as image data Vd1 to Vd3. Is.
In the present embodiment, when the precharge control signal Nrg is H level and precharge is designated, the S / P conversion circuit 320 has an image corresponding to, for example, black regardless of reading from the line memory 310. Data Vd1 to Vd3 are output.

The D / A conversion circuit group 330 is an aggregate of D / A converters provided for each channel,
The image data Vd1 to Vd3 are converted into analog voltages corresponding to the gradation values.
In the present embodiment, the image data Vin is subjected to analog conversion after phase expansion, but it is needless to say that analog conversion may be performed before phase expansion.

The polarity inversion circuit 340 converts the analog signal voltage of the D / A converted three-channel analog signal to a higher voltage with the voltage Vc as a reference when the positive polarity is instructed by the polarity instruction signal Pol. On the other hand, when the negative polarity is instructed, the voltage Vc is converted into a lower voltage and output as data signals Vid1 to Vid3, respectively.
The data signals Vid1 to Vid3 are supplied to the image signal lines in the display panel 10. The voltage Vc is the amplitude center potential of the data signal, is a reference for the writing polarity to the pixel, and is approximately an intermediate voltage of the power supply voltage (Vdd-Gnd) (see FIGS. 8 and 9 described later). .
In other words, in the present embodiment, for the data signal, the higher side than the voltage Vc has a positive polarity, and the lower side has a negative polarity. The voltage is based on the ground potential Gnd of the power supply unless otherwise specified.

The reason why the polarity of the data signal is inverted by the polarity inverting circuit 340 is to drive the pixel by alternating current. Here, as to how the pixels are inverted during the frame period (vertical scanning period), (a) every scanning line, (b) every data line, (c) every pixel, (d) surface (frame) Although there are various modes such as every frame, in the present embodiment, it is assumed that (d) polarity reversal for each frame. However, the present invention is not limited to this.

The scanning control circuit 52 includes a first function for controlling scanning of the display panel 10 and the line memory 3.
A second control for controlling reading of the image data Vin for one row stored in the memory 10 in accordance with the scan.
And a third function for controlling the phase expansion so as to synchronize with the horizontal scanning of the display panel 10 with respect to the S / P conversion circuit 320 described above.
Here, the first function will be described in detail. The scanning control circuit 52 generates transfer start pulses DX1 and DX2 and a clock signal CLX in synchronization with the supply of the image data Vin, and controls the horizontal scanning of the display panel 10. Along with the transfer start pulse DY and the clock signal CLY
To control the vertical scanning of the display panel 10. The scan control circuit 52 outputs a precharge control signal Nrg for precharging the data line at the start of the horizontal scan period in synchronization with the horizontal scan. As described above, in this embodiment, since polarity inversion is performed for each frame, the scanning control circuit 52 inverts and outputs the logic level of the polarity instruction signal Pol for each frame period.
Next, the second function will be described. The scanning control circuit 52 divides a horizontal scanning period for selecting one row of scanning lines into a first half period and a second half period as described in detail. Of the rows corresponding to the scanning lines selected in the horizontal scanning period, the image data corresponding to the pixels in the odd-numbered column is sequentially read in the first half period, while the image data corresponding to the pixels in the even-numbered column is sequentially read in the second half period. It has a configuration.
Next, the third function will be described. The scan control circuit 52 includes an S / P conversion circuit 320.
4 and 4 enable signals Enb1 to Enb4 are output so as to be synchronized with the phase expansion.

On the other hand, the display panel 10 has a configuration in which an element substrate and a counter substrate on which a common electrode is formed are bonded together with a sealing material with a certain gap, and for example, a TN liquid crystal is sealed in the gap. A predetermined image is formed by the electro-optic change of the liquid crystal.

FIG. 2 is a block diagram showing a detailed configuration of the display panel 10.
As shown in this figure, in the display area 100 of the display panel 10, 864 rows of scanning lines 112 extend in the X (horizontal) direction in the figure, while 1152 columns of data lines 114 are Y (vertical) in the figure. ) Extends in the direction. These scanning lines 112 and data lines 1
The pixels 110 are provided so as to correspond to the intersections with the pixels 14. Therefore, in this embodiment, the pixels 110 are arranged in a matrix of 864 rows × 1152 columns in the display region 100.
In this embodiment, 1152 columns of data lines 114 are divided into blocks every 6 columns in order from the left in the figure. Therefore, for convenience of explanation, the first, second, third,..., 192nd blocks are denoted as B1, B2, B3,.

FIG. 3 is a diagram showing a detailed configuration of the pixel 110 in the display panel 10 and corresponds to the intersection of the p row and the (p + 1) row adjacent thereto, the q column and the (q + 1) column adjacent thereto. A 2 × 2 configuration for a total of four pixels is shown. Here, p and (p + 1) are symbols for generally indicating the row in which the pixels 110 are arranged, and are integers of 1 to 864, and q, (
q + 1) is a symbol for generally indicating a column in which the pixels 110 are arranged.
It is an integer of 2 or less.

As shown in FIG. 3, in the pixel 110, the source of an n-channel TFT (thin film transistor) 116 is connected to the data line 114, and the drain thereof is connected to the pixel electrode 118, while the gate is the scanning line. 112.
On the other hand, the common electrode 108 is provided in common to all the pixels so as to face the pixel electrode 118 formed on the element substrate. A liquid crystal 105 is sandwiched between the pixel electrode 118 and the common electrode 108. For this reason, a liquid crystal capacitor 120 including the pixel electrode 118, the common electrode 108, and the liquid crystal 105 is formed for each pixel.
A constant voltage LCcom is applied to the common electrode 108 over time, and this voltage (potential)
Is the same as the reference voltage Vc in this embodiment. However, it may be set slightly lower than the reference voltage Vc for reasons described later.
Here, the liquid crystal capacitor 120 is configured such that the average amount of transmitted light per unit time changes according to the held voltage effective value. Specifically, the liquid crystal capacitor 120 is set to be in a normally white mode in which the amount of transmitted light increases as the effective value of the holding voltage decreases.

A storage capacitor 109 is provided for each pixel. The storage capacitor 109 is electrically connected in parallel with the liquid crystal capacitor 120, and the capacitor line maintained at the same voltage as the drain (pixel electrode 118) of the TFT 116 and a constant potential, for example, the applied voltage LCcom of the common electrode 108. 107
Between the two. In this example, the capacitor line 107 is maintained at the voltage LCcom, but may be maintained at the ground potential Gnd, for example.

Returning to FIG. 2, the scanning line driving circuit 130, the shift register group 140, the data line selection circuit 150, and the sampling circuit 16 are arranged around the display area 100 in which the pixels 110 are arranged.
Peripheral circuits such as 0 are provided.
Among these, the scanning line driving circuit 130 supplies the scanning signals G1, G2, G3,..., G864 to the scanning lines 112 in the 1, 2, 3,. The details of the scanning line driving circuit 130 are omitted because they are not directly related to the present invention, but in this embodiment, as shown in FIG. 6, the scanning line driving circuit 130 is supplied at the beginning of each frame period and the clock signal CLY.
The transfer start pulse DY having a pulse width (H level) corresponding to one cycle of the clock signal C
At the timing when the LY level transitions, the latter half is taken in the clock signal C.
The width of the half cycle of LY is reduced to a scanning signal G1, and this scanning signal G1 is
The clock signals CLY are sequentially delayed by half a cycle and output as scanning signals G2, G3,..., G864. Here, a period during which the scanning signals G1, G2, G3,..., G864 are at the H level (a period corresponding to a half cycle of the clock signal CLY) is the horizontal scanning period H, and the scanning signal at the H level is supplied. The scanning line to be selected is selected.

Next, the configuration of the shift register group 140 will be described with reference to FIG.
As shown in this figure, the shift register group 140 includes a first shift register 142 and a second shift register 144.
Among these, the first shift register 142 is “1” which is the total number of blocks in the present embodiment.
“96” stage, which is half of “92”, and, as shown in FIG.
The first stage of the transfer start pulse DX1 supplied at the beginning of the period Sub1 is the clock signal CL.
At the timing when the level of X transitions, this is taken as a shift signal S1,
The second, third,..., And 96th stages of the shift signal S1 are sequentially delayed by half a cycle of the clock signal CLX and output as odd shift signals S3, S5,.
Here, since the transfer start pulse DX1 has a pulse width corresponding to one cycle of the clock signal CLX, the pulse widths of the shift signals S1, S3, S5,. The signal CLX overlaps every half cycle.

Similarly to the first shift register 142, the second shift register 144 has “96} stages, and as shown in FIG. 7, the transfer supplied at the beginning of the second period Sub2 in the horizontal scanning period H. The start pulse DX2 is captured at the timing when the level of the clock signal CLX transitions in the first stage, and this is used as the shift signal S2.
The third,..., And 96th stages are sequentially delayed by half a cycle of the clock signal CLX and output as even shift signals S4, S6,.
Since the transfer start pulse DX2 also has a pulse width corresponding to one cycle of the clock signal CLX, like the transfer start pulse DX1, the shift signals S2, S4, S6,.
As for the pulse width of S192, the adjacent pulse widths overlap each other by a half cycle of the clock signal CLX.

Next, the configuration of the data line selection circuit 150 will be described with reference to FIG.
As shown in this figure, the shift signals S1, S2, S3, S4,..., S191, S19
The two supply paths are divided into two. Specifically, the shift signal S1 output from the first stage of the first shift register 142 and the shift signal S2 output from the first stage of the second shift register 144 correspond to the blocks B1 and B2. , Respectively. Generally speaking, the j-th in the first shift register 142 and the second shift register 144
Shift signals S (2j−1), S (2j) output from the stage (j is an integer from 1 to 96)
) Are each divided into two so as to correspond to the blocks B (2j-1) and B (2j). In other words, the block B (2j-1) includes shift signals S (2j-1), S (2j
) And shift signals S (2j-1) and S (2j) correspond to block B (2j) in the same manner.

A group of NAND circuits 1512 and 1514 and NOT circuits 1516 and 1518 are provided on the shift signal dividing path, respectively. Among these, the NAND circuit 1512 includes the divided shift signal supplied to one input terminal and the enable signals Enb1 to Enb1 supplied to the other input terminal.
The NAND circuit 1514 outputs a negative logical product signal of the negative logical product signal from the NAND circuit 1512 and a signal obtained by logically inverting the precharge control signal Nrg by the NOT circuit 1520. The NOT circuit 1516 is connected to the NAND circuit 15
14 is logically inverted, and the NOT circuit 1518 reinverts the logically inverted signal from the NOT circuit 1516.

Here, in the odd-numbered block B (2j-1), the output signal of the NOT circuit 1518, which is a group of final outputs obtained by processing the shift signal S (2j-1), is used as the sampling signal R (4j-3).
The output signal of the NOT circuit 1518, which is a group of final outputs obtained by processing the shift signal S (2j), is expressed as a sampling signal R (4j-2). Similarly, even block B (2j
), A NOT circuit 15 which is a group of final outputs obtained by processing the shift signal S (2j-1).
The output signal of 18 is expressed as a sampling signal R (4j-1), and the output signal of the NOT circuit 1518 which is a group of final outputs obtained by processing the shift signal S (2j) is the sampling signal R (4j
).
For example, since the odd block B3 has 3 = 2 × 2-1, j = 2, and the shift signals S3 and S4 from the second stage are supplied to the first group circuit of the block B3, and the sampling signal R5
(= 4 × 2-3) and R6 (= 4 × 2-2) correspond, and even block B192 is 1
Since 92 = 2 × 96, j = 96, and the shift signals S191 and S1 from the 96th stage are obtained.
92 is supplied to the first group circuit of the block B192 and the sampling signal R383 (= 4 × 9
6-1) and R384 (= 4 × 96) correspond.

Note that the shift signals S1, S3, S5,.
The following enable signal is supplied to the other input terminal of the NAND circuit 1512 to which 191 is supplied.
That is, the shift signal S (2) output from the j-th stage in the first shift register 142.
j-1) is supplied to the two paths so as to correspond to the blocks B (2j-1) and B (2j). If j is an odd number (1, 3, 5,..., 95), the block N corresponding to B (2j-1)
An enable signal Enb1 is supplied to the other input terminal of the AND circuit 1512, and the block B
The enable signal Enb2 is supplied to the other input terminal of the NAND circuit 1512 corresponding to (2j), and if j is an even number (2, 4, 6,..., 96), the block B (2j−1) )
The enable signal Enb3 is supplied to the other input terminal of the NAND circuit 1512 corresponding to, and the enable signal Enb4 is supplied to the other input terminal of the NAND circuit 1512 corresponding to the block B (2j).

On the other hand, the shift signals S2, S4, S6,.
The following enable signal is supplied to the other input terminal of the NAND circuit 1512 to which 192 is supplied.
That is, the shift signal S (2) output from the j-th stage in the second shift register 144.
j), if j is an odd number (1, 3, 5,..., 95), the enable signal Enb 1 is supplied to the other input terminal of the NAND circuit 1512 corresponding to the block B (2j−1). The other input terminal of the NAND circuit 1512 corresponding to the block B (2j) has an enable signal Enb
2 is supplied while j is an even number (2, 4, 6,..., 96), block B (2j−
The enable signal Enb3 is supplied to the other input terminal of the NAND circuit 1512 corresponding to 1), and the enable signal Enb4 is supplied to the other input terminal of the NAND circuit 1512 corresponding to the block B (2j).

The enable signals Enb1 to Enb4 are all clock signals CLX as shown in FIG.
And a pulse having a width shorter than a quarter cycle of the clock signal CLX (H
Level) and have a phase shifted by 90 degrees from each other. Specifically, in the first period Sub1 and the second period Sub2 of the horizontal scanning period H, the enable signal E
Pulses are output in the order of nb1 → Enb2 → Enb3 → Enb4 (→ Enb1), and the pulses of the enable signals Enb1 and Enb2 are output so as to sandwich the timing at which the clock signal CLX falls, and the timing at which the clock signal CLX rises The pulses of the enable signals Enb3 and Enb4 are output so as to sandwich the signal.

Next, the configuration of the sampling circuit 160 will be described.
As shown in FIG. 5, the sampling circuit 160 is an aggregate of n-channel TFTs 165 whose drains are connected to the data lines 114.
Here, the source of the TFT 165 is connected to one of the three image signal lines 162 to which the data signals Vid1 to Vid3 are supplied in the following relationship. That is, in the TFT 165 whose drain is connected to one end of the q-th data line 114 counted from the left in the figure, if the remainder obtained by dividing q by 6 is “1” or “2”, the source is Similarly, the remainder of dividing q by 6 is connected to the image signal line 162 to which the data signal Vid1 is supplied.
The TFT 165 whose drain is connected to the data line 114 is connected to the image signal line 162 to which the data signal Vid2 is supplied, and the remainder obtained by dividing q by 6 is “5” or “0”. The source of the TFT 165 whose drain is connected to the data line 114 is connected to the image signal line 162 to which the data signal Vid3 is supplied.
For example, in FIG. 5, a TFT 165 whose drain is connected to the data line 114 in the eleventh column.
Since the remainder obtained by dividing “11” by 6 is “5”, the source is connected to the image signal line 162 to which the data signal Vid3 is supplied.

On the other hand, the sampling signal is supplied to the gate of the TFT 165 in the following relationship.
That is, the odd numbered block B (2j-1) has sampling signals R (4j-3), R (
4j-2) is supplied, but six columns of data lines 114 belonging to the block B (2j-1).
Among these, the TFTs 165 whose drains are connected to the odd-numbered data lines are commonly supplied with the odd-numbered sampling signal R (4j-3), and the TFTs 165 whose drains are connected to the even-numbered data lines. The sampling signal R (4j-2) which is an even number is supplied in common.
Further, the sampling signals R (4j−1) and R (4j) are supplied to the even-numbered block B (2j). Of the six columns of data lines 114 belonging to the block B (2j), the odd-numbered columns B (2j) are supplied. The TFT 165 whose drain is connected to the data line has an odd number sampling signal R.
(4j-1) is supplied in common, and the TFTs 165 whose drains are connected to the data lines in even columns
Are commonly supplied with an even-numbered sampling signal R (4j).
For example, since odd block B3 (= 2 × 2-1) is j = 2, sampling signals R5 (= 4 × 2-3) and R6 (= 4 × 2-2) are supplied. Of the 13, 14, 15, 16, 17, 18th data lines belonging to the block B3, odd numbers 13, 15, 17
The sampling signal R is connected to the gate of the TFT 165 whose drain is connected to the data line of the column.
3 is commonly supplied, while the sampling signal R4 is commonly supplied to the gates of the TFTs 165 whose drains are connected to the even-numbered 14, 16, and 18th data lines.

In such a sampling circuit 160, when an odd-numbered sampling signal of two sampling signals supplied to a certain block becomes H level, the TFT1 in the odd-numbered column
When 65 is turned on at the same time and the data signals Vid1 to Vid3 are sampled on the odd-numbered data lines among the six data lines 114 belonging to the block, the even-numbered sampling signal becomes H level when the even-numbered sampling signal becomes H level. The TFTs 165 are simultaneously turned on, and the data signals Vid1 to Vid3 are sampled on the even-numbered data lines.
This is because when one of the two sampling signals supplied to a certain block becomes H level, the block is in a designated state, and among these, an odd-numbered sampling signal becomes H level. In addition, the odd-numbered data line 114 is selected, and when the even-numbered sampling signal becomes H level, the even-numbered data line 114 is selected, and in any case, the data signal is sampled on the selected data line. It is synonymous with.
Note that the scanning line driving circuit 130, the shift register group 140, the data line selection circuit 150,
The constituent elements of the sampling circuit 160 are formed by a manufacturing process common to the TFT 116 in the display region 100, and contribute to downsizing and cost reduction of the entire device.

Next, the operation of the electro-optical device 1 according to the embodiment will be described.
In the present embodiment, the scanning control circuit 52 supplies a transfer start pulse DY to the scanning line driving circuit 130 at the beginning of a period of one frame. By this supply, as shown in FIG. 6, the scanning signals G1, G2, G3,..., G864 sequentially and exclusively become H level every horizontal scanning period H.
Among these, the horizontal scanning period H in which the scanning signal G1 is at the H level will be described. Note that, during this frame period, positive writing is performed for all pixels.
First, the scanning control circuit 52 sets the precharge control signal Nrg to the H level at the beginning of the horizontal scanning period H as shown in FIG. As a result, the S / P conversion circuit 320 outputs the image data Vd1 to Vd3 designating the black gradation to the three channels irrespective of the reading from the line memory 310, so that the three image signal lines 162 are output. Are supplied with data signals Vid1 to Vid3 of positive polarity and corresponding to black. On the other hand, the precharge control signal Nrg is H
When the level is reached, the other input terminal of the NAND circuit 1514 in the data line selection circuit 150 becomes the L level, so that the output signal of the NAND circuit 1514 is forcibly set to the H level. Therefore, the sampling signals R1, R2, R3, R4,..., R384 all become H level.
As a result, as a result of all the TFTs 165 being turned on, all the data lines 114 in the 1st to 1152th columns are precharged to a voltage corresponding to positive polarity and black, and the initial state before writing is made uniform. become.
Thereafter, since the precharge control signal Nrg becomes L level, the logic level of each sampling signal is defined by the shift signal and the enable signal.

Since the scanning control circuit 52 supplies the transfer start pulse DX1 at the start of the first period Sub1 in the horizontal scanning period H, the shift signals S1, S3,
S5,..., S191 have a relationship in which the transfer start pulse DX1 is sequentially delayed by half a cycle of the clock signal CLX. The scan control circuit 52 outputs the pulses of the enable signals Enb1 and Enb2 before and after the timing when the clock signal falls, and the pulses of the enable signals Enb3 and Enb4 before and after the timing when the clock signal rises.
Furthermore, in the first period Sub1, the sampling signal (4j-3) to the odd block B (2j-1) where j is an odd number is the shift signal S (2j-) from the first shift register 142.
The sampling signal (4j-1) to the even-numbered block B (2j) where j is an odd number is extracted from the pulse of 1) with the pulse of the enable signal Enb1.
The pulse of 1) is extracted by the pulse of the enable signal Enb2, and the sampling signal (4j-3) to the odd block B (2j-1) where j is an even number is the shift signal S.
The pulse (2j-1) is extracted by the pulse of the enable signal Enb3, and the sampling signal (4j-1) to the even block B (2j) where j is an even number is the same as the shift signal S.
The pulse of (2j-1) is extracted with the pulse of the enable signal Enb4.
In the first period Sub1, the second shift register 144 receives a transfer start pulse DX.
Since 2 is not yet supplied, the shift operation is not executed, so that the shift signals S2, S4
, S6,..., S192 are at the L level.
Therefore, when the clock signal CLX is output for at least 98 cycles after the transfer start pulse DX1 is supplied in the first period Sub1, the odd-numbered sampling signals R1, R3, R5, R7,. , R383 sequentially become H level exclusively.

On the other hand, before the scanning signal G1 becomes H level, the first row is 1, 2, 3, 4,.
Image data Vin corresponding to the pixels 110 in the 52nd column is sequentially supplied from the host device and stored in the line memory 310.
Here, the scanning control circuit 52 includes the horizontal scanning period H in which the scanning signal G1 is at the H level.
Immediately before the sampling signal R1 becomes H level in the first period Snb1 (strictly speaking, during the period when the sampling signal R1 becomes H level, the enable signal Enb1 becomes H level during the period when the shift signal S1 becomes H level. 8, immediately before the enable signal Enb1 is set to the H level), as shown in FIG. 8, the operation of reading out the image data corresponding to the pixels in the first row and the odd columns from the line memory 310 is started. To do. That is, in the first period Sub1, image data Vout corresponding to the pixels 110 in the first row and the columns 1, 3, 5, 7, 9,.
The read image data Vout is expanded three times on the time axis by the S / P conversion circuit 320 in accordance with the period in which the sampling signal R1 is at the H level, and corresponds to the first, third, and fifth columns. The image data is distributed in the order of image data Vd1, Vd2, and Vd3. The distributed image data Vd1, Vd2, and Vd3 are converted into analog signals by the D / A converter circuit group 330, respectively, and further converted into positive signals by the polarity inversion circuit 340, respectively, and are used as data signals Vid1, Vid2, and Vid3. Is output.
As a result, the data signal Vid1 becomes a positive voltage corresponding to the gradation of the pixel 110 in the first row and the first column. Similarly, the data signals Vid2 and Vid3 are the pixels 110 in the first row and the third column and the first row and the fifth column, respectively.
It becomes a positive voltage according to the gradation. The previous data signals Vid1, Vid2, and Vid3 are precharge voltages.

If the sampling signal R1 is at the H level, the TFTs 165 corresponding to the first, third, and fifth columns of the odd columns among the first to sixth columns belonging to the block B1 are turned on.
In the same way, a data signal Vid1 having a positive voltage corresponding to the gradation of the pixel 110 in the first row and the first column is sampled. Similarly, the third and fifth data lines 114 have the first row, the third column and the first row, the fifth column Pixel 1 of
Data signals Vid2 and Vid3 having a positive voltage corresponding to 10 gradations are sampled.
Since the scanning signal G1 is at the H level, all the TFTs 116 whose gates are connected to the scanning line 112 in the first row are on. For this reason, the data signal Vid1 sampled on the data line 114 in the first column is applied to the pixel electrode 118 in the first row and the first column corresponding to the intersection of the scanning line 112 in the first row and the data line 114 in the first column. Will be. Data lines 11 in the third and fifth columns
Similarly, the data signals Vid2 and Vid3 sampled at 4 are each 1
The voltage is applied to the pixel electrodes 118 in the third row and the first column.

In the first period Sub1, the sampling signal R3 becomes H level next to the sampling signal R1. In accordance with the period when the sampling signal R3 is at the H level, the image data Vout corresponding to the pixels 110 in the first row and the seventh, ninth, and eleventh columns is expanded three times on the time axis, The data is distributed to data Vd1, Vd2, and Vd3, converted into a positive analog signal, and output as data signals Vid1, Vid2, and Vid3. As a result, the data signal Vid1 becomes a positive voltage corresponding to the gradation of the pixel 110 in the first row and the seventh column. Similarly, the data signals Vid2 and Vid3 have positive voltages corresponding to the gray levels of the pixels 110 in the 1st row and 9th column and the 1st row and 11th column, respectively.
If the sampling signal R3 is at the H level, the TFTs 165 corresponding to the seventh, ninth, and eleventh columns of the odd-numbered columns among the first to sixth columns belonging to the block B2 are turned on.
4, a data signal Vid1 having a positive voltage corresponding to the gradation of the pixel 110 in the first row and the seventh column is sampled. Similarly, the data line 114 in the ninth and eleventh columns has the first row, the ninth column, and the first row, 11 Data signals Vid2 and Vid3 having a positive voltage corresponding to the gradation of the pixels 110 in the column are sampled. Therefore, the data signal Vid1 sampled on the data line 114 in the seventh column is applied to the pixel electrode 118 in the first row and the seventh column. The data signals Vid2 and Vid3 sampled on the data lines 114 in the ninth and eleventh columns are also applied to the pixel electrodes 118 in the first row and the ninth column and the first row and the eleventh column, respectively.

Similarly, in the first period Sub1, odd-numbered sampling signals R5, R7, R9 are used.
,..., R383 sequentially become H level, blocks B3, B4, B5,..., B192 are designated and the data signal Vid is applied to the odd-numbered data lines 114 of the designated block.
1, Vid2, and Vid3 are sampled, and writing to the pixel electrode is performed.

Next, the operation in the second period Sub2 in the horizontal scanning period H will be described.
The scanning control circuit 52 supplies the transfer start pulse DX2 at the start of the second period Sub2. For this reason, the shift signals S2, S4, S6,.
In 192, the transfer start pulse DX2 is sequentially delayed by half a cycle of the clock signal CLX. Also, the enable signals Enb1, Enb2, Enb3 and E in the second period Sub2
nb4 is output in the same manner as in the first period Sub1.
Further, in the second period Sub2, the sampling signal (4j-2) to the odd block B (2j-1) where j is an odd number is the shift signal S (2j) from the second shift register 144.
The sampling signal (4j) to the even-numbered block B (2j) where j is an odd number is extracted with the pulse of the enable signal Enb1, and the pulse of the shift signal S (2j) is the pulse of the enable signal Enb2. The sampling signal (4j-2) to the odd block B (2j-1) where j is an even number is extracted from the pulse of the shift signal S (2j) with the pulse of the enable signal Enb3. The sampling signal (4j) to the even block B (2j) where j is an even number is obtained by extracting the pulse of the shift signal S (2j) with the pulse of the enable signal Enb4.
Further, in the second period Sub2, the first shift register 142 has already completed the transfer of the transfer start pulse DX1, so that the shift operation is not executed. For this reason, the shift signal S1
, S3, S5,..., S191 are at the L level.
Therefore, when the clock signal CLX is output for at least 98 cycles after the transfer start pulse DX2 is supplied in the second period Sub2, the even-numbered sampling signals R2, R4, R6, R8,... Over the second period Sub2. , R384 sequentially become H level exclusively.

On the other hand, the scanning control circuit 52 determines that the sampling signal R2 is at the H level in the second period Snb2 (strictly speaking, the period during which the sampling signal R2 is at the H level is the period during which the shift signal S2 is at the H level). Since the enable signal Enb1 is at the H level, immediately before the enable signal Enb1 is set to the H level, as shown in FIG.
The operation of reading out the image data corresponding to the pixels 110 in the even-numbered columns from the line memory 310 is started. That is, in the second period Sub2, it is the first row and is 2, 4, 6, 8, 1
Image data Vout corresponding to the pixels 110 of 0,.
The read image data Vout is expanded three times on the time axis by the S / P conversion circuit 320 in accordance with the period in which the sampling signal R2 is at the H level, and corresponds to the second, fourth, and sixth columns. The image data is distributed in the order of the image data Vd1, Vd2, and Vd3, respectively, converted into analog signals by the D / A conversion circuit group 330, and further converted into a positive signal by the polarity inversion circuit 340, respectively. Output as Vid1, Vid2, and Vid3.
If the sampling signal R2 is at the H level, the TFTs 165 corresponding to the second, fourth, and sixth columns of the even-numbered columns among the first to sixth columns belonging to the block B1 are turned on.
The positive voltage data signal Vid1 corresponding to the gray level of the pixel 110 in the first row and the second column is sampled. Similarly, the fourth and sixth columns of the data line 114 have the first row, the fourth column, and the first row, the sixth column. Pixel 1 of
Data signals Vid2 and Vid3 having a positive voltage corresponding to 10 gradations are sampled. In the second period Sub2, since the scanning signal G1 is at the H level continuously from the first period Sub1, the data signal Vid1 sampled on the data line 114 in the second column is the scanning line 1 in the first line.
This is applied to the pixel electrode 118 in the first row and the second column corresponding to the intersection of the 12th and the second data line 114. Data signal Vid2 sampled on the data lines 114 in the fourth and sixth columns
And Vid3 are similarly applied to the pixel electrodes 118 in the first row and the fourth column and the first row and the sixth column, respectively.
Will be applied.

Similarly, in the second period Sub2, the even-numbered sampling signals R4, R6, R8
, R10,..., R384 become H level in order, blocks B2, B3, B4, B5,
..., B192 is designated, and data signals Vid1, Vid2, and Vid3 are sampled on the data lines 114 in the even-numbered columns of the designated block, respectively, and writing to the pixel electrodes is performed.
The above is the operation in the horizontal scanning period in which the scanning signal G1 is at the H level, but each horizontal scanning period in which the scanning signals G2, G3,..., G864 are at the H level also corresponds to the selected scanning line 112. A similar operation will be performed on the row. As a result, in this frame, writing of the positive voltage corresponding to the gradation is completed over all the pixels in the 1st to 864th rows.
In the next frame, the same writing is executed in the 1st to 864th lines. However, in this embodiment, since the polarity inversion is performed for each frame as described above, gradation is applied to all pixels. Accordingly, writing of the negative polarity voltage is executed.

Here, the voltage of the data signal Vid1 (to Vid3) will be described. As shown in FIG. 8 in the first period Sub1, and in the second period Sub2, as shown in FIG. In addition to being synchronized with the phase expansion operation by 320, the polarity is converted to the polarity designated by the polarity instruction signal Pol and output.
If the positive polarity writing is designated, the voltage of the data signal Vid1 is the voltage Vwp corresponding to white.
From the reference voltage Vc of the polarity in the range from the voltage Vwm corresponding to white to the voltage Vbm corresponding to black. The voltage is shifted by an amount corresponding to the gradation of the pixel (in the figure, it is indicated by ↑ for positive polarity and ↓ for negative polarity). Here, the positive voltage Vwp (and V
bp) and negative voltage Vwm (and Vbm) are symmetrical with each other about voltage Vc.
Of the logical levels of the scanning signal and sampling signal, the H level is the power supply voltage Vdd, and the L level is the voltage reference in this embodiment and is the ground potential Gnd. In addition, FIG.
And the vertical scale of the voltage of the data signal in FIG. 9 is enlarged compared with the voltage waveform which is another logic signal.

According to the present embodiment, as shown in FIG. 10, in the horizontal scanning period H in which one row of a certain scanning line is selected, blocks B1, B2, B3,..., B192 are designated in the first period Sub1. At the same time, the voltage corresponding to the gradation is written to the odd-numbered columns of the designated block, while the blocks B1, B2, B3,..., B192 are designated and designated in the second period Sub2. A voltage corresponding to the gradation is written to an even column of the block. For this reason, in the present embodiment, as seen in the entire screen of the display area 100, as shown in FIG. 11, after writing, pixels that are written in adjacent pixels on the left and right of the column (first in FIG. 11). Since writing is performed in the period Sub1, the pixel is not written at all in the adjacent pixels on the left and right of the column after writing (writing is performed in the second period Sub2 in FIG. 11). Since this is done, “2” will appear alternately in each column.
On the other hand, in the case of the three-phase development in the conventional technique, as shown in FIG.
In the horizontal scanning period H in which a row is selected, the blocks B1, B2, B3,..., B192 are designated, and only the voltage corresponding to the gradation is written to the three columns of the designated block. is there. For this reason, according to the conventional technique, as shown in FIG. 31, after writing, the pixel to be written in the adjacent pixel on the right side of the column (denoted as “b” in the drawing) With respect to a pixel (indicated by “a” in the drawing) where writing is not performed in an adjacent pixel, the pixel appears in a cycle of “3” columns as the number of phase expansions. In FIG. 31, the final 1152 column is represented as “b” for convenience, but strictly speaking, it is “a” because there is no adjacent pixel on the right side of the column.

In the pixel where writing is performed in the adjacent pixel after writing, it is considered that the written voltage fluctuates due to writing in the adjacent pixel. For pixels that are not performed, there is a case where a subtle gradation difference occurs even if the same gradation is displayed.
In this case, in the conventional technique, the gradation difference appears with a period of “3” columns, which is the number of phase expansions, so that it is easy to visually recognize, but in this embodiment, the odd-numbered columns and even-numbered columns Since they appear alternately and disperse, it is possible to make it difficult to visually recognize the gradation difference associated with the phase development drive method.
In the present embodiment, only the first column has no adjacent pixel on the left side of the column.
It is also conceivable that the influence after writing is different from the other odd-numbered columns 3, 5,..., 1151 (pixels in which writing is performed in adjacent pixels on both the left and right after writing). In this case, the first row may be shielded from light as a dummy area.

<Another example of pixel arrangement: Part 1>
Next, some examples in which the pixel arrangement is changed will be described.
In the first embodiment described above, the gradation difference appears alternately for each column in the odd and even columns,
It can be said that the gradation difference is difficult to visually recognize as compared with the conventional technique. However, since pixels to which writing is performed in adjacent pixels after writing and pixels to which writing is not performed are aligned in the same column, there is a high possibility that the pixels are visually recognized as linear stripes.
Therefore, in this example 1, for example, as shown in FIG. 13, odd numbers (1, 3, 5,..., 86
3) In the horizontal scanning period H for selecting the scanning line of the row, as in the first embodiment, in the first period Sub1, the blocks B1, B2, B3,. A voltage corresponding to the gradation is written to the column, and in the second period Sub2, the block B
1, B 2, B 3,..., B 192 are designated and a voltage corresponding to the gradation is written to an even column of the designated block, while scanning lines of even (2, 4, 6,..., 864) rows are written. In the horizontal scanning period H to be selected, on the contrary, in the first period Sub1, the voltage corresponding to the gradation is written to the even number column of the designated block, and in the second period Sub2, the odd number column of the designated block is written. Thus, the voltage corresponding to the gradation is written.
As a result, in Example 1, as viewed in the entire screen of the display area 100, as shown in FIG. 14, pixels that are written to adjacent pixels on the left and right of the column after writing (denoted as “1”) In addition, pixels that are not written at all at the left and right sides of the column after writing (denoted as “2”) alternately appear not only in the column direction but also in the row direction.
For this reason, according to Example 1, it is possible to make the difference in gradation associated with the phase development drive method less noticeable than in the first embodiment.

In Example 1, in the horizontal scanning period in which even-numbered scanning lines are selected, the scanning control circuit 5
12, as shown in FIG. 12, the transfer start pulse DX2 is output in the first period Sub1, and the transfer start pulse DX1 is output in the second period Sub2. As a result, in the first period Sub1, the voltage is written to the even-numbered columns of the designated block, and in the second period Sub2, the voltage is written to the odd-numbered columns of the designated block.
In Example 1, it is needless to say that odd and even rows may be replaced with the above example.

<Another example of pixel arrangement: Part 2>
Next, Example 2 in which the pixel arrangement is changed will be described.
In Example 2, for example, as shown in FIG. 15A, in a horizontal scanning period H in which one row of scanning lines is selected in a certain n frame (for convenience, an odd frame), the first embodiment Similarly, in the first period Sub1, the voltage corresponding to the gradation is written to the odd-numbered columns of the sequentially designated block, and in the second period Sub2, the gradation is applied to the even-numbered columns of the sequentially designated block. When the corresponding voltage is written, as shown in FIG. 15B, in the horizontal scanning period H in which one scanning line is selected in the next (n + 1) frame (even number frame), On the other hand, in the first period Sub1, the voltage corresponding to the gradation is written to the even-numbered columns of the sequentially designated blocks, and in the second period Sub2, the gradation is applied to the odd-numbered columns of the sequentially designated blocks. To write the voltage Those were.
As a result, in Example 2, the entire screen of the display area 100 is shown in FIG.
As shown in (a), in even frames, as shown in FIG. 16 (b), pixels that are written to adjacent pixels on the left and right of the column after writing (denoted as “1”), respectively. And pixels that are not performed (denoted as “2”) appear alternately in time, so that when two frames are taken as a unit period, the difference in gradation in each pixel is averaged.
Therefore, according to Example 2, it is possible to make the difference in gradation associated with the phase development driving method even more inconspicuous than in the first embodiment.
In Example 2, it is needless to say that the odd frame and the even frame may be replaced with the above example.

<Another example of pixel arrangement: Part 3>
Next, Example 3 in which the pixel arrangement is changed will be described.
In Example 3, the concept of time change in Example 2 is applied to Example 1.
Specifically, in Example 3, as shown in FIG. 17, among the horizontal scanning periods H in which the odd-numbered scanning lines are selected over the odd frames, in the first period Sub1, the odd-numbered columns of the sequentially designated blocks are selected. In the second period Sub2, the voltage is written to the even-numbered columns of the designated block in order, and in the first period Sub1 of the horizontal scanning period H in which the scanning lines of the subsequent even-numbered rows are selected. In the case where the voltage is written to the even-numbered column of the block and the voltage is written to the odd-numbered column of the designated block in the second period Sub2, in FIG.
As shown in FIG. 8, in the horizontal scanning period H for selecting odd-numbered scanning lines, the first period Sub1
In the second period Sub2, in the second period Sub2,
In the first period Sub1, among the horizontal scanning period H in which the voltage is written to the odd-numbered columns of the sequentially designated block and the subsequent even-numbered scanning lines are selected, the voltage is written to the odd-numbered columns of the designated block. In the second period Sub2, the voltage is written to the even-numbered columns of the designated block.
Thus, in Example 3, the entire screen of the display area 100 is shown in FIG.
As shown in (a), in even frames, as shown in FIG. 19 (b), pixels that are written to adjacent pixels on the left and right of the column after writing (denoted as “1”), respectively. And non-performed pixels (denoted as “2”) appear alternately in every row and column in the same frame and alternately in every adjacent frame in time. As a result, the gradation difference in each pixel is averaged.
Therefore, according to Example 3, the difference in gradation associated with the phase development driving method than in Example 1 and Example 2 is
It can be made even less noticeable.
In Example 3, odd-numbered rows and even-numbered rows may be interchanged with the above example, and odd-numbered frames and even-numbered frames may be interchanged with the above-described example.

<Another example of pixel arrangement: Part 4>
Subsequently, Example 4 in which the pixel arrangement is changed will be described.
In this example 4, the time change concept in example 3 is applied when the area scanning drive method described in, for example, Japanese Patent Application Laid-Open No. 2004-177930 is adopted as the drive method.
Since the detailed contents of the area scanning drive method are described in the above publication, a detailed description is avoided. However, in brief, the display area 100 is an upper area (corresponding to the first to 432th scanning lines).
The first area) and the lower area (second area) corresponding to the scanning lines in the 433th to 864th rows are logically divided, while one frame is divided into the first and second fields as shown in FIG. In each field, 1, 433, 2, 434, 3, 435, ..., 432, 864 are divided.
This is a driving method in which scanning lines are selected in the order of rows, that is, the upper area and the lower area alternately and in the order in which each area is directed downward.
Note that the logical division of the display area here does not mean that the display area is physically cut and divided, and it is not distinguished when viewed in the display area, but it is necessary to distinguish when viewed in the scanning order. It means that it was separated for convenience.

Further, in the area scanning drive method, for example, when a positive voltage is written for a pixel belonging to the upper area in the first field and a negative voltage is written for a pixel belonging to the lower area, the upper area is written in the second field. A negative voltage is written for pixels belonging to, and a positive voltage is written for pixels belonging to the lower region. As a result, the ratio of the polarity of the voltage sampled on the data line after writing becomes approximately 50% for each of the positive polarity and the negative polarity regardless of the scanning line row for writing. As a result, the bias of the voltage polarity of the data line is eliminated, and the display quality is equalized.
In this area scanning drive method, since data signals are supplied in each of the first and second fields, the line memory 310 in FIG. 1 is a frame memory that stores image data Vin supplied from the host device for one frame. Is replaced.

Now, in Example 4, as shown in FIG. 21, in the odd-numbered frame, in the first period Sub1 in the horizontal scanning period H in which the scanning lines in the upper row are selected, the odd-numbered blocks specified in order are displayed. In the second period Sub2, when the voltage is written to the column and the voltage is written to the even-numbered column of the sequentially designated block, the next selected scanning line is the odd-numbered scanning line in the lower region. . For this reason, in the horizontal scanning period H in which the odd-numbered scanning lines in the lower region are selected, in the first period Sub1, in the same way as in the horizontal scanning period in which the odd-numbered scanning lines in the upper region are selected, the blocks designated in order. In the second period Sub2, the voltage is written in the even-numbered columns of the designated block.
The scanning line selected next to the odd-numbered scanning line in the lower region is an even-numbered scanning line following the odd-numbered row in the upper region. For this reason, in the horizontal scanning period H in which the even-numbered scanning lines in the upper region are selected, in the first period Sub1, in contrast to the horizontal scanning period in which the even-numbered scanning lines in the upper region are selected, the blocks designated in order. In the second period Sub2, the voltage is written in the odd-numbered columns of the designated block.
The scanning line selected next to the even-numbered scanning line in the upper region is an even-numbered scanning line following the odd-numbered row in the lower region. Therefore, in the horizontal scanning period H in which the even-numbered scanning lines in the lower region are selected, in the first period Sub1, the blocks designated in order are opposite to the horizontal scanning period in which the odd-numbered scanning lines in the lower region are selected. In the second period Sub2, the voltage is written in the odd-numbered columns of the designated block.
In the subsequent even frame, as shown in FIG. 22 and in the same manner as in Example 3, in the first period Sub1 and the second period Sub2 of each row, the relationship between the odd column and the even column is the same as the relationship of the odd frame. Replaced.

Thus, in Example 4, the entire screen of the display area 100 is shown in FIG.
As shown in (a), in the even frame, as shown in FIG.
The pixels denoted by “2” and the pixels denoted by “2” appear alternately in each row and column in the same frame and alternately in every adjacent frame in time. When viewed as a unit period, the difference in gradation in each pixel is averaged.
Therefore, according to Example 4, it is possible to make the difference in gradation associated with the phase development driving method even more inconspicuous while enjoying the effect of the region scanning driving method.

Second Embodiment
Next, a second embodiment of the present invention will be described.
In the second embodiment, the shift register group 140 (see FIG. 4) in the first embodiment is replaced with the configuration shown in FIG.
In the figure, the shift register group 140 according to the second embodiment includes a transfer start pulse DX in response to a signal Sel indicating that an odd column should be selected first (/ Sel indicating that an even column should be selected first). The first shift register 142 or the second shift register 144 are mutually exclusive.
It is set as the structure supplied to.
Specifically, each of the clocked inverters 146 and 148 receives the transfer start pulse DX, and among these, the clocked inverter 146 performs an inversion operation only when the signal Sel is at the H level, and the signal Sel is L In the case of the level, the output is in a high impedance state, and the clocked inverter 148 has a signal / S that is in a logical inversion relationship with the signal Sel.
The inversion operation is executed only when el is at H level, and when signal / Sel is at L level,
The output is in a high impedance state. Therefore, the clocked inverter 1
46 and 148 constitute a pulse selection circuit.
Note that the inverters 147 and 148 are simple logic inversion circuits.

24, when the shift register group 140 shown in FIG. 24 is applied, the scan control circuit 52 starts transfer at each start of the first period Sub1 and the second period Sub2, as shown in FIG. 25 and FIG. The pulse DX is output.
Further, the scan control circuit 52 samples the data signal on the odd-numbered data line in the first period Sub1 and also samples the data signal on the even-numbered data line in the second period Sub2 (odd-numbered column destination). As shown in FIG. 25, the signal Sel is set to the H level in the first period Sub1, and the signal Sel is set to the L level in the second period Sub2, while the data signal is sampled on the data lines in the even columns in the first period Sub1. At the same time, when the data signal is sampled on the odd-numbered data lines in the second period Sub2 (even column destination), as shown in FIG. 26, the signal Sel is set to the L level in the first period Sub1, and the second period Sub2 At S, the signal Sel is set to H level.
Therefore, since the transfer start pulse DX is supplied only to the first shift register 142 in the first period Sub1, and only to the second shift register 144 in the second period Sub2, in the case of the odd column ahead, the shift is eventually performed. As shown in FIG. 25, the signal and the sampling signal have the same waveform as that in FIG. On the other hand, the transfer start pulse DX is supplied only to the second shift register 144 in the first period Sub1 in the case of the even column ahead, and the first shift register 1 in the second period Sub2.
Similarly, as shown in FIG. 26, the shift signal and the sampling signal have the same waveforms as those in FIG.

In both the first and second embodiments described above, the number of phase expansions m, which is the number of data lines to be simultaneously written, is set to “3”, and the number of image signal lines 162 is also set to “3” corresponding to this. , “2” or more.

<Modification>
Next, a modified example of the present invention will be described.
In the first and second embodiments described above, a voltage is written to one of the odd-numbered columns or even-numbered columns in the first period Sub1, and a voltage is written to the other of the odd-numbered columns or even-numbered columns in the second period Sub2 and adjacent after writing. Although the pixel in which writing is performed and the pixel in which writing is not performed appear alternately, the same effect can be obtained in the modification example shown in FIG.
That is, in the modified example, as shown in the figure, the number of phase expansions is set to “2”, and in the first period Sub1, the data lines are selected in order every two columns and the data signal is sampled. The voltage of the data signal is written to the pixel, and in the second period Sub2, the data lines not selected in the first period Sub1 are selected every two columns, the data signal is sampled, and the voltage of the data signal is written to the pixel. The configuration is as follows.
In this modification, since the number of phase expansions is “2”, the number of data lines belonging to one block is “4”.

For this reason, in the modification example, as shown in FIG. 28, when the entire screen of the display area 100 is viewed, after writing, pixels that are written to adjacent pixels on either the left or right side of the column (
And a pixel (noted as “2”) in which writing is not performed at all on adjacent pixels on the left and right sides of the column after writing alternately appears every two columns. It becomes possible to make the difference in gradation inconspicuous.
Of course, in the modification, any one of the ideas in Examples 1 to 4 may be applied.

In the above description, all the data lines 1 are immediately before the data signal is sampled.
Although 14 is configured to be precharged, it does not have to be.
The processing circuit 20 processes the digital image data Vin. However, the processing circuit 20 may be configured to input an analog image signal and develop the phase.

In the embodiments and the like, the voltage LCcom applied to the common electrode 108, had to match the potential V _C is a measure of the polarity inversion, when TFT is an n-channel type, the gate and drain of the TFT Due to the parasitic capacitance between the drain and the drain (pixel electrode 118) from on to off.
) Occurs (also called push-down, punch-through, field-through, etc.). In order to prevent deterioration of the liquid crystal, AC drive is the principle for pixel capacitance,
Although the alternate write out high side (positive polarity) lower side (negative polarity) to the common electrode 108, while being matched voltage LCcom the voltage V _C, when the alternating writing, for pushdown The effective voltage value of the pixel capacitance is larger in the negative polarity writing than in the positive polarity writing. Therefore, as the voltage effective value of the pixel capacity and the positive polarity and negative polarity writing at the same gray level are equal to each other, the voltage LCcom of the common electrode 108, the voltage V _C is the amplitude reference of the data signal May be set slightly lower.

Further, in the embodiment, when viewed in FIG. 2, the vertical scanning direction is the downward direction and the horizontal scanning direction is the right direction. However, in order to cope with a projector or a rotatable display device described later. The scanning direction may be switched.
Furthermore, instead of the normally white mode in which white display is performed when the effective voltage value of the pixel capacitance is small, a normally black mode in which black display is performed may be used.

In addition, the liquid crystal device has been described with respect to the embodiment and the like. However, in the present invention, the image data (video signal) is phase-expanded and can be simultaneously sampled on a plurality of data lines.
For example, the present invention can be applied to an apparatus using an EL (Electronic Luminescence) element, an electron emitting element, an electrophoretic element, a digital mirror element, or a plasma display.

<Electronic equipment>
Next, as an example of an electronic apparatus using the electro-optical device according to the above-described embodiment, a projector using the above-described display panel 10 as a light valve will be described.
FIG. 29 is a plan view showing the configuration of the projector. As shown in this figure, a projector 2100 has a lamp unit 21 formed of a white light source such as a halogen lamp.
02 is provided. The projection light emitted from the lamp unit 2102 is R (by the three mirrors 2106 and two dichroic mirrors 2108 arranged inside.
The light valve 100 is divided into three primary colors of red, G (green), and B (blue), and corresponds to each primary color.
Guided to R, 100G and 100B, respectively. Note that B light has a longer optical path than other R and G colors, and therefore, in order to prevent the loss, B light passes through a relay lens system 2121 including an incident lens 2122, a relay lens 2123, and an exit lens 2124. Led.

Here, the configuration of the light valves 100R, 100G, and 100B is the same as that of the display panel 10 in the above-described embodiment, and R, supplied from a processing circuit (not shown in FIG. 29).
It is driven by an image signal corresponding to each color of G and B. That is, the projector 2100 has a configuration in which three sets of electro-optical devices 1 including the display panel 10 are provided corresponding to the colors R, G, and B.
The lights modulated by the light valves 100R, 100G, and 100B are incident on the dichroic prism 2112 from three directions. In the dichroic prism 2112, the R and B light beams are refracted at 90 degrees, while the G light beam travels straight.
Therefore, after the images of the respective colors are combined, the projection lens 2114 is displayed on the screen 2120.
As a result, a color image is projected.

The light valves 100R, 100G, and 100B include a dichroic mirror 2
Since light corresponding to the primary colors of R, G, and B is incident by 108, there is no need to provide a color filter. Further, the transmission images of the light valves 100R and 100B are projected after being reflected by the dichroic mirror 2112, whereas the transmission image of the light valve 100G is projected as it is, so the horizontal scanning direction by the light valves 100R and 100B is The image is reversed in the horizontal scanning direction by the light valve 100G and displayed in an inverted image.

In addition to the electronic devices described with reference to FIG. 29, the electronic devices include a television, a viewfinder type / monitor direct-view type video tape recorder, a car navigation device, a pager, an electronic notebook, a calculator, a word processor, a workstation, a television. Examples include a telephone, a POS terminal, a digital still camera, a mobile phone, and a device equipped with a touch panel. Needless to say, the above-described electro-optical device can be applied to these various electronic devices.

1 is a diagram illustrating an overall configuration of an electro-optical device according to a first embodiment of the invention. FIG. 3 is a diagram showing a configuration of a display panel in the same electro-optical device. FIG. It is a figure which shows the structure of the pixel in the display panel. It is a figure which shows the structure of the shift register group in the display panel. It is a figure which shows the structure of the data line selection circuit in the display panel. FIG. 6 is a diagram for explaining a vertical scanning operation of the electro-optical device. It is a figure for demonstrating the operation | movement of the horizontal scanning of the same electro-optical apparatus. FIG. 6 is a diagram for explaining a data signal writing operation of the electro-optical device. FIG. 6 is a diagram for explaining a data signal writing operation of the electro-optical device. It is a figure for demonstrating writing of the same electro-optical apparatus. It is a figure which shows the writing state of the same electro-optical device. It is a figure for demonstrating the operation | movement of the horizontal scanning of Example 1 which changed pixel arrangement | positioning. 10 is a diagram for explaining writing according to Example 1. FIG. FIG. 6 is a diagram showing a writing state according to Example 1. It is a figure for demonstrating the writing which concerns on the example 2 which changed pixel arrangement | positioning. FIG. 10 is a diagram showing a writing state according to Example 2. It is a figure for demonstrating the writing which concerns on the example 3 which changed pixel arrangement | positioning. 10 is a diagram for explaining writing according to Example 3. FIG. FIG. 10 is a diagram showing a writing state according to Example 3. It is a figure which shows the operation | movement of the vertical scanning which concerns on the example 4 which changed pixel arrangement | positioning. 10 is a diagram for explaining writing according to Example 4. FIG. 10 is a diagram for explaining writing according to Example 4. FIG. FIG. 10 is a diagram showing a write state according to Example 4. It is a figure which shows the structure of the shift register group which concerns on 2nd Embodiment of this invention. It is a figure which shows the operation | movement of the horizontal scanning of the same shift register group. It is a figure which shows the operation | movement of the horizontal scanning of the same shift register group. It is a figure for demonstrating the writing which concerns on a modification. It is a figure which shows the write state which concerns on a modification. It is a figure which shows the structure of the projector to which the same electro-optical apparatus is applied. It is a figure for demonstrating the writing which concerns on a prior art. It is a figure which shows the writing state which concerns on a prior art.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Electro-optical apparatus, 10 ... Display panel, 20 ... Processing circuit, 100 ... Display area, 105 ... Liquid crystal, 110 ... Pixel, 112 ... Scan line, 114 ... Data line, 116 ... TFT, 118 ... Pixel electrode, 120 ... Liquid crystal capacitance, 130... Scanning line driving circuit, 140... Shift register group, 142
... 1st shift register, 144 ... 2nd shift register, 150 ... Data line selection circuit, 16
DESCRIPTION OF SYMBOLS 0 ... Sampling circuit, 162 ... Image signal line, 165 ... TFT, 1612 ... NAND circuit, 1614 ... NOR circuit, 1616, 1618 ... NOT circuit, 2100 ... Projector

Claims (7)

Provided corresponding to the intersection of a plurality of rows of scanning lines and a plurality of columns of data lines blocked every 2m (m is an integer of 2 or more), each of which is selected when the scanning line is selected. A drive circuit for an electro-optical device having a plurality of pixels having gradations according to a data signal sampled on the data line,
A scanning line driving circuit for selecting the plurality of scanning lines in a predetermined order;
A period in which one row of scanning lines is selected by the scanning line driving circuit is divided into a first period and a second period. Among these, a first shift register that sequentially outputs a predetermined pulse in the first period; A second shift register for sequentially outputting predetermined pulses in the second period;
In the first period, the blocks are designated in order according to the output from the first shift register, and one of the odd-numbered or even-numbered data lines among 2m-column data lines belonging to the designated block is designated as m columns. Selected,
In the second period, the blocks are designated in order according to the output from the second shift register, and the other data line of the odd number column or the even number column among the 2m data lines belonging to the designated block is selected. A data line selection circuit to perform,
a sampling circuit for sampling the data signals supplied to the m image signal lines to m columns of data lines selected by the data line selection circuit;
An electro-optical device driving circuit comprising: The first shift register outputs a signal obtained by sequentially shifting the first pulse input at the start of the first period by a predetermined clock signal;
The second shift register outputs a signal obtained by sequentially shifting the second pulse input at the start of the second period with the clock signal,
The drive circuit of the electro-optical device according to claim 1, wherein the data line selection circuit sequentially designates the blocks in accordance with shift signals from the first and second shift registers. A pulse selection circuit for supplying a predetermined input pulse to the first shift register at the start of the first period, and to supply the second shift register at the start of the second period;
The first and second shift registers output signals obtained by sequentially shifting the supplied input pulses with a predetermined clock signal,
The drive circuit of the electro-optical device according to claim 1, wherein the data line selection circuit sequentially designates the blocks in accordance with shift signals from the first and second shift registers. The first and second shift registers output a pulse signal obtained by sequentially shifting a predetermined input pulse with a predetermined clock signal in correspondence with two or more of the blocks,
The data line selection circuit includes a logic circuit that causes the pulse signals output from the first and second shift registers to be mutually exclusive in the two or more blocks by a logical operation with a predetermined enable signal. ,
The drive circuit of the electro-optical device according to claim 1. The first and second shift registers sequentially shift a predetermined input pulse with a predetermined clock signal, and output pulse signals whose pulse widths overlap each other between adjacent ones,
The data line selection circuit is a logic that causes the pulse signals output from the first and second shift registers to be mutually exclusive in the blocks corresponding to the pulse signals by performing a logical operation with a predetermined enable signal. Having a circuit,
The drive circuit of the electro-optical device according to claim 1. Provided corresponding to the intersection of a plurality of rows of scanning lines and a plurality of columns of data lines blocked every 2m (m is an integer of 2 or more), each of which is selected when the scanning line is selected. A plurality of pixels having gradation according to a data signal sampled on the data line;
A scanning line driving circuit for selecting the plurality of scanning lines in a predetermined order;
A period in which one row of scanning lines is selected by the scanning line driving circuit is divided into a first period and a second period. Among these, a first shift register that sequentially outputs a predetermined pulse in the first period; A second shift register for sequentially outputting predetermined pulses in the second period;
In the first period, the blocks are designated in order according to the output from the first shift register, and one of the odd-numbered or even-numbered data lines among 2m-column data lines belonging to the designated block is designated as m columns. Selected,
In the second period, the blocks are designated in order according to the output from the second shift register, and the other data line of the odd number column or the even number column among the 2m data lines belonging to the designated block is selected. A data line selection circuit to perform,
a sampling circuit for sampling the data signals supplied to the m image signal lines to m columns of data lines selected by the data line selection circuit;
An electro-optical device comprising:   An electronic apparatus comprising the electro-optical device according to claim 6.

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