JP2006276119A - Data signal supply circuit, supply method, opto-electronic apparatus and electronic apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a data signal supply circuit and a supply method, by which data signals are supplied to an opto-electronic apparatus capable of displaying an image with high definition by suppressing occurrence of display unevenness caused in the vertical direction, and to provide an opto-electronic apparatus and an electronic apparatus. <P>SOLUTION: A memory circuit 3304 stores a coefficient, corresponding to a channel by relating to an odd block. In an interpolation circuit 3306, when the odd block is selected, the coefficient corresponding to a selection block is read out, as it is; whereas, when an even block is selected, the coefficient, corresponding to the selection block, is calculated by interpolating from the coefficient of the odd block which adjoins to the even block and outputted. A multiplier 3312 and an adder 3314 which are provided, according to each channel correct image data Vd1d to Vd6d according to a specified grayscale value and coefficient. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a technique for preventing deterioration in display quality appearing in a so-called vertical direction.

In recent years, projectors that form a small image on a display panel using liquid crystal or the like and enlarge and project the small image using an optical system are becoming widespread. The projector does not have a function of creating an image by itself, and is supplied with video data (or video signal) from a host device such as a personal computer or a TV tuner. This video data designates the gradation (brightness) of the pixels, and is supplied in the form of vertical scanning and horizontal scanning of the pixels arranged in a matrix. It is appropriate to drive according to this format. For this reason, in the display panel used in the projector, the scanning lines are selected in order, and the data lines are selected one by one in the period during which one scanning line is selected (one horizontal scanning period). In general, driving is performed in a dot sequential manner in which a data signal (image signal) obtained by converting data so as to be suitable for driving a liquid crystal is supplied to a selected data line.

On the other hand, recently, high definition display images have been progressing as in high-definition images. High definition can be achieved by increasing the number of scanning lines and the number of data lines. However, an increase in the number of scanning lines shortens one horizontal scanning period. Further, in the dot sequential method, the number of data lines is increased. With this increase, the data line selection period is also shortened. For this reason, in the dot sequential method, it becomes impossible to secure a sufficient time for supplying the data signal to the data line as the definition becomes higher, and writing to the pixels has started to be insufficient.
Therefore, a method called phase expansion drive has been devised for the purpose of eliminating the point where writing becomes insufficient (see Patent Document 1). This phase expansion drive simultaneously selects a predetermined number of data lines, for example, every six lines, in one horizontal scanning period, and outputs a data signal to pixels corresponding to the selected scanning line and the selected data line as a time axis. In this method, the data is expanded to 6 times and supplied to each of the selected six data lines. In this phase development driving method, the time for supplying the data signal to the data line can be secured 6 times in this example as compared with the dot sequential method, and thus it is considered suitable for high definition. Yes.
JP 2000-112437 A

However, when the phase development drive method is used, as shown in FIG. 9, even if it is intended to display all pixels with the same gradation value, vertical streaky unevenness occurs. ,
There was a problem that the display quality deteriorated.
The present invention has been made in view of the above-described circumstances, and an object of the present invention is to supply a data signal to an electro-optical device that enables high-quality display while suppressing occurrence of display unevenness appearing in the vertical direction. The present invention provides a data signal supply circuit, a supply method, an electro-optical device, an electronic apparatus, and the like.

In order to achieve the above object, according to the present invention, a plurality of scanning lines and a plurality of data lines are provided corresponding to each other, and when the scanning line is selected, a level corresponding to the voltage of the data line is selected. A pixel, a scanning line driving circuit that selects scanning lines in a predetermined order, a block selection circuit that sequentially selects a block composed of a plurality of data lines over a period in which the scanning lines are selected, and the block A plurality of images each provided with a data signal having a voltage corresponding to the gradation of the pixel corresponding to the selected scanning line and the data line belonging to the block. A table having a signal line, and a sampling switch provided on each of the data lines and sampling a data signal supplied to the image signal line to a data line belonging to a selected block. A data signal supply circuit for supplying a data signal to the panel, a storage circuit for storing coefficients corresponding to the blocks and series, and the coefficients corresponding to the blocks selected by the block selection circuit for each series A readout circuit that reads from the circuit;
And a correction circuit that corrects the voltage of the data signal distributed to each series in a predetermined order with a correction amount defined by the coefficient of the corresponding series among the read coefficients. According to the present invention, it is possible to correct a data signal so as to eliminate the gradation difference even if the gradation difference caused by the difference in series differs depending on the position of the block.

In the present invention, the storage circuit stores a coefficient corresponding to a series corresponding to a smaller number of blocks than the block of the electro-optical device, and the coefficient corresponding to the block selected by the block selection circuit is When not stored in the storage circuit, a configuration having an interpolation circuit that obtains a coefficient corresponding to the selected block by interpolating from a coefficient corresponding to a block adjacent to the selected block is preferable.
In the present invention, it is also preferable that the correction circuit calculates a correction amount using a function having a tone value and a coefficient specified by the voltage of the data signal before correction as arguments.
The present invention can be conceptualized not only as a data signal supply circuit, but also as a data signal supply method, an electro-optical device, and an electronic apparatus having the electro-optical device.

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram illustrating the overall configuration of the electro-optical device according to the present embodiment.
As shown in this figure, the electro-optical device 10 is roughly divided into a processing circuit 50 and a display panel 100. Among these, the processing circuit 50 is a circuit module formed on a printed board, and is connected to the display panel 100 by an FPC (Flexible Printed Circuit) board or the like.

The processing circuit 50 further includes a data signal supply circuit 300 and a scanning control circuit 52. Among these, the data signal supply circuit 300 includes an S / P conversion circuit 320, an image correction circuit 330, and a D.
/ A conversion circuit group 340 and amplification / inversion circuit 350 are included.
The S / P conversion circuit 320 receives image data Vid supplied from a host device (not shown) in synchronization with the vertical scanning signal Vs, the horizontal scanning signal Hs, and the dot clock signal Dclk. ("Channel" is used as a term meaning "series")
Are also expanded by 6 times on the time axis (also referred to as phase expansion or serial-parallel conversion) and output as image data Vd1d to Vd6d. here,
The image data Vid is digital data that designates the gradation (brightness) of the pixel, and is designated as the lowest gradation (black) in the horizontal blanking period.
Note that the reason for designating the lowest gradation in the horizontal blanking period is mainly because the pixel does not contribute to the display even if it is supplied to the pixel due to timing shift or the like. For convenience of explanation, the image data Vd1d to Vd6d are referred to as channels 1 to 6, respectively.

The image correction circuit 330 corrects the image data Vd1d to Vd6d for each channel and outputs the corrected image data Vd1a to Vd6a, respectively. Details of the image correction circuit 330 will be described later.
The D / A converter circuit group 340 is an aggregate of D / A converters provided for each channel,
The corrected image data Vd1a to Vd6a are converted into analog signals having voltages corresponding to the gradation values, respectively.
The amplifying / inverting circuit 350 performs normal rotation or polarity inversion on the analog-converted signal with reference to a voltage Vc described later, and supplies the signal to the display panel 100 as data signals Vid1 to Vid6.

For polarity inversion, (a) every scanning line, (b) every data signal, (c) every pixel, (d) surface (
There are various modes such as every frame). In this embodiment, it is assumed that (a) polarity inversion is performed for each scanning line. However, the present invention is not limited to this.
The voltage Vc is the amplitude center voltage of the image signal as shown in FIG. In the present embodiment, for the sake of convenience, the amplitude center voltage V V is applied to the data signals Vid1 to Vid6.
The higher side than c is referred to as positive polarity, and the lower side is referred to as negative polarity.
In this embodiment, the image data Vid is converted to analog after serial-parallel conversion, but it is needless to say that analog conversion may be performed before serial-parallel conversion.

For convenience, the configuration of the display panel 100 will be described. The display panel 100 forms a predetermined image by electro-optic change. FIG. 2 is a block diagram showing an electrical configuration of the display panel 100, and FIG. 3 is a diagram showing a detailed configuration of pixels of the display panel 100. The display panel 100 has a configuration in which an element substrate and a counter substrate on which a common electrode is formed are bonded together with a sealing material with a certain gap, and liquid crystal is sealed in the gap.
As shown in FIG. 2, in the display panel 100, 864 rows of scanning lines 112 extend in the X (horizontal) direction in the figure, while 1152 (= 192 × 6) columns of data lines 114 in the figure Y ( It extends in the (vertical) direction. Pixels 110 are provided so as to correspond to the intersections between the scanning lines 112 and the data lines 114. Therefore, the pixel 110 is
Although the display area 100a is arranged in a matrix of 864 rows × 1152 columns, the present invention is not limited to this.
In this embodiment, 1152 columns of data lines 114 are divided into blocks every six columns. For convenience of explanation, the first, second, third,..., 192th blocks from the left are denoted as B1, B2, B3,.

As for the detailed configuration of the pixel 110, as shown in FIG.
A thin film transistor (116) has a source connected to the data line 114, a drain connected to the pixel electrode 118, and a gate connected to the scanning line 112.
Further, the common electrode 108 is provided in common to all the pixels so as to face the pixel electrode 118 formed on the element substrate. A liquid crystal 105 is sandwiched between the pixel electrode 118 and the common electrode 108. For this reason, a pixel capacitor composed of the pixel electrode 118, the common electrode 108, and the liquid crystal 105 is formed for each pixel.
Note that the voltage LCcom is applied to the common electrode 108, but the potential is set slightly lower than the amplitude center voltage Vc for the reason described later.

Although not shown in particular, the opposing surfaces of both substrates are respectively provided with alignment films that have been rubbed so that the major axis direction of the liquid crystal molecules is continuously twisted between the substrates by, for example, about 90 degrees. A polarizer corresponding to the orientation direction is provided on each back side of the substrate.
If the effective voltage applied to the pixel capacitor is zero, the light passing between the pixel electrode 118 and the common electrode 108 rotates about 90 degrees along the twist of the liquid crystal molecules, while the effective voltage value is As it increases, the liquid crystal molecules tilt in the direction of the electric field, and as a result, their optical rotation disappears. For this reason, for example, in a transmission type, when polarizers whose polarization axes are orthogonal to each other according to the alignment direction are arranged on the incident side and the back side, if the voltage effective value is close to zero, the light transmittance is While the maximum is white display, the amount of transmitted light decreases as the effective voltage value increases, and finally black display with the minimum transmittance is obtained (normally white mode).

Further, in order to reduce the influence of charge leakage from the pixel capacitor via the TFT 116 at the off time, the storage capacitor 109 is formed for each pixel. One end of the storage capacitor 109 is
While connected to the pixel electrode 118 (the drain of the TFT 116), the other end is commonly connected to the capacitor line 107 over all pixels. Although not shown in FIG. 2, the capacitor line 107 is maintained at a constant temporal potential, for example, the lower voltage Vss of the power source.
Note that the TFT 116 in the pixel 110 is formed by a manufacturing process common to a scanning line driving circuit 130, a block selection circuit 140, a sampling switch 151, and the like described below, and contributes to downsizing and cost reduction of the entire device. ing.

The voltage LCcom applied to the common electrode 108 is ideally the potential V _C,
Since the sampling switch 151 is a thin film transistor equivalent to the TFT 116 for switching the pixel electrode 118, the gates of the TFTs constituting the sampling switch 151
Due to the parasitic capacitance between the drains, a phenomenon (referred to as push-down, penetration, field-through, etc.) in which the potential of the drain (pixel electrode 118) decreases from on to off occurs. In order to prevent the deterioration of the liquid crystal, AC driving is basically used for the pixel capacitance, so that the same gradation is alternately written on the common electrode 108 on the high side (positive polarity) and on the low side (negative polarity). , in a state of being matched voltage LCcom the voltage V _C, when the alternating writing, for pushdown, the effective voltage value of the pixel capacitance, who negative writing becomes larger than the positive polarity writing . Therefore, as the voltage effective value of the pixel capacity and the positive polarity and negative polarity writing at the same gray level are equal to each other, the voltage LCcom of the common electrode 108, the voltage V _C is the amplitude reference of the data signal Is set slightly lower.

Subsequently, peripheral circuits such as a scanning line driving circuit 130 and a block selection circuit 140 are provided around the display region 100a in which the pixels 110 are arranged.
Among these, as shown in FIG. 6, the scanning line driving circuit 130 receives scanning signals G1, G2, G3,.
This is supplied to the scanning line 112 in the second row, the second row, the third row,.
The details of the scanning line driver circuit 130 are omitted because they are not directly related to the present invention, but are supplied at the beginning of one vertical scanning period (1F) and have a pulse width (H of about a half cycle of the clock signal CLY. The transfer start pulse DY having a level) is output as scanning signals G1, G2, G3,..., G864 in a form that is sequentially shifted every time the level of the clock signal CLY transitions (rises or falls), The display panel 100 is configured to perform vertical scanning.

Next, as shown in FIG. 6, the block selection circuit 140 is supplied with a transfer start pulse DX having a pulse width (H level) of about one cycle of the clock signal CLX while being supplied at the start of one horizontal scanning period. Each time the level of the clock signal CLX transitions, the signal is sequentially shifted, and the pulse width is narrowed and output as sampling signals S1, S2, S3,..., S192, and the display panel 100 is horizontally scanned.
The voltage corresponding to the H level of the scanning signal or sampling signal is the higher voltage Vdd of the power supply.
The voltage corresponding to the L level is the lower voltage Vss of the power supply, and this voltage Vss is the ground potential Gnd (voltage zero) (see FIG. 7).

The sampling circuit 150 is an aggregate of sampling switches 151 provided corresponding to each of the data lines 114. Each sampling switch 151 is, for example, an n-channel TFT, and its drain is connected to the data line 114.
Here, the sampling signals corresponding to the blocks are commonly supplied to the gates of the six sampling switches 151 corresponding to the data lines 114 belonging to the same block. For example, the sampling signal S4 corresponding to the block B4 is commonly supplied to the gates of the six sampling switches 151 corresponding to the 19th to 24th data lines 114 belonging to the block B4.

The source of the sampling switch 151 is connected to the data signals Vid1 to Vi according to the following relationship.
It is connected to one of the six image signal lines 171 supplied with d6.
That is, in the sampling switch 151 whose drain is connected to one end of the data line 114 in the j-th column from the left in FIG. 2, if the remainder obtained by dividing j by 6 is “1”, the source is the data Similarly, it is connected to the image signal line 171 to which the signal Vid1 is supplied, and similarly to the data line 114 whose remainders obtained by dividing j by 6 are “2”, “3”, “4”, “5”, “0”. The sampling switch 151 to which the drain is connected has its source connected to the data signal Vid2.
Each is connected to an image signal line 171 supplied with Vid6. For example, in FIG. 2, the source of the sampling switch 151 whose drain is connected to the data line 114 in the 23rd column has a remainder of “5” obtained by dividing “23” by 6; Connected to the signal line 171.
In addition, j is a code | symbol for demonstrating the row | line | column of the data line 114, and is 1 or more and 1152 or less integer in this embodiment.

Here, when a certain sampling signal becomes H level, the six sampling switches 151 of the block corresponding to the sampling signal are turned on, and the data signals Vid1 to Vid6 supplied to the image signal line 171 are supplied to the block. Sampling is performed on the data lines 114 belonging to six columns.

Returning to FIG. 1 again, the scanning control circuit 52 generates a transfer start pulse DX and a clock signal CLX from the dot clock signal Dclk, the vertical scanning signal Vs and the horizontal scanning signal Hs supplied from the host device, and blocks them. While controlling the horizontal scanning by the selection circuit 140, the transfer start pulse DY and the clock signal CLY are generated, and the scanning line driving circuit 13
This controls vertical scanning by zero. Further, the scanning control circuit 52 controls the phase expansion so as to synchronize with the horizontal scanning with respect to the above-described S / P conversion circuit 320, and specifies the writing polarity for the amplification / inversion circuit 350 by the signal Pol To do.

Next, the writing operation of the electro-optical device 10 will be described.
The present embodiment is characterized by the image correction circuit 330. Before describing the image correction circuit 330, the operation when the image correction circuit 330 does not exist and the problems associated with the operation will be described. In addition, when the image correction circuit 330 exists, how to solve the problem will be described in the flow.

FIG. 6 is a timing chart showing vertical and horizontal scanning of the electro-optical device 10 according to this embodiment, and FIG. 7 is a diagram showing an example of a voltage waveform of a data signal supplied over a continuous horizontal scanning period. .
As described above, the scanning signals G1, G2, G3,..., G864 are sequentially and exclusively set to the H level for each horizontal scanning period by the scanning line driving circuit 130 as shown in FIG.
In each horizontal scanning period, the image data Vid supplied in synchronization with the horizontal scanning is, first, S
/ P conversion circuit 320 distributes the signals to 6 channels, and expands 6 times with respect to the time axis. Second, each signal is converted into an analog signal by D / A conversion circuit group 340. Third, the analog If the signal is positive writing by the amplification / inversion circuit 350, the voltage Vc
Is output in the normal direction, and in the negative polarity writing, the output is inverted with reference to the voltage Vc.

Here, in the horizontal scanning period in which the scanning signal G1 is at the H level, assuming that writing is performed with a positive polarity, the data signal V by the amplification / inversion circuit 350 in the horizontal scanning period.
The voltages id1 to Vid6 become higher than the voltage Vc as the pixels are darkened (see FIG. 7).
On the other hand, in the horizontal scanning period in which the scanning signal G1 is at the H level, the transfer start pulse DX is sequentially shifted by the block selection circuit 140, and the pulse width is narrowed, so that the sampling signals S1, S2, S3,. Is output.

In the horizontal scanning period in which the scanning signal G1 is at the H level, the TFT 116 of the pixel 110 located on the scanning line 112 in the first row is in a conductive (on) state between the source and the drain. On the other hand, when the sampling signal S1 becomes H level, the data signals Vid1 to Vid6 are sampled on the data lines 114 in the first to sixth columns belonging to the block B1, respectively. Therefore, the sampled data signals Vid1 to Vid6 are pixels that intersect the first scanning line 112 counted from the top in FIG. 2 and the six (first to sixth columns counted from the left) data lines 114. The pixel electrodes 118 are applied respectively.
After this, when the sampling signal S2 becomes H level, this time, it belongs to the block B2.
The data signals Vid1 to Vid6 are sampled on the data line 114 in the twelfth column, respectively, and these data signals Vid1 to Vid6 are connected to the scanning line 112 in the first row and the seventh to seventh data lines 114, respectively.
This is applied to the pixel electrode 118 of each pixel intersecting the twelfth column data line 114.

In the same manner, when the sampling signals S3, S4,..., S192 sequentially become H level exclusively, the data signals Vid1 to Vid6 correspond to the six columns of data lines 114 belonging to the blocks B3, B4,. Are sampled, and these data signals Vid1 to Vid6 are respectively applied to the pixel electrodes 118 of the pixels intersecting the scanning lines 112 in the first row and the data lines 114 in the six columns. As a result, writing to all the pixels in the first row is completed. After that, even if the scanning signal G1 becomes L level and the TFT 116 is turned off, the written voltage is held by the pixel capacitor or the storage capacitor 109.

Subsequently, a period during which the scanning signal G2 is at the H level will be described. In the present embodiment, as described above, since polarity inversion is performed in units of scanning lines, negative polarity writing is performed in this horizontal scanning period.
On the other hand, the image data Vid designates the blackening of the pixel in the horizontal blanking period, but since the positive writing was performed in the immediately preceding horizontal effective display period, the data signals Vid1 to Vid6 are as shown in FIG. At a substantially central timing of this horizontal blanking period, a negative electrode that, when applied to the pixel electrode 118, causes the pixel to have the lowest gradation black from the positive voltage Vb (+) that causes the pixel to have the lowest gradation black. Switched to the voltage Vb (-).
In addition, referring to the relationship of the voltages in FIG. 7, when the voltages Vw (−) and Vg (−) are applied to the pixel electrode 118, the pixel is set to the highest gradation white and the intermediate gradation gray, respectively. Negative voltage. On the other hand, Vw (+) and Vg (+) are positive voltages that, when applied to the pixel electrode 118, cause the pixel to have the highest gray level and the intermediate gray level, respectively.
When the voltage Vc is used as a reference, there is a symmetrical relationship with Vw (−) and Vg (−).

The operation in the horizontal scanning period in which the scanning signal G2 is at the H level is the same as the horizontal scanning period in which the scanning signal G1 is at the H level, and the sampling signals S1, S2, S3,. Thus, writing to all the pixels in the second row is completed. However, since the horizontal scanning period in which the scanning signal G2 is at the H level is negative writing, the amplification / inversion circuit 350 applies the signal Vc distributed and expanded to 6 channels to the voltage Vc corresponding to the negative writing. Inverted with reference to output. For this reason, the voltage of the data signals Vid1 to Vid6 becomes lower than the voltage Vc as the pixels are darkened (see FIG. 7).

Similarly, the scanning signals G3, G4,..., G864 become the H level, the third row,
Writing is performed on the pixels in the fourth row,..., The 864th row. Thus, positive polarity writing is performed on the pixels in the odd-numbered rows, and negative polarity writing is performed on the pixels in the even-numbered rows. In this one vertical scanning period, the first to 864th rows are performed. Writing will be completed across all of the eye pixels.
The data signals Vid1 to Vid6 are substantially at the center timing of the horizontal blanking period.
When shifting from the horizontal effective display period of positive polarity writing to the horizontal effective display period of negative polarity writing, the voltage Vb (+) is changed to the voltage Vb (-), and the positive polarity is applied from the horizontal effective display period of negative polarity writing. When shifting to the horizontal effective display period of writing, the voltage Vb (−) is switched to the voltage Vb (+).
Further, similar writing is performed in the next one vertical scanning period, but at this time, the writing polarity with respect to the pixels in each row is switched. That is, in the next one vertical scanning period, the negative polarity writing is performed on the pixels in the odd-numbered rows, while the positive polarity writing is performed on the pixels in the even-numbered rows.
In this way, since the writing polarity for the pixel is switched every vertical scanning period, the liquid crystal 1
No direct current component is applied to 05, and deterioration of the liquid crystal 105 is prevented.

By the way, in the electro-optical device 10 in which the writing operation is executed in this way, the display area 10
When all the pixels 110 of 0a are displayed with the same gradation value, for example, gray, the vertical stripe-shaped unevenness is displayed as shown in FIG. As stated.
Examining the characteristics of the vertical streak-like unevenness, it occurs in units of 6 columns, which is the phase expansion period, but it is recognized that it occurs depending on the horizontal direction (horizontal scanning direction) of the screen. . For example, in the example shown in FIG. 9, in the left part of the screen, the pixel column corresponding to channel 3 is different in gradation from the other pixel columns, but the difference disappears in the central part of the screen. On the other hand, on the center side of the screen, the pixel column corresponding to channel 5 starts to differ from the gradation of the other pixel columns, and further, closer to the center, the pixel column corresponding to another channel 2 However, on the right side of the screen, the gradation difference in channels 2 and 5 disappears. Note that the display unevenness shown in FIG. 9 is merely an example.

Here, unevenness occurs in the vertical direction, which means that the voltage of the data signal to be sampled equally for each data line 114 is different from the other data lines 114 only for a specific data line 114. It shows that.
If the data line 114 where the unevenness occurs is not regular, a coefficient (correction coefficient) is stored in advance so as to correspond to all the data lines 114 in the 1st to 1152 columns, and the voltage of the data signal is corrected by the coefficient. Although a configuration is conceivable, in this configuration, the capacity required for the storage circuit for storing the coefficients increases.
In view of this, in the present embodiment, the image correction circuit 330 is configured to correct the voltage of the data signal by paying attention to the feature that causes the unevenness. In general, the image correction circuit 330 stores not only all the data lines 114 but only the coefficients corresponding to the data lines 114 belonging to the odd block, and when the odd block is selected, the selected odd block is selected. If the even block is selected, the coefficient of the selected even block is interpolated and calculated from the coefficient of the adjacent odd block genus. Thus, the data signal is corrected with the calculated coefficient.

A detailed configuration of the image correction circuit 330 will be described. FIG. 4 is a block diagram illustrating a configuration of the image correction circuit 330.
As shown in this figure, the image correction circuit 330 includes a readout circuit 3302 and a storage circuit 330.
4 and an interpolation circuit 3306. Among these, the storage contents of the storage circuit 3304 are as shown in FIG. 5, and the channels 1 to 6 in the odd blocks B1, B3, B5,.
Coefficients for positive polarity writing and negative polarity writing are stored for each. These coefficients are
At the time of inspection at the time of factory shipment, the display unevenness is intentionally generated without correction, and then the unevenness is set to be eliminated.

The read circuit 3302 designates an address for reading a coefficient corresponding to the write polarity from the storage circuit 3304, which is a block selected by the horizontal scanning signal Hs, the dot clock Dclk, and the signal Pol. is there.
Here, since six periods of the dot clock Dclk correspond to the block selection period, the readout circuit 3302 resets the count result by, for example, the horizontal scanning signal Hs and counts every time the dot clock Dclk counts six periods. Is counted up one by one, and the block selected at this time is known from the count result.

In principle, when the count result indicates that the block to be selected is an odd block, the read circuit 3302 has a coefficient corresponding to the write polarity designated by the signal Pol and the odd block. Read the channel. For example, when the block B3 is selected and the negative polarity writing is performed, the reading circuit 3302 receives coefficients k1-3b of channels (ch) 1 to 6 from the memory circuit 3304 as shown in FIG. Read ~ k6-3b. On the other hand, when the selected block is an even block, the read circuit 3302 reads the coefficients corresponding to the write polarity specified by the signal Pol, which are two odd blocks adjacent to the even block, for 12 channels. .
Exceptionally, when the final block B192 is selected, the reading circuit 3302 reads the coefficients corresponding to the writing polarity designated by the signal Pol in blocks B189 and B191 for 12 channels.
Further, the readout circuit 3302 notifies the interpolation circuit 3306 of the selected block number.

In principle, when the interpolation circuit 3306 is notified that the selected block is an odd number block, the coefficient of the channels 1 to 6 read from the storage circuit 3304 is k1 without performing any processing. If the selected block is notified that the selected block is an even block, the average value of the same channels among the coefficients read from the storage circuit 3304 is output for each channel 1 to 6. Calculate and output as coefficients k1 to k6. Thereby, the coefficient of the even block is calculated by internal interpolation from two odd blocks adjacent to the even block.
However, since the final block B192 has only one adjacent block (only the block B191), when it is notified that the selected block is the final block B192, the interpolation circuit 3306 is exceptionally used. Calculates the coefficient corresponding to the block B192 by externally interpolating the coefficients of the same channel in the blocks B189 and B191 for each of the channels 1 to 6, and outputs them as coefficients k1 to k6.

The image correction circuit 330 also includes a multiplier 3312 and an adder 3314 for each channel.
Here, the multiplier 3312 corresponding to the channel 1 outputs the multiplication value of the phase-expanded image data Vd1d and the coefficient k1 corresponding to the channel 1 as the correction value a1, and the adder 3314 corresponding to the channel 1 is output. The image data Vd1d is corrected with the correction value a1 and output as corrected image data Vd1a.
Therefore, the corrected image data Vd1a is corrected with the correction value a1 obtained by the function (multiplication) having the gradation value designated by the original image data Vd1d and the coefficient k1 as arguments. Further, the coefficient k1 is output according to the writing polarity regardless of whether the selected block is an odd number or an even number, so that the corrected image data Vd1a is output.
Is corrected to reflect the writing polarity.
The same applies to the other channels, and the corrected image data Vd2a to Vd6a are obtained by a function (multiplication) having gradation values specified by the original image data Vd2d to Vd6d and coefficients k2 to k6 as arguments. The correction values a2 to a6 are corrected.

Since the gradation values specified by the corrected image data Vd1a to Vd6a are corrected in a direction to eliminate display unevenness of the original image data Vd1d to Vd6d, the corrected image data Vd1a to Vd6a are converted to analog. When conversion is performed and normal rotation / inversion is performed in accordance with the writing polarity, sampling is performed on the data line 114 of the selected block and writing is performed on the pixel 110, display unevenness as illustrated in FIG. 9 is eliminated. .
That is, in this embodiment, the voltage of the data signals Vid1 to Vid6 distributed to each channel is corrected by the multiplier 3312, the adder 3314, the D / A conversion circuit group 340, and the amplification / inversion circuit 350 of each channel. The
Therefore, according to the present embodiment, as shown in FIG. 9, vertical streak-like unevenness that occurs depending on the horizontal scanning direction of the screen in units of 6 columns that are the phase expansion phase is stored in the storage circuit 330.
This can be solved with the storage capacity of 4 being reduced.

In the above-described embodiment, the odd-numbered block coefficient is stored in the storage circuit 3304. However, the even-numbered block coefficient is stored, and the odd-numbered block coefficient is obtained by interpolation from the adjacent even-numbered block coefficient. May be.
In the embodiment, the coefficient of odd-numbered blocks is stored, and the interval between the blocks to be stored is “2”, but may be “2” or more. For example, blocks B1, B5, B9,
The interval between the stored blocks such as B13,... May be “4”, or the interval may not be constant.

In the embodiment, the vertical scanning direction is G1 → G864 downward, and the horizontal scanning direction is S1 →
Although it was the right direction of S192, it is good also as a structure which can switch a scanning direction in order to cope with the case where it is set as the projector mentioned later and a rotatable display apparatus.
In the embodiment, the six lines of data lines 114 are blocked to generate image data Vd.
Although the phase expansion drive method for converting the channels to 1d to Vd6d is adopted, the number of channels and the number of data lines applied simultaneously (that is, the number of data lines belonging to one block) are not limited to “6”.
Further, the data signal supply circuit 300 processes the digital image data Vid, but may be configured to process an analog image signal. In the embodiment, the description has been given of the normally white mode in which white display is performed when the voltage effective value between the common electrode 108 and the pixel electrode 118 is small. However, a normally black mode in which black display is performed may be employed.

In the above-described embodiment, the TN type is used as the liquid crystal, but BTN (Bi-stable Twisted Ne) is used.
matic) and ferroelectric types such as bistable types with memory properties, polymer dispersed types, and dyes that have anisotropy in visible light absorption in the long and short axis directions of molecules (guests) ) May be dissolved in a liquid crystal (host) having a certain molecular arrangement, and a GH (guest host) type liquid crystal in which dye molecules are arranged in parallel with the liquid crystal molecules may be used.
In addition, the liquid crystal molecules are arranged in a vertical direction with respect to both substrates when no voltage is applied, while the liquid crystal molecules are arranged in a horizontal direction with respect to both substrates when a voltage is applied. The liquid crystal molecules are aligned in the horizontal direction with respect to both substrates when no voltage is applied, while the liquid crystal molecules are aligned in the vertical direction with respect to both substrates when a voltage is applied. It is good also as a structure. As described above, the present invention can be applied to various liquid crystal and alignment methods.

Next, as an example of an electronic apparatus using the electro-optical device according to the above-described embodiment, a projector using the above-described display panel 100 as a light valve will be described. FIG.
It is a top view which shows the structure of this projector. As shown in this figure, the projector 2
Inside the 100, a lamp unit 2102 made of a white light source such as a halogen lamp is provided. The projection light emitted from the lamp unit 2102 is separated into three primary colors of R (red), G (green), and B (blue) by three mirrors 2106 and two dichroic mirrors 2108 arranged inside. Light valves 100R and 100G corresponding to each primary color
And 100B, respectively. B light is compared with other R and G colors.
Since the optical path is long, the light is guided through a relay lens system 2121 including an incident lens 2122, a relay lens 2123, and an output lens 2124 in order to prevent the loss.

Here, the configuration of the light valves 100R, 100G, and 100B is the same as that of the display panel 100 in the above-described embodiment, and R, supplied from a processing circuit (not shown in FIG. 8).
It is driven by an image signal corresponding to each color of G and B. In other words, the projector 2100 has a configuration in which three sets of electro-optical devices including the display panel 100 are provided corresponding to the R, G, and B colors.
The lights modulated by the light valves 100R, 100G, and 100B are incident on the dichroic prism 2112 from three directions. In the dichroic prism 2112, the R and B light beams are refracted at 90 degrees, while the G light beam travels straight.
Therefore, after the images of the respective colors are combined, the projection lens 2114 is displayed on the screen 2120.
As a result, a color image is projected.

The light valves 100R, 100G, and 100B include a dichroic mirror 2
Since light corresponding to the primary colors of R, G, and B is incident by 108, there is no need to provide a color filter. Further, the transmission images of the light valves 100R and 100B are projected after being reflected by the dichroic mirror 2112, whereas the transmission image of the light valve 100G is projected as it is, so the horizontal scanning direction by the light valves 100R and 100B is The image is reversed in the horizontal scanning direction by the light valve 100G and displayed in an inverted image.

In addition to the electronic devices described with reference to FIG. 8, the electronic devices include a television, a viewfinder type / monitor direct-view type video tape recorder, a car navigation device, a pager, an electronic notebook, a calculator, a word processor, a workstation, a television. Examples include a telephone, a POS terminal, a digital still camera, a mobile phone, and a device equipped with a touch panel. Needless to say, the above-described electro-optical device can be applied to these various electronic devices.

1 is a block diagram illustrating a configuration of an electro-optical device according to an embodiment of the invention. FIG. 3 is a diagram showing a configuration of a display panel in the same electro-optical device. FIG. It is a figure which shows the structure of the pixel in the display panel. It is a figure which shows the structure of the data signal correction circuit in the same electro-optical device. It is a figure which shows the memory content of the memory in the data signal correction circuit. It is a figure for demonstrating the vertical and horizontal scanning of the same electro-optical apparatus. It is a figure for demonstrating the sampling in the same electro-optical apparatus. FIG. 2 is a diagram illustrating a configuration of a projector as an example of an electronic apparatus to which the electro-optical device is applied. It is a figure which shows the display nonuniformity which appears in the vertical direction.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 ... Display panel, 105 ... Liquid crystal, 110 ... Pixel, 112 ... Scan line, 114 ... Data line, 116 ... TFT, 118 ... Pixel electrode, 130 ... Scan line drive circuit, 140 ... Block selection circuit, 150 ... Sampling circuit, 151 ... Sampling switch 300 ... Data signal supply circuit 330 ... Image correction circuit 2100 ... Projector 3302 ... Reading circuit 3
304 ... Memory circuit, 3306 ... Interpolator, 3312 ... Multiplier, 3314 ... Adder

Claims (6)

Pixels corresponding to a plurality of scanning lines and a plurality of data lines, and having a gradation corresponding to the voltage of the data line when the scanning line is selected;
A scanning line driving circuit for selecting the scanning lines in a predetermined order;
A block selection circuit for sequentially selecting blocks composed of a plurality of data lines over a period in which the scanning lines are selected;
A plurality of data signals provided corresponding to the series of the number of data lines constituting the block and supplied with voltages corresponding to the gradations of the pixels corresponding to the selected scanning line and the data line belonging to the block, respectively. Image signal lines,
A data signal supply circuit for supplying a data signal to a display panel provided on each of the data lines and having a sampling switch for sampling the data signal supplied to the image signal line to the data line belonging to the selected block Because
A storage circuit for storing coefficients corresponding to blocks and series;
A readout circuit for reading out coefficients from the storage circuit for each series according to the block selected by the block selection circuit;
And a correction circuit that corrects the voltage of the data signal distributed to each series in a predetermined order with a correction amount defined by the coefficient of the corresponding series among the read coefficients. Signal supply circuit. The storage circuit stores a coefficient corresponding to a series corresponding to a smaller number of blocks than the block of the electro-optical device,
When the coefficient corresponding to the block selected by the block selection circuit is not stored in the storage circuit, the coefficient corresponding to the selected block is interpolated from the coefficient corresponding to the block adjacent to the selected block. The data signal supply circuit according to claim 1, further comprising an interpolation circuit to be calculated. The data signal supply circuit according to claim 1, wherein the correction circuit calculates a correction amount by using a function having a gradation value and a coefficient specified by a data signal before correction as arguments. Pixels corresponding to a plurality of scanning lines and a plurality of data lines, and having a gradation corresponding to the voltage of the data line when the scanning line is selected;
A scanning line driving circuit for selecting the scanning lines in a predetermined order;
A block selection circuit for sequentially selecting blocks composed of a plurality of data lines over a period in which the scanning lines are selected;
A plurality of images provided corresponding to each of the data lines constituting the block and supplying a data signal having a voltage corresponding to the gradation of the pixel corresponding to the selected scanning line and the data line belonging to the block. A signal line;
A data signal supply method for supplying a data signal to a display panel provided on each of the data lines and having a sampling switch for sampling the data signal supplied to the image signal line to the data line belonging to the selected block Because
Pre-store coefficients corresponding to blocks and series,
The coefficient corresponding to the selected block is read out for each series, and the voltage of the data signal distributed to each series in a predetermined order is corrected by the correction amount defined by the coefficient of the corresponding series to correspond. A method for supplying a data signal of an electro-optical device, comprising: supplying to a series of image signal lines. An electro-optical device having a display panel and a data signal supply circuit for supplying a data signal to the display panel,
The display panel is
Pixels corresponding to a plurality of scanning lines and a plurality of data lines, and having a gradation corresponding to the voltage of the data line when the scanning line is selected;
A scanning line driving circuit for selecting the scanning lines in a predetermined order;
A block selection circuit for sequentially selecting blocks composed of a plurality of data lines over a period in which the scanning lines are selected;
A plurality of data signals provided corresponding to the series of the number of data lines constituting the block and supplied with voltages corresponding to the gradations of the pixels corresponding to the selected scanning line and the data line belonging to the block, respectively. Image signal lines,
A sampling switch that is provided in each of the data lines and samples a data signal supplied to the image signal line to a data line belonging to a selected block;
Have
The data signal supply circuit includes:
A storage circuit for storing coefficients corresponding to blocks and series;
A readout circuit for reading out coefficients from the storage circuit for each series according to the block selected by the block selection circuit;
And a correction circuit that corrects the voltage of the data signal distributed to each series in a predetermined order with a correction amount defined by the coefficient of the corresponding series among the read coefficients. Optical device.   An electronic apparatus comprising the electro-optical device according to claim 5.

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