JP2006189722A - Electrooptical apparatus, data signal supply circuit, data signal supply method, and electronic equipment - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To suppress the generation of vertical stripes in a display region. <P>SOLUTION: According to a series of sampling signals respectively extracted by enable signals Enb1 to Enb4, the electrooptical apparatus is provided with a first correction circuit 310 for correcting the voltage of the data signal to be supplied to a data line according to a gradation value. A correction amount corresponding to the gradation value is considered to vary with write polarities in some cases and therefore the correction amount is divided to that for the positive polarity and that for the negative polarity. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a technique for preventing deterioration of display quality appearing in an electro-optical device.

  In recent years, projectors that form a small image using an electro-optical panel such as a liquid crystal and enlarge and project the small image using an optical system are becoming widespread. The projector does not have a function of creating an image by itself, and is supplied with image data (or an image signal) from a host device such as a personal computer or a TV tuner. This image data specifies the gradation (brightness) of the pixels, and is supplied in the form of vertical and horizontal scanning of the pixels arranged in a matrix, so that the display panel used in the projector is also this It is appropriate to drive according to the format. For this reason, in the display panel used in the projector, the scanning lines are selected one by one in a predetermined order, and the data lines are sequentially arranged one by one in a period during which one scanning line is selected (one horizontal scanning period). In general, driving is performed in a dot-sequential manner in which a data signal selected and converted so that image data is suitable for driving a liquid crystal is supplied to a selected data line.

On the other hand, recently, high definition of a display image is progressing like high vision. High definition can be achieved by increasing the number of scanning lines and the number of data lines, but since the frame frequency is fixed, the increase in the number of scanning lines shortens one horizontal scanning period, In the dot sequential method, the data line selection period is shortened by increasing the number of data lines. For this reason, in the dot sequential method, it becomes impossible to secure a sufficient time for supplying the data signal to the data line as the definition becomes higher, and writing to the pixels has started to be insufficient.
Therefore, a method called phase expansion drive has been devised for the purpose of eliminating the shortage of writing (see Patent Document 1). In this phase expansion drive, data lines are blocked every predetermined column, for example, every six columns, and blocks are selected one by one in a predetermined order in one horizontal scanning period, and six columns belonging to the selected block are selected. In this method, a data signal expanded to 6 times the time axis is supplied to each data line. In this phase development driving method, the time for supplying the data signal to the data line can be secured 6 times in this example as compared with the dot sequential method, and thus it is considered suitable for high definition. Yes.
JP 2000-112437 A

By the way, in such a phase expansion drive method, due to the configuration in which the blocks are selected one by one, vertical stripe-shaped unevenness, that is, the gradation of the pixels slightly differs every six columns corresponding to one block. As a result, the degradation of display quality has become conspicuous.
The present invention has been made in view of the above-described circumstances, and an object of the present invention is to provide an electro-optical device capable of suppressing a deterioration phenomenon of display quality during high definition, a data signal supply circuit of the electro-optical device, To provide a data signal supply method and an electronic apparatus.

  In order to achieve the above object, the present invention is provided at each intersection of a plurality of rows of scanning lines and a plurality of columns of data lines, and data signals are sampled on the data lines during a period in which the scanning lines are selected. When the scanning line is selected in a predetermined order and the scanning line is selected, the predetermined pulse signal is sequentially transmitted in accordance with a predetermined clock signal. A sampling signal defined by the pulse signal and sequentially transferred enable signals are output, and the data signal supplied to the image signal line is sampled on the data line according to the sampling signal. A first correction process is performed on the data signal on the display panel, and a data signal based on the corrected signal is supplied to the image signal line. In the data signal supply method, the first correction processing corrects the gradation specified by the data signal according to a predetermined relationship corresponding to each series of the enable signals. . According to the present invention, even if the timing, waveform, width, and the like of the sampling signal differ depending on the series of enable signals, the data signal sampled on the data line can be made uniform by the first correction process.

In the present invention, it is preferable that a negative polarity data signal on the lower side and a positive polarity data signal on the higher side are alternately supplied with a predetermined potential as a reference. In the case of supplying alternately, it is preferable that the first correction process corrects the gradation specified by the data signal corresponding to the positive polarity or the negative polarity of the data signal together with the series of enable signals.
When the data lines are alternately supplied, the data lines are divided into blocks every predetermined number, and the data signal is supplied via a predetermined number of image signal lines corresponding to the data lines belonging to one block. A sampling signal that samples the data signals supplied to the predetermined number of image signal lines to the data lines belonging to the same block at approximately the same time, and outputs the selected scanning lines and sampling signals to be located at both ends of the block. The pixel data signal corresponding to the intersection with the line may be subjected to a second correction process, and the second correction process may correct the gradation specified by the data signal for each polarity according to a predetermined relationship. . By correcting in this way, it is possible to suppress unevenness that occurs at the block boundaries.
The present invention can be conceptualized not only as a data signal supply method for an electro-optical device, but also as a data signal supply circuit, the electro-optical device itself, and also as an electronic apparatus having the electro-optical device.

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram illustrating the overall configuration of the electro-optical device according to the present embodiment.
As shown in this figure, the electro-optical device 10 is roughly divided into a processing circuit 50 and a display panel 100. Among these, the processing circuit 50 is a circuit module formed on a printed board, and is connected to the display panel 100 by an FPC (Flexible Printed Circuit) board or the like.

The processing circuit 50 includes a data signal supply circuit 300 and a control circuit 52. Of these, the former data signal supply circuit 300 further includes a first correction circuit 310, an S / P conversion circuit 320, and a second correction circuit. 331, 336, a D / A conversion circuit group 340, and an amplification / inversion circuit 350.
Although the details will be described later, the first correction circuit 310 converts the digital image data Vd supplied from a host device (not shown) into 6 pixels in synchronization with the vertical scanning signal Vs, the horizontal scanning signal Hs, and the dot clock signal DCLK. Four series of first correction processes are sequentially performed every minute and output as image data Vda. Here, the image data Vd is data that designates the gradation (brightness) of the pixel in the horizontal effective display period, and designates the pixel in the lowest gradation (black) in the horizontal blanking period. Note that the reason why a pixel is designated as the lowest gradation in the horizontal blanking period is mainly because the pixel does not contribute to display even if it is supplied to the pixel due to timing shift or the like.

The S / P conversion circuit 320 distributes the corrected image data Vda to 6 channels and expands the image data by 6 times on the time axis (phase expansion or serial-parallel conversion) to generate image data Vd1d to Vd6d. Is output as For convenience of explanation, the image data Vd1d to Vd6d are referred to as channels 1 to 6, respectively.
Here, the reason for serial-parallel conversion of the image data Vda is to secure a sample-and-hold time and a charge / discharge time by increasing a time during which a data signal is applied in a sampling switch described later.

  The second correction circuit 331 performs second correction processing on the converted image data Vd1d of channel 1 for each writing polarity, and outputs the result as image data Vd1f. . The second correction circuit 336 performs second correction processing on the converted image data Vd6d of the channel 6 for each writing polarity, and outputs the result as image data Vd6f. . The detailed configuration of the second correction circuits 331 and 336 will be described later.

The D / A conversion circuit group 340 is an aggregate of D / A converters provided for each channel, and converts the image data Vd1f, Vd2d to Vd5d, Vd6f into analog signals having voltages corresponding to the gradation values. To convert.
The amplifying / inverting circuit 350 performs normal rotation or polarity inversion on the analog-converted signal with reference to a voltage Vc described later, and supplies the signal to the display panel 100 as data signals Vid1 to Vid6.
Regarding polarity inversion, there are various modes such as (a) every scanning line, (b) every data signal, (c) every pixel, and (d) every surface (frame). ) It is assumed that the polarity is inverted for each scanning line. However, the present invention is not limited to this.
The voltage Vc is the amplitude center voltage of the image signal as shown in FIG. In the present embodiment, for the sake of convenience, for the data signals Vid1 to Vid6, the higher side than the amplitude center voltage Vc is referred to as positive polarity, and the lower side is referred to as negative polarity.
In this embodiment, the image data Vda is converted from analog to serial after parallel-to-parallel conversion. However, it is needless to say that analog conversion may be performed before serial-to-parallel conversion.

Here, the configuration of the display panel 100 will be described. The display panel 100 forms a predetermined image by electro-optic change, FIG. 2 is a block diagram showing an electrical configuration of the display panel 100, and FIG. 3 shows details of pixels of the display panel 100. FIG. The display panel 100 has a configuration in which an element substrate and a counter substrate on which a counter electrode is formed are bonded together with a certain gap, and liquid crystal is sealed in the gap.
As shown in FIG. 2, in the display panel 100, 864 rows of scanning lines 112 extend in the horizontal (horizontal) direction in the figure, while 1152 columns (= 192 × 6) data lines 114 are vertical (in the figure). It extends in the (vertical) direction. Pixels 110 are provided so as to correspond to the intersections between the scanning lines 112 and the data lines 114. Therefore, in this embodiment, the pixels 110 are arranged in a matrix of 864 rows × 1152 columns. However, the present invention is not limited to this.
In this embodiment, 1152 columns of data lines 114 are divided into blocks every six columns. For convenience of explanation, the first, second, third,..., 192th blocks from the left are denoted as B1, B2, B3,.

As for the detailed configuration of the pixel 110, as shown in FIG. 3, the source of an n-channel TFT (thin film transistor) 116 is connected to the data line 114, the drain is connected to the pixel electrode 118, and the gate Is connected to the scanning line 112.
Further, the common electrode 108 is provided in common to all the pixels so as to face the pixel electrode 118, and is maintained at the voltage LCcom supplied from the control circuit 52. A liquid crystal layer 105 is sandwiched between the pixel electrode 118 and the common electrode 108. Therefore, a liquid crystal capacitor composed of the pixel electrode 118, the common electrode 108, and the liquid crystal layer 105 is formed for each pixel.

Although not shown in particular, the opposing surfaces of both substrates are respectively provided with alignment films that have been rubbed so that the major axis direction of the liquid crystal molecules is continuously twisted between the substrates by, for example, about 90 degrees. A polarizer corresponding to the orientation direction is provided on each back side of the substrate.
If the effective voltage applied to the liquid crystal capacitance is zero, the light passing between the pixel electrode 118 and the common electrode 108 is rotated about 90 degrees along the twist of the liquid crystal molecules, while the effective voltage is As it increases, the liquid crystal molecules tilt in the direction of the electric field, and as a result, their optical rotation disappears. For this reason, for example, in a transmission type, when polarizers whose polarization axes are orthogonal to each other according to the alignment direction are arranged on the incident side and the back side, if the voltage effective value is close to zero, the light transmittance is While the maximum is white display, the amount of transmitted light decreases as the effective voltage value increases, and finally black display with the minimum transmittance is obtained (normally white mode).
Further, in order to reduce the influence of charge leakage from the liquid crystal capacitor via the TFT 116, the storage capacitor 109 is formed for each pixel. One end of the storage capacitor 109 is connected to the pixel electrode 118 (the drain of the TFT 116), and the other end is commonly grounded to, for example, the lower potential Vss of the power supply over all pixels.
Note that the TFT 116 in the pixel 110 is formed by a manufacturing process common to a scanning line driving circuit 130, a shift register 140, a sampling switch 151, and the like described below, and contributes to downsizing and cost reduction of the entire device. Yes.

  Subsequently, peripheral circuits such as a scanning line driving circuit 130 and a shift register 140 are provided around the pixel region. Among these, as shown in FIG. 6, the scanning line driving circuit 130 receives scanning signals G1, G2, G3,. The lines are supplied to the scanning lines 112 in the third, third,. The details of the scanning line driver circuit 130 are omitted because they are not directly related to the present invention, but are supplied at the beginning of one vertical scanning period (1F) and have a pulse width (H of about a half cycle of the clock signal CLY. A transfer start pulse DY having a level) is output as scanning signals G1, G2, G3,..., G864 in a form that is sequentially shifted every time the level of the clock signal CLY transitions (rises or falls). It has become.

  Next, as shown in FIG. 7, the shift register 140 supplies a transfer start pulse DX having a pulse width (H level) of about one cycle of the clock signal CLX while being supplied at the start of one horizontal scanning period. Each time the level of the clock signal CLX having a duty ratio of 50% transitions, the signal is sequentially shifted and output as signals F1, F2, F3,. Note that the signals F1, F2, F3,..., F96 are different from the scanning signals G1, G2, G3, G864 and are sequentially shifted by the half cycle of the clock signal CLX. Overlap each other (for example, signals F1 and F2). The first signal F1 is output so as to be at the H level when the clock signal CLX is at the H level and the subsequent L level.

The signal paths of the signals F1, F2,..., F96 by the shift register 140 branch left and right in the drawing, and an AND circuit (logic operation circuit) 142 is provided for each branch path. Here, if m is an integer of 1 to 96 and the number of stages of the signals F1, F2,..., F96 by the shift register 140 is not specified and generally expressed as Fm, m is an odd number (1, 3, 5, ..., 95), the AND circuit 142 corresponding to the left branch path in FIG. 2 of the supply path of the signal Fm uses the AND signal of the signal Fm and the enable signal Enb1 as the sampling signal S ( On the other hand, the AND circuit 142 corresponding to the right branch path outputs a logical product signal of the signal Fm and the enable signal Enb2 as the sampling signal S (2m).
When m is an even number (2, 4, 6,..., 96), the AND circuit 142 corresponding to the left branch path in FIG. 2 among the signal Fm supply paths is enabled with the signal Fm. While the logical product signal with the signal Enb3 is output as the sampling signal S (2m-1), the AND circuit 142 corresponding to the right branch path outputs the logical product signal of the signal Fm and the enable signal Enb4 to the sampling signal S. Output as (2m).
The sampling signals S (2m−1) and S (2m) are output corresponding to the blocks B (2m−1) and B (2m), respectively.

  Here, as shown in FIG. 7, the enable signals Enb1 to Enb4 have substantially the same pulse width period in which they are at the H level, do not overlap each other, and the phases of the pulses are 90 degrees from each other. There is a shifted relationship. Further, the pulses of the enable signals Enb4 and Enb1 are output in order during the period when the clock signal CLX is at the H level, and the pulses of the enable signals Enb2 and Enb3 are output in order during the period when the clock signal CLX is at the L level. Is done.

The sampling circuit 150 is an aggregate of sampling switches 151 provided corresponding to each of the data lines 114. Each sampling switch 151 is, for example, an n-channel TFT, and its drain is connected to the data line 114.
Here, the sampling signals corresponding to the blocks are commonly supplied to the gates of the six sampling switches 151 corresponding to the data lines 114 belonging to the same block. For example, the sampling signal S4 corresponding to the block B4 is commonly supplied to the gates of the six sampling switches 151 corresponding to the 19th to 24th data lines 114 belonging to the block B4.

Further, the source of the sampling switch 151 is connected to the image signal line 171 to which the data signals Vid1 to Vid6 are supplied in the following relationship.
That is, in the sampling switch 151 whose drain is connected to one end of the data line 114 in the j-th column from the left in FIG. 2, if the remainder obtained by dividing j by 6 is “1”, the source is the data Similarly, it is connected to the image signal line 171 to which the signal Vid1 is supplied, and similarly to the data line 114 whose remainders obtained by dividing j by 6 are “2”, “3”, “4”, “5”, “0”. The sampling switch 151 to which the drain is connected has its source connected to the image signal line 171 to which the data signals Vid2 to Vid4 are supplied.
For example, in FIG. 2, the source of the sampling switch 151 whose drain is connected to the data line 114 in the 23rd column has a remainder of “5” obtained by dividing “23” by 6; Connected to the signal line 171.

Returning to FIG. 1 again, the control circuit 52 generates a transfer start pulse DX and a clock signal CLX from the dot clock signal DCLK, the vertical scanning signal Vs, and the horizontal scanning signal Hs supplied from the host device to generate a shift register. In addition to controlling horizontal scanning by 140, a transfer start pulse DY and a clock signal CLY are generated to control vertical scanning by the scanning line driving circuit 130.
The control circuit 52 controls the phase expansion in the above-described S / P conversion circuit 320 in synchronization with the horizontal scanning, and outputs the signal PL for designating the writing polarity and the signal Md for designating the mode. .

Here, in the present embodiment, the mode includes a display mode that is a normal display operation and an adjustment mode for adjustment. In the adjustment mode, the control circuit 52 causes the voltage LCcom applied to the common electrode 108 to swing higher and lower than the value in the display mode. Note that the voltage LCcom in the display mode is set to be lower than the voltage Vc which is a reference for polarity inversion.
The amplification / inversion circuit 350 performs normal rotation on the signals converted by the D / A conversion circuit group 340 if the positive polarity writing is designated by the signal PL, while the negative polarity writing is performed by the signal PL. If specified, the polarity is inverted and output as data signals Vid1 to Vid6, respectively.

Next, the operation of the electro-optical device 10 will be described.
The present embodiment is characterized by the first correction circuit 310 and the second correction circuit 331 (336). Therefore, in the display mode, the operation when the first correction circuit 310 and the second correction circuit 331 (336) do not exist and the problems associated with the operation will be described, and then the first correction circuit 310 and the second correction circuit. An explanation will be given of the development of how to solve the problem when 331 (336) exists.

First, the operation when the first correction circuit 310 and the second correction circuit 331 (336) are not present, that is, the image data Vd is developed into the image data Vd1d to Vd6d without being subjected to the first correction process, and the image data Vd1d. The operation when Vd6d is D / A converted without being subjected to the second correction process will be described.
6 is a timing chart showing vertical scanning of the electro-optical device 10 according to the present embodiment, FIG. 7 is a timing chart showing horizontal scanning, FIG. 8 is a timing chart showing sampling, and FIG. These are figures which show the example of the voltage waveform of the data signal supplied over a continuous horizontal scanning period.

As described above, the scanning signals G1, G2, G3,..., G864 are sequentially exclusively exclusively H level for one horizontal effective period by the scanning line driving circuit 130 as shown in FIG.
Here, paying attention to the horizontal scanning period in which the scanning signal G1 is at the H level, the horizontal scanning period is divided into a horizontal blanking period and a subsequent horizontal effective display period. In the horizontal scanning period in which the scanning signal G1 is at the H level, writing is performed with positive polarity.
In the horizontal effective display period, the image data Vid supplied in synchronization with the horizontal scanning is first distributed to the six channels by the S / P conversion circuit 320 and expanded six times with respect to the time axis. Second, each signal is converted into an analog signal by the D / A converter circuit group 340. Third, the signal is output by the amplifier / inverter circuit 350 by rotating forward with reference to the voltage Vc corresponding to the positive polarity writing. The For this reason, the voltages of the data signals Vid1 to Vid6 by the amplifier / inverter circuit 350 become higher than the voltage Vc as the pixels are darkened (see FIG. 11).

On the other hand, in the horizontal scanning period in which the scanning signal G1 is at the H level, the transfer start pulse DX is sequentially shifted by the shift register 140 and output as signals F1, F2, F3,..., F96 as shown in FIG. The
Among these, when m is an odd number, the signal Fm branched to the left side is obtained by ANDing the enable signal Enb1 in the AND circuit 142, the pulse width is narrowed, and the sampling signal S (2m− On the other hand, the signal branched to the right side is output as 1), and the AND circuit 142 obtains the logical product with the enable signal Enb2, so that the pulse width is narrowed and output as the sampling signal S (2m).
Further, when m is an even number, the signal Fm branched to the left side is obtained by ANDing the enable signal Enb3 in the AND circuit 142, the pulse width is narrowed, and the sampling signal S (2m-1 ) Is output to the right side, and the AND circuit 142 obtains the logical product of the enable signal Enb4 and the pulse width is narrowed to be output as the sampling signal S (2m).
Here, the positive pulse widths of the enable signals Enb4 and Enb1 (the period when the clock signal CLX is at the H level) are included in the period when the clock signal CLX is at the H level, and the positive pulse widths of the enable signals Enb2 and Enb3 are the clock signal CLX. Are included in the period when the signal is at the L level, and the positive pulse widths are output so as not to overlap each other. Further, the signal F1 is output during a period in which the clock signal CLX first becomes H level and then L level after the transfer start pulse DX is supplied, and the phases of the enable signals Enb1 to Enb4 are shifted by 90 degrees. is doing. As a result, the sampling signals S1, S2, S3, S4,..., S192 are also output so that the positive pulse widths do not overlap as shown in FIG.

Here, in the horizontal scanning period in which the scanning signal G1 is at the H level, in the TFT 116 of the pixel 110 located in the scanning line 112 in the first row, the source and the drain are in a conductive (ON) state. On the other hand, when the sampling signal S1 becomes H level, the data signals Vid1 to Vid6 are sampled on the data lines 114 in the first to sixth columns belonging to the first block B1 from the left, respectively. Therefore, the sampled data signals Vid1 to Vid6 are pixels that intersect the first scanning line 112 counted from the top in FIG. 2 and the six (first to sixth columns counted from the left) data lines 114. The pixel electrodes 118 are applied respectively.
Thereafter, when the sampling signal S2 becomes H level, the data signals Vid1 to Vid6 are sampled on the data lines 114 of the 7th to 12th columns belonging to the second block B2, respectively, and these data signals Vid1 To Vid6 are respectively applied to the pixel electrodes 118 of the pixels intersecting with the scanning line 112 in the first row and the data lines 114 in the seventh to twelfth columns.

  In the same manner, when the sampling signals S3, S4,..., S192 are sequentially set to the H level, data is transferred to the six columns of data lines 114 belonging to the third, fourth,. The corresponding ones of the signals Vid1 to Vid6 are sampled, and these data signals Vid1 to Vid6 are respectively applied to the pixel electrodes 118 of the pixels intersecting with the scanning line 112 of the first row and the data lines 114 of the six columns. It will be. As a result, writing to all the pixels in the first row is completed. After that, even if the scanning signal G1 becomes L level and the TFT 116 is turned off, the written voltage is held by the liquid crystal capacitor or the storage capacitor 109.

Subsequently, a period during which the scanning signal G2 is at the H level will be described. In the present embodiment, as described above, since polarity inversion is performed in units of scanning lines, negative polarity writing is performed in this horizontal scanning period.
On the other hand, the image data Vid designates pixel blackening in the horizontal blanking period, but since the writing was positive in the immediately preceding horizontal effective display period, the data signals Vid1 to Vid6 are as shown in FIG. At the approximate center timing of the horizontal blanking period, when applied to the pixel electrode 118 of the pixel 110, the pixel is made the black of the lowest gradation from the positive voltage Vb (+) that makes the pixel the black of the lowest gradation. It switches to the negative polarity voltage Vb (-).
In addition, referring to the relationship of the voltages in FIG. 11, when the voltages Vw (−) and Vg (−) are applied to the pixel electrode 118 in the pixel 110, the pixel is set to the highest gradation white and intermediate gradation, respectively. It is a negative polarity voltage which makes it gray. On the other hand, Vw (+) and Vg (+) are positive voltages that, when applied to the pixel electrode 118 in the pixel 110, cause the pixel to have the highest gray level and the intermediate gray level, respectively. When the voltage Vc is used as a reference, there is a symmetrical relationship with Vw (−) and Vg (−).

  The operation in the horizontal scanning period in which the scanning signal G2 is at the H level is the same as the horizontal scanning period in which the scanning signal G1 is at the H level, and the sampling signals S1, S2, S3,. Thus, writing to all the pixels in the second row is completed. However, since the horizontal scanning period in which the scanning signal G2 is at the H level is negative writing, the amplification / inversion circuit 350 applies the signal Vc distributed and expanded to 6 channels to the voltage Vc corresponding to the negative writing. Inverted with reference to output. For this reason, the voltage of the data signals Vid1 to Vid6 becomes lower than the voltage Vc as the pixels are darkened (see FIG. 11).

Similarly, the scanning signals G3, G4,..., G864 become H level, and writing is performed on the pixels in the third row, fourth row,. Thus, positive polarity writing is performed on the pixels in the odd-numbered rows, and negative polarity writing is performed on the pixels in the even-numbered rows. In this one vertical scanning period, the first to 864th rows are performed. Writing will be completed across all of the eye pixels.
Note that the data signals Vid1 to Vid6 are supplied from the voltage Vb (+) when shifting from the horizontal effective display period of positive polarity writing to the horizontal effective display period of negative polarity writing at substantially the center timing of the horizontal blanking period. When shifting from the horizontal effective display period for negative polarity writing to the horizontal effective display period for positive polarity writing, the voltage Vb (−) is switched to the voltage Vb (+).
Further, similar writing is performed in the next one vertical scanning period, but at this time, the writing polarity with respect to the pixels in each row is switched. That is, in the next one vertical scanning period, the negative polarity writing is performed on the pixels in the odd-numbered rows, while the positive polarity writing is performed on the pixels in the even-numbered rows.
In this way, since the writing polarity for the pixels is switched every vertical scanning period, a direct current component is not applied to the liquid crystal layer 105, and deterioration of the liquid crystal layer 105 is prevented.

  By the way, in the present embodiment, the signal F1 output from the shift register 140 is divided by the enable signals Enb1 and Enb2 to be the sampling signals S1 and S2, respectively. Similarly, the signal F2 is divided by the enable signals Enb3 and Enb4. The sampling signals are S3 and S4, respectively. Specifically, when m is an odd number, the signal Fm is divided by the enable signals Enb1 and Enb2, and when m is an even number, the signal Fm is divided by the enable signals Enb3 and Enb4, respectively. In other words, the sampling signal S (2m−1) is a portion of the pulse (H level) of the signal Fm in the temporally forward portion. On the other hand, the sampling signal S (2m) is extracted from the temporally rear portion of the same signal Fm pulse.

  In the configuration of the present embodiment, when resistance or capacitance is parasitic on the supply path of the transfer start pulse DX or the clock signal CLX in the FPC board that connects the processing circuit 50 and the display panel 100 or the display panel 100 itself, the shift register 140 In addition to the dull waveform of the transfer start pulse DX and the clock signal CLX at the time of reaching, the signal Fm shifted by these signals also has a dull waveform as shown in FIG. In FIG. 9, the time axis is expanded as compared with FIG. 7 for convenience of explanation.

When the sampling signal S (2m-1) extracted at the front portion in time is compared with the sampling signal S (2m) extracted at the rear portion in time from the signal Fm in which the waveform becomes blunt. As shown in FIG. 9, there is a difference in waveform shape, particularly a difference in H level potential (Cause 1).
On the other hand, even when the enable signals Enb1 to Enb4 are in a phase-shifted state by 90 degrees at the time of output of the control circuit 52, differences in supply paths of the enable signals Enb1 to Enb4 on the FPC board and the display panel and parasitic Due to the capacitance or the like, there may be a deviation in the phase relationship due to the difference in delay time at the input time of the AND circuit 142 (Cause 2). In such a case, it is considered that the uniformity of the waveform and pulse width of the sampling signal is lost or the output timing is slightly shifted.

Here, when a sampling signal having two different differences is supplied to the gate of the sampling switch 151, even if the voltages of the data signals Vid1 to Vid6 supplied to the image signal line 171 are the same, the actual data The voltage sampled on line 114 differs between what is sampled by one sampling signal and what is sampled by another sampling signal. Since this difference is nothing but the difference in the effective voltage value of the liquid crystal capacitance, it appears as a difference in transmittance in the pixel 110, that is, a gradation difference.
In particular, in the present embodiment, since one sampling signal drives the sampling switches 151 corresponding to six columns of data lines 114 at the same time, the period of gradation difference is 6 pixels, which is very conspicuous.

The enable signals Enb1 to Enb4 are the first to fourth series, respectively. Here, if the cause 1 is dominant, the sampling signals S1, S5, S9,..., S189 extracted by the first sequence enable signal Enb1, and the sampling signal S3 extracted by the third sequence enable signal Enb3 are extracted. , S7, S11,..., S199 tend to be similar, sampling signals S2, S6, S10,..., S190 extracted by the second series of enable signals Enb2 and extraction by the fourth series of enable signals Enb4. The sampling signals S4, S8, S12,..., S192 that are output tend to be similar, but the sampling signals extracted by the first and third series of enable signals and the second and fourth series of enable signals Since there is a difference in tendency between the sampling signals extracted in step B1, the blocks B1, B3, B ,..., B191 and the gradations of the pixels belonging to blocks B2, B4, B6,..., B192 appear as differences between the gradations of the pixels belonging to blocks B2, B4, B6,. Should appear.
On the other hand, if cause 2 is dominant, a difference occurs between the sampling signals extracted by the first, second, third, and fourth series of enable signals. The block should appear as one period.
The actual display tendency of the display panel 100 is that there is a large difference between the gradation of the pixels belonging to the odd blocks and the gradation of the pixels belonging to the even blocks, and the pixels and blocks belonging to the blocks B1, B5, B9,. .., B191 have small gradation differences from the pixels belonging to B3, B7, B11,..., B191. Similarly, pixels belonging to blocks B2, B6, B10,..., B190 and pixels belonging to blocks B4, B8, B12,. A phenomenon appears in which the above-mentioned causes 1 and 2 are combined, that is, the difference in gradation is small.

  In any case, the difference in the series of enable signals is considered to be a difference in the waveform of the sampling signal and the like, causing a gradation difference. For this reason, when a measure for eliminating such a tone difference for each series is examined, even if the sampling signal is different for each series, the voltage of the data signal finally sampled on the data line is different between the series. The image data Vd should be corrected in advance so that they match with each other (when the gradation of each pixel is the same).

In the present embodiment, the first correction circuit 310 in FIG. 1 executes the first correction process for correcting the image data Vd in accordance with the series of enable signals. FIG. 4 is a block diagram showing a detailed configuration of the first correction circuit 310 in FIG.
In this figure, a signal Ed is a signal supplied from the control circuit 52, and when the data signal after phase development of the image data Vd supplied from the host device is sampled according to the sampling signal, the sampling is performed. The signal is a signal indicating which series of enable signals the shift signal from the shift register 140 is extracted from.
The selector (demultiplexer) 3102 selects the output terminal A when the signal Ed indicates the first series of enable signals Enb1, and is the second, third, and fourth series of enable signals. In the case shown, the output terminals B, C, and D are selected, respectively, and the image data Vd is output to the selected output terminal.

The control circuit 52 generates the signal Ed from the image data Vd supplied from the higher-level device by the following method.
First, for example, when the image data Vd specifies the gradation of the pixel in the nth column counting from the left in FIG. 2, the value obtained by incrementing the quotient obtained by dividing (n−1) by 6 by 1 is the block number. When the block number is divided by 4 and the remainder becomes “1”, the sampling signal extracted by the first series of enable signals Enb1 is used, and the remainder is “2” and “3”. , “0” uses sampling signals extracted by second, third, and fourth series enable signals, respectively. For example, when the image data Vd specifying the gradation value of the pixel in the 1130th column is supplied, the quotient obtained by dividing (1130-1) by 6 is “188”, and this is incremented by “189”. Is the block number, and when the block number “189” is divided by 4, the remainder is “1”. Therefore, the data signal based on the image data corresponding to the pixels in the 1130th column is the first series of enable signals. The data line is sampled according to the sampling signal extracted at Enb1.
Further, the column of the image data Vd is determined by counting the dot clock DCLK after the image data Vd corresponding to the pixel of the first column is supplied.
Therefore, the control circuit 52 obtains a block number from the count result, obtains a remainder obtained by dividing the block number by “4”, and generates a signal Ed according to the remainder.

The conversion table 3111 stores correction data in advance corresponding to the positive polarity and the negative polarity for each gradation value specified by the image data Vd corresponding to the first series. Here, the conversion table 3111 corresponds to the gradation value specified by the image data Vd when the signal PL indicates that the image data Vd is converted into a positive data signal after phase expansion. When the correction data corresponding to the positive polarity is output and the image data Vd is converted into the negative polarity data signal after the phase expansion, the level specified by the image data Vd is output. Correction data corresponding to the tone value and corresponding to the negative polarity is output.
The conversion tables 3112, 3113, and 3114 correspond to the second, third, and fourth series, respectively. Like the conversion table 3111, for each gradation value specified by the image data Vd, positive polarity and Correction data is stored in advance corresponding to each of the negative polarity, and correction data corresponding to the gradation value specified by the image data Vd and corresponding to the polarity specified by the signal PL is output. .
Here, the correction data of the conversion tables 3111, 3112, 3113, and 3114 are, for example, values in a state where the display difference is the smallest among the pixels of each series when the correction amount is gradually changed from the zero correction state. That is, even if the sampling signal is different for each series, the correction value is such that the voltage of the data signal finally sampled on the data line is matched between the series, and is previously obtained experimentally and stored in advance. It is a thing.

The adder 3121 adds the image data Vd output when the output terminal A is selected by the selector 3102 and the correction data output from the conversion table 3111, and outputs the result as image data Vd1. Similarly, the adders 3122 (3123, 3123) are output from the image data Vd output when the output terminal B (C, D) is selected by the selector 3102 and the conversion table 3112 (3113, 3114), respectively. The correction data is added and output as image data Vd2 (Vd3, Vd4).
When the signal Ed indicates that sampling is performed according to the sampling signal extracted by the first series of enable signals Enb1 when the image data Vd supplied from the host apparatus is phase-expanded by the signal Ed. When input terminal A is selected and sampling is indicated according to the sampling signals extracted by the second, third, and fourth series of enable signals, input terminals B, C, and D are selected, respectively. Then, the image data supplied to the selected input terminal is output as the image data Vda subjected to the first correction process.

The operation of the first correction circuit 310 having such a configuration will be described.
The selector 3102 selects an output end corresponding to the sequence specified by the signal Ed, and the selector 3104 selects an input end corresponding to the sequence specified by the signal Ed.
When the output terminal A and the input terminal A corresponding to the first series are selected, the image data Vd supplied from the host device is corrected by the conversion table 3111 and the adder 3121. That is, in the conversion table 3111, correction data corresponding to the gradation specified by the image data Vd and corresponding to the polarity specified by the signal PL is read, and the correction data and the image data Vd are added to each other. 312 is added.
Similarly, when the output terminal B and the input terminal B (the output terminal C and the input terminal C, the output terminal D and the input terminal D) corresponding to the second (third, fourth) series are selected, Similarly, the image data Vd supplied from the apparatus is corrected by the conversion table 3112 and the adder 3122 (conversion table 3113 and adder 3123, conversion table 3114 and adder 3124).

Here, the correction data output from the conversion table 3111 (3112 to 3114) is subjected to phase conversion of the image data Vd and converted into a data signal having the polarity specified by the signal PL, and supplied to the image signal line 171. In addition, when the output signal of the shift register 140 is sampled on the data line 114 according to the sampling signal extracted by the first (second to fourth) series of enable signals, the voltage of the data signal sampled on the data line is It is a value that matches each series.
Therefore, according to the present embodiment, when the first correction process causes the display panel 100 to display with the same gradation over a wide area, the display unevenness due to the above causes 1 and 2 is eliminated. It becomes possible to suppress.

Note that the correction data output from the conversion tables 3111 to 3114 may be multiplied by a coefficient that gradually changes from the beginning to the end of the horizontal scanning period. The reason for this is that the delay and the waveform dullness of the enable signals Enb1 to Enb4 are considered to gradually increase from the block B1 to B192 when viewed at the input terminal of the AND circuit 142, and the supply path of the clock signal CLX is also considered. This is because the same can be said.
Further, if the conversion tables 3111 to 3114 are configured to output the corrected image data directly instead of the correction data to be added to the image data, the adders 3121 to 3124 can be omitted.

In the present embodiment, the gradation difference caused by the difference in the enable signal for each series is suppressed to some extent by the first correction circuit 310 executing the first correction process. However, this time, the display quality may be degraded based on a cause that is completely different from the above causes 1 and 2.
Therefore, this cause will be examined below. In the present embodiment, the voltage LCcom applied to the common electrode 108 in the display mode is set to be lower than the voltage Vc that is a reference for polarity inversion. This is because the influence of the push-down of the TFT constituting the so-called sampling switch 151 is taken into consideration. Briefly explaining this pushdown, the voltage held on the drain side decreases when the gate voltage (sampling signal) of the TFT changes from the H level to the L level (when turning off from on). . This cause is particularly due to parasitic capacitance between the gate and the source, and becomes more prominent as the source voltage is lower.

The effect of this pushdown is illustrated as a waveform. For example, when focusing on one pixel, in order to make the pixel gray, the voltages Vg (+) and Vg (−) are alternately written as the data signal every vertical scanning period. The voltage waveform of the electrode 118 is as shown in FIG.
That is, the TFT 116 is turned on over one horizontal scanning period in which the pixel is selected, but the sampling switch 151 of the data line corresponding to the pixel is only in the period in which the block corresponding to the pixel is selected in the horizontal scanning period. Turns on. For this reason, the sampling switch 151 is turned off during the horizontal scanning period.
Therefore, the data signal sampled on the data line 114 is affected by push-down when the sampling switch 151 is turned off. Furthermore, as shown in this figure, the pushdown immediately after writing the negative gray equivalent voltage Vg (-) is more than the pushdown immediately after writing the positive gray equivalent voltage Vg (+). growing.
Therefore, when the voltage Vc, which is a reference for polarity inversion, is applied to the common electrode 108, the effective voltage of the liquid crystal capacitance is larger in the negative polarity writing than in the positive polarity writing. A direct current component is applied. To avoid this, the voltage LCcom applied to the common electrode 108 is lower than the voltage Vc so that the effective voltage value applied to the liquid crystal capacitance is equal even if the pushdown amount differs in polarity. It is set to.
Here, a voltage LCcom in which effective voltages of both polarities are equal to each other when a voltage having a symmetrical relationship with respect to the voltage Vc is written in the positive polarity writing and the negative polarity writing is particularly referred to as an optimum LCcom. I will decide.

On the other hand, when the arrangement pitch of the data lines 114 is narrow, a certain data line has a higher degree of capacitive coupling with a data line adjacent thereto.
In the present embodiment, a phase expansion drive method is adopted in which six columns of data lines are made into blocks and selected together. In this phase development driving method, when a certain block is selected, when the data line of each of the data lines (data lines corresponding to channels 2 to 5) other than both ends of the block changes its voltage (data When the signal is sampled), the adjacent data lines on both sides also change voltage simultaneously. On the other hand, regarding the data lines at the both ends of the block (data lines corresponding to channels 1 and 6), when the voltage of the data line of its own changes, the voltage of the adjacent data line on one side changes simultaneously. The adjacent data lines on the side do not change in voltage. For this reason, this is equivalent to an increase in the additional capacity, and the pushdown amount is compressed in the data lines at both ends of the block as compared with the data lines at the portions other than both ends of the block (FIG. 13A and FIG. b)).
For this reason, the pixels at both ends of the block differ in the effective voltage value of the liquid crystal capacitance as compared with the pixels at the portions other than both ends of the block. Therefore, even if display is performed with the same gradation, the gradation of the pixels at both ends of the block is different from the gradation of the pixels at the portions other than both ends of the block. Here, the difference in gradation of the pixel occurs along both ends of the block, so that it appears as a vertical stripe in the display area 100a.

Therefore, a measure for eliminating such vertical stripes will be examined. As described above, the main cause of the vertical stripe is that the pushdown amount in the data lines at both ends of the block is different from the pushdown amount in the data lines at portions other than both ends of the block. For this reason, even if the pushdown amount in the data lines at both ends of the block is different from the pushdown amount in the data lines at the portions other than both ends of the block, the voltages finally held (after the pushdown) match. It should be a good configuration. The following two types are assumed as such a configuration.
That is, the image data (or data signal) is corrected so that the voltage finally held in the data lines at the portions other than both ends of the block matches the voltage finally held at the data lines at both ends of the block. In contrast, in the plan (1), conversely, the image data (in order that the voltage finally held in the data lines at both ends of the block coincides with the voltage finally held in the data lines at the portions other than both ends of the block. Alternatively, there are two plans (2) for correcting the data signal).
Among these, in the former plan (1), the data signals of the majority channels 2 to 5 are corrected, and the voltage LCcom needs to be readjusted. In this embodiment, the plan (2) Is adopted.

  The second correction circuit 331, 336 in FIG. 1 is a specific example of such a plan (2). Among these, the correction circuit 331 uses the voltage finally held on the data line corresponding to the channel 1 in the both ends of the block, and the voltage finally held on the data lines of the channels 2 to 5 other than both ends of the block. The correction circuit 336 corrects the voltage finally held by the data line corresponding to the channel 6 among the both ends of the block so that it matches the channel 2 other than both ends of the block. The image data Vd6d is corrected so as to match the voltage finally held by the data lines ˜5.

Since the second correction circuits 331 and 336 have substantially the same configuration, the details of the second correction circuit 331 will be described with reference to FIG.
In this figure, the selector (demultiplexer) 3312 selects the output terminal A when the positive polarity writing is designated by the signal PL, while the output terminal A is selected when the negative polarity writing is designated by the signal PL. B is selected, and the image data Vd1d subjected to the first correction process and phase expanded is output to the selection side.
The conversion table 3322 corresponds to the case of positive writing, and stores correction data for each gradation value specified by the image data Vd1d. Here, when the display mode is designated by the signal Md, the conversion table 3322 reads out and outputs correction data corresponding to the gradation value designated by the image data Vd1d, while the adjustment mode is designated by the signal Md. In this case, regardless of the stored contents, a correction amount zero value is output as correction data, and correction data stored in correspondence with a certain gradation value is output from adjustment unit 3316 described later. Change to Px.
The adder 3324 adds the image data Vd1d directly output from the selector 3312 and the correction data output from the conversion table 3322 and outputs the result.

Further, when the adjustment mode is designated by the signal Md, the adjuster 3316 generates and outputs positive adjustment data Px and negative adjustment data Mx under the control of the control circuit 52, respectively. To do. On the other hand, the adjuster 3316 outputs zero data as the adjustment data Px and Mx when the display mode is designated by the signal Md.
The adder 3326 adds the addition data from the adder 3324 and the adjustment data Px from the adjuster 3316 and supplies the result to the input terminal A of the selector 3314.

  On the other hand, the conversion table 3332 corresponds to negative polarity writing, and stores correction data for each gradation value specified by image data. Here, when the display mode is designated by the signal Md, the conversion table 3332 reads out and outputs correction data corresponding to the gradation value designated by the image data Vd1d, while the adjustment mode is designated by the signal Md. In this case, regardless of the stored contents, a correction amount zero value is output as correction data, and correction data stored in correspondence with a certain gradation value is output from adjustment unit 3316 described later. Change to Mx.

The adder 3334 adds the directly output image data Vd1d output from the selector 3312 and the correction data output from the conversion table 3332 and outputs the result. The adder 3336 adds the addition data from the adder 3334 and the adjustment data Mx from the adjuster 3316 and supplies the result to the input terminal B of the selector 3314.
The selector (multiplexer) 3314 selects the input terminal A when the positive polarity writing is designated by the signal PL, and selects the input B when the negative polarity writing is designated by the signal PL. Data supplied to the selected input terminal is supplied as corrected image data Vd1f.
The correction circuit 336 corresponding to the channel 6 has the same configuration as that in FIG. 5, and supplies the image data Vd6d subjected to the first correction process and phase-expanded as corrected image data Vd6f.

Here, the operation in the adjustment mode will be described. This adjustment mode is a mode for storing / updating correction data corresponding to the gradation value in the conversion tables 3322 and 3324. In the adjustment mode, for example, a CCD camera or the like is installed on the display surface of the display panel 100, and the actually displayed screen is subjected to image processing and inspected (the configuration is not shown). In this adjustment mode, the operations of the first to fourth steps are repeated for each gradation value K ₄ , K ₈ , K ₁₂ .
In the present embodiment, as shown in FIG. 10A, the lowest gradation (black) of the pixel is the gradation value K ₀ and the highest gradation (white) of the pixel is the gradation value K _16. It is assumed that the gradation between them is defined by the gradation values K _{1 to} K ₁₅ . Therefore, the gradation corresponding to the gradation value K _8, which corresponds exactly to the middle between the lowest gradation and the highest gradation. The gradation value K ₄ corresponds to an intermediate between the lowest gradation and a gradation value K _8, the tone value K ₁₂ corresponds to the middle between the tone value K ₈ and the highest gradation.

First, a description will be given first to fourth steps for the gray-scale value _{K 8.} Incidentally, in the first to fourth steps of the gradation value K _8, the image data Vd supplied from the host device becomes all the pixels to those specified in the gradation corresponding to the gradation value K _8.
First, in the first step, the control circuit 52 controls the adjuster 3316 of the correction circuit 331 (336) so that the values of the adjustment data Px and Mx are zero.
In the correction circuit 331 (336), when positive polarity writing is designated by the signal PL, the selector 3312 selects the output terminal A, and the selector 3314 selects the input terminal A. Therefore, the image data Vd1d is converted into the conversion table 3322. , Via adders 3324 and 3326. However, in the adjustment mode, since the conversion table 3322 outputs zero correction amount data regardless of the gradation specified by the image data Vd, the addition result by the adder 3324 is the phase-developed image data Vd1d itself. It is. In addition, in the adjustment mode, the adder 3326 gives the addition result of the image data Vd1d and the adjustment data Px, which is the addition result by the adder 3324. At this stage, the adjustment data Px is zero, so the image data Vd1d. Is supplied to the input terminal A of the selector 3314 as it is.

On the other hand, when negative polarity writing is designated by the signal PL, the selector 3312 selects the output terminal B, and the selector 3314 selects the input terminal B, so that the image data Vd1d is converted into the conversion table 3332 and the adders 3334, 3336. However, the image data Vd1d is supplied to the input terminal B of the selector 3314 as it is for the same reason as when the positive polarity writing is designated.
Therefore, in the first step, the corrected image data Vd1f (Vd6f) output from the selector 3314 is the image data Vd1d (Vd6d) itself, and the voltage waveform applied to the pixel electrode 118 of each pixel is shown in FIG. As shown in a). That is, the voltage waveform itself is the same as the waveform of FIG. FIG. 14A shows that the gradation value K _{8 corresponds} to the data signal voltage Vg (+) in the positive polarity and to the data signal voltage Vg (−) in the negative polarity. Yes.

  In the first step, the control circuit 52 shifts the voltage LCcom to be applied to the common electrode 108 to a higher side than the optimum LCcom as shown in FIG. When the voltage LCcom is shifted to the higher side in this manner, the effective voltage due to negative polarity writing increases, whereas the effective voltage due to positive polarity writing decreases. Here, since the final gradation of the pixel is determined by the effective voltage value in units of two vertical scanning periods over the negative polarity writing and the positive polarity writing, the smaller effective voltage value in the writing polarity. It will be greatly influenced by. For this reason, when the voltage LCcom is shifted to the higher side, an effective voltage difference in positive polarity writing mainly appears as a gradation difference.

  As described above, the pushdown amount generated in the data lines at both ends of the block is compressed more than the pushdown amount generated in the data lines at portions other than both ends of the block. Are larger than the pixels other than the ends of the block, and become darker in terms of gradation (normally white mode). For this reason, in the display by the display panel 100, vertical stripes appearing darker than gray appear.

Next, as a second step, the control circuit 52 causes the adjuster 3316 of the second correction circuit 331 corresponding to channel 1 to gradually increase the values of the adjustment data Px and Mx from zero at the same pace. On the other hand, the controller 3316 of the second correction circuit 336 corresponding to the channel 6 is controlled to maintain the values of the adjustment data Px and Mx at zero.
The addition result of the adder 3326 (3336) is a value obtained by adding the adjustment data Px (Mx) to the image data Vd1d (Vd6d) in the adjustment mode. For this reason, when the values of the adjustment data Px and Mx increase, the addition result of the adder 3326 (3336) also increases, so that the corrected image data Vd1f changes in the direction of increasing the gradation of the pixel. .
Accordingly, the pixels corresponding to the data line of the channel 1 in the vertical stripe gradually become brighter, so the gradation is substantially the same as the pixels corresponding to the data lines of the channels 2 to 5, and a part of the vertical stripe is There is a timing to resolve. When it becomes clear from the result of image processing on the display screen of the display panel 100 that the same gradation has been obtained, the control circuit 52 sends the adjustment data Px and the adjustment data Px to the adjuster 3316 of the second correction circuit 331 corresponding to the channel 1. the increase in Mx with stops, the adjustment data Px at that time, the stored contents are stored or updated as correction data P ₈ corresponding to the gradation value K ₈ positive polarity writing. As a result, the correction data P ₈ corresponding to the gradation value K ₈ of the positive polarity writing is obtained in the second correction circuit 331 of the channel 1 (see FIG. 10B).

Similarly, the control circuit 52 controls the adjuster 3316 of the second correction circuit 336 corresponding to the channel 6 so that the values of the adjustment data Px and Mx are gradually increased at the same pace. When it is determined from the result of image processing on the display screen of the display panel 100 that the pixel corresponding to the data line of the channel 6 has the same gradation as the pixel corresponding to the data line of the channels 1 to 5, the control is performed. The circuit 52 causes the adjuster 3316 of the second correction circuit 336 corresponding to the channel 6 to stop increasing the adjustment data Px and Mx, and uses the adjustment data Px at that time as the gradation value K for positive polarity writing. _The stored content is stored or updated as correction data corresponding to ₈ . Thus, in the second correction circuit 336 of the channel 6 the correction data corresponding to the tone value K ₈ of the positive polarity writing is obtained.

Next, in the third step, the control circuit 52 causes the adjuster 3316 of the second correction circuit 331 (336) to set the values of the adjustment data Px and Mx to zero.
In the third step, the control circuit 52 shifts the voltage LCcom to be applied to the common electrode 108 to a lower side than the optimum LCcom as shown in FIG. If the voltage LCcom is shifted to the lower side in this way, the effective voltage due to the negative polarity writing decreases, while the effective voltage due to the positive polarity writing increases conversely. A large voltage difference mainly appears as a gradation difference. For this reason, in the display by the display panel 100, vertical stripes appearing brighter than gray are displayed.

Next, as a fourth step, the control circuit 52 causes the adjuster 3316 of the second correction circuit 331 corresponding to the channel 1 to gradually decrease the values of the adjustment data Px and Mx from zero at the same pace. On the other hand, the controller of the correction circuit 336 corresponding to the channel 6 is controlled so as to maintain the values of the adjustment data Px and Mx at zero. For this reason, when the values of the adjustment data Px and Mx are lowered, the addition result of the adder 3326 (3336) is substantially the subtraction result, and thus the corrected image data Vd1f is in the direction of darkening the gradation of the pixel. Will change.
Accordingly, the pixels corresponding to the data line of the channel 1 in the vertical stripe gradually become dark, so that the gradation is substantially the same as the pixels corresponding to the data lines of the channels 2 to 5, and a part of the vertical stripe is There is a timing to resolve. When it becomes clear from the result of image processing on the display screen of the display panel 100 that the same gradation has been obtained, the control circuit 52 sends the adjustment data Px and the adjustment data Px to the adjuster 3316 of the second correction circuit 331 corresponding to the channel 1. the reduction of Mx with stops, against the conversion table 3332, adjustment data Px corresponding to the gradation value K ₈ of the negative polarity writing correction is stored or updated stored contents to the data M ₈ at that time. As a result, the correction data M ₈ corresponding to the gradation value K ₈ of negative polarity writing is obtained in the second correction circuit 331 of the channel 1.

Similarly, the control circuit 52 controls the adjuster 3316 of the second correction circuit 336 corresponding to the channel 6 so that the values of the adjustment data Px and Mx are gradually decreased at the same pace. When it is determined from the result of image processing on the display screen of the display panel 100 that the pixel corresponding to the data line of the channel 6 has the same gradation as the pixel corresponding to the data line of the channels 1 to 5, the control is performed. The circuit 52 causes the adjuster 3316 of the second correction circuit 336 corresponding to the channel 6 to stop the decrease of the adjustment data Px and Mx, and writes the adjustment data Px at that time to the conversion table 3332 with negative polarity writing. the stored contents are stored or updated to the correction data corresponding to the gray-scale value K _8. Accordingly, it becomes possible to correct the data corresponding to the tone value K ₈ of the negative polarity writing is obtained in the second correction circuit 336 of the channel 6.

Similar first to fourth steps are similarly repeated. That is, supplied with image data Vd specifying the gray scale value K _4, the first to fourth steps of the gradation value K ₄ is running, the supply of the image data Vd specifying the gray scale value K ₈ receiving, the first to fourth steps of the gradation value K ₈ is executed.
Thus, in the second correction circuit 331,336 of the channels 1, 6, the tone value _{K 4,} the positive correction data _{P 4, P 12} that correspond to _{K 12,} the negative correction data _{M 4, M 12} And is obtained. Among these, the positive correction data P ₄ and P ₁₂ are stored in the conversion table 3322, while the negative correction data M ₄ and M ₁₂ are stored in the conversion table 3332 (FIG. 10B). )reference).

At this stage, in the second correction circuits 331 and 336 of the channels 1 and 6, positive correction data P ₄ , P ₈ and P ₁₂ corresponding to the gradation values K ₄ , K ₈ and K ₁₂ , and negative polarity Only correction data M ₄ , M ₈ and M ₁₂ were obtained. Therefore, the control circuit 52 obtains correction data corresponding to other positive tone values by interpolation from the already obtained correction data P ₄ , P ₈ , P ₁₂ and stores them in the conversion table 3322. The correction data corresponding to other gradation values for the negative polarity is obtained by interpolation from the already obtained correction data M ₄ , M ₈ , M ₁₂ and stored in the conversion table 3332. Accordingly, for example, the positive correction data P _{0 to} P ₁₆ corresponding to each of the gradation values K _{0 to} K ₁₆ are stored in the conversion table 3322 with the characteristics shown in FIG. Negative correction data M _{0 to} M ₁₆ corresponding to each of the gradation values K _{0 to} K ₁₆ are stored in the conversion table 3332. Needless to say, this interpolation operation is executed in both channels 1 and 6.

In this embodiment, K ₄ , K ₈ , and K ₁₂ are selected as representative gradation values, but any gray range that is close to the intermediate value may be used. The reason is that the voltage-transmission (reflectance) characteristic of the liquid crystal is the steepest in gray, and an effective voltage difference tends to appear as a display difference. In other words, the gradation range in the vicinity of the lower limit gradation value K ₀ and the upper limit gradation value K ₁₆ hardly appears as a display difference even if the effective voltage difference is large. This is difficult to use as a gradation value.

Next, the operation of the second correction circuit 331 (336) in the display mode will be described. In the display mode, a normal display operation is assumed, and a CCD camera or the like in the adjustment mode is not particularly required.
First, when positive polarity writing is designated by the signal PL, the selector 3312 selects the output terminal A, and the selector 3314 selects the input terminal A. Therefore, the image data Vd1d (Vd6d) is converted into the conversion table 3322, the adder. Corrections are made along the routes 3324 and 3326.
In this path, in the conversion table 3322, positive correction data corresponding to the gradation designated by the image data Vd1d (Vd6d) is read, and the correction data and the image data Vd1d (Vd6d) are added to the adder 3324. Is added. Since the adjustment data Px is zero in the display mode, the corrected image data Vd1f (Vd6f) is eventually obtained by adding positive correction data to the image data Vd1d (Vd6d).
On the other hand, when negative polarity writing is designated by the signal PL, the selector 3312 selects the output terminal B and the selector 3314 selects the input terminal B, so that the image data Vd1d (Vd6d) is converted into the conversion table 3332, the adder. Correction is performed in the paths 3334 and 3336.
In this path, in the conversion table 3332, negative-polarity correction data corresponding to the gradation specified by the image data Vd1d (Vd6d) is read, and the correction data and the image data Vd1d (Vd6d) are added to the adder 3324. Is added by. Since the adjustment data Mx is zero in the display mode, the corrected image data Vd1f (Vd6f) is eventually obtained by adding negative correction data to the image data Vd1d.

  In the present embodiment, as described above, both the positive correction data and the negative correction data have the voltage finally held by the data line of the channel 1 (6) as the data lines of the channels 2 to 5. Since the image data Vd1d (Vd6d) is corrected so as to coincide with the voltage finally held in step S1, the pixels are displayed when the display panel 100 displays the same gradation in a large area. As a result, the voltages finally written in FIG. 8 are matched, so that occurrence of vertical streak-like unevenness in the display panel 100 is suppressed.

In the above-described embodiment, after obtaining correction data corresponding to representative gradation values in the adjustment mode, correction data corresponding to other gradation values is obtained by interpolation, and the conversion table 3322 (3332) is used. While the correction data is stored for each gradation value, in the display mode, the correction data corresponding to the gradation value specified by the image data is read from the conversion table 3322 (3332). good.
That is, correction data corresponding to a representative gradation value is obtained in the adjustment mode, and only this correction data is stored in the conversion table 3322 (3332). In the display mode, the gradation value specified by the image data is If it is stored in the conversion table 3322 (3332), it is read out, but if it is not stored in the conversion table 3322 (3332), it may be obtained by interpolation from the stored correction data of gradation values. .
That is, the interpolation may be executed in the adjustment mode as in the embodiment, or may be executed in the display mode.
In the configuration in which the interpolation is performed in the adjustment mode as in the embodiment, the calculation delay associated with the interpolation need not be considered in the display mode, but the storage capacity required for the conversion table 3322 (3332) increases. On the other hand, in the configuration in which the interpolation is performed in the display mode, the storage capacity required for the conversion table 3322 (3332) can be reduced, but it is necessary to take into account the delay in calculation associated with the interpolation in the display mode.

  In the embodiment, since the capacitance is parasitic on each data line 114, when the data signal is sampled in the horizontal effective display period, the voltage of the data signal remains until just before the next sampling. Therefore, in the horizontal blanking period, each data line 114 is precharged to a predetermined voltage, the remaining voltage component is cleared, and the condition for sampling the data signal on the data line 114 in the horizontal effective display period is made uniform. Anyway.

FIG. 15 shows an example in which the data line is precharged with a voltage close to the voltage LCcom before the positive polarity writing, while the data line is precharged with a voltage close to zero before the negative polarity writing. .
When such precharge is executed, as shown in the figure, when a certain block is selected, the data line corresponding to channel 1 in the block changes from the precharge potential to the write potential.
Here, the data line located on the right side of the data line is less affected by the voltage change of the data line because the voltage changes simultaneously with the data line, but the data line located on the left side is already Since the signal sampling is completed, the signal line is affected by the voltage change.
Therefore, when the horizontal scanning direction is the right direction, a voltage change in the data line of channel 1 in a certain block causes a data line on the left side (specifically, in a block selected immediately before that block). The voltage of the data line (channel 6) fluctuates.
For this reason, the data line of the channel 6 fluctuates not only by pushdown but also by the precharge voltage.

In the embodiment, the voltage LCcom of the common electrode 108 is shifted to the higher level in the first step of the adjustment mode, and the voltage LCcom is shifted to the lower level in the third step. The reason why the voltage LCcom is shifted to the higher side in the first step is to make the effective voltage difference in the positive polarity appear as a display difference, and the reason why the voltage LCcom is shifted to the lower side in the third step. This is because an effective voltage difference in the negative polarity appears as a display difference.
In order to make such an effective voltage difference in the positive / negative polarity appear as a display difference, the following method can be cited in addition to the configuration in which the voltage LCcom is shifted to the higher side / lower side. It is done. That is, in the first step of the adjustment mode, the image data Vd is replaced with data designating the lowest gradation (the gradation at which the effective voltage is the highest) during negative polarity writing. If replaced in this way, the voltage waveform applied to the pixel electrode 118 is equivalent to the case where the voltage LCcom is shifted to the higher side as shown in FIG. Difference appears as a display difference. Similarly, in the third step of the adjustment mode, the image data Vd is replaced with data designating the lowest gradation at the time of positive polarity writing. If replaced in this way, the voltage waveform applied to the pixel electrode 118 is equivalent to the case where the voltage LCcom is shifted to the lower side as shown in FIG. Difference appears as a display difference.
Note that the gradation for replacement in this way is not limited to the lowest gradation, but may be a gradation in the vicinity thereof and a gradation that exhibits the same effect. Specifically, if the luminance of the lowest gradation is 0%, the gradation range corresponding to the luminance of 10% or less may be used.

  In the embodiment, the positive correction data is obtained in the first and second steps and the negative correction data is obtained in the third and fourth steps. However, the negative correction data is obtained in the first and second steps. The correction data may be obtained, and positive correction data may be obtained in the third and fourth steps.

  By the way, as shown in FIG. 2, the display panel 100 has a configuration in which a pulse signal having an overlapping portion of the shift register 140 is branched and is extracted as an enable sampling signal Enb1 to Enb4 and output as a sampling signal. When one correction process is considered, as shown in FIGS. 17 and 18, pulse signals that are sequentially output are extracted in a plurality of series (two series in FIGS. 17 and 18) and output as sampling signals. It is good also as composition to do. Even in this configuration, the first correction circuit 310 may be corrected corresponding to each series.

In the embodiment described above, the image data is corrected by the first correction circuit 310 and the second correction circuits 331 and 336, but the image data Vd for one frame is stored in a frame memory or the like, and the signal stored in the memory is stored. Alternatively, the corrected image data may be sequentially output from the frame memory after the correction is performed collectively. In this case, it is suitable to perform correction calculation using a CPU.
Further, in the embodiment, the vertical scanning direction is the downward direction of G1 → G864 and the horizontal scanning direction is the right direction of S1 → S192. However, when a projector or a rotatable display device described later is used, scanning is performed. Need to reverse direction.

Further, if the supply method of the image data Vd is changed, the selection order of the scanning lines is not necessarily the order of the first, second, third,..., 864th row, for example, 1, 3, 5,. 2, 4, 6,..., 864, or may be scanned in an interlaced manner, or 1, 433, 2, 434, 3, 435,. The areas may be alternately selected and each area may be scanned sequentially from the top. That is, after a certain scanning line is selected, it is only necessary that another scanning line is selected and all the scanning lines are selected as a result in a certain unit period (vertical scanning period).
In the embodiment, since the positive polarity writing is performed in one vertical scanning period and the negative polarity writing is performed in the next one vertical scanning period, the AC driving cycle is two vertical scanning periods. Of course, the AC drive may be performed periodically.

  In the embodiment described above, the phase expansion drive method is adopted in which the six data lines 114 are blocked and converted into six channels of image data Vd1d to Vd6d. However, the number of channels and the number of data lines applied simultaneously (that is, the number of data lines applied simultaneously) The number of data lines belonging to one block) is not limited to “6”. Further, if it is limited to the first correction process, dot sequential driving may be used.

  On the other hand, in the above-described embodiment, the data signal supply circuit 300 processes the digital image data Vd. However, the data signal supply circuit 300 may be configured to process an analog image signal. Furthermore, in the above-described embodiment, the description has been given of the normally white mode in which white display is performed when the effective voltage value between the common electrode 108 and the pixel electrode 118 is small. However, the normally black mode in which black display is performed may be used. good.

In the above-described embodiment, the TN type is used as the liquid crystal. However, a bistable type having a memory property such as a BTN (Bi-stable Twisted Nematic) type or a ferroelectric type, a polymer dispersed type, or a molecular length A dye (guest) having anisotropy in the absorption of visible light in the axial direction and the minor axis direction is dissolved in a liquid crystal (host) having a certain molecular arrangement, and the dye molecule is arranged in parallel with the liquid crystal molecule (GH) A guest-host type liquid crystal may be used.
In addition, the liquid crystal molecules are arranged in a vertical direction with respect to both substrates when no voltage is applied, while the liquid crystal molecules are arranged in a horizontal direction with respect to both substrates when a voltage is applied. The liquid crystal molecules are aligned in the horizontal direction with respect to both substrates when no voltage is applied, while the liquid crystal molecules are aligned in the vertical direction with respect to both substrates when a voltage is applied. It is good also as a structure. As described above, the present invention can be applied to various liquid crystal and alignment methods.

  Next, as an example of an electronic apparatus using the electro-optical device according to the above-described embodiment, a projector using the above-described display panel 100 as a light valve will be described. FIG. 19 is a plan view showing the configuration of the projector. As shown in this figure, a lamp unit 2102 made of a white light source such as a halogen lamp is provided inside the projector 2100. The projection light emitted from the lamp unit 2102 is separated into three primary colors R (red), G (green), and B (blue) by three mirrors 2106 and two dichroic mirrors 2108 arranged inside. Are guided to the light valves 100R, 100G and 100B corresponding to the respective primary colors. Note that B light has a longer optical path than other R and G colors. Therefore, in order to prevent the loss, B light passes through a relay lens system 2121 including an incident lens 2122, a relay lens 2123, and an exit lens 2124. Led.

Here, the configuration of the light valves 100R, 100G, and 100B is the same as that of the display panel 100 in the above-described embodiment, and images corresponding to the R, G, and B colors supplied from the processing circuit (not shown in FIG. 19). Each is driven by a signal. That is, in this projector 2100, three sets of electro-optical devices including the display panel 100 are provided corresponding to each color of R, G, and B, and the display unevenness on the display panel of each color is corrected so as to be inconspicuous. It is the composition which becomes.
The lights modulated by the light valves 100R, 100G, and 100B are incident on the dichroic prism 2112 from three directions. In the dichroic prism 2112, the R and B light beams are refracted at 90 degrees, while the G light beam travels straight. Therefore, after the images of the respective colors are combined, a color image is projected onto the screen 2120 by the projection lens 2114.

  Since light corresponding to the primary colors R, G, and B is incident on the light valves 100R, 100G, and 100B by the dichroic mirror 2108, it is not necessary to provide a color filter as described above. The transmitted images of the light valves 100R and 100B are projected after being reflected by the dichroic mirror 2112, whereas the transmitted image of the light valve 100G is projected as it is, so the horizontal scanning direction by the light valves 100R and 100B is The image is reversed in the horizontal scanning direction by the light valve 100G and displayed in an inverted image.

  In addition to the electronic device described with reference to FIG. 19, the electronic device includes a television, a viewfinder type / monitor direct-view type video tape recorder, a car navigation device, a pager, an electronic notebook, a calculator, a word processor, a workstation, a television. Examples include a telephone, a POS terminal, a digital still camera, a mobile phone, and a device equipped with a touch panel. Needless to say, the display panel according to the present invention is applicable to these various electronic devices.

1 is a block diagram illustrating an overall configuration of an electro-optical device according to an embodiment of the invention. 3 is a diagram showing a configuration of a display panel in the same electro-optical device. FIG. It is a figure which shows the structure of the pixel of the display panel. It is a figure which shows the structure of the 1st correction circuit in the same electro-optical apparatus. It is a figure which shows the structure of the 2nd correction circuit in the same electro-optical apparatus. FIG. 6 is a diagram for explaining a vertical scanning operation of the electro-optical device. It is a figure for demonstrating operation | movement of the horizontal scanning of the same electro-optical apparatus. It is a figure for demonstrating the sampling in the same electro-optical apparatus. It is a figure for demonstrating the difference of a sampling signal. It is a figure which shows the content of the conversion table in a 2nd correction circuit. FIG. 6 is a diagram for explaining an operation of the electro-optical device. It is a figure for demonstrating pushdown. It is a figure for demonstrating the change of the holding voltage of the data line by the difference in pushdown. It is a figure which shows the shift of the voltage LCcom in a 1st, 3rd step. It is a figure for demonstrating the influence which the fluctuation | variation from a precharge electric potential changes to a write electric potential. It is a figure for demonstrating the effect equivalent to the shift of the voltage LCcom. It is a figure which shows the structure of the display panel which concerns on the modification of this invention. It is a figure for demonstrating the operation | movement of the horizontal scanning which concerns on a modification. FIG. 2 is a diagram illustrating a configuration of a projector as an example of an electronic apparatus to which the electro-optical device is applied.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 10 ... Electro-optical apparatus, 50 ... Processing circuit, 52 ... Control circuit, 100 ... Display panel, 112 ... Scan line, 114 ... Data line, 116 ... TFT, 118 ... Pixel electrode, 130 ... Scanning line drive circuit, 140 ... Shift Register 151, sampling switch 171 image signal line 300 data signal supply circuit 310 first correction circuit 331 336 second correction circuit 2100 projector

Claims (8)

Provided at the intersections of a plurality of rows of scanning lines and a plurality of columns of data lines, respectively, and when the data signal is sampled on the data line during the period when the scanning line is selected, the gradation corresponding to the data signal With the pixel
Selecting the scan lines in a predetermined order;
When the scanning line is selected, a predetermined pulse signal is sequentially transferred according to a predetermined clock signal,
Output a sampling signal defined by the sequentially transferred pulse signal and a predetermined plurality of series of enable signals,
Sampling the data signal supplied to the image signal line on the data line according to the sampling signal on the display panel,
A data signal supply method for performing a first correction process on the data signal and supplying a data signal based on the corrected signal to the image signal line,
The first correction process includes
A method of supplying a data signal of an electro-optical device, wherein a gradation specified by the data signal is corrected in a predetermined relationship corresponding to each series of the enable signals. 2. The data signal supply of the electro-optical device according to claim 1, wherein a negative polarity data signal on a lower side and a positive polarity data signal on a higher side are alternately supplied with a predetermined potential as a reference. Method. The first correction process corrects a gradation specified by the data signal corresponding to a positive polarity or a negative polarity of the data signal, together with a series of enable signals. Data signal supply method for electro-optical device. The data lines are blocked every predetermined number,
The data signal is supplied through a predetermined number of image signal lines corresponding to each of the data lines belonging to one block,
With one sampling signal, the data signals supplied to the predetermined number of image signal lines are sampled substantially simultaneously on the data lines belonging to the same block,
A second correction process is performed on the data signal of the pixel corresponding to the intersection of the selected scanning line and the sampling signal output and the data line located at both ends of the block;
The second correction process includes
The method of supplying a data signal for an electro-optical device according to claim 2, wherein the gradation specified by the data signal is corrected for each polarity according to a predetermined relationship. Provided at the intersections of a plurality of rows of scanning lines and a plurality of columns of data lines, respectively, and when the data signal is sampled on the data line during the period when the scanning line is selected, the gradation corresponding to the data signal And a pixel
A scanning line selection circuit for selecting the scanning lines in a predetermined order;
A shift register for sequentially transferring a predetermined pulse signal according to a signal of a predetermined clock when the scanning line is selected;
A circuit that outputs a sampling signal defined by sequentially transferred pulse signals and a predetermined plurality of series of enable signals;
A sampling switch provided on each of the data lines and configured to sample the data signal supplied to the image signal line on the data line according to the sampling signal;
A data signal supply circuit that performs a first correction process on the data signal and supplies the corrected data signal to the image signal line,
The data signal supply circuit of the electro-optical device, wherein the first correction processing corrects a gradation specified by the data signal according to a predetermined relationship corresponding to each series of the enable signals. 6. The data signal supply of an electro-optical device according to claim 5, wherein a negative polarity data signal on the lower side and a positive polarity data signal on the higher side are alternately supplied with a predetermined potential as a reference. circuit. Provided at the intersections of a plurality of rows of scanning lines and a plurality of columns of data lines, respectively, and when the data signal is sampled on the data line during the period when the scanning line is selected, the gradation corresponding to the data signal And a pixel
A scanning line selection circuit for selecting the scanning lines in a predetermined order;
A shift register for sequentially transferring a predetermined pulse signal according to a signal of a predetermined clock when the scanning line is selected;
A circuit that outputs a sampling signal defined by sequentially transferred pulse signals and a predetermined plurality of series of enable signals;
A first correction process for the data signal, and a data signal supply circuit for supplying the corrected data signal to the image signal line;
A sampling switch that is provided on each of the data lines and samples the data signal supplied to the image signal line on the data line according to the sampling signal;
The electro-optical device according to claim 1, wherein the first correction processing corrects a gradation specified by the data signal in a predetermined relationship corresponding to each series of the enable signals.   An electronic apparatus comprising the electro-optical device according to claim 7.

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