JP2007017564A - Electro-optical device, driving method and electronic equipment - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To suppress decrease in display quality when a phase expansion driving system is employed. <P>SOLUTION: A TFT 1820 serving as a sampling switch is disposed on each data line 114 and samples a data signal supplied to any image signal line 170 onto the data line when the switch is turned on. The data lines 114 are grouped by each four lines. One sampling signal is supplied to adjacent two groups, and when a sampling signal is output, continuous four sampling switches among eight sampling switches belonging to the two groups are simultaneously turned on. The combination of four sampling switches to be simultaneously turned on is shifted in the right direction by one line in one frame by signals Sel1 to Sel8 supplied to a selection line 182. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

The present invention relates to a technique for suppressing deterioration in display quality when a so-called phase expanded data signal is sampled.

In recent years, projectors that form a small reduced image by using a display panel such as a liquid crystal and enlarge and project the small reduced image by an optical system are becoming widespread. The projector does not have a function of creating an image by itself, and is supplied with image data (or an image signal) from a host device such as a personal computer or a TV tuner. This image data specifies the gradation (brightness) of the pixels, and is supplied in the form of vertical and horizontal scanning of the pixels arranged in a matrix, so that the display panel used in the projector is also this It is appropriate to drive according to the format. For this reason, in a display panel used in a projector, scanning lines are selected one by one in a predetermined order, and data lines are selected one by one in order in a period in which one scanning line is selected. In general, driving is performed in a dot sequential manner in which a data signal converted to be suitable for driving a liquid crystal is supplied to a selected data line.

On the other hand, recently, high definition of a display image is progressing like high vision. High definition can be achieved by increasing the number of scanning lines and the number of data lines, but since the frame frequency is fixed, the increase in the number of scanning lines shortens one horizontal scanning period. Furthermore, in the dot sequential method, the data line selection period is shortened by increasing the number of data line columns. For this reason, in the dot sequential method, it becomes impossible to secure a sufficient time for supplying the data signal to the data line as the definition becomes higher, and writing to the pixels has started to be insufficient.
Therefore, a method called phase expansion drive has been devised for the purpose of eliminating the shortage of writing (see Patent Document 1). In this phase expansion drive, the data lines are grouped into predetermined columns, for example, every four columns (6 columns in Patent Document 1), and four columns are selected in a predetermined order in one horizontal scanning period. In this method, the data signals expanded four times with respect to the time axis are respectively supplied to the four data lines. In this phase development driving method, the time for supplying the data signal to the data line can be secured four times in this example as compared with the dot sequential method, so it was considered suitable for high definition. .
JP 2000-112437 A

By the way, in such a phase development driving method, vertical streak-like unevenness in which the gradation of the pixel is slightly different for every four columns selected at the same time has occurred, and the deterioration in display quality has become conspicuous. .
The present invention has been made in view of the above-described circumstances, and an object of the present invention is to provide an electro-optical device, a driving method, and an electronic device capable of suppressing deterioration in display quality when a phase expansion driving method is employed. To provide equipment.

In order to achieve the above object, in the present invention, a plurality of scanning lines and m (m is an integer of 2 or more).
Provided corresponding to a plurality of data lines grouped for each book, each of which has a gradation corresponding to a data signal sampled on the data line when the scanning line is selected; A scanning line driving circuit for selecting a plurality of scanning lines in a predetermined order; a sampling signal output circuit for sequentially outputting a plurality of sampling signals corresponding to the group; and m image signal lines for supplying the data signals; A sampling switch that is provided in each of the data lines and samples a data signal supplied to one of the image signal lines in an ON state on the data line;
When one sampling signal is supplied to two adjacent groups and the sampling signal is output, m consecutive sampling switches among 2m sampling switches belonging to the two groups are simultaneously turned on. And a block changing circuit that changes a combination of m sampling switches that are simultaneously turned on by the sampling control circuit in a predetermined order every predetermined period. . According to the present invention, it is avoided that m blocks sampled simultaneously are fixed.

In the present invention, among the two groups to which one sampling signal is supplied, (2m-1) sampling switches belonging to one group are supplied with the sampling signal output next to the sampling signal 2 A configuration in which (2m-1) sampling switches belonging to the other group among the two groups is preferable.
In the present invention, it is also preferable that the block changing circuit shifts m sampling switches one frame at a time.
On the other hand, the block changing circuit divides the 2m selection lines into two, and outputs control signals so as to alternately become exclusive levels with respect to the m selection lines divided into two. At the same time, the combination of m selection lines to be divided may be changed in a predetermined order at regular intervals. In this configuration, the sampling control circuit further includes: a logical sum circuit for obtaining a logical sum signal between two sampling signals for each sampling switch; and the logical sum signal and any one of the 2m control signals. An AND circuit that obtains an AND signal and indicates an ON or OFF state may be used.
In addition, a processing circuit for supplying a data signal of a pixel corresponding to the intersection of the selected scanning line and a data line for which the ON state of the sampling switch is designated to the m image signal lines,
Furthermore, it is good also as a structure which has.
In addition to the electro-optical device, the present invention can be conceptualized as a driving method of the electro-optical device, and also as an electronic apparatus having the electro-optical device.

Embodiments of the present invention will be described below with reference to the drawings.
In the phase development driving method described above, the cause of vertical streak-like unevenness in the cycle of the number of columns selected at the same time is because the block of the data line that simultaneously writes the data signal through the data line is fixed. The present inventor thought.
Therefore, in the embodiment described below, the data line block in which the data signal is simultaneously written is changed over a plurality of frames (vertical scanning period) via the data line, thereby making it difficult to visually recognize vertical stripe-shaped unevenness. It is intended.

An electro-optical device according to an embodiment of the invention will be described. FIG. 1 is a block diagram showing the overall configuration of the electro-optical device.
As shown in this figure, the electro-optical device 10 is roughly divided into a processing circuit 50 and a display panel 100. Among these, the processing circuit 50 is a circuit that controls the operation of the display panel 100 and the like, and is a circuit module mounted on a printed circuit board. The display panel 100 is an FPC.
(Flexible Printed Circuit) Connected by a substrate or the like.

The processing circuit 50 further includes a scanning control circuit 52, a line memory 310, and an S / P conversion circuit 3.
20, a D / A conversion circuit group 330 and a polarity inversion circuit 340.
The line memory 310 stores one line of image data Vin supplied from a host device (not shown) in synchronization with the vertical scanning signal Vs, the horizontal scanning signal Hs, and the dot clock signal Dclk, and then the scanning memory 52 It is read according to the instruction and output as image data Vout. Here, the image data Vin (Vout) is digital data for designating the gradation (brightness) of the pixel.
The S / P conversion circuit 320 expands the image data Vout read from the line memory 310 four times on the time axis (also referred to as serial-parallel conversion or phase expansion) in accordance with an instruction from the scanning control circuit 52. In accordance with this instruction, the data are distributed to channels ch1 to ch4 and output as image data Vd1 to Vd4. Since the image data Vin is not supplied in the blanking period, the S / P conversion circuit 320 outputs the image data Vd1 to Vd4 in the blanking period by replacing the pixels with data for black display.

The D / A conversion circuit group 330 is an aggregate of D / A converters provided for each channel,
The image data Vd1 to Vd4 are converted into analog voltages corresponding to the gradation values.
In the present embodiment, the image data Vin is converted to analog after serial-parallel conversion. However, it is needless to say that analog conversion may be performed before serial-parallel conversion.

The polarity inversion circuit 340 converts the D / A converted 4-channel analog signal to the higher level than the voltage Vc by the voltage of the analog signal when the positive polarity is instructed by the scanning control circuit 52. On the other hand, when the negative polarity is instructed, it is converted to a lower side than the voltage Vc and is output as data signals Vid1 to Vid4, respectively. The data signals Vid1 to Vid4 are supplied to four image signal lines 170 in the display panel 100.
Here, the voltage Vc is an amplitude center potential of the data signal, although not particularly shown, is a reference for the polarity of writing to the pixel, and is substantially an intermediate voltage of the power supply voltage (Vdd-Gnd). In other words, in the present embodiment, for the data signal, the higher side than the voltage Vc is referred to as positive polarity, and the lower side is referred to as negative polarity. The voltage is based on the ground potential Gnd of the power supply unless otherwise specified.

The reason why the polarity of the data signal is inverted by the polarity inversion circuit 340 is to drive the pixel alternating current. Here, regarding how to invert the pixels in one frame, (a)
There are various modes such as each scanning line, (b) every data line, (c) every pixel, and (d) every surface (frame). In this embodiment, (a) polarity inversion for each scanning line Suppose there is. However, the present invention is not limited to this.

The scanning control circuit 52 has a first function for controlling the scanning of the display panel 100 and the S / S described above.
The P conversion circuit 320 controls the phase expansion so as to synchronize with the horizontal scanning of the display panel 100, and also has a second function that defines distribution to four channels according to the frame number, and the phase expansion and the frame number. The third function for controlling the reading of the image data Vin for one row stored in the line memory 310 and the logic level according to the frame numbers of the selection signals A1 and A0 in the order determined by the line memory 310 over one vertical scanning period It mainly has the 4th function to fix.

Here, the first function will be described in detail. The scanning control circuit 52 generates the transfer start pulse DX and the clock signal CLX from the dot clock signal Dclk, the vertical scanning signal Vs, and the horizontal scanning signal Hs supplied from the host device. Then, the horizontal scanning of the display panel 100 is controlled, and the transfer start pulse DY and the clock signal CLY are generated to control the vertical scanning of the display panel 100.
The second function is synchronized with the phase expansion by the S / P conversion circuit 320.
Control signals Enb1 and Enb2 are output. Note that the logic levels of the control signals Enb1 and Enb2 are inverted from each other.
On the other hand, the S / P conversion circuit 320 distributes the image data expanded on the time axis to the four channels, but the distribution method is different for each frame. The scanning control circuit 52 determines how this distribution is performed by S /
The P conversion circuit 52 is instructed.
Here, the frame number is for distinguishing the vertical scanning period (frame),
In the present embodiment, there are four from “1” to “4”. For the fourth function, the scanning control circuit 52 sets the logic levels of the selection signals A1 and A0 to the L and L levels in the first frame of the frame number “1” as shown in FIG.
The second frame with the frame number “2” is set to the L and H levels, respectively, and the third frame with the frame number “3” is set to the H and L levels, respectively, and the fourth frame with the frame number “4”.
The frames are set to H and H levels, respectively.

On the other hand, the display panel 100 has a configuration in which an element substrate and a counter substrate on which a common electrode is formed are bonded together with a sealing material with a certain gap, and for example, a TN liquid crystal is sealed in the gap. A predetermined image is formed by the electro-optic change of the liquid crystal.
The details of the display panel 100 are as follows. As shown in FIG.
Extends in the X (horizontal) direction in the figure, while 1152 columns of data lines 114 extend in the Y (vertical) direction in the figure. Pixels 110 are provided so as to correspond to the intersections between the scanning lines 112 and the data lines 114. Therefore, in this embodiment, the pixels 110 are arranged in a matrix of 864 rows × 1152 columns in the display region 100a. However, in the present embodiment, 1 to 4 for reasons described later.
Since the columns and the columns 1149 to 1152 are used as dummy pixels, these dummy pixels are shielded from light by a black matrix or the like. Therefore, in this embodiment, the effective pixel arrangement for display is 864 rows × 1144 columns excluding the left and right columns.
In this embodiment, 1152 columns of data lines 114 are grouped every four columns. Therefore, for convenience of explanation, the first, second, third,..., 288th groups from the left are denoted as B1, B2, B3,.

FIG. 3 is a diagram showing a detailed configuration of the pixel 110 in the display panel 100, corresponding to the intersection of the i row and the (i + 1) row adjacent thereto, the j column and the (j + 1) column adjacent thereto. A 2 × 2 configuration for a total of four pixels is shown. Here, i and (i + 1) are symbols for generally indicating the row in which the pixels 110 are arranged, and are integers of 1 to 864, and j, (j
+1) is a symbol for generally indicating a column in which the pixels 110 are arranged.
The following integers.
As shown in FIG. 3, in the pixel 110, the source of an n-channel TFT (thin film transistor) 116 is connected to the data line 114, and the drain thereof is connected to the pixel electrode 118, while the gate is the scanning line. 112.
Further, the common electrode 108 is provided in common to all the pixels so as to face the pixel electrode 118 formed on the element substrate. A liquid crystal 105 is sandwiched between the pixel electrode 118 and the common electrode 108. For this reason, a liquid crystal capacitor 120 including the pixel electrode 118, the common electrode 108, and the liquid crystal 105 is formed for each pixel.
Note that a voltage LCcom that is constant in time is applied to the common electrode 108.
In this embodiment, the potential is the same as the reference voltage Vc. However, for reasons described below,
There is a case where it is set slightly lower than the reference voltage Vc.

Although not shown in particular, the opposing surfaces of both substrates are respectively provided with alignment films that have been rubbed so that the major axis direction of the liquid crystal molecules is continuously twisted between the substrates by, for example, about 90 degrees. A polarizer corresponding to the orientation direction is provided on each back side of the substrate.
If the voltage effective value applied to the liquid crystal capacitor 120 is zero, the light passing between the pixel electrode 118 and the common electrode 108 rotates about 90 degrees along the twist of the liquid crystal molecules, while the voltage effective value As is increased, the liquid crystal molecules are tilted in the direction of the electric field, and as a result, their optical rotation disappears. For this reason, for example, in the transmission type, when the polarizers are respectively arranged on the incident side and the back side so that the polarization axis coincides with the alignment direction, the light transmittance is maximum if the voltage effective value is close to zero. On the other hand, while the white display is obtained, the amount of transmitted light decreases as the effective voltage value increases, and finally the black display with the minimum transmittance is obtained (normally white mode).

In addition, in order to reduce the influence of charge leakage from the liquid crystal capacitor 120 via the TFT 116 at the off time, the storage capacitor 109 is formed for each pixel. One end of the storage capacitor 109 is connected to the pixel electrode 118 (the drain of the TFT 116), while the other end is commonly connected to the capacitor line 107 over all pixels. The capacitor line 107 is not shown in FIG. 2, but in the present embodiment, the same voltage LC as that of the common electrode 108 is used as shown in FIG.
kept in com. Specifically, although the capacitor line 107 is formed on the element substrate and the common electrode 108 is formed on the counter substrate, the capacitor line 107 and the common electrode 108 are formed by a conductive material (not shown).
Is an electrical connection. For this reason, the pixel electrode 118 (the drain of the TFT 116) and the common electrode 108 have a configuration in which a liquid crystal capacitor 120 and a storage capacitor 109 are added in parallel for each pixel 110.
Note that the TFT 116 in the pixel 110 is formed by a manufacturing process common to a scanning line driving circuit 130, a sampling signal output circuit 140, a sampling circuit 180, and the like described below, and contributes to downsizing and cost reduction of the entire device. is doing.

In FIG. 2, around the display area 100a in which the pixels 110 are arranged, a scanning line driving circuit 1 is provided.
30 and peripheral circuits such as a sampling signal output circuit 140 and a sampling circuit 180 are provided.
Among these, the scanning line driving circuit 130 supplies the scanning signals G1, G2, G3,..., G864 to the scanning lines 112 in the first row, the second row, the third row,. is there.
The details of the scanning line driving circuit 130 are omitted because they are not directly related to the present invention. For example, as shown in FIG. 6, the scanning line driving circuit 130 is supplied at the beginning of each vertical effective display period and the half period of the clock signal CLY. A transfer start pulse DY having a corresponding pulse width (H level) is taken in at the timing when the level of the clock signal CLY transitions, and this is used as a scanning signal G1, and this scanning signal G1 is used as a half cycle of the clock signal CLY. The scanning signals are sequentially delayed and output as scanning signals G2, G3,..., G864.
In the present embodiment, the vertical scanning period is divided into a vertical effective display period and a vertical blanking period following this period. Here, as shown in FIG. 6, the vertical effective display period is the scanning signal G1.
Is a period from the timing when the signal becomes H level to the timing when the scanning signal G864 returns to the L level, and a period excluding the vertical effective display period in the vertical scanning period is defined as a vertical blanking period.

Next, as shown in FIG. 6 or FIG. 7, the sampling signal output circuit 140 is supplied at the beginning of each horizontal effective display period and has a pulse width (H level) corresponding to a half cycle of the clock signal CLX. The transfer start pulse DX is captured at the timing when the level of the clock signal CLX transitions, and this is used as the sampling signal S1, and the sampling signal S1 is sequentially delayed by half a cycle of the clock signal CLX to obtain the sampling signal S2.
, S3,..., S288.
In the present embodiment, the horizontal scanning period is divided into a horizontal effective display period and a horizontal blanking period following this period. Here, as shown in FIG. 7, the horizontal effective display period is a period from the timing when the sampling signal S1 becomes H level to the timing when the sampling signal S288 becomes L level, and the horizontal effective display period in the horizontal scanning period. The period excluding the period is the horizontal blanking period.

On the other hand, in FIG. 2, the block changing circuit 160 divides the eight selection lines 182 into two of four lines in one vertical scanning period, and any one of the four divided lines in the phase expansion period. Each selection line 182 is set to the H level.

Details of the block change circuit 160 will be described with reference to FIG.
As shown in this figure, the block change circuit 160 includes NOT circuits 161 and 162,
NAND circuits 163, 164, 165, and 166 and transistor groups E1 to E8 are included.
Among them, the NOT circuits 161 and 162 output the negative signals of the selection signals A1 and A0, respectively, and the NAND circuit 163 outputs the negative logical product signal / D1 of the negative signal of the selection signal A1 and the negative signal of the selection signal A0. The NAND circuit 164 outputs a negative logical product signal / D2 of the negative signal of the selection signal A1 and the selection signal A0, and the NAND circuit 165 outputs the selection signal A
1 and a NAND signal / D3 of the selection signal A0, and the NAND circuit 166 outputs a NAND signal / D4 of the selection signal A1 and the selection signal A0.

Each of the transistor groups E1 to E8 includes four p-channel transistors.
Here, the gates of the transistors constituting the transistor groups E1 and E2 are connected to the signal / D1.
Are supplied in common. The control signal Enb1 is supplied in common to the sources of the four transistors that constitute the transistor group E1, while the drains of the transistors E1 to 4 are sequentially arranged.
The second selection line 182 is connected. The sources of the four transistors constituting the transistor group E2 are commonly supplied with the control signal Enb2, while the drains are connected to the fifth to eighth selection lines 182 in order.
A signal / D2 is commonly supplied to the gates of the transistors constituting the transistor groups E3 and E4. The control signals Enb1 are commonly supplied to the sources of the four transistors constituting the transistor group E3, while the drains are connected to the second to fifth selection lines 182 in order. Further, the sources of the four transistors constituting the transistor group E4 are commonly supplied with the control signal Enb2, while the drains thereof are connected to the sixth to eighth and first selection lines 182 in order. .
A signal / D3 is commonly supplied to the gates of the transistors constituting the transistor groups E5 and E6. The control signals Enb1 are commonly supplied to the sources of the four transistors constituting the transistor group E5, while the drains are connected to the third to sixth selection lines 182 in order. Further, the sources of the four transistors constituting the transistor group E6 are commonly supplied with the control signal Enb2, while the drains thereof are connected to the seventh to eighth and the first and second selection lines 182 in order. ing.
A signal / D4 is commonly supplied to the gates of the transistors constituting the transistor groups E7 and E8. The control signals Enb1 are commonly supplied to the sources of the four transistors constituting the transistor group E7, while the drains are connected to the fourth to seventh selection lines 182 in order. Further, the sources of the four transistors constituting the transistor group E8 are commonly supplied with the control signal Enb2, while the drains thereof are connected to the eighth and first to third selection lines 182 in order. .
For convenience, the signals supplied to the first to eighth selection lines 182 are respectively Sel1 to Se.
Indicated as l8.

Here, for example, in the first frame, since both the selection signals A1 and A0 are at the L level, only / D1 of the signals / D1 to / D4 is at the L level, and the transistor groups E1 and E2
Are turned on. Therefore, the eight selection lines 182 are 1 to 4
It is divided into two, the main and the fifth to eighth. On the other hand, the control signals Enb1 and Enb2 are in a relationship in which the logic levels are inverted. Therefore, the signals Sel1 to Sel of the first to fourth selection lines 182 are displayed.
el4 has the same logic level as the control signal Enb1, while the fifth to eighth selection lines 182
The signals Sel5 to Sel8 are at a logic level obtained by inverting the control signal Enb1.
Further, for example, in the second frame, since the selection signals A1 and A0 are L and H levels, respectively, only / D2 is L level among the signals / D1 to / D4, so that the transistor group E3,
Each of the transistors constituting E4 is turned on. Therefore, the eight selection lines 182 are 2
-5, 6-8, and 1 are divided into two, and the signals Sel2 to Sel5 have the same logic level as the control signal Enb1, while the signals Sel6 to Sel8 and Sel1
Becomes a logic level obtained by inverting the control signal Enb1.

Subsequently, the sampling circuit 180 converts the data signals Vid1 to Vid4 supplied via the four image signal lines 170 into sampling signals S1 to S288 and signals Sel1 to Se.
Sampling is performed on the data lines 114 defined according to l8.

Details of the sampling circuit 180 will be described with reference to FIG.
As shown in this figure, in principle, each group is supplied with a sampling signal having the same number as the group number and a sampling signal having a number smaller by “1”. However, since a number smaller than “1” does not exist in the group B1, it exceptionally corresponds only to the sampling signal S1.
Conversely, one sampling signal Sk is supplied to a group Bk having the same number k as that sampling signal and a group B (k + 1) having a number “1” larger than k. However, the sampling signal Sk is not supplied to the data line 114 corresponding to the rightmost among the four data lines 114 belonging to the group having a larger number by “1”. For example, the sampling signal S3 is supplied corresponding to the group B3 having the same number as “3” and the group B4 having a number “1” larger than this, but the 16 columns positioned at the rightmost end in the group B4. It is not supplied to the data line 114 of the eye. Note that k is the sampling signal S1, S.
2, S3,..., S288 is a convenient code when not specified, and is 1 or more and 2
It is an integer of 88 or less.

On the other hand, each of the data lines 114 is provided with an n-channel TFT 1820 as a transmission gate (sampling switch). Here, TFT1
The drain of 820 is connected to the corresponding data line 114. TFT 1820
The source is connected to one of the four image signal lines 170 to which the data signals Vid1 to Vid4 are supplied in the following relationship.
That is, in the TFT 1820 having a drain connected to one end of the j-th data line 114 in FIG. 5 from the left, if the remainder obtained by dividing j by 4 is “1”, the source is the data signal Vid1. Similarly, the TFT 182 whose drain is connected to the data line 114 whose remainders obtained by dividing j by 4 are “2”, “3”, and “0”.
The source 0 is connected to the image signal line 170 to which the data signals Vid2, Vid3, and Vid4 are supplied.
For example, in FIG. 5, the TFT 182 whose drain is connected to the data line 114 in the eleventh column.
Since the remainder of dividing “11” by 4 is “3”, the source of 0 is connected to the third image signal line 170 to which the data signal Vid3 is supplied.

The gate signal supplied to the TFT 1820 is divided into an even group and an odd group and has the following relationship.
That is, in the even-numbered group (B2, B4, B6,..., B288), the NOR circuit 1812 that outputs a negative logical sum signal of two corresponding sampling signals for each data line 114 constituting the group, and the negative NOT circuit 18 for outputting a negative signal of the logical sum signal
14, a NAND circuit 1816 that outputs a negative logical product signal of the negative signal and any one of the signals Sel 5 to Sel 8, and a NOT circuit 1 that outputs a negative signal of the negative logical product signal
818. In addition, when the NOR circuit 1812 and the NOT circuit 1814 are combined,
It becomes a positive logic OR circuit, and when the NAND circuit 1816 and the NOT circuit 1818 are combined, it becomes a positive logic AND circuit.
Here, in the even-numbered group, the NA corresponding to the j-th data line 114 counting from the left is shown.
If the remainder obtained by dividing j by 4 is “1”, the ND circuit 1816 outputs a negative logical product signal of the NOT signal from the NOT circuit 1814 and the signal Sel5, and similarly, the remainder obtained by dividing j by 4 The NAND circuit 1816 corresponding to the data line 114 having “2”, “3”, and “0” is N
A negative logical product signal of the negative signal from the OT circuit 1814 and the signals Sel6, Sel7, and Sel8 is output.

On the other hand, in the odd group (B3, B5, B7,..., B288) excluding the group B1, a NOR circuit 1812 and a NOT circuit 1814 are provided for each data line 114 constituting the group.
The NAND circuit 1816 is common to the even number group in that it has a combination of a NAND circuit 1816 and a NOT circuit 1818.
It differs from the even number group in that a negative logical product signal with any one of 1 to Sel4 is output.
That is, in the odd group, N corresponding to the j-th data line 114 counting from the left.
If the remainder obtained by dividing j by 4 is “1”, “2”, “3”, “0”, the AND circuit 1816 outputs a negative signal from the NOT circuit 1814 and the signals Sel1, Sel2, Sel3, Sel.
4 is different from the even-numbered group in that a negative logical product signal with 4 is output.

By the way, in the first group B1, other odd groups (B3, B5, B7,...
Unlike B287), since only one sampling signal S1 corresponds, the NOR circuit 1812 and the NOT circuit 1814 do not exist.
In addition, since the sampling signal having a number smaller by “1” than the group number is not supplied to the 4, 8, 12, 16,..., 1152 columns, the NOR circuit 1812 in the corresponding column has N
It functions as an OT circuit.
Note that a series of these NOR circuit 1812, NOT circuit 1814, NAND circuit 181.
6 and the NOT circuit 1818 function as a sampling control circuit for defining whether the TFT 1820 is on or off.

In such a sampling circuit 180, when one of the two corresponding sampling signals (only the sampling signal S1 in the group B1) becomes the H level, the signal Sel1 to Sel8 becomes the H level. TFT1820 corresponding to what
Are simultaneously turned on, the data signal supplied to the image signal line 170 is sampled, and the data line 114 is sampled.

Note that a pull-down circuit 1830 is provided at each end of the eight selection lines 182. For this reason, even if all of the transistors (see FIG. 4) constituting the transistor groups E1 to E8 are off, the selection line 182 does not enter a high impedance (floating) state and is set to the L level that is the ground potential Gnd. It will be confirmed.

Next, the operation of the electro-optical device 10 according to the embodiment will be described.
In the present embodiment, the scanning line driving circuit 130 includes, at the beginning of one vertical scanning effective display period,
A transfer start pulse DY is supplied. By this supply, as shown in FIG. 6, the scanning signals G1, G2, G3,..., G864 sequentially and exclusively become H level every horizontal scanning period. The operation of the scanning line driving circuit 130 is common over the first to fourth frames.
First, a horizontal effective display period in which the scanning signal G1 is at the H level in the first frame will be described. It is assumed that positive writing is performed during this horizontal effective display period.
On the other hand, the sampling signal output circuit 140 sequentially outputs the sampling signals S1, S2, S3,..., S288 in order so as to be exclusively H level over the period when the scanning signal G1 is H level.

In the first frame, the scanning control circuit 52 selects the selection signal A1 as shown in FIG.
, A0 are set to L level, and the control signals Enb1, Enb2 are set to H level during the period in which the sampling signal S1 is set to H level. Thereafter, the sampling signals S2, S3, S4,. Control signal Enb1, E
Inverts the logic level of nb2.

Here, if both the selection signals A1 and A0 are at the L level, only the signal / D1 among the signals / D1 to / D4 is at the L level in the block change circuit 160, so that the transistor groups E1 and E2 are configured. Only the transistor to turn on. For this reason, during the period in which the control signal Enb1 is at the H level (the period in which the control signal Enb2 is at the L level), the signals Sel1 to Sel1.
While Sel4 becomes H level and signals Sel5 to Sel8 become L level, control signal E
In a period in which nb1 is at L level (a period in which the control signal Enb2 is at H level), the signals Sel1 to Sel4 are at L level and the signals Sel5 to Sel8 are at H level.
For this reason, in the first frame, sampling of data signals to the four columns of data lines 114 corresponding to the signals Sel1 to Sel4, and sampling of data signals to the four columns of data lines 114 corresponding to the signals Sel5 to Sel8 are performed. Are executed alternately.

On the other hand, before the scanning signal G1 becomes H level, the image data Vin corresponding to the pixels 110 in the first row and the columns 1, 2, 3, 4,. Stored in the line memory 310.
Here, immediately before the scanning signal G1 becomes H level and the sampling signal S1 becomes H level as shown in FIG.
The readout of the image data corresponding to the pixel 110 in the first row and the first column is started, and thereafter 2,
The image data corresponding to the pixels 110 in columns 3, 4,.
The read image data Vout is expanded four times on the time axis by the S / P conversion circuit 320 in accordance with the period in which the sampling signal S1 is at the H level, and 1, 2, 3
The image data corresponding to the fourth column is image data Vd1, Vd2, Vd3, Vd4, respectively.
Are distributed in this order.
The distributed image data Vd1 to Vd4 are converted into analog signals by the D / A conversion circuit group 330, respectively, and further converted into positive signals by the polarity inversion circuits 340, respectively, and output as data signals Vid1 to Vid4. The
As a result, the data signal Vid1 becomes a positive voltage corresponding to the gradation of the pixel 110 in the first row and the first column. Similarly, the data signals Vid2, Vid3, and Vid4 are 1 row and 2 columns, respectively.
The positive voltage corresponds to the gradation of the pixels 110 in the first row and third column and the first row and fourth column.

As shown in FIG. 8, since the control signal Enb1 is at the H level (the control signal Enb2 is at the L level) in accordance with the period during which the sampling signal S1 is at the H level, the signals Sel1 to Sel.
el4 becomes H level. Therefore, when the sampling signal S1 becomes H level, only the TFT 1820 of the data line 114 in the first to fourth columns is turned on among the data lines 114 of the groups B1 and B2 corresponding to the sampling signal S1.
As a result of the four TFTs 1820 being turned on, the data signal Vid1 having a positive voltage corresponding to the gray level of the pixel 110 in the first row and the first column is sampled on the data line 114 in the first column. The data line 114 in the fourth column has pixels 1 in 1 row, 2 columns, 1 row 3 columns, and 1 row 4 columns.
Data signals Vid2, Vid3 and Vid4 having a positive voltage corresponding to 10 gradations are sampled.
Since the scanning signal G1 is at the H level, all the TFTs 116 whose gates are connected to the scanning line 112 in the first row are on. Therefore, the data signal Vid1 sampled on the data line 114 in the first column corresponds to the intersection of the scanning line 112 in the first row counted from the top and the data line 114 in the first column counted from the left in FIG. This is applied to the pixel electrode 118 of the pixel of 1 row and 1 column. The data signal V sampled on the data lines 114 in the second, third and fourth columns
Similarly, id2, Vid3, and Vid4 are applied to the pixel electrodes 118 of the pixels in the first row, the second column, the first row, the third column, and the first row, the fourth column, respectively.

Subsequently, the image data Vout corresponding to the pixels 110 in the first row and the fifth to eighth columns is expanded four times on the time axis in accordance with the period in which the sampling signal S2 is at the H level, and 5 , 6, 7, and 8 are image data Vd1, Vd2,
The signals are distributed in the order of Vd3 and Vd4, converted into an analog signal, converted into a positive signal, and output as data signals Vid1 to Vid4.
As a result, the data signal Vid1 becomes a positive voltage corresponding to the gradation of the pixel 110 in the first row and the fifth column. Similarly, the data signals Vid2, Vid3, and Vid4 are 1 row and 6 columns, respectively.
The positive voltage corresponds to the gradation of the pixels 110 in the first row and the seventh column and the first row and the eighth column.

Since the control signal Enb1 is at the L level (the control signal Enb2 is at the H level) in accordance with the period during which the sampling signal S2 is at the H level, the signals Sel5 to Sel8 are at the H level this time. Therefore, when the sampling signal S2 becomes H level, the data line 1 in the fifth to eighth columns among the data lines 114 of the groups B2 and B3 corresponding to the sampling signal S2.
Only 14 TFTs 1820 are turned on.
As a result of the four TFTs 1820 being turned on, the data signal Vid1 having a positive voltage corresponding to the gradation of the pixel 110 in the first row and the fifth column is sampled on the fifth data line 114. The data line 114 in the fourth column has pixels 1 in 1 row, 6 columns, 1 row, 7 columns, and 1 row, 8 columns.
Data signals Vid2, Vid3 and Vid4 having a positive voltage corresponding to 10 gradations are sampled.
Therefore, the data signal Vid1 sampled on the data line 114 in the fifth column is 1
This is applied to the pixel electrode 118 of the pixel in the row 5 column. 6th, 7th and 8th data line 1
Similarly, the data signals Vid2, Vid3, and Vid4 sampled at 14 are applied to the pixel electrodes 118 of the pixels in the first row, the sixth column, the first row, the seventh column, and the first row, the eighth column, respectively.

Similarly, when the odd-numbered sampling signal becomes H level, the control signal Enb1 becomes H level.
The signals Sel1 to Sel4 become H level. Therefore, when the odd-numbered sampling signal becomes H level, among the two groups corresponding to the sampling signal, that is, among the group having the same number and the group having the next number, the four numbers belonging to the same group belong to the same group. The data signals Vid1 to Vid4 are sampled on the data line 114, and writing to the pixel electrodes is performed.
On the other hand, when the even-numbered sampling signal becomes H level, the control signal Enb2 becomes H level, and the signals Sel5 to Sel8 become H level. Therefore, when the even-numbered sampling signal becomes H level, among the two groups corresponding to the sampling signal, that is, among the group having the same number and the group having the next number, 4 belonging to the group having the next number related to the latter. The data signals Vid1 to Vid4 are sampled on the data lines 114, respectively, and writing to the pixel electrodes is performed.
That is, in the first frame, when the sampling signal Sk is at the H level, the i-th row selected is the (4k-3) th column, the (4k-2) th column, and the (4k-1) th column. Eyes and (
The data signals corresponding to the pixels in the 4k) column are distributed in the order of the channels ch1 to ch4 and supplied to the image signal line 170 as the data signals Vid1, Vid2, Vid3, and Vid4, while the (4k-3) th column. , (4k-2) th column, (4k-1) th column and (4k)
The TFT 1820 in the column is turned on at the same time, and the (4k-3) th column, the (4k-2) th column, (4k)
-1) Data signals Vid1, Vid2, Vi on the data line 114 of the column and (4k) column
d3 and Vid4 are sampled.
Such an operation is repeatedly executed until the sampling signal S288 becomes H level.

When the sampling signal S288 becomes H level, writing to the pixel 110 in the first row is completed, and the same operation is repeated until the second row, the third row, the fourth row,.
In the present embodiment, as described above, since the polarity inversion is performed in units of scanning lines, the data signals Vid1 to Vd are generated in the horizontal effective display period in which the scanning signal of the even-numbered row is at the H level.
id4 becomes negative polarity. In this manner, positive polarity writing is performed for the pixels in the odd-numbered rows, while negative polarity writing is performed for the pixels in the even-numbered rows. In this first frame, the 1st to 864th rows are written. Writing will be completed across all of the pixels.

Here, a block of the data line 114 in which the data signals Vid1 to Vid4 are simultaneously sampled in the first frame will be described with reference to FIG.
As shown in this figure or as described above, in the first frame, when the sampling signal S1 becomes H level, writing in the first, second, third, and fourth columns is performed at the same time, and the sampling signal S2 Since the data in the fifth, sixth, seventh and eighth columns are simultaneously written when the signal becomes H level (the description of the sampling signal S3 and later is omitted), the data signals Vid1 to Vi
The block of data lines 114 where d4 is sampled simultaneously matches the group. That is, when the sampling signal S1 becomes H level, sampling is simultaneously performed on the data lines 114 belonging to the group B1, and when the sampling signal S2 becomes H level, the four data lines 114 belonging to the group B2 are obtained. Are simultaneously sampled.

Next, the operation after the second frame will be described.
The operation after the second frame differs from the first frame in that the logic levels of the selection signals A1 and A0, the start point of the image data Vout read from the line memory 310, and the S /
Distribution in the P conversion circuit 320.
Therefore, in the second and subsequent frames, this difference will be mainly described.

First, in the second frame, the selection signals A1 and A0 are at the L and H levels, respectively.
For this reason, in the block change circuit 160, only the signal / D2 among the signals / D1 to / D4 is at the L level, so that only the transistors constituting the transistor groups E3 and E4 are turned on. As a result, the control signal Enb1 is at the H level. In the period in which the signals Sel2 to Sel5 are H
During the period when the control signal Enb1 is at the L level, the signals Sel6 to Se
l8 and Sel1 become H level.
On the other hand, in the second frame, immediately before the scanning signal G1 becomes H level and the sampling signal S1 becomes H level as shown in FIG. Reading of the image data corresponding to the pixels 110 in the column is started, and thereafter, the image data corresponding to the pixels 110 in the 3, 4, 5,. That is, the pixel readout start point is in the second column.
The read image data Vout is expanded four times on the time axis by the S / P conversion circuit 320 in accordance with the period in which the sampling signal S1 is at the H level, and 2, 3, 4
The image data corresponding to the fifth column is image data Vd2, Vd3, Vd4, Vd1, respectively.
Are distributed in this order. The distributed image data Vd1 to Vd4 are converted into analog signals, respectively, and then converted to negative signals and output as data signals Vid1 to Vid4. As a result, the data signal Vid1 becomes a negative voltage corresponding to the gradation of the pixel 110 in the first row and the fifth column. Similarly, the data signals Vid2, Vid3, and Vid4 have negative voltages corresponding to the gray levels of the pixels 110 in the first row and second column, the first row and third column, and the first row and fourth column, respectively.

As shown in FIG. 9, since the control signal Enb1 becomes H level in accordance with the period in which the sampling signal S1 becomes H level, the signals Sel2 to Sel5 become H level. Therefore, when the sampling signal S1 becomes H level, the TFTs 18 of the data lines 114 in the second to fifth columns among the data lines 114 of the groups B1 and B2 corresponding to the sampling signal S1.
Only 20 is turned on.
As a result of the four TFTs 1820 being turned on, the data signal Vid2 having a negative voltage corresponding to the gray level of the pixel 110 in the first row and the second column is sampled on the data line 114 in the second column. The data line 114 in the fifth column includes pixels 1 in 1 row, 3 columns, 1 row, 4 columns, and 1 row, 5 columns.
Data signals Vid3, Vid4, and Vid1 having a negative voltage corresponding to 10 gradations are sampled.
Since the scanning signal G1 is at the H level, the data signal Vid2 sampled on the data line 114 in the second column is applied to the pixel electrode 118 of the pixel in the first row and the second column. 3, 4
And data signals Vid3, Vid4, and V sampled on the data line 114 in the fifth column.
Similarly, id1 is applied to the pixel electrodes 118 of the pixels in the first row, the third column, the first row, the fourth column, and the first row, the fifth column.

Subsequently, the image data Vout corresponding to the pixels 110 in the first row and the sixth to ninth columns is expanded four times on the time axis in accordance with the period in which the sampling signal S2 is at the H level. , 7, 8, and 9 are image data Vd2, Vd3,
After being distributed in the order of Vd4 and Vd1 and converted into an analog signal, it is converted to a negative polarity signal and output as data signals Vid1 to Vid4.
As a result, the data signal Vid1 becomes a negative voltage corresponding to the gradation of the pixel 110 in the first row and the ninth column. Similarly, the data signals Vid2, Vid3, and Vid4 are 1 row and 6 columns, respectively.
The negative voltage corresponds to the gradation of the pixels 110 in the first row and the seventh column and the first row and the eighth column.

Since the control signal Enb1 is at the L level (the control signal Enb2 is at the H level) in accordance with the period during which the sampling signal S2 is at the H level, this time, the signals Sel6 to Sel8 and Sel
el1 becomes H level. Therefore, when the sampling signal S2 becomes H level, only the TFT 1820 of the data lines 114 in the sixth to ninth columns is turned on among the data lines 114 of the blocks B2 and B3 corresponding to the sampling signal S2.
As a result of the four TFTs 1820 being turned on, a positive voltage data signal Vid2 corresponding to the gray level of the pixel 110 in the first row and the sixth column is sampled on the sixth column data line 114. The data line 114 in the ninth column has pixels 1 in 1 row, 7 columns, 1 row, 8 columns, and 1 row, 9 columns.
Data signals Vid3, Vid4, and Vid1 having a positive voltage corresponding to 10 gradations are sampled.
Therefore, the data signal Vid2 sampled on the data line 114 in the sixth column is applied to the pixel electrode 118 of the pixel in the first row and the sixth column. Data lines 11 in the sixth, seventh and eighth columns
Similarly, the data signals Vid3, Vid4, and Vid1 sampled at 4 are applied to the pixel electrodes 118 of the pixels in the first row, the seventh column, the first row, the eighth column, and the first row, the ninth column, respectively.

Similarly, the odd-numbered sampling signal and the even-numbered sampling signal alternately become H level and are repeatedly executed until the sampling signal S288 becomes H level.
When the sampling signal S288 becomes H level, writing to the pixel 110 in the first row is completed, and the same operation is repeated until the second row, the third row, the fourth row,.
In the second frame, negative writing is performed in the odd-numbered rows, and positive writing is performed in the even-numbered rows.

As described above, in the second frame, when the sampling signal Sk is at the H level, the i-th row selected is the (4k + 1) th column, the (4k-2) th column, and the (4k-1) th column. The data signals corresponding to the pixels in the eye and the (4k) th column are distributed in the order of channels ch1 to ch4, respectively, and are supplied to the image signal line 170 as data signals Vid1, Vid2, Vid3, Vid4, while (4k-2) ), (4k-1), (4k) and (4k + 1)
) TFT 1820 in the column is turned on at the same time, and the (4k-2) th column, (4k-1) th column, (4
k) The data signals Vid2, Vid3, V on the data lines 114 of the columns and (4k + 1) th column
id4 and Vid1 are sampled.

Here, a block of the data line 114 in which the data signals Vid1 to Vid4 are simultaneously sampled in the second frame will be described with reference to FIG.
As shown in this figure, in the second frame, when the sampling signal S1 becomes H level, writing in the second, third, fourth, and fifth columns is performed, and when the sampling signal S2 becomes H level. Since writing in the sixth, seventh, eighth and ninth columns is performed, the data signals Vid1 to Vid
The block of the data line 114 in which 4 is sampled simultaneously has a relationship shifted to the right by one column with respect to the group.

Next, in the third frame, the selection signals A1 and A0 are at the H and L levels, respectively.
For this reason, in the block change circuit 160, only the signal / D3 among the signals / D1 to / D4 is at the L level, so that only the transistors constituting the transistor groups E5 and E6 are turned on. As a result, the control signal Enb1 is at the H level. In the period in which the signals Sel3 to Sel6 are H
During the period when the control signal Enb1 is at the L level, the signals Sel7, Se
l8, Sel1 and Sel2 are at H level.
On the other hand, in the third frame, immediately before the scanning signal of the selected row becomes H level and the sampling signal S1 becomes H level as shown in FIG. The readout of the image data corresponding to the three columns of pixels 110 in the row is started, and the image data corresponding to the pixels 110 of the 4, 5, 6,. That is, the pixel readout start point is in the third column.

For this reason, in the third frame, when the sampling signal Sk is at the H level, the i-th row selected is the (4k + 1) th column, the (4k + 2) th column, the (4k-1) th column, and (
The data signals corresponding to the pixels in the 4k) column are distributed in the order of the channels ch1 to ch4 and supplied to the image signal line 170 as the data signals Vid1, Vid2, Vid3, and Vid4, while the (4k-1) th column. , (4k) th column, (4k + 1) th column and (4k + 2)
The TFT 1820 in the column is turned on at the same time, and the (4k−1) th column, the (4k) th column, (4k + 1)
) And data signals Vid3, Vid4, Vi on the data line 114 of the column and the (4k + 2) th column.
d1 and Vid2 are sampled.
In the third frame, as in the first frame, positive writing is performed in the odd-numbered rows,
In even-numbered rows, negative polarity writing is performed.

A block of the data line 114 in which the data signals Vid1 to Vid4 are simultaneously sampled will be described with reference to FIG. 12C. In the third frame, the sampling signal S
When 1 becomes H level, writing in the third, fourth, fifth and sixth columns is performed, and when sampling signal S2 becomes H level, writing is performed in the seventh, eighth, ninth and tenth columns. The blocks of the data lines 114 on which the data signals Vid1 to Vid4 are simultaneously sampled are shifted to the right by two columns with respect to the group.

In the fourth frame, the selection signals A1 and A0 are both H and H level.
Therefore, in the block change circuit 160, only the signal / D4 among the signals / D1 to / D4 is at the L level, so that only the transistors constituting the transistor groups E7 and E8 are turned on. As a result, the control signal Enb1 is at the H level. In the period in which the signals Sel4 to Sel7 are H
In a period when the control signal Enb1 is at the L level, the signals Sel8 and Sel1 to Sel3 are at the H level.
On the other hand, in the fourth frame, immediately before the scanning signal of the selected row becomes H level and the sampling signal S1 becomes H level as shown in FIG. , Reading of image data corresponding to the four columns of pixels 110 in the row is started, and image data corresponding to the pixels 110 of 5, 6, 7,. That is, the pixel readout start point is in the fourth column.

Therefore, in the fourth frame, when the sampling signal Sk is at the H level, the i-th row selected is the (4k + 1) th column, the (4k + 2) th column, the (4k + 3) th column and (
4k) The data signals corresponding to the pixels in the column are distributed in the order of the channels ch1 to ch4 and supplied to the image signal line 170 as the data signals Vid1, Vid2, Vid3, Vid4, while the (4k) column, ( 4k + 1) th column, (4k + 2) th column and (4k + 3)
The TFT 1820 in the column is turned on at the same time, and the (4k) th column, (4k + 1) th column, (4k + 2)
) And data signals Vid4, Vid1, Vi on the data line 114 in the (4k + 3) th column.
d2 and Vid3 are sampled.
In the fourth frame, as in the second frame, negative writing is performed in the odd-numbered rows,
In even-numbered rows, positive writing is performed. In addition, after the fourth frame, the process returns to the first frame.

A block of the data line 114 in which the data signals Vid1 to Vid4 are simultaneously sampled will be described with reference to FIG. 12D. In the fourth frame, the sampling signal S
When 1 becomes H level, writing in the 4, 5, 6, and 7th columns is performed, and when sampling signal S2 becomes H level, writing in the 8, 9, 10, and 11th columns is performed. The blocks of the data line 114 where the data signals Vid1 to Vid4 are simultaneously sampled are shifted to the right by three columns with respect to the group.

By the way, in the horizontal effective display period, the scanning signal supplied to any one of the scanning lines is at the H level, so that the TFT 116 of the pixel 110 corresponding to the scanning line is in the ON state.
Therefore, as long as the horizontal effective display period is concerned, the potential fluctuation in the data line 114 changes the gradation of the pixel 110 not only at the time of sampling the data signal on the data line 114 but also after sampling. It will be a direct cause.
On the other hand, the data lines 114 in the display panel 100 are not only parasitic in capacitance, but are capacitively coupled because the data lines 114 are close to each other. For this reason,
When a data signal is sampled on a certain data line (at the time of writing), the voltage of the data signal is correctly held, but after sampling to the data line, another data signal is applied to the data line adjacent to the data line. Is sampled, the voltage change in the sampling affects the data line, and the voltage of the data signal sampled initially is changed.
Therefore, if the data signal is sampled on a data line adjacent to the target data line after sampling the data signal on a certain target data line in the horizontal effective display period, the voltage of the target data line changes, and the target data line changes. The gradation of the pixel corresponding to the intersection of the data line and the selected scanning line will fluctuate from the initial target value.

In the present embodiment, for example, in the first frame, in a certain horizontal effective display period, 5, 6,
Since the data signal is simultaneously sampled on each data line in the seventh column, the data signal is not sampled on the data line adjacent in the right or left direction after the sampling. On the other hand, the data signal of the eighth column is simultaneously sampled with the data lines of the fifth, sixth, and seventh columns, but after the sampling, the data signal is applied to the ninth data line adjacent to the right. Are sampled. For this reason, in the first frame, in the pixels in the eighth column, voltage fluctuation occurs due to sampling of the adjacent data lines in the ninth column, and display unevenness occurs. In the first frame, 12, 1 located at the right end of simultaneously selected blocks
.., The display unevenness also occurs in the columns.
However, in this embodiment, by sequentially cycling from the first frame to the fourth frame, each data line related to the effective display area is sampled once to the adjacent data line after sampling, and is equal. It becomes. Therefore, in this embodiment, each data line (each pixel) in the effective display area has the same condition after sampling (condition after writing) of each data line (each pixel) when one frame is taken as one cycle. Therefore, it becomes possible to make display unevenness difficult to see.

For the data lines in columns 1 to 4 and 1149 to 1152 (not shown in FIG. 12), the conditions are not the same as those for other data lines when four frames are taken as one cycle. For this reason, in the present embodiment, the pixels in the 1st to 4th columns and the 1149 to 1152th columns are configured to be shielded from light as dummy pixels.

In the above-described embodiment, the first frame → second frame → third frame → fourth frame (
→ The first frame), but the order does not matter.
In the embodiment, the image data Vin is configured to be developed in four phases. However, the number m of channels to be expanded (the number of image signal lines and the number of data lines constituting a group) is not limited to “4”. It may be “2” or more.
On the other hand, in the horizontal blanking period before sampling the data signal, all the data lines 114 are
May be precharged to a predetermined voltage (for example, Vc).
In the above-described embodiment, the processing circuit 50 processes the digital image data Vin. However, the processing circuit 50 may be configured to input an analog image signal and develop the phase.

Further, in the embodiment, the common voltage LCcom applied to the electrode 108, had to match the potential V _C is a measure of the polarity inversion, due to the parasitic capacitance between the gate and drain of the TFT,
A phenomenon in which the potential of the drain (pixel electrode 118) decreases from on to off (pushdown,
This is called punch-through or field-through). In order to prevent the deterioration of the liquid crystal
Since the pixel capacitor is principle AC driving, a state will be the alternate write out with high side with respect to the common electrode 108 (positive polarity) and low side (negative polarity), which are matched to the voltage LCcom the voltage V _C When alternate writing is performed, the voltage effective value of the pixel capacitance becomes larger in the negative polarity writing than in the positive polarity writing because of the push-down. For this reason, the voltage LC of the common electrode 108 is set so that the effective voltage values of the pixel capacitors are equal to each other even when positive polarity / negative polarity writing is performed at the same gradation.
com may be set slightly lower than the voltage V _C is the amplitude reference of the data signal.

In the embodiment, the vertical scanning direction is the downward direction of G1 → G864, and the horizontal scanning direction is the right direction of S1 → S72. However, in order to cope with a projector or a rotatable display device described later. In addition, the scanning direction may be switched.
Furthermore, instead of the normally white mode in which white display is performed when the effective voltage value of the pixel capacitance is small, a normally black mode in which black display is performed may be used.

In the above-described embodiment, the TN type is used as the liquid crystal, but BTN (Bi-stable Twisted Ne) is used.
matic) and ferroelectric types such as bistable types with memory properties, polymer dispersed types, and dyes that have anisotropy in visible light absorption in the long and short axis directions of molecules (guests) ) May be dissolved in a liquid crystal (host) having a certain molecular arrangement, and a GH (guest host) type liquid crystal in which dye molecules are arranged in parallel with the liquid crystal molecules may be used.
In addition, the liquid crystal molecules are arranged in a vertical direction with respect to both substrates when no voltage is applied, while the liquid crystal molecules are arranged in a horizontal direction with respect to both substrates when a voltage is applied. The liquid crystal molecules are aligned in the horizontal direction with respect to both substrates when no voltage is applied, while the liquid crystal molecules are aligned in the vertical direction with respect to both substrates when a voltage is applied. It is good also as a structure.
Further, in the present invention, the electro-optical material is not limited to liquid crystal, and thus, the present invention can be applied to various liquid crystal and alignment methods.
The liquid crystal device has been described so far. In the present invention, image data (video signal) is used.
For example, EL (for example, EL (
The present invention can also be applied to an apparatus using an electronic luminescence element, an electron emission element, an electrophoretic element, a digital mirror element, or a plasma display.

<Electronic equipment>
Next, as an example of an electronic apparatus using the electro-optical device according to the above-described embodiment, a projector using the above-described display panel 100 as a light valve will be described.
FIG. 13 is a plan view showing the configuration of the projector. As shown in this figure, a projector 2100 has a lamp unit 21 formed of a white light source such as a halogen lamp.
02 is provided. The projection light emitted from the lamp unit 2102 is separated into three primary colors R (red), G (green), and B (blue) by three mirrors 2106 and two dichroic mirrors 2108 arranged inside. Light valve 100R corresponding to each primary color
, 100G and 100B, respectively. Note that the light of B color has a long optical path compared to other R colors and G colors, so that the incident lens 2122 and the relay lens 2 are used to prevent the loss.
123 and a relay lens system 2121 including an exit lens 2124.

Here, the configuration of the light valves 100R, 100G, and 100B is the same as that of the display panel 100 in the above-described embodiment, and R and R supplied from the processing circuit (not shown in FIG. 13).
It is driven by an image signal corresponding to each color of G and B. In other words, the projector 2100 has a configuration in which three sets of electro-optical devices including the display panel 100 are provided corresponding to the R, G, and B colors.
The lights modulated by the light valves 100R, 100G, and 100B are incident on the dichroic prism 2112 from three directions. In the dichroic prism 2112, the R and B light beams are refracted at 90 degrees, while the G light beam travels straight. Therefore, after the images of the respective colors are combined, a color image is projected onto the screen 2120 by the projection lens 2114.

The light valves 100R, 100G, and 100B include a dichroic mirror 21.
Since the light corresponding to the primary colors of R, G, and B is incident by 08, there is no need to provide a color filter. Further, the transmission images of the light valves 100R and 100B are projected after being reflected by the dichroic mirror 2112, whereas the transmission image of the light valve 100G is projected as it is, so the horizontal scanning direction by the light valves 100R and 100B is The image is reversed in the horizontal scanning direction by the light valve 100G and displayed in an inverted image.

In addition to the electronic device described with reference to FIG. 13, the electronic device includes a television, a viewfinder type / monitor direct-view type video tape recorder, a car navigation device, a pager, an electronic notebook, a calculator, a word processor, a workstation, a television. Examples include a telephone, a POS terminal, a digital still camera, a mobile phone, and a device equipped with a touch panel. Needless to say, the above-described electro-optical device can be applied to these various electronic devices.

1 is a diagram illustrating an overall configuration of an electro-optical device according to an embodiment of the invention. 3 is a diagram showing a configuration of a display panel in the same electro-optical device. FIG. It is a figure which shows the structure of the pixel in the display panel. It is a figure which shows the structure of the block change circuit in the display panel. It is a figure which shows the structure of the sampling circuit in the display panel. FIG. 6 is a diagram for explaining an operation of the electro-optical device. FIG. 6 is a diagram for explaining an operation of the electro-optical device. FIG. 10 is a diagram for explaining an operation of a first frame of the electro-optical device. FIG. 10 is a diagram for explaining an operation of a second frame of the electro-optical device. FIG. 10 is a diagram for explaining an operation of a third frame of the electro-optical device. FIG. 10 is a diagram for explaining an operation of a fourth frame of the same electro-optical device. FIG. 3 is a diagram showing data line blocks in the same electro-optical device. It is a figure which shows the structure of the projector to which the same electro-optical apparatus is applied.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 ... Electro-optical apparatus, 50 ... Processing circuit, 100 ... Display panel, 105 ... Liquid crystal, 110 ...
Pixels 112, scanning lines 114, data lines 116, TFTs 118, pixel electrodes 120
Liquid crystal capacitor, 130 Scanning line drive circuit, 140 Sampling signal output circuit, 160 Block change circuit, 170 Image signal line, 180 Sampling circuit, 182 Selection line, 1
812 ... NOR circuit, 1814 ... NOT circuit, 1816 ... NAND circuit, 1818 ... NO
T circuit, 1820 ... TFT, 2100 ... projector

Claims (8)

Provided in correspondence with a plurality of scanning lines and a plurality of data lines grouped by m (m is an integer of 2 or more), each sampled to a data line when the scanning line is selected A pixel having a gradation according to the data signal,
A scanning line driving circuit for selecting the plurality of scanning lines in a predetermined order;
A sampling signal output circuit for sequentially outputting a plurality of sampling signals corresponding to the group;
M image signal lines for supplying the data signal;
A sampling switch that is provided in each of the data lines and samples a data signal supplied to one of the image signal lines in an ON state on the data line;
When one sampling signal is supplied to two adjacent groups and the sampling signal is output, m consecutive sampling switches among 2m sampling switches belonging to the two groups are simultaneously turned on. A sampling control circuit to be
A block changing circuit for changing a combination of m sampling switches which are simultaneously turned on by the sampling control circuit in a predetermined order for each predetermined period;
An electro-optical device comprising: Of the two groups supplied with one sampling signal, (2m−1) sampling switches belonging to one group are:
2. The electro-optic according to claim 1, wherein among the two groups to which a sampling signal output next to the sampling signal is supplied, (2m−1) sampling switches belonging to the other group. apparatus. The electro-optical device according to claim 1, wherein the block changing circuit shifts m sampling switches one by one for each frame. The block change circuit includes:
The control signal is output so that the 2m selection lines are divided into two, and the selection lines are alternately exclusive to the m selection lines divided into two.
The electro-optical device according to claim 1, wherein the combination of m selection lines to be divided is changed in a predetermined order for each predetermined period. The sampling control circuit includes:
For each sampling switch,
An OR circuit for obtaining an OR signal between two sampling signals;
A logical product circuit that obtains a logical product signal of the logical sum signal and any one of the 2m control signals and indicates an on or off state;
The electro-optical device according to claim 4, comprising: A processing circuit for supplying a data signal of a pixel corresponding to an intersection of a selected scanning line and a data line for which an ON state of a sampling switch is designated to the m image signal lines;
The electro-optical device according to claim 1, further comprising: Provided in correspondence with a plurality of scanning lines and a plurality of data lines grouped by m (m is an integer of 2 or more), each sampled to a data line when the scanning line is selected A pixel having a gradation according to the data signal,
A scanning line driving circuit for selecting the plurality of scanning lines in a predetermined order;
A sampling signal output circuit for sequentially outputting a plurality of sampling signals corresponding to the group;
M image signal lines for supplying the data signal;
A sampling switch that is provided in each of the data lines and samples a data signal supplied to one of the image signal lines in an ON state to the data line;
When one sampling signal is supplied to two adjacent groups and the sampling signal is output, among 2m sampling switches belonging to the two groups,
While simultaneously turning on m consecutive sampling switches,
A method for driving an electro-optical device, wherein a combination of m sampling switches that are simultaneously turned on is changed in a predetermined order at regular intervals.   An electronic apparatus comprising the electro-optical device according to claim 1.

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