JP4645493B2 - ELECTRO-OPTICAL DEVICE, DRIVE CIRCUIT THEREOF, AND ELECTRONIC DEVICE - Google Patents

Description

  The present invention relates to a technique for making a deterioration in display quality caused when sampling a so-called phase expanded data signal inconspicuous.

  In recent years, projectors that form a small reduced image by using a display panel such as a liquid crystal and enlarge and project the small reduced image by an optical system are becoming widespread. The projector does not have a function of creating an image by itself, and is supplied with image data (or an image signal) from a host device such as a personal computer or a TV tuner. This image data specifies the gradation (brightness) of the pixels, and is supplied in the form of vertical and horizontal scanning of the pixels arranged in a matrix, so that the display panel used in the projector is also this It is appropriate to drive according to the format. For this reason, in the display panel used for the projector, the scanning lines are selected by selecting the scanning lines one by one in a predetermined order and selecting the data lines by one column at a time during the period in which the scanning lines of one row are selected. In general, the data lines are driven in a dot sequential manner in which a data signal obtained by converting image data so as to be suitable for driving a liquid crystal is supplied.

On the other hand, recently, high definition of a display image is progressing like high vision. High definition of the display image can be achieved by increasing the number of rows of scanning lines and the number of columns of data lines to increase the number of pixels corresponding to the intersection of the scanning lines and the data lines. Since the frame frequency is fixed, one horizontal scanning period is shortened by increasing the number of scanning line rows. Furthermore, in the dot sequential method, the data line selection period is also shortened by increasing the number of data line columns. For this reason, in the dot sequential method, it becomes impossible to secure a sufficient time for supplying the data signal to the data line as the definition becomes higher, and writing to the pixels has started to be insufficient.
Therefore, a method called phase expansion drive has been devised for the purpose of eliminating the shortage of writing (see Patent Document 1). In this phase expansion drive, the data lines are grouped into predetermined columns, for example, every three columns (in Patent Document 1, every six columns), and the data lines are sequentially selected and selected every three columns over one horizontal scanning period. In this method, data signals expanded three times in the time axis direction are supplied to the three data lines. In this phase development driving method, the time for supplying the data signal to the data line can be secured three times in this example as compared with the dot sequential method, so it was considered suitable for high definition. .
JP 2000-112437 A

By the way, in such a phase development drive method, vertical streak-like unevenness occurs in which the gradation of the pixels is slightly different in the period of every three columns selected at the same time, and the deterioration of the display quality is conspicuous. became.
The present invention has been made in view of the above-described circumstances, and an object of the present invention is to provide an electro-optical device, a driving circuit thereof, and an electronic apparatus in which deterioration in display quality is not noticeable when a phase expansion driving method is employed. Is to provide.

In order to achieve the above object, the present invention is provided corresponding to the intersection of a plurality of scanning lines and a data line that is blocked every 2m (m is an integer of 2 or more) columns, A driving circuit of an electro-optical device having a plurality of pixels having gradations according to a data signal sampled on the data line when the scanning line is selected, the scanning lines of the plurality of rows being set in advance; The scanning line driving circuit for selecting in this order, and the predetermined two pulse signals for each of the blocks over the first and second periods obtained by dividing the period during which one scanning line is selected by the scanning line driving circuit. a shift register for sequentially outputting in response to, the following pulse signal outputted by the shift register with specifying the block of two by two in sequence, in one of the first or second time period Of the 2m columns of data lines belonging to the specified block, m columns of odd-numbered data lines are selected, and in the other of the first or second period, of the 2m columns of data lines belonging to the specified block, even columns A data line selection circuit for selecting m data lines, a sampling circuit for sampling the data signals supplied to the m image signal lines on m data lines selected by the data line selection circuit, and It is characterized by comprising. According to the present invention, m columns of data lines from which data signals are simultaneously sampled are distributed in odd columns and even columns, so that the deterioration in display quality can be made inconspicuous.

In the present invention, the data line selection circuit selects an odd-numbered data line by a logical operation of a period designation signal designating one of the first or second periods and a pulse signal from the shift register, An even column data line may be selected by a logical operation of a period designation signal designating the other of the first or second periods and a pulse signal from the shift register.
In this configuration, the data line selection circuit includes a logic circuit for odd columns and even columns corresponding to each block, and the logic circuit for odd columns is one of the first or second period. A signal for selecting m columns of odd-numbered data lines in one of the first or second periods is output by a logical operation of a period specifying signal for specifying this, a pulse signal from the shift register, and a predetermined enable signal. Then, the logic circuit for the even-numbered column performs the logical operation of a period specifying signal that specifies the other of the first or second period, a pulse signal by the shift register, and a predetermined enable signal. A signal for selecting m columns of even-numbered data lines may be output in the other of the first and second periods. Further, in the above configuration, the data line selection circuit, corresponding to each block, causes the pulse signal from the shift register to be an exclusive signal for each block by a logical operation with a predetermined enable signal. And an odd column data line in one of the first or second period by a logical operation of a period designating signal designating one of the first or second periods and an output signal from the common logic circuit. By logic operation of the logic circuit for odd columns that outputs a signal for selecting m columns, a period designation signal that designates the other of the first or second periods, and an output signal from the common logic circuit, A logic circuit for even columns that outputs a signal for selecting m columns of data lines of even columns in the other of the first or second period.

In the present invention, the shift register outputs each pulse signal obtained by sequentially shifting an input pulse with a clock signal in correspondence with two adjacent blocks, and the data line selection circuit includes the shift register. It is also possible to have a logic circuit that makes the pulse signals output by the above-mentioned two blocks to be mutually exclusive by a logical operation with a predetermined enable signal.
On the other hand, in the present invention, the shift register outputs each pulse obtained by sequentially shifting the input pulse with a clock signal while the pulse widths of adjacent ones overlap each other, and the data line selection circuit includes the shift register. A configuration may be adopted in which a logic circuit is provided that allows the pulse signals output by the above to be mutually exclusive in the blocks corresponding to the pulse signals by a logical operation with a predetermined enable signal.
The present invention can be conceptualized as an electro-optical device as well as an electronic apparatus having the electro-optical device, in addition to the drive circuit of the electro-optical device.

Embodiments of the present invention will be described below with reference to the drawings.
FIG. 1 is a block diagram illustrating an overall configuration of an electro-optical device according to an embodiment of the invention. As shown in this figure, the electro-optical device 1 is roughly divided into a display panel 10 and a processing circuit 20. Among these, the processing circuit 20 is a circuit module that controls the operation and the like of the display panel 10, and is connected to the display panel 10 by, for example, an FPC (Flexible Printed Circuit) substrate.

The processing circuit 20 is further divided into a scanning control circuit 52, a line memory 310, an S / P conversion circuit 320, a D / A conversion circuit group 330, and a polarity inversion circuit 340.
Among these, the line memory 310 stores one line of the image data Vin supplied from a host device (not shown), and then reads it according to an instruction from the scanning control circuit 52 and outputs it as image data Vout. Here, the image data Vin (Vout) is digital data for designating the gradation (brightness) of the pixel.
The S / P conversion circuit 320 converts the image data Vout read from the line memory 310 into
In accordance with an instruction from the scanning control circuit 52, the data is expanded three times in the time axis direction (also referred to as phase expansion or serial-parallel conversion), and distributed to channels ch1 to ch3 according to the instruction as image data Vd1 to Vd3. Output.
In the present embodiment, when the precharge control signal Nrg is H level and precharge is designated, the S / P conversion circuit 320 has an image corresponding to, for example, black regardless of reading from the line memory 310. Data Vd1 to Vd3 are output.

  The D / A conversion circuit group 330 is an aggregate of D / A converters provided for each channel, and converts the image data Vd1 to Vd3 into analog voltages corresponding to the gradation values. In the present embodiment, the image data Vin is subjected to analog conversion after phase expansion, but it is needless to say that analog conversion may be performed before phase expansion.

The polarity inversion circuit 340 converts the D / A converted three-channel analog signal into a high-order voltage based on the voltage Vc if the positive polarity is instructed by the polarity instruction signal Pol. On the other hand, if the negative polarity is instructed, the voltage Vc is converted into a lower voltage with reference to the voltage Vc and output as data signals Vid1 to Vid3, respectively.
The data signals Vid1 to Vid3 are supplied to the image signal lines in the display panel 10. Further, the voltage Vc is the amplitude center potential of the data signal, is a reference for the writing polarity to the pixel, and is substantially an intermediate voltage of the power supply voltage (Vdd-Gnd) (see FIGS. 7 and 8 to be described later). . In other words, in the present embodiment, if the data signal is limited, the higher side than the voltage Vc is positive and the lower side is negative. On the other hand, the voltage is based on the ground potential Gnd of the power supply unless otherwise specified.

  The reason why the polarity of the data signal is inverted by the polarity inversion circuit 340 is to drive the pixel AC. Here, as to how the pixels are inverted during the frame period (vertical scanning period), (a) every scanning line, (b) every data line, (c) every pixel, (d) surface (frame) Although there are various modes such as every frame, in the present embodiment, it is assumed that (d) polarity reversal for each frame. However, the present invention is not limited to this.

The scanning control circuit 52 has a first function for controlling scanning of the display panel 10, a second function for controlling reading of image data for one row stored in the line memory 310 in accordance with the scanning, and the above-described scanning function. The S / P conversion circuit 320 mainly has a third function for controlling the phase expansion so as to be synchronized with the horizontal scanning of the display panel 10.
Here, the first function will be described in detail. The scanning control circuit 52 generates the transfer start pulse DX and the clock signal CLX in synchronization with the supply of the image data Vin, thereby controlling the horizontal scanning of the display panel 10. At the same time, a transfer start pulse DY and a clock signal CLY are generated, and thereby vertical scanning of the display panel 10 is controlled. On the other hand, the scanning control circuit 52 outputs a precharge control signal Nrg for precharging the data line at the start of the horizontal scanning period in synchronization with the horizontal scanning.
Note that, as described above, in this embodiment, since polarity inversion is performed for each frame, the scanning control circuit 52 inverts the writing polarity instructed by the polarity instruction signal Pol for each frame period.
Next, the second function will be described. The scanning control circuit 52 performs a horizontal scanning period for selecting one scanning line in a first half period (first period) and a second half period (second period) as will be described later. Therefore, among the rows corresponding to the scanning lines selected in the horizontal scanning period, the image data corresponding to the odd-numbered columns of pixels is sequentially read out from the line memory 310 in the first half period, while the pixels corresponding to the even-numbered columns are corresponded in the second half period. Similarly, the image data to be read is sequentially read from the line memory 310. Further, the scanning control circuit 52 outputs a signal Sel that becomes H level in the first half period and L level in the second half period in order to define the first half period and the second half period. That is, the signal Sel is a period designation signal that designates the first half period, and the signal / Sel obtained by logically inverting the signal Sel is a period designation signal that designates the first half period.
Next, the third function will be described. The scanning control circuit 52 controls the phase expansion by the S / P conversion circuit 320 and outputs four systems of enable signals Enb1 to Enb4 so as to be synchronized with the phase expansion. .

  On the other hand, the display panel 10 has a configuration in which an element substrate and a counter substrate on which a common electrode is formed are bonded together with a sealing material with a certain gap, and for example, a TN liquid crystal is sealed in the gap. A predetermined image is formed by the electro-optic change of the liquid crystal.

FIG. 2 is a block diagram showing a detailed configuration of the display panel 10.
As shown in this figure, in the display area 100 of the display panel 10, 864 rows of scanning lines 112 extend in the X (horizontal) direction in the figure, while 1152 columns of data lines 114 are Y (vertical) in the figure. ) Extends in the direction. The pixels 110 are provided so as to correspond to the intersections between the scanning lines 112 and the data lines 114. Therefore, in this embodiment, the pixels 110 are arranged in a matrix of 864 rows × 1152 columns in the display region 100.
In this embodiment, 1152 columns of data lines 114 are divided into blocks every 6 columns in order from the left in the figure. Therefore, for convenience of explanation, the first, second, third,..., 192nd blocks are denoted as B1, B2, B3,.

  FIG. 3 is a diagram showing a detailed configuration of the pixel 110 in the display panel 10 and corresponds to the intersection of the p row and the (p + 1) row adjacent thereto, the q column and the (q + 1) column adjacent thereto. A 2 × 2 configuration for a total of four pixels is shown. Here, p and (p + 1) are symbols for generally indicating the row in which the pixels 110 are arranged, and are integers of 1 to 864, and q and (q + 1) are the pixels 110 being arranged. This is a symbol for generally indicating a column to be performed, and is an integer of 1 to 1152.

As shown in FIG. 3, in the pixel 110, the source of an n-channel TFT (thin film transistor) 116 is connected to the data line 114, and the drain thereof is connected to the pixel electrode 118, while the gate is the scanning line. 112.
On the other hand, the common electrode 108 is provided in common to all the pixels so as to face the pixel electrode 118 formed on the element substrate. A liquid crystal 105 is sandwiched between the pixel electrode 118 and the common electrode 108. For this reason, a liquid crystal capacitor 120 including the pixel electrode 118, the common electrode 108, and the liquid crystal 105 is formed for each pixel.
A constant voltage LCcom is applied to the common electrode 108 over time, and this voltage (potential)
Is the same as the reference voltage Vc in this embodiment. However, it may be set slightly lower than the reference voltage Vc for reasons described later.
The liquid crystal capacitor 120 is configured such that the amount of transmitted light per unit time changes according to the held voltage effective value. Specifically, the liquid crystal capacitor 120 is set to be in a normally white mode in which the amount of transmitted light increases as the effective value of the holding voltage decreases.

A storage capacitor 109 is provided for each pixel. The storage capacitor 109 is electrically connected in parallel with the liquid crystal capacitor 120, and the capacitor line maintained at the same voltage as the drain (pixel electrode 118) of the TFT 116 and a constant potential, for example, the applied voltage LCcom of the common electrode 108. 107
Between the two. In this example, the capacitor line 107 is kept at the voltage LCcom, but may be kept at the ground potential Gnd, for example, as long as it is kept at a constant potential.

Returning to FIG. 2, peripheral circuits such as a scanning line driving circuit 130, a shift register 140, a data line selection circuit 150, and a sampling circuit 160 are provided around the display region 100 in which the pixels 110 are arranged. .
Among these, the scanning line driving circuit 130 supplies the scanning signals G1, G2, G3,..., G864 to the scanning lines 112 in the 1, 2, 3,. The details of the scanning line driving circuit 130 are omitted because they are not directly related to the present invention, but in this embodiment, as shown in FIG. 5, one cycle of the clock signal CLY is supplied at the beginning of each frame period. The transfer start pulse DY having a pulse width (H level) corresponding to the clock signal CLY is captured at the timing when the level of the clock signal CLY transitions, and the rear half thereof is narrowed to the width of the half cycle of the clock signal CLY, and this is scanned. In addition to G1, the scanning signal G1 is sequentially delayed by half a cycle of the clock signal CLY and output as scanning signals G2, G3,..., G864. Here, a period during which the scanning signals G1, G2, G3,..., G864 are at the H level (a period corresponding to a half cycle of the clock signal CLY) is the horizontal scanning period H, and an H level scanning signal is supplied. It shows that the scanning line is in a selected state.

Next, the shift register 140 has “96” stages, which is half of the total number of blocks “192” in the present embodiment, and, as shown in FIG. 6, in the horizontal scanning period H, the first half period Sub1 and the second half period. The transfer start pulse DX supplied first in Sub2 is taken in at the timing when the level of the clock signal CLX transitions in the first stage, and this is used as the shift signal S1, and the shift signal S1 is set to 2, 3 ,..., The 96th stage is sequentially delayed by half a cycle of the clock signal CLX and output as shift signals S2, S3,.
Here, since the transfer start pulse DX has a pulse width corresponding to one cycle of the clock signal CLX, the pulse widths of the shift signals S1, S2, S3,. It will overlap every half cycle.

Next, detailed configurations of the data line selection circuit 150 and the sampling circuit 160 in FIG. 2 will be described with reference to FIG.
First, the data line selection circuit 150 will be described. As shown in FIG. 4, the supply path of the shift signals S1, S2, S3,..., S96 is divided into four. Specifically, the shift signal S1 output from the first stage of the shift register 140 is divided into four so as to correspond to the odd and even columns in the blocks B1 and B2, respectively. Generally speaking, the shift signal Sj output from the j-th stage (j is an integer of 1 to 96) in the shift register 140 is an odd column, an even column, and a block B in the block B (2j−1). Dividing into four corresponding to the odd and even columns in (2j).

In each block, a group circuit of NAND circuits 1512 and 1514 and NOT circuits 1516 and 1518 are provided corresponding to odd columns, while a group circuit of NAND circuits 1522 and 1524 and NOT circuits 1526 and 1528 correspond to even columns. Provided.
Among these, the NAND circuits 1512 and 1522 are of a three-input type, and one of the shift signal supplied to the first input terminal, the enable signals Enb1 to Enb4 supplied to the second input terminal, and the third input The signal Sel supplied to the terminal or the logical product signal of the signal Sel obtained by logically inverting the signal Sel by the NOT circuit 1510 is output.
The NAND circuit 1514 (1524) is a two-input type, and outputs a negative logical product signal of a negative logical product signal from the NAND circuit 1512 (1522) and a signal obtained by logically inverting the precharge control signal Nrg by the NOT circuit 1520. . The NOT circuit 1516 (1526) logically inverts the NAND signal of the NAND circuit 1514 (1524), and the NOT circuit 1518 (1528) reinverts the logic inversion signal of the NOT circuit 1516 (1526).

Here, the following enable signals are supplied to the second input terminals of the NAND circuit 1512 corresponding to the odd-numbered columns and the NAND circuit 1522 corresponding to the even-numbered columns of each block. That is, as described above, the shift signal Sj output from the j-th stage in the shift register 140 is supplied to the odd and even columns in the block B (2j-1) and the odd and even columns in the block B (2j). Correspondingly, it is supplied by being divided into four, but when j is an odd number (1, 3, 5,..., 95), an NAND circuit 1512 corresponding to an odd column of the block B (2j−1) and an even number An enable signal Enb1 is supplied to each of the second input terminals of the NAND circuit 1522 corresponding to the column, and the NAND circuits 1512, 1 of the block B (2j) are supplied.
On the other hand, an enable signal Enb2 is supplied to each of the second input terminals 522 and 522,
When j is an even number (2, 4, 6,..., 96), the enable signal Enb3 is supplied to the second input terminals of the NAND circuits 1512 and 1522 of the block B (2j-1), respectively. The enable signal Enb4 is supplied to the second input terminals of the NAND circuits 1512 and 1522 of the block B (2j).
For example, when j is 2, the shift signal S2 is divided into four corresponding to the odd and even columns in the block B3 and the odd and even columns in the block B4. The enable signal Enb3 is supplied to the second input terminals of the NAND circuit 1512 corresponding to the column and the NAND circuit 1522 corresponding to the even column.

Here, as shown in FIG. 6, each of the enable signals Enb1 to Enb4 is a pulse (H level) having the same frequency as that of the clock signal CLX and a width shorter than a quarter cycle of the clock signal CLX. The signals are continuous and have a phase shifted by 90 degrees from each other. Specifically, in the first half period Sub1 and the second half period Sub2 of the horizontal scanning period H, pulses are output in the order of the enable signal Enb1 → Enb2 → Enb3 → Enb4 (→ Enb1).
The pulses of the enable signals Enb1 and Enb2 are output so as to sandwich the timing when the clock signal CLX falls, and the pulses of the enable signals Enb3 and Enb4 are outputted so as to sandwich the timing when the clock signal CLX rises.

  On the other hand, the signal Sel or the signal / Sel is supplied to the third input terminals of the NAND circuit 1512 corresponding to the odd-numbered columns and the NAND circuit 1522 corresponding to the even-numbered columns in the following relationship. That is, the signal Sel is supplied to the third input terminal of the NAND circuit 1512 corresponding to the odd column of each block, and the signal / signal is supplied to the third input terminal of the NAND circuit 1522 corresponding to the even column of each block. Sel is supplied.

Here, among the shift signals Sj, the final output of the group circuit that processes the signals supplied corresponding to the odd columns of the block B (2j-1), that is, the odd columns of the block B (2j-1). While the output signal from the NOT circuit 1518 is expressed as a sampling signal R (4j-3), the final output of the group circuit that processes the signals supplied corresponding to the even columns of the block B (2j-1), that is, An output signal from the NOT circuit 1528 in the even-numbered column of the block B (2j-1) is expressed as a sampling signal R (4j-2). Similarly, the final output signal of the group circuit that processes the shift signal Sj supplied corresponding to the odd-numbered columns of the block B (2j) is expressed as a sampling signal R (4j-1) while the even-numbered signal The final output signal of the group circuit that processes the signals supplied corresponding to the columns is represented as a sampling signal R (4j).

Next, the configuration of the sampling circuit 160 will be described.
As shown in FIG. 4, the sampling circuit 160 is an aggregate of n-channel TFTs 165 whose drains are connected to the data lines 114.
Here, the source of the TFT 165 is connected to one of the three image signal lines 162 to which the data signals Vid1 to Vid3 are supplied in the following relationship. That is, in the TFT 165 whose drain is connected to one end of the q-th data line 114 counted from the left in the figure, if the remainder obtained by dividing q by 6 is “1” or “2”, the source is Similarly, the source of the TFT 165 is connected to the image signal line 162 to which the data signal Vid1 is supplied, and the drain of the TFT 165 is connected to the data line 114 whose remainder is “3” or “4” when q is divided by 6. The remainder obtained by dividing q by 6 is connected to the image signal line 162 to which the signal Vid2 is supplied, and “5” or “0”.
The source of the TFT 165 whose drain is connected to the data line 114 is connected to the image signal line 162 to which the data signal Vid3 is supplied.
For example, in FIG. 4, the source of the TFT 165 whose drain is connected to the data line 114 in the eleventh column has a remainder of “5” obtained by dividing “11” by 6; therefore, the image signal line to which the data signal Vid3 is supplied. 162.

On the other hand, the sampling signal is supplied to the gate of the TFT 165 in the following relationship.
That is, the sampling signals R (4j-3) and R (4j-2) are supplied to the block B (2j-1), but the six lines of data lines 114 belonging to the block B (2j-1) Among them, the sampling signal R (4j-3) is commonly supplied to the gates of the TFTs 165 whose drains are connected to the odd-numbered data lines, and the gates of the TFTs 165 whose drains are connected to the even-numbered data lines are The sampling signal R (4j-2) is supplied in common.
Further, the sampling signals R (4j−1) and R (4j) are supplied to the block B (2j). Of the six data lines 114 belonging to the block B (2j), the odd-numbered column data The sampling signal R (4j-1) is commonly supplied to the gates of the TFTs 165 whose drains are connected to the lines, and the sampling signals R (4j) are supplied to the gates of the TFTs 165 whose drains are connected to the even-numbered data lines. Are supplied in common.
For example, the sampling signal R5, R6 corresponds to the block B3 in which j is 2, but among the 13, 14, 15, 16, 17, 18th data lines belonging to the block B3, odd numbers 13, 15 The sampling signal R5 is supplied in common to the gates of the TFTs 165 whose drains are connected to the 17th data line, while the gates of the TFTs 165 whose drains are connected to the data lines of the even-numbered 14, 16th and 18th columns. Are commonly supplied with the sampling signal R6.

In such a sampling circuit 160, when the odd-numbered sampling signal (4j-3) or (4j-1) among the two sampling signals supplied to a certain block becomes H level, six columns belonging to the block Among the data lines 114, the TFTs 165 corresponding to the data lines 114 of the odd-numbered columns are simultaneously turned on, and the data signals Vid1 to Vid3 are sampled on the odd-numbered data lines, while the even-numbered sampling signals ( When 4j-2) or (4j) becomes H level, the TFTs 165 corresponding to the data lines 114 of the even-numbered columns are simultaneously turned on, and the data signals Vid1 to Vid3 are sampled on the data lines of the even-numbered columns. It has a configuration.
This is because when one of the two sampling signals supplied to a certain block becomes H level, the block is in a designated state, and among these, an odd-numbered sampling signal becomes H level. In addition, the odd-numbered data line 114 is selected, and when the even-numbered sampling signal becomes H level, the even-numbered data line 114 is selected, and in any case, the data signal is sampled on the selected data line. It is synonymous with.
Note that the constituent elements of the scanning line driver circuit 130, the shift register 140, the data line selection circuit 150, and the sampling circuit 160 are formed by a manufacturing process common to the TFT 116 in the display region 100, thereby reducing the size and cost of the entire device. Has contributed to

Next, the operation of the electro-optical device 1 according to this embodiment will be described.
In the present embodiment, the scanning control circuit 52 supplies a transfer start pulse DY to the scanning line driving circuit 130 at the beginning of a period of one frame. By this supply, as shown in FIG. 5, the scanning signals G1, G2, G3,..., G864 are sequentially set to the H level every horizontal scanning period H in this order.
Among these, the horizontal scanning period H in which the scanning signal G1 is at the H level will be described. Note that, during this frame period, positive writing is performed for all pixels.
First, the scanning control circuit 52 sets the precharge control signal Nrg to the H level at the beginning of the horizontal scanning period H as shown in FIG. As a result, the S / P conversion circuit 320 outputs the image data Vd1 to Vd3 designating the black gradation to the three channels irrespective of the reading from the line memory 310, so that the three image signal lines 162 are output. Are supplied with data signals Vid1 to Vid3 of positive polarity and corresponding to black.
On the other hand, when the precharge control signal Nrg becomes H level, the other input terminals of the NAND circuits 1514 and 1524 in the data line selection circuit 150 become L level, so that the output signals of the NAND circuits 1514 and 1524 are forcibly set to H level. become. Therefore, the sampling signals R1, R2, R3, R4,..., R384 all become H level.
As a result, as a result of all the TFTs 165 being turned on, all the data lines 114 in the 1st to 1152th columns are precharged to a voltage corresponding to positive polarity and black, and the initial state before writing is made uniform. become.
Thereafter, since the precharge control signal Nrg becomes L level, the logic level of each sampling signal is defined by the shift signal, the enable signal, and the signal Sel (or signal / Sel).

The scanning control circuit 52 supplies the transfer start pulse DX at the start of the first half period Sub1 in the horizontal scanning period H and sets the signal Sel to the H level. Thereby, the shift signals S1, S2, S3,..., S96 by the shift register 140 are in a relationship in which the transfer start pulse DX is sequentially delayed by half a cycle of the clock signal CLX, and the signal / Sel becomes L level. For this reason, in the first half period Sub1, the sampling signal corresponding to the odd-numbered column of each block is at the H level during the pulse output period of the enable signal during the period in which the shift signal is at the H level. The sampling signal corresponding to the column never becomes H level.
Here, the scanning control circuit 52 outputs the pulses of the enable signals Enb1 and Enb2 before and after the timing when the clock signal falls, and outputs the pulses of the enable signals Enb3 and Enb4 before and after the timing when the clock signal rises.

Therefore, in the first half period Sub1, the sampling signal R (4j-3) to the block B (2j-1) where j is an odd number is obtained by extracting the pulse of the shift signal Sj with the pulse of the enable signal Enb1, The sampling signal R (4j−1) to the block B (2j) whose odd number is odd is obtained by extracting the pulse of the shift signal Sj with the pulse of the enable signal Enb2, and the block B (2j whose j is even number). The sampling signal R (4j-3) to -1) is obtained by extracting the pulse of the shift signal Sj with the pulse of the enable signal Enb3, and the sampling signal R (to the even number block B (2j) where j is an even number. 4j-1) is obtained by extracting the pulse of the shift signal Sj with the pulse of the enable signal Enb4.
Therefore, when the transfer start pulse DX is supplied in the first half period Sub1, the odd-numbered sampling signals R1, R3, R5, R7,..., R383 sequentially become H level exclusively, and the even-numbered sampling signals R2, R4,. R6, R8,..., R384 are kept at the L level.

On the other hand, before the scanning signal G1 becomes the H level, the image data Vin corresponding to the pixels 110 in the first row and the columns 1, 2, 3, 4,. Stored in the line memory 310.
In the state where the image data of the first row is stored, the scanning control circuit 52 immediately before the sampling signal R1 becomes H level in the first half period Sub1 in the horizontal scanning period H in which the scanning signal G1 becomes H level (strictly, In other words, the period in which the sampling signal R1 is at the H level is a period in which the enable signal Enb1 is at the H level in the period in which the shift signal S1 is at the H level, and immediately before the enable signal Enb1 is at the H level). As shown in FIG. 7, the operation of reading out the image data corresponding to the pixels in the odd-numbered columns in the first row from the line memory 310 is started. That is, in the first half period Sub1, the first row is 1, 3, 5, 7,
The image data Vout corresponding to the pixels 110 in the 9th, 1151, 1151 columns are read in order.
The read image data Vout is expanded three times in the time axis direction by the S / P conversion circuit 320 in accordance with the period in which the sampling signal R1 is at the H level, and corresponds to the first, third, and fifth columns. The image data to be distributed is distributed in the order of image data Vd1, Vd2, and Vd3. The distributed image data Vd1, Vd2, and Vd3 are converted into analog signals by the D / A conversion circuit group 330, respectively, and are converted to positive signals by the polarity inversion circuit 340, respectively, and are used as data signals Vid1, Vid2, and Vid3. Is output.
As a result, the data signal Vid1 becomes a positive voltage corresponding to the gradation of the pixel 110 in the first row and the first column. Similarly, the data signals Vid2 and Vid3 are the pixels 11 in the first row and the third column and the first row and the fifth column, respectively.
A positive voltage corresponding to a gradation of 0 is obtained. The previous data signals Vid1, Vid2, Vid3
Are precharge voltages.

If the sampling signal R1 is at the H level, the TFTs 165 corresponding to the odd-numbered first, third, and fifth columns among the first to sixth columns belonging to the block B1 are turned on. A positive voltage data signal Vid1 corresponding to the gray level of the pixel 110 in the column is sampled, and similarly, the data lines 114 in the third and fifth columns are connected to the floors of the pixels 110 in the first row and third column and the first row and fifth column. Data signals Vid2 and Vid3 having a positive voltage corresponding to the key are sampled.
Since the scanning signal G1 is at the H level, all the TFTs 116 whose gates are connected to the scanning line 112 in the first row are on. For this reason, the data signal Vid1 sampled on the data line 114 in the first column is applied to the pixel electrode 118 in the first row and the first column corresponding to the intersection of the scanning line 112 in the first row and the data line 114 in the first column. Will be. The data signals Vid2 and Vid3 sampled on the data lines 114 in the third and fifth columns are also applied to the pixel electrodes 118 in the first row and third column and the first row and fifth column, respectively.

In the first half period Sub1, the sampling signal R3 becomes H level next to the sampling signal R1. In accordance with the period when the sampling signal R3 is at the H level, the image data Vout corresponding to the pixels 110 in the first row and the seventh, ninth, and eleventh columns is expanded three times in the time axis direction. It is distributed to image data Vd1, Vd2, and Vd3, converted to a positive analog signal, and output as data signals Vid1, Vid2, and Vid3. As a result, the data signal Vid1 becomes a positive voltage corresponding to the gradation of the pixel 110 in the first row and the seventh column. Similarly, the data signals Vid2 and Vid3 have positive voltages corresponding to the gray levels of the pixels 110 in the 1st row and 9th column and the 1st row and 11th column, respectively.
If the sampling signal R3 is at the H level, the TFTs 165 corresponding to the odd-numbered seventh, ninth, and eleventh columns among the first to sixth columns belonging to the block B2 are turned on. A positive voltage data signal Vid1 corresponding to the gray level of the pixel 110 in the column is sampled, and similarly, the data lines 114 in the 9th and 11th columns are connected to the floors of the pixels 110 in the 1st row 9th column and the 1st row 11th column. Data signals Vid2 and Vid3 having a positive voltage corresponding to the key are sampled. Therefore, the data signal Vid1 sampled on the data line 114 in the seventh column is applied to the pixel electrode 118 in the first row and the seventh column. The data signals Vid2 and Vid3 sampled on the data lines 114 in the ninth and eleventh columns are also applied to the pixel electrodes 118 in the first row and the ninth column and the first row and the eleventh column, respectively.

Similarly, in the first half period Sub1, odd-numbered sampling signals R5, R7, R9
,..., And R383 are sequentially set to the H level, blocks B3, B4, B5,..., B192 are designated, and data signals Vid1, Vid2, and Vid3 are sampled on the odd-numbered data lines 114 of the designated block, respectively. Then, writing to the pixel electrode is performed.

Next, the operation in the second half period Sub2 in the horizontal scanning period H will be described.
The scanning control circuit 52 supplies the transfer start pulse DX even at the start of the second half period Sub2. Therefore, the shift signals S1, S2, S3,..., S96 by the shift register 140 have a relationship in which the transfer start pulse DX is sequentially delayed by half a cycle of the clock signal CLX even in the second half period Sub2.
However, since the scanning control circuit 52 sets the signal Sel to the L level in the second half period Sub2, the signal / Sel is set to the H level. For this reason, in the second half period Sub2, the sampling signal corresponding to the even-numbered columns of each block becomes H level during the pulse output period of the enable signal during the period in which the shift signal is H level. The sampling signal corresponding to the column never becomes H level.
Further, the scanning control circuit 52 outputs the enable signals Enb1, Enb2, Enb3, and Enb4 in the second half period Sub2 similarly to the first half period Sub1.
Therefore, when the transfer start pulse DX is supplied in the second half period Sub2, the even-numbered sampling signals R2, R4, R6, R8,..., R384 sequentially become H level exclusively, and the odd-numbered sampling signals R1, R3,. R5, R7,..., R383 are kept at the L level.

On the other hand, the scan control circuit 52 immediately before the sampling signal R2 becomes H level in the second half period Sub2 (strictly speaking, the period when the sampling signal R2 becomes H level is the period during which the shift signal S2 becomes H level. Since this is a period in which the enable signal Enb1 is at the H level, immediately before the enable signal Enb1 is set to the H level), as shown in FIG.
The operation of reading out the image data corresponding to the pixels 110 in the even-numbered columns from the line memory 310 is started. That is, in the second half period Sub2, it is the first row and is 2, 4, 6, 8, 1
Image data Vout corresponding to the pixels 110 of 0,.
The read image data Vout is expanded three times in the time axis direction by the S / P conversion circuit 320 in accordance with the period in which the sampling signal R2 is at the H level, and corresponds to the second, fourth, and sixth columns. The image data to be distributed is distributed in the order of image data Vd1, Vd2, and Vd3, respectively, converted into analog signals by the D / A conversion circuit group 330, and further converted into positive signals by the polarity inversion circuits 340, respectively. The signals Vid1, Vid2, and Vid3 are output.
If the sampling signal R2 is at the H level, the TFTs 165 corresponding to the even, second, fourth, and sixth columns among the first to sixth columns belonging to the block B1 are turned on. A positive voltage data signal Vid1 corresponding to the gray level of the pixel 110 in the column is sampled. Similarly, the data lines 114 in the 4th and 6th columns are connected to the floor of the pixel 110 in the 1st row 4th column and the 1st row 6th column. Data signals Vid2 and Vid3 having a positive voltage corresponding to the key are sampled. In the second half period Sub2, the scanning signal G1 is at the H level continuously from the first half period Sub1, so the data signal Vid1 sampled on the second column data line 114 is the first scanning line 112.
Is applied to the pixel electrode 118 in the first row and the second column corresponding to the intersection of the data line 114 in the second column. The data signals Vid2 and Vid3 sampled on the data lines 114 in the fourth and sixth columns are also applied to the pixel electrodes 118 in the first row and fourth column and the first row and sixth column, respectively.

Similarly, in the second half period Sub2, the even-numbered sampling signals R4, R6, R8
, R10,..., R384 are sequentially set to H level, blocks B2, B3, B4, B5,..., B192 are designated and data signals Vid1, Vid2, Vid3 are applied to the data lines 114 in the even-numbered columns of the designated block, respectively. Are sampled and writing to the pixel electrode is performed.
The above is the operation in the horizontal scanning period in which the scanning signal G1 is at the H level. However, the horizontal scanning period in which the scanning signals G2, G3,. In the first half period Sub1 and in the second half period Sub2, the odd-numbered columns of image data are read from the line memory 310 and written to the pixel electrodes through phase expansion, and the scanning line to be selected next to the selected scanning line The operation of storing the image data of the row in the line memory 310 is executed in the same manner. As a result, in this frame, writing of the positive voltage corresponding to the gradation is completed over all the pixels in the 1st to 864th rows.
The above is the operation in the horizontal scanning period in which the scanning signal G1 is at the H level, but each horizontal scanning period in which the scanning signals G2, G3,..., G864 are at the H level also corresponds to the selected scanning line 112. For the rows, writing in odd columns in the first half period Sub1 and writing in even columns in the second half period Sub2 are performed in the same manner. As a result, in this frame, writing of the positive voltage corresponding to the gradation is completed over all the pixels in the 1st to 864th rows.
In the next frame, the same writing is executed in the 1st to 864th lines. However, in this embodiment, as described above, the polarity inversion is performed for each frame. On the other hand, negative voltage writing corresponding to the gradation is executed.

Here, the voltage of the data signal Vid1 (to Vid3) will be described. As shown in FIG. 7 in the first half period Sub1 and as shown in FIG. 8 in the second half period Sub2, the S / P conversion circuit 320 respectively. In addition to being synchronized with the phase expansion operation, the signal is converted to the polarity specified by the polarity instruction signal Pol and output.
If the positive polarity writing is designated, the voltage of the data signal Vid1 is the voltage Vwp corresponding to white.
From the reference voltage Vc of the polarity in the range from the voltage Vwm corresponding to white to the voltage Vbm corresponding to black. The voltage is shifted by an amount corresponding to the gradation of the pixel (in the figure, it is indicated by ↑ for positive polarity and ↓ for negative polarity). Here, the positive voltage Vwp (and Vbp) and the negative voltage Vwm (and Vbm) are symmetric with respect to the voltage Vc.
Of the logical levels of the scanning signal and sampling signal, the H level is the power supply voltage Vdd, and the L level is the voltage reference in this embodiment and is the ground potential Gnd. Further, the vertical scale of the voltage of the data signal in FIGS. 7 and 8 is enlarged as compared with the voltage waveform which is another logic signal.

According to this embodiment, as shown in FIG. 9, in the horizontal scanning period H in which one row of a certain scanning line is selected, blocks B1, B2, B3,..., B192 are designated in the first half period Sub1. At the same time, the voltage corresponding to the gradation is written to the odd-numbered columns of the designated block, while the blocks B1, B2, B3,..., B192 are also designated in the second half period Sub2. A voltage is written to the even-numbered column of the block according to the gradation. For this reason, in this embodiment, as seen in the entire screen of the display area 100, as shown in FIG. 10, after writing, pixels are written in adjacent pixels on the left and right sides of the column (the first half period in FIG. 10). “1” because writing is done in the first time called Sub1
And a pixel that is not written at all in the adjacent pixels on the left and right sides of the column after writing (indicated as “2” because writing is performed in the second half period Sub2 in FIG. 10). Appear alternately one column at a time.
On the other hand, in the case of three-phase development in the prior art, as shown in FIG. 25, blocks B1, B2, B3,..., B192 are designated in the horizontal scanning period H in which one row of a certain scanning line is selected. At the same time, the voltage is only written in accordance with the gradation to the three columns of the designated block. Therefore, according to the conventional technique, as shown in FIG. 26, after writing, a pixel to be written in a pixel adjacent to the right of the column (denoted as “b” in the drawing) With respect to a pixel (indicated by “a” in the drawing) where writing is not performed in an adjacent pixel, the pixel appears in a cycle of “3” columns as the number of phase expansions.
In FIG. 26, the final 1152 column is represented as “b” for convenience, but strictly speaking, it is “a” because there is no adjacent pixel on the right side of the column.

In the pixel where writing is performed in the adjacent pixel after writing, it is considered that the written voltage fluctuates due to writing in the adjacent pixel. For pixels that are not performed, there is a case where a subtle gradation difference occurs even if the same gradation is displayed.
In this case, in the conventional technique, the gradation difference appears with a period of “3” columns, which is the number of phase expansions, so that it is easy to visually recognize, but in this embodiment, the odd-numbered columns and even-numbered columns Since they appear alternately and disperse, it is possible to make it difficult to visually recognize the gradation difference associated with the phase development drive method.
In the present embodiment, since there is no adjacent pixel on the left side of the column in the first column only, the influence after writing is affected by the other odd number 3, 5,..., 1151 columns (left and right columns after writing). It is also conceivable that the pixel is different from the pixel in which writing is performed in adjacent pixels. In this case, the first row may be shielded from light as a dummy area.

In the present embodiment, in the data line selection circuit 150, the NAND circuit 1512 provided corresponding to the odd number column of each block has a sampling signal H in the second half period Sub2.
The NAND circuit 1522 provided corresponding to the even number column of each block prohibits the signal from becoming the level, and the signal /
Since the configuration is prohibited by Sel, the enable signals Enb1 to Enb4 can be shared throughout the first half period Sub1 and the second half period Sub2, and the first NAND circuit 1512 in the odd column and the first NAND circuit 1522 in the even column in one block. A common shift signal can be supplied to the input terminals. For this reason, according to the present embodiment, the configuration for generating the enable signal is prevented from being complicated, and the shift register 140 may require two systems for the first half period Sub1 and the second half period Sub2. Since only one system is required, the configuration can be simplified.

  In addition, in the present embodiment, in the data line selection circuit 150, the enable signal Enb1 (or Enb3) is supplied corresponding to the odd number column of the block B (2j-1), and the block B (2j-1) is supplied. While the enable signals Enb2 (or Enb4) are supplied corresponding to the odd-numbered columns of the adjacent blocks (2j), the mutually exclusive pulses are output from the enable signals Enb1 to Enb4. In B (2j-1) and B (2j), the shift signal Sj can be made to correspond in common. Therefore, in this embodiment, the number of stages of the shift register 140 is reduced, and in this sense, the configuration of the shift register 140 can be simplified.

<Another example of pixel writing order: Part 1>
Next, some examples in which the order of writing to the pixel column is changed will be described.
In the above-described embodiment, the gradation difference appears alternately in the odd-numbered column and the even-numbered column, so that the gradation difference is difficult to visually recognize as compared with the conventional technique (see FIGS. 25 and 26). It can be said. However, since pixels to which writing is performed in adjacent pixels after writing and pixels to which writing is not performed are aligned in the same column, there is a high possibility that the pixels are visually recognized as linear stripes.
Therefore, in Example 1, as shown in FIG. 12, for example, in the horizontal scanning period H in which scanning lines of odd (1, 3, 5,..., 863) rows are selected, the first half period is the same as in the embodiment. In Sub1, the voltage corresponding to the gradation is written to the odd-numbered columns of the blocks designated in order, and in the second half period Sub2, the voltage corresponding to the gradation is written to the even-numbered columns of the designated blocks designated in order. In the horizontal scanning period H in which scanning lines of even (2, 4, 6,..., 864) rows are selected, on the contrary, in the first half period Sub1, the voltage corresponding to the gradation is applied to the even column of the designated block. In the second half period Sub2, the voltage corresponding to the gradation is written to the odd-numbered columns of the designated block.
As a result, in Example 1, as viewed in the entire screen of the display area 100, as shown in FIG. 13, a pixel in which writing is performed on adjacent pixels on the left and right of the column after writing (denoted as “1”). In addition, pixels that are not written at all at the left and right sides of the column after writing (denoted as “2”) alternately appear not only in the column direction but also in the row direction.
For this reason, according to Example 1, it becomes possible to make the difference in gradation associated with the phase development drive method less noticeable than in the embodiment.

In Example 1, in the horizontal scanning period in which even-numbered scanning lines are selected, the scanning control circuit 52 sets the signal Sel to the L level in the first half period Sub1 and the H level in the second half period Sub2, as shown in FIG. And As a result, in the first half period Sub1 of the horizontal scanning period for selecting the scanning lines of even rows, the voltage is written to the even number columns of the designated block, and in the second half period Sub2, the odd number columns of the designated block are written. The voltage will be written.
In Example 1, it is needless to say that odd and even rows may be replaced with the above example.

<Another example of pixel writing order: Part 2>
Next, Example 2 in which the order of writing to the pixel column is changed will be described.
In Example 2, for example, as shown in FIG. 14A, in a horizontal scanning period H in which one scanning line is selected in an n frame (for convenience, an odd frame is used), the same as in the embodiment. In the first half period Sub1, the voltage corresponding to the gradation is written to the odd-numbered columns of the block designated in order, and in the second half period Sub2, the voltage corresponding to the gradation is applied to the even-numbered column of the sequentially designated block. In the case of writing, as shown in FIG. 14B, in the horizontal scanning period H in which one row scanning line is selected in the next (n + 1) frame (even frame), on the contrary, in the first half period Sub1, The voltage corresponding to the gradation is written to the even-numbered column of the block designated in FIG. 2, and the voltage corresponding to the gradation is written to the odd-numbered column of the block designated in order in the second half period Sub2.
As a result, in Example 2, the entire screen of the display area 100 is displayed after writing as shown in FIG. 15A in the odd frame and in FIG. 15B in the even frame. Since pixels that are written to the adjacent pixels on the left and right (denoted as “1”) and pixels that are not performed (denoted as “2”) appear alternately in time, two frames are taken as a unit cycle. As a result, the gradation difference in each pixel is averaged.
Therefore, according to Example 2, it is possible to make the difference in gradation associated with the phase development driving method even more inconspicuous than in the embodiment.
In Example 2, it is needless to say that the odd frame and the even frame may be replaced with the above example.

<Another example of pixel writing order: Part 3>
Next, Example 3 in which the order of writing to the pixel column is changed will be described.
In Example 3, the concept of time change in Example 2 is applied to Example 1.
Specifically, in Example 3, as shown in FIG. 16, in the first half period Sub1 of the horizontal scanning period H in which the scanning lines of the odd rows are selected over the odd frames, the odd-numbered columns of the blocks designated in order are selected. In the second half period Sub2, in the second half period Sub2, the voltage is written in the even-numbered columns of the designated block in order, and among the horizontal scanning period H in which the scanning lines of the subsequent even-numbered rows are selected, in the first half period Sub1, When the voltage is written to the column and the voltage is written to the odd-numbered column of the designated block in the second half period Sub2, the horizontal scanning period for selecting the scanning lines of the odd-numbered rows as shown in FIG. Of H, the first half period Sub1
Then, the voltage is written to the even-numbered columns of the blocks designated in order, and in the second half period Sub2,
In the first half period Sub1 of the horizontal scanning period H in which the voltage is written to the odd-numbered columns of the designated block and the subsequent even-numbered scanning lines are selected, the voltage is written to the odd-numbered columns of the designated block. In the period Sub2, the voltage is written to the even-numbered columns of the designated block.
Thus, in Example 3, the entire screen of the display area 100 is displayed after writing as shown in FIG. 18A in the odd frame and in FIG. 18B in the even frame. In the same frame, pixels that are written to the pixels adjacent to the left and right (denoted as “1”) and pixels that are not performed (denoted as “2”) are alternately arranged for each row and column, and Since they appear alternately switched in every temporally adjacent frame, the gradation difference in each pixel is averaged when two frames are considered as a unit period.
Therefore, according to Example 3, it is possible to make the difference in gradation associated with the phase development driving method even more inconspicuous than in Example 1 and Example 2.
In Example 3, odd and even lines may be interchanged with the above example. Further, the odd frame and the even frame may be exchanged with the above example, and the exchange cycle may be two frames or more.

<Another example of pixel writing order: Part 4>
Next, Example 4 in which the order of writing to the pixel column is changed will be described.
In this example 4, the time change concept in example 3 is applied when the area scanning drive method described in, for example, Japanese Patent Application Laid-Open No. 2004-177930 is adopted as the drive method.
Since the detailed contents of the area scanning drive method are described in the above publication, a detailed description is avoided, but in brief, the display area 100 is an upper area (first area corresponding to the first to 432th scanning lines). Group) and the lower region (second group) corresponding to the scanning lines in the 433th to 864th rows, while one frame is divided into first and second fields as shown in FIG. In each field, the order of the first, 433, 2, 434, 3, 435,... 432, 864th row, that is, the upper region and the lower region are alternated, and the respective regions are directed downward. In this driving method, scanning lines are selected in the order in which they are headed.
Note that the logical division of the display area here does not mean that the display area is physically cut and divided, and it is not distinguished when viewed in the display area, but it is necessary to distinguish when viewed in the scanning order. It means that it was separated for convenience.

In the area scanning drive method, for example, when a positive voltage is written to a pixel belonging to the upper area in the first field and a negative voltage is written to a pixel belonging to the lower area, the pixel belongs to the upper area in the second field. A negative voltage is written for the pixels, and a positive voltage is written for the pixels belonging to the lower region. As a result, the ratio of the polarity of the voltage sampled on the data line after writing becomes approximately 50% for each of the positive polarity and the negative polarity regardless of the scanning line row for writing. As a result, the bias of the voltage polarity of the data line is eliminated, and the display quality is equalized.
In this area scanning drive method, since data signals are supplied in each of the first and second fields, the line memory 310 in FIG. 1 is a frame memory that stores image data Vin supplied from the host device for one frame. Is replaced.

In Example 4, as shown in FIG. 20, in the odd-numbered frame, in the first half period Sub1 of the horizontal scanning period H in which the scanning lines in the upper row are selected in the odd-numbered frames, the odd-numbered columns of the blocks designated in order. In the second half period Sub2, when the voltage is written to the even-numbered columns of the sequentially designated blocks, the next selected scanning line is the odd-numbered scanning line in the lower region. For this reason, in the horizontal scanning period H in which the odd-numbered scanning lines in the lower region are selected, in the first half period Sub1, in the same manner as in the horizontal scanning period in which the odd-numbered scanning lines in the upper region are selected, The voltage is written to the odd-numbered columns, and the voltage is written to the even-numbered columns of the designated block in the second half period Sub2.
The scanning line selected next to the odd-numbered scanning line in the lower region is an even-numbered scanning line following the odd-numbered row in the upper region. For this reason, in the horizontal scanning period H in which the even-numbered scanning lines in the upper region are selected, the horizontal scanning period in which the even-numbered scanning lines in the upper region are selected. The voltage is written to the even-numbered column, and the voltage is written to the odd-numbered column of the designated block in the second half period Sub2.
The scanning line selected next to the even-numbered scanning line in the upper region is an even-numbered scanning line following the odd-numbered row in the lower region. For this reason, in the horizontal scanning period H in which the even-numbered scanning lines in the lower region are selected, in the first half period Sub1, in contrast to the horizontal scanning period in which the odd-numbered scanning lines in the lower region are selected, The voltage is written to the even-numbered column, and the voltage is written to the odd-numbered column of the designated block in the second half period Sub2.
In the subsequent even frame, as shown in FIG. 21 and in the same manner as in Example 3, the relationship between the odd-numbered columns and the even-numbered columns is replaced with the relationship between the odd-numbered frames in the first half period Sub1 and the second half period Sub2 of each row. .

Thus, in Example 4, the entire screen of the display area 100 is expressed as “1” as shown in FIG. 22A in the odd frame and as shown in FIG. 22B in the even frame. And the pixel labeled “2” appear alternately in every row and column in the same frame and alternately in every adjacent frame in time. When viewed, the difference in gradation in each pixel is averaged.
Therefore, according to Example 4, it is possible to make the difference in gradation associated with the phase development driving method even more inconspicuous while enjoying the effect of the region scanning driving method.

<Another example of data line selection circuit>
The data line selection circuit 150 described above is not limited to the configuration shown in FIG. Therefore, another configuration of the data line selection circuit 150 will be described next.
FIG. 23 is a diagram showing an example of another configuration for the data line selection circuit 150.
In FIG. 23, NAND circuits 1502, 1532, and 1544 and a NOT circuit 1504 are provided corresponding to each block instead of the 3-input NAND circuits 1512 and 1522 corresponding to the odd and even columns of each block in FIG. The configuration after the NAND circuits 1514 and 1524 is the same as that of FIG.
In this configuration, the shift signal Sj is supplied in two branches corresponding to the blocks B (2j-1) and B (2j), not in the four branches.

A NAND circuit (common logic circuit) 1502 provided corresponding to each block is a two-input type, and a divided shift signal supplied to one input terminal and enable signals Enb1 to Enb4 supplied to the other input terminal. And the NOT circuit 1504 logically inverts the NAND signal generated by the NAND circuit 1502. The NAND circuits 1532 and 1542 are both of a two-input type, and are for odd columns and even columns in each block. Among these, the NAND circuit 1532 for odd-numbered columns outputs a negative logical product signal of the logical inversion signal from the NOT circuit 1504 supplied to one input terminal and the signal Sel supplied to the other input terminal, The column NAND circuit 1542 outputs a negative logical product signal of the logically inverted signal from the NOT circuit 1504 supplied to one input terminal and the signal / Sel supplied to the other input terminal.

Here, an enable signal is supplied to the other input terminal of the NAND circuit 1502 in the blocks B (2j-1) and B (2j) in the following relationship. That is, when j is an odd number, the enable signal Enb1 is supplied to the other input terminal of the NAND circuit 1502 in the block B (2j-1), and the other input terminal of the NAND circuit 1502 in the block B (2j). When the enable signal Enb2 is supplied and j is an even number, the other input terminal of the NAND circuit 1502 in the block B (2j-1) is supplied with the enable signal Enb3 and the block B (2j) The other input terminal of the NAND circuit 1502 has
An enable signal Enb4 is supplied.
Therefore, in the configuration in FIG. 23, sampling signals R1, R2, R3, R4,..., R384 similar to the configuration shown in FIG.

  According to the configuration shown in FIG. 23, since the signal Sel or the signal / Sel is not a three-input type but a two-input type NAND circuit 1502, not only can the drive capability decrease in the NAND circuit be avoided, Since the shift signal division path is halved to “2” and the number of NAND circuits connected to each output stage in the shift register 140 is reduced from four to two, the gate capacitance is halved, resulting in high driving. There is no need for ability. Therefore, in the data line selection circuit 150 shown in FIG. 23, not only its own data line selection circuit 150 but also the shift register 140 can be reduced in transistor size in the constituent elements, so that the circuit scale can be reduced. It becomes possible.

  Note that the data line selection circuit 150 shown in FIGS. 4 and 23 has a configuration in which a NOT circuit 1510 is built in and the signal Sel output from the scanning control circuit 52 is inverted to obtain the signal / Sel. However, the scanning control circuit 52 may output the signal / Sel together with the signal Sel.

In the embodiment and the like described above, the number of phase expansions m, which is the number of data lines to be simultaneously written, is set to “3”, and the number of image signal lines 162 corresponding to this is also set to “3”, but m is “2” or more. I just need it.
Further, in the above description, all the data lines 114 are precharged in the period immediately before sampling the data signal. However, a configuration in which no precharge is performed may be used.
The processing circuit 20 processes the digital image data Vin. However, the processing circuit 20 may be configured to input an analog image signal and develop the phase.

In each of the embodiments, the voltage LCcom applied to the common electrode 108 is matched with the potential Vc that is a reference for polarity inversion. However, when the TFT is an n-channel type, the gate-drain distance of the TFT is the same. Due to the parasitic capacitance, a phenomenon (also referred to as push-down, penetration, field-through, or the like) in which the potential of the drain (pixel electrode 118) decreases from on to off occurs. In order to prevent deterioration of the liquid crystal, alternating current drive is a principle in pixel capacitance, so that the common electrode 108 is alternately written on the higher side (positive polarity) and the lower side (negative polarity), but the voltage LCcom is set to the voltage If alternate writing is performed in a state where the voltage coincides with Vc, the effective voltage value of the pixel capacitance is larger in negative polarity writing than in positive polarity writing because of pushdown. For this reason, the voltage LCcom of the common electrode 108 is higher than the voltage Vc, which is the amplitude reference of the data signal, so that the effective voltage values of the pixel capacitors are equal to each other even when positive polarity / negative polarity writing is performed at the same gradation. May be set slightly lower.

In addition, in the embodiment and the like, the vertical scanning direction is the downward direction and the horizontal scanning direction is the right direction as viewed in FIG. 2, but in order to cope with a projector or a rotatable display device described later. In addition, the scanning direction may be switched.
Furthermore, instead of the normally white mode in which white display is performed when the effective voltage value of the pixel capacitance is small, a normally black mode in which black display is performed may be used.

In addition, the embodiments and the like have been described for the liquid crystal device. However, in the present invention, for example, an EL (Electronic) may be used as long as image data (video signal) is phase-expanded and simultaneously sampled on a plurality of data lines. The present invention is also applicable to a device using a (Luminescence) element, an electron emission element, an electrophoretic element, a digital mirror element, or a plasma display.

<Electronic equipment>
Next, as an example of an electronic apparatus using the electro-optical device according to the above-described embodiment, a projector using the above-described display panel 10 as a light valve will be described.
FIG. 24 is a plan view showing the configuration of the projector. As shown in this figure, a lamp unit 2102 made of a white light source such as a halogen lamp is provided inside the projector 2100. The projection light emitted from the lamp unit 2102 is separated into three primary colors of R (red), G (green), and B (blue) by three mirrors 2106 and two dichroic mirrors 2108 arranged inside. Are guided to the light valves 100R, 100G and 100B corresponding to the respective primary colors. Note that B light has a longer optical path than other R and G colors, and therefore, in order to prevent the loss, B light passes through a relay lens system 2121 including an incident lens 2122, a relay lens 2123, and an exit lens 2124. Led.

Here, the configuration of the light valves 100R, 100G, and 100B is the same as that of the display panel 10 in the above-described embodiment, and images corresponding to the R, G, and B colors supplied from the processing circuit (not shown in FIG. 24). Each is driven by a signal. That is, the projector 2100 has a configuration in which three sets of electro-optical devices 1 including the display panel 10 are provided corresponding to the colors R, G, and B.
The lights modulated by the light valves 100R, 100G, and 100B are incident on the dichroic prism 2112 from three directions. In the dichroic prism 2112, the R and B light beams are refracted at 90 degrees, while the G light beam travels straight. Therefore, after the images of the respective colors are combined, a color image is projected onto the screen 2120 by the projection lens 2114.

  Since light corresponding to the primary colors R, G, and B is incident on the light valves 100R, 100G, and 100B by the dichroic mirror 2108, it is not necessary to provide a color filter. The transmitted images of the light valves 100R and 100B are projected after being reflected by the dichroic mirror 2112, whereas the transmitted image of the light valve 100G is projected as it is, so the horizontal scanning direction by the light valves 100R and 100B is The image is reversed in the horizontal scanning direction by the light valve 100G and displayed in an inverted image.

  In addition to the electronic device described with reference to FIG. 24, the electronic device includes a television, a viewfinder type / monitor direct-view type video tape recorder, a car navigation device, a pager, an electronic notebook, a calculator, a word processor, a workstation, a television. Examples include a telephone, a POS terminal, a digital still camera, a mobile phone, and a device equipped with a touch panel. Needless to say, the above-described electro-optical device can be applied to these various electronic devices.

1 is a diagram illustrating an overall configuration of an electro-optical device according to an embodiment of the invention. 3 is a diagram showing a configuration of a display panel in the same electro-optical device. FIG. It is a figure which shows the structure of the pixel in the display panel. It is a figure which shows the structure of the data line selection circuit in the display panel. FIG. 6 is a diagram for explaining a vertical scanning operation of the electro-optical device. It is a figure for demonstrating the operation | movement of the horizontal scanning of the same electro-optical apparatus. FIG. 6 is a diagram for explaining a data signal writing operation of the electro-optical device. FIG. 6 is a diagram for explaining a data signal writing operation of the electro-optical device. It is a figure for demonstrating writing of the same electro-optical apparatus. It is a figure which shows the writing state of the same electro-optical device. It is a figure for demonstrating the operation | movement of the horizontal scanning of Example 1 which changed the writing order. 10 is a diagram for explaining writing according to Example 1. FIG. FIG. 6 is a diagram showing a writing state according to Example 1. It is a figure for demonstrating the writing which concerns on the example 2 which changed the writing order. FIG. 10 is a diagram showing a writing state according to Example 2. It is a figure for demonstrating the writing which concerns on the example 3 which changed the writing order. 10 is a diagram for explaining writing according to Example 3. FIG. FIG. 10 is a diagram showing a writing state according to Example 3. It is a figure which shows the operation | movement of the vertical scanning which concerns on the example 4 which changed writing order. 10 is a diagram for explaining writing according to Example 4. FIG. 10 is a diagram for explaining writing according to Example 4. FIG. FIG. 10 is a diagram showing a write state according to Example 4. It is a figure which shows another structure of the data line selection circuit in the same display panel. It is a figure which shows the structure of the projector to which the same electro-optical apparatus is applied. It is a figure for demonstrating the writing which concerns on a prior art. It is a figure which shows the writing state which concerns on a prior art.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Electro-optical apparatus, 10 ... Display panel, 20 ... Processing circuit, 100 ... Display area, 105 ... Liquid crystal, 110 ... Pixel, 112 ... Scan line, 114 ... Data line, 116 ... TFT, 118 ... Pixel electrode, 120 ... Liquid crystal capacitor, 130 ... scanning line drive circuit, 140 ... shift register, 150 ... data line selection circuit, 160 ... sampling circuit, 162 ... image signal line, 165 ... TFT, 1512, 1514, 1522, 1524 ... NAND circuit, 1516, 1518, 1526, 1528 ... NOT circuit, 2100 ... Projector

Claims (9)

Provided in correspondence with the intersection of a plurality of scanning lines and data lines blocked every 2m (m is an integer of 2 or more) columns, each of the data lines when the scanning line is selected A driving circuit of an electro-optical device having a plurality of pixels having gradations according to the data signal sampled in
A scanning line driving circuit for selecting the plurality of scanning lines in a predetermined order;
A shift register that sequentially outputs a predetermined pulse signal corresponding to each of the two blocks over a first period and a second period obtained by dividing a period in which one scanning line is selected by the scanning line driving circuit;
According to the pulse signal output by the shift register, two blocks are specified in order, and one of the first or second period is an odd column among 2m columns of data lines belonging to the specified block. A data line selection circuit that selects m columns of even-numbered data lines among the 2m columns of data lines belonging to the specified block in the other of the first or second period;
a sampling circuit for sampling the data signals supplied to the m image signal lines to m columns of data lines selected by the data line selection circuit;
An electro-optical device driving circuit comprising: The data line selection circuit includes:
Selecting a data line in an odd column by a logical operation of a period designation signal designating one of the first or second periods and a pulse signal from the shift register;
Electrical according to claim 1, wherein the selecting the data lines of the even rows by the logic operation of the pulse signal by the shift register and the period designating signal for designating that the other of said first or second time period Drive circuit for optical device. The data line selection circuit includes:
Corresponding to each block, it has a logic circuit for odd columns and even columns,
The logic circuit for the odd-numbered column performs the first operation by performing a logical operation on a period designation signal that designates one of the first or second periods, a pulse signal from the shift register, and a predetermined enable signal. Alternatively, a signal for selecting m columns of odd-numbered data lines in one of the second periods is output.
The logic circuit for the even columns is
An even column in the other of the first or second period is obtained by a logical operation of a period specifying signal that specifies the other of the first or second period, a pulse signal from the shift register, and a predetermined enable signal. The drive circuit of the electro-optical device according to claim 2, wherein a signal for selecting m columns of the data lines is output. The data line selection circuit corresponds to each block,
A common logic circuit that makes a pulse signal by the shift register an exclusive signal for each block by a logical operation with a predetermined enable signal;
By the logical operation of the period designation signal designating one of the first or second periods and the output signal from the common logic circuit, the odd-numbered data lines are connected to m in one of the first or second periods. A logic circuit for odd columns that outputs a signal for column selection;
By means of a logical operation of a period designating signal designating the other of the first or second period and an output signal from the common logic circuit, the data lines in the even columns in the other of the first or second period are A logic circuit for an even column that outputs a signal for column selection;
The drive circuit of the electro-optical device according to claim 2, wherein The shift register outputs each pulse signal obtained by sequentially shifting an input pulse with a clock signal in correspondence with two adjacent blocks,
The data line selection circuit includes a logic circuit that causes the pulse signals output from the shift register to be mutually exclusive in the two blocks by a logical operation with a predetermined enable signal.
The drive circuit of the electro-optical device according to claim 1. The shift register outputs each pulse obtained by sequentially shifting the input pulse using a clock signal while overlapping the pulse widths between adjacent ones.
The data line selection circuit includes a logic circuit that causes the pulse signal output from the shift register to be mutually exclusive in a block corresponding to the pulse signal by a logical operation with a predetermined enable signal.
The drive circuit of the electro-optical device according to claim 1. Dividing the plurality of rows of scanning lines into at least a first group and a second group along an arrangement direction of the scanning lines, and dividing a vertical scanning period into at least first and second fields;
The scanning drive circuit selects the scanning lines belonging to the first and second groups alternately and sequentially in a predetermined direction in each of the first and second fields. Item 8. A drive circuit for an electro-optical device according to Item 1. Provided in correspondence with the intersection of a plurality of scanning lines and data lines blocked every 2m (m is an integer of 2 or more) columns, each of the data lines when the scanning line is selected A plurality of pixels having gradation according to the data signal sampled in
A scanning line driving circuit for selecting the plurality of scanning lines in a predetermined order;
A shift register that sequentially outputs a predetermined pulse signal corresponding to each of the two blocks over a first period and a second period obtained by dividing a period in which one scanning line is selected by the scanning line driving circuit;
According to the pulse signal output by the shift register, two blocks are specified in order, and one of the first or second period is an odd column among 2m columns of data lines belonging to the specified block. A data line selection circuit that selects m columns of even-numbered data lines among the 2m columns of data lines belonging to the specified block in the other of the first or second period;
a sampling circuit for sampling the data signals supplied to the m image signal lines to m columns of data lines selected by the data line selection circuit;
An electro-optical device comprising:   An electronic apparatus comprising the electro-optical device according to claim 8.

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