JP2001337654A - Flat display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve such an inferior display such as an unevenness in a display without requiring a complicated configuration. SOLUTION: A flat display device consists of the insulative panel 10, the plural display pixel PX installed in a matrix shape on the panel 10, the plural signal lines X1-X2n which are installed on one side of each column of the display pixel and almost in parallel each other, the plural switching element W which is connected between each of corresponding signal line and corresponding display pixel and conducted to concurrently select the display pixel in each row, the plural signal distribution portion AS1-ASn which are installed to classify plural signal lines to plural blocks consisting of each of 2 adjacent signal lines and distribute the pixel picture signal on each 1/2 canning period basis to the corresponding signal line in the corresponding block in a selecting period of the display pixel in each row, and the dummy signal line XD installed on the other side of the display pixel in column which is an end not wedged between the 2 signal lines. Tins device also consists of the dummy electric potential control portion ASD to impress the dummy pixel picture signal to dummy signal line XD during the 1/2 horizontal scanning period.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a flat display device in which a plurality of display pixels are arranged in a matrix and driven through a plurality of signal lines formed along the columns of the display pixels. The present invention relates to a flat panel display device which distributes pixel video signals to signal lines and even-numbered column signal lines for a predetermined time.

[0002]

2. Description of the Related Art Flat display devices represented by liquid crystal display devices are used in devices such as personal computers and portable information terminals because of their light weight and low power consumption.
A typical liquid crystal display device includes a liquid crystal panel and a control unit that controls the liquid crystal panel. The liquid crystal panel has a plurality of display pixels arranged in a matrix, a plurality of scanning lines formed along a row of the plurality of display pixels, a plurality of signal lines formed along a column of the plurality of display pixels, A plurality of thin film transistors (TFTs) are provided adjacent to the intersections of the lines and the scanning lines, and each supply a pixel video signal from the corresponding signal line to a corresponding display pixel in response to a scanning signal from the corresponding scanning line. The control unit includes a scanning line driving circuit for driving each of the scanning lines, a signal line driving circuit for driving each of the signal lines, and a display timing control unit for controlling operations of the scanning line driving circuit and the signal line driving circuit. Each display pixel includes a thin film transistor driven via a corresponding scanning line and a pixel electrode connected to a corresponding signal line via the thin film transistor, and the potential of the signal line corresponding to the pixel video signal is determined by the light transmittance of the display pixel. Is set to the pixel electrode via the thin film transistor in order to control. The signal line drive circuit is composed of, for example, a plurality of TAB-ICs fixed to one end of the liquid crystal panel. Generally, these TAB-ICs have a plurality of output terminals respectively connected to a plurality of signal lines, and are configured to sequentially output pixel video signals from these output terminals in each horizontal scanning period. However, in the case where the number of pixels is increased by reducing the pixel size in order to increase the resolution of the liquid crystal panel, the TAB-I is limited under the restriction of the panel size.
The number of output terminals of C must be increased, the connection pitch between all the output terminals of the TAB-IC and the signal lines is also reduced, and it becomes difficult to connect them.

Conventionally, to solve such a problem, T
There is known a time division driving technique in which each output of the AB-IC is distributed to an odd column signal line and an even column signal line via a corresponding analog switch and driven. In this technology, TAB-I
C sequentially supplies pixel video signals to odd-numbered column signal lines via analog switches in the first half of one horizontal scanning period, and sequentially supplies pixel video signals to even-numbered signal lines via analog switches in the second half of this horizontal scanning period. Supply. When the pixel video signals are allocated in this way, the total output fraction of all TAB-ICs can be reduced to １ ／ of the number of signal lines.

[0004]

However, in this time-division driving technique, a signal line not electrically connected to the TAB-IC output by an analog switch is in a floating state. Each signal line is susceptible to a change in potential of a signal line that is capacitively coupled adjacent to the signal line at a small interval in a floating state, and thus display unevenness may occur.

[0005] In view of such problems, an object of the present invention is to provide:
An object of the present invention is to provide a flat panel display device that can improve display defects such as display unevenness without requiring a complicated configuration.

[0006]

According to the present invention, there is provided an insulating panel, a plurality of display pixels arranged in a matrix on the insulating panel, and a plurality of display pixels arranged on one side of each column of display pixels. A plurality of substantially parallel signal lines, a plurality of switching elements connected between the corresponding signal lines and the corresponding display pixels, and a plurality of switching elements which are turned on so as to simultaneously select the display pixels in each row; A plurality of signal distributing units that are arranged so as to divide a plurality of signal lines into blocks, and that distribute pixel video signals to adjacent signal lines of a corresponding block by a predetermined time during a selection period of display pixels in each row; And a dummy signal line disposed on the other side of the display pixel in a column which is an end not sandwiched by two of the above.
Further, there is provided a flat panel display device including a dummy potential control unit for applying a dummy pixel video signal to a dummy signal line for a predetermined time.

In this flat panel display, the dummy potential controller applies a dummy pixel video signal to the dummy signal line for a predetermined time. Thereby, the display pixel arranged next to the dummy signal line can be set in an environment that is electrically similar to other display pixels. Therefore, it is possible to improve display unevenness that occurs in the edge display pixels.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a flat panel display according to an embodiment of the present invention will be described with reference to the accompanying drawings. FIG. 1 schematically shows the structure of the flat panel display. The flat panel display includes a liquid crystal panel 10 having a structure in which a liquid crystal layer LQ is held between an array substrate AR and a counter substrate CT, and a control circuit board 20 for controlling the liquid crystal panel 10.
The liquid crystal panel 10 has a rectangular display section including a plurality of display pixels PX arranged in a matrix.

FIG. 2 shows a part of the array substrate AR shown in FIG. 1 in more detail. The array substrate AR includes m × 2n pixel electrodes PE arranged in a matrix, and these pixel electrodes PE
Scanning lines Y1 to Ym formed along the row of the pixel electrodes PE, 2n signal lines X1 to X2n formed along the columns of the pixel electrodes PE, these signal lines X1 to X2n and the scanning lines Y1 to Ym.
There are a plurality of polysilicon thin film transistors W which are arranged in the vicinity of the intersection of Ym and constitute switching elements which respectively supply a potential of the corresponding signal line to the corresponding pixel electrode PE in response to a scanning signal from the corresponding scanning line. Counter substrate C
T is a single common electrode CE facing a plurality of pixel electrodes PE.
Having. Further, the array substrate AR has m auxiliary capacitance lines which are formed insulated so as to cross the pixel electrodes PE of the corresponding rows and are set to the potential of the common electrode CE. Each pixel electrode PE forms an auxiliary capacitance Cs in cooperation with an auxiliary capacitance line,
A liquid crystal capacitor CLC is formed in cooperation with the common electrode CE. Each display pixel PX is configured using a thin film transistor W, a pixel electrode PE, a common electrode CE, a liquid crystal capacitor, and an auxiliary capacitor Cs, and is set to a potential set to the pixel electrode PE and the common electrode CE via the thin film transistor W. The light transmittance corresponding to the potential difference from the potential is set.

The liquid crystal panel 10 further includes an array substrate AR
And a scanning line drive circuit 12 arranged in an outer region of the matrix array of the display pixels PX along one end of the display pixel PX. The scanning line driving circuit 12 is connected to the scanning lines Y1 to Ym, and sequentially drives these scanning lines Y1 to Ym. Here, the scanning line drive circuit 12 is composed of a plurality of polysilicon thin film transistors integrally formed on the array substrate AR, like the thin film transistors W forming the switching elements. Further, the flat display device includes a plurality of TAB-LEDs fixed to one end of the array substrate AR and one end of the control circuit substrate 20, respectively.
The signal line driving circuit 22 including the IC 30 is provided. The signal line drive circuit 22 outputs pixel video signals from the output terminals D1 to Dn for the odd column signal lines X1, X3,... X2n-1 and the even column signal lines X2, X4,. These output terminals D1 to Dn are connected to n pairs of first and second analog switches AS1, AS2 arranged outside the matrix array of the display pixels PX;
AS3, AS4; ...; AS2n-1 and AS2n, respectively, are connected to the first analog switches AS1, AS3, ..., AS2n-1.
Are connected to odd column signal lines X1, X3,... X2n-1, respectively.
The second analog switches AS2, AS4,..., AS2n are connected to the even-numbered signal lines X2, X4,.

The control circuit board 20 includes a timing control section 23 for controlling the timing of the scanning line driving circuit 12 and the signal line driving circuit 22. The timing control unit 23 receives a video signal and a synchronization signal supplied from the external computer PC, and outputs a horizontal start pulse S
TH, horizontal clock signal CLK, vertical start pulse S
TV, vertical clock signals φ1, φ2 and video signal DAT
A is generated as before. Here, the pixel video signal DA
TA is the pixel electrode P of the display pixel PX adjacent in the row direction.
E are signals whose polarities are inverted with respect to the potential of the common electrode CE in order to be applied to the common electrode CE.
TV is a pulse generated for each frame, vertical clock signals φ1 and φ2 are complementary clock signals generated in a vertical clock cycle corresponding to one horizontal scanning period, and a horizontal start pulse STH is ２. The horizontal clock signal CLK is a pulse signal generated every horizontal scanning period, and the horizontal clock signal CLK is a clock signal generated in a horizontal clock cycle corresponding to a 1 / 2n horizontal scanning period. Video signal DATA,
Horizontal start pulse STH and horizontal clock signal C
LK is supplied to the signal line drive circuit 22. The vertical start pulse STV and the vertical clock signals φ1 and φ2 are TAB
-It is supplied to the scanning line drive circuit 12 using the empty wiring 30 of the IC. The vertical clock signal φ1 is used as a switch control signal for the first analog switches AS1, AS3,.
AS2n-1 is supplied to the non-inverting clock input terminal.
The second analog switches AS2, AS4,..., AS2n are supplied to inverted clock input terminals. The vertical clock signal φ2 is used as a switch control signal for the second analog switch AS2,
, AS2n, and the first analog switches AS1, AS3,.
It is supplied to the inverted clock input terminal of S2n-1.

The signal line drive circuit 22 responds to an output signal obtained from a parallel output terminal of the shift register, for example, by shifting a horizontal start pulse STH sequentially in synchronization with the horizontal clock signal CLK, and a video signal DATA. It includes n analog switches to be sampled, and n output buffers that output voltage signals sampled by these analog switches from the output terminals D1 to Dn as pixel video signals.

The scanning line driving circuit 12 has a shift register SR and an output circuit BF as shown in FIG. The shift register SR is composed of m flip-flops F1 to Fm connected in series, shifts the vertical start pulse STV in one direction in synchronization with the vertical clock signals φ and φ bar, and outputs these flip-flops as sequential scanning signals. Output from the output terminals of the loops F1 to Fm. The output circuit BF includes m output buffers OB1 to OBm that output scanning signals obtained from the output terminals of the flip-flops F1 to Fm to the scanning lines Y1 to Ym, respectively. As shown in FIG. 3, the scanning lines Y1 to Ym sequentially receive a scanning signal every one horizontal scanning period, and select a row of the display pixels PX. Display pixel P of each row
In X, the pixel electrode PE is connected to the signal lines X1 to X2n via the corresponding thin film transistor W which becomes conductive in response to the scanning signal.
Is electrically connected to As shown in FIG. 3, the vertical clock signals φ1 and φ2 are clock pulses having a phase difference of 差 horizontal scanning period. Therefore, the first analog switches AS1, AS3,..., AS2n-1 and the second analog switches AS2, AS4,. As a result, the even column signal lines X2, X4,
, X2n are sequentially set to a potential corresponding to the pixel video signal in the first half of one horizontal scanning period, and the odd-numbered signal lines X1, X3,.
.. X2n-1 are sequentially set to a potential corresponding to the pixel video signal in the latter half of one horizontal scanning period. That is, in each row, the pixel electrode PE of the odd-numbered display pixel PX is set to a potential corresponding to the pixel video signal in the first half of one horizontal scanning period, and the pixel electrode PE of the even-numbered display pixel PX is set in the second half of one horizontal scanning period. The potential is set according to the pixel video signal.

In this flat panel display, the signal lines X1 to X2n
Are partially laminated on each of the adjacent pixel electrodes PE so as to function as a light-shielding layer, and are disposed substantially parallel to the left side of the column of the display pixels PX. The signal line X2n blocks light passing through the left side of the column of the end display pixels PX, but light passing through the right side of the column of the end display pixels PX cannot be blocked because no signal line is provided. For this reason, the dummy signal line XD is further arranged on the right side of the column of the end display pixels PX so as to form a light shielding layer like the signal lines X1 to X2n. This allows
All the columns of the display pixels PX are sandwiched between two of the X1 to the signal lines X2n and the dummy signal lines XD. This dummy signal line XD is connected to a dummy potential control unit that controls the potential of the dummy signal line XD. This dummy potential control unit applies the dummy pixel video signal to the dummy signal line XD when the pixel video signal is applied to the pixel electrode PE of the display pixel PX adjacent in the row direction with the polarity inverted with respect to the potential of the common electrode CE. Is configured to match the pixel video signal applied to the signal line X2n-1 disposed further adjacent to the signal line X2n adjacent to. The dummy potential control unit is, for example, an analog switch ASD having a structure similar to that of the analog switches AS1 to AS2n and connected between the output terminal Dn of the signal line driving circuit 22 and the dummy signal line XD. In this case, the vertical clock signal φ1 is supplied as a switch control signal to the non-inverted clock input terminal of the analog switch ASD, and the vertical clock signal φ2 is supplied as a switch control signal to the inverted clock input terminal of the analog switch ASD.

FIG. 4 shows the operation of the flat panel display device.
This will be described with reference to FIG. When a scanning signal is supplied to the scanning line Y1 to select, for example, the display pixels PX in the first row,
All the thin film transistors W connected to the scanning line Y1 are turned on, and all the thin film transistors W connected to the scanning lines Y2 to Ym are turned off. The display pixel PX in the first row is 1
It is selected over the horizontal scanning period (1H). When the first analog switches AS1, AS3,..., AS2n-1 become conductive in response to the rise of the switch control signal φ1 (vertical clock signal), the potentials of the odd column signal lines X1, X3,. It changes according to the pixel video signal output from the output terminals D1 to Dn of the circuit 22. For example, the odd signal line X2n-1
Rises from the initial potential V0 toward the potential V1 as shown in FIG. The switch control signal φ1 is maintained at a high level for a 1 / 2H sampling period Tw1, and falls after the sampling period TW1 has elapsed. The first analog switches AS1, AS3,..., AS2n-1 are turned off in response to the fall of the switch control signal φ1. Thereby, the potentials of the odd-numbered column signal lines X1, X3,... X2n-1 are held, and the potential of the pixel electrode PE is set via the odd-numbered column thin film transistor W.

On the other hand, the second analog switches AS1, AS
, AS2n-1 become conductive in response to the rise of the switch control signal φ2 (vertical clock signal), the potentials of the even column signal lines X2, X4,.
It changes according to the pixel video signal output from 1 to Dn. For example, the potential of the even signal line X2n falls from the initial potential V2 toward the potential V0 as shown in FIG. The switch control signal φ2 is maintained at a high level for a 1 / 2H sampling period TW2, and falls after the elapse of the sampling period TW2. The second analog switches AS2, AS4,
..., AS2n becomes non-conductive in response to the fall of the switch control signal φ2. As a result, the even column signal lines X2, X4,
The potential of X2n is held, and the potential of the pixel electrode PE is set via the even-numbered thin film transistors W.

The thin film transistor W in each row outputs a scanning signal of 1
It becomes non-conductive by falling after the horizontal scanning period.
Therefore, the potential of the pixel electrode PE is held until the scanning signal rises again in the next frame.

Here, the odd column signal line X2n-1 is electrically connected to the pixel electrode PE capacitively coupled to the even column signal line X2n via the thin film transistor W as shown by Cf in FIGS. Therefore, when the floating state occurs in the sampling period TW1, the even-numbered column signal line X2n
As shown in FIG. 3, the potential fluctuates by V1 -.DELTA.V1 in accordance with the potential change of. The even-numbered column signal lines X2n are shown in FIGS.
Since the pixel electrode PE is electrically connected to the pixel electrode PE capacitively coupled to the dummy signal line XD via the thin film transistor W as indicated by Cf in the sampling period TW2, the floating state occurs during the sampling period TW2 due to the potential change of the dummy signal line XD. As shown in FIG. 3, the potential fluctuates by V1−ΔV1. Incidentally, when the potential of the dummy signal line XD is fixed as in the related art, the potential of the signal line X2n does not fluctuate.
The environment is electrically different from X.

In the flat display device of the present embodiment, the analog switch ASD applies a dummy pixel video signal corresponding to the pixel video signal applied to the signal line X2n-1 to the dummy signal line XD for a sampling period of 1 / 2H. . As a result, the column of the display pixels PX arranged next to the dummy signal line XD is set to an environment that is electrically similar to the columns of the other display pixels PX. Therefore, it is possible to eliminate display defects such as display unevenness in which only the right end display pixel PX becomes slightly black without requiring a complicated configuration.

In the case where the plurality of color display pixels CPX are each constituted by three display pixels PX of red (R), green (G), and blue (B) adjacent in the row direction, the dummy potential control is performed. Section is a dummy pixel video signal to a dummy signal line X
The corresponding signal line X2n-5 of the color display pixel CPX arranged next to the color display pixel CPX including the signal line X2n adjacent to D
Is configured to match the pixel video signal supplied to the pixel. Specifically, as shown in FIG. 5, the analog switch ASD is connected between the output terminal Dn-2 of the signal line driving circuit 22 and the dummy signal line XD, and the analog switch ASn-2
Is configured to be conducted in conjunction with. As a result, good image display can be obtained, especially during color raster display.

In the above-described embodiment, as shown in FIG. 6, the thin film transistor W is disposed on the right side of each of the signal lines X1 to 2n.
When the pixels are arranged on the left side of each of n, display unevenness occurs in which only the column of the display pixels PX at the left end becomes black. In this case, the dummy signal line XD may be arranged on the left side of the display pixel PX at the left end, and the analog switch ASD may be connected to the dummy signal line XD.

Further, the flat display device according to the above-described embodiment includes:
Although the configuration is such that the pixel video signal obtained from each output terminal of the signal line drive circuit 22 is distributed to two signal lines, the pixel video signal may be distributed to more than two signal lines. .

The scanning line driving circuit 12 and the signal line driving circuit 22 shown in FIG. 1 use the same manufacturing process as the thin film transistor W as the switching element to form the array substrate AR.
Since it can be formed above, there is no need to separately provide a manufacturing process.

[0024]

According to the present invention, it is possible to provide a flat display device capable of improving display defects such as display unevenness without requiring a complicated structure.

[Brief description of the drawings]

FIG. 1 is a plan view schematically showing a structure of a flat panel display according to an embodiment of the present invention.

FIG. 2 is a plan view showing a part of the array substrate shown in FIG. 1 in more detail.

FIG. 3 is a time chart illustrating an operation of the scanning line driving circuit illustrated in FIG. 2;

FIG. 4 is a time chart for explaining potentials of a signal line and a dummy signal line set via the analog switch shown in FIG. 2;

FIG. 5 is a diagram illustrating parasitic capacitance between pixel electrodes and signal lines for a plurality of display pixels illustrated in FIG. 2;

6 is a diagram showing a parasitic capacitance between a pixel electrode and a signal line for the end display pixel shown in FIG. 2;

FIG. 7 is a view for explaining a modification of the flat panel display device shown in FIG. 1;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 ... Liquid crystal panel 20 ... Control circuit board 30 ... TAB-IC 12 ... Scanning line drive circuit 22 ... Signal line drive circuit 23 ... Timing control part AR ... Array substrate LQ ... Liquid crystal layer CT ... Counter substrate CE ... Common electrode PE ... Pixel Electrode PX: Display pixel X1 to X2n: Signal line Y1 to Ym: Scan line

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 2H093 NA16 NA33 NC16 NC22 NC50 ND09 ND34 5C006 AA21 AC21 AF59 BB16 BC11 BF24 FA22 FA31 5C080 AA10 BB05 CC03 DD05 DD10 DD12 FF11 JJ02 JJ03 JJ04 JJ06 5C094 AA19 EA04 EB02 FB12

Claims (4)

[Claims] 1. An insulating panel, a plurality of display pixels arranged in a matrix on the insulating panel, a plurality of signal lines arranged on one side of each column of display pixels and substantially parallel to each other, A plurality of switching elements connected between the corresponding signal lines and the corresponding display pixels and conducting so as to simultaneously select display pixels in each row, and the plurality of signal lines are divided into a plurality of blocks each including a predetermined number of adjacent signal lines. A plurality of signal distributing units that are arranged so as to distribute pixel video signals to adjacent signal lines of a corresponding block by a predetermined time during a selection period of a display pixel of each row, and are sandwiched by two of the plurality of signal lines. A dummy signal line disposed on the other side of the display pixel in the column that is not the end portion, and a dummy potential control unit that applies a dummy pixel video signal to the dummy signal line for the predetermined time. A flat panel display characterized by the above-mentioned. 2. A plurality of insulating panels each comprising first and second transparent substrates and a liquid crystal layer held between these transparent substrates, wherein each display pixel is arranged in a matrix on the first transparent substrate. Pixel electrode, a common electrode disposed on the second transparent substrate so as to face the plurality of pixel electrodes, and a part of a liquid crystal layer corresponding to between the pixel electrode and the common electrode. When the polarities are applied to the pixel electrodes of the display pixels adjacent in the row direction with the polarities inverted with respect to the potential of the common electrode, the dummy potential control unit outputs the dummy pixel video signal to a signal line adjacent to the dummy signal line. 2. The flat display device according to claim 1, wherein the flat display device is configured to match a pixel video signal applied to a signal line disposed further adjacent to. 3. When the plurality of color display pixels are each composed of a predetermined number of display pixels adjacent in the row direction, the dummy potential control unit includes a dummy pixel video signal including a signal line adjacent to the dummy signal line. The flat display device according to claim 2, wherein the flat display device is configured to match a pixel video signal applied to a corresponding signal line of the color display pixel arranged next to the color display pixel. 4. The flat display device according to claim 1, wherein the plurality of signal lines and the dummy signal lines are stacked so as to partially overlap display pixels in a column interposed therebetween.