JPH06148680A - Matrix type liquid crystal display device - Google Patents
Matrix type liquid crystal display deviceInfo
- Publication number
- JPH06148680A JPH06148680A JP29840392A JP29840392A JPH06148680A JP H06148680 A JPH06148680 A JP H06148680A JP 29840392 A JP29840392 A JP 29840392A JP 29840392 A JP29840392 A JP 29840392A JP H06148680 A JPH06148680 A JP H06148680A
- Authority
- JP
- Japan
- Prior art keywords
- tft
- liquid crystal
- thin film
- signal
- film transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Liquid Crystal (AREA)
- Thin Film Transistor (AREA)
- Liquid Crystal Display Device Control (AREA)
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明は、マトリクス表示装置に
係わり、特に信号側の駆動回路の規模を低減でき使用数
を少なくし、表示装置の小型化を可能にするマトリクス
装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a matrix display device, and more particularly to a matrix device which can reduce the size of a drive circuit on the signal side, reduce the number of used circuits, and downsize the display device.
【0002】[0002]
【従来の技術】フラットディスプレイとして、MOS,
薄膜トランジスタ(以下TFTと称す。)等の3端子素
子及び、MIM(Metal-Insurator-Metal)等の2端子素
子とスイッチング素子として用い、画像を表示する液晶
アクティブマトリクス表示装置が知られている。2. Description of the Related Art As a flat display, MOS,
There is known a liquid crystal active matrix display device that displays an image by using a three-terminal element such as a thin film transistor (hereinafter referred to as a TFT) and a two-terminal element such as a MIM (Metal-Insurator-Metal) and a switching element.
【0003】従来の技術によるTFTの駆動による液晶
アクティブマトリクス表示装置としては特開昭60−9732
2 号に示されているものがある。これは各画素を夫々独
立に駆動するためのTFTがマトリクス状に形成された
基板を有する液晶マトリクスパネルにおいて2個以上の
同一電気特性のTFTをまとめたTFT群からなり、同
一の群に含まれるTFTは同一の走査線及び信号線に接
続されていることを特徴としている。この時1つのTF
T群に含まれるTFTに接続されている各画素を合わせ
たものを1つの画素とみなすことで、TFTの動作不良
による完全な画素欠陥の発生を低減することが可能であ
る。A conventional liquid crystal active matrix display device by driving a TFT is disclosed in JP-A-60-9732.
There is one shown in No. 2. This is composed of a TFT group in which two or more TFTs having the same electric characteristics are combined in a liquid crystal matrix panel having a substrate in which TFTs for independently driving each pixel are formed in a matrix, and are included in the same group. The TFT is characterized in that it is connected to the same scanning line and signal line. One TF at this time
By considering each pixel connected to the TFTs included in the T group as one pixel, it is possible to reduce the occurrence of complete pixel defects due to defective operation of the TFTs.
【0004】[0004]
【発明が解決しようとする課題】上記、従来の技術によ
る液晶アクティブマトリクス表示装置においては複数個
の分割画素で1つの画素を形成しているためパネルに形
成するTFT数及び分割画素数が多くなり1画素の大き
さを一定とするとTFT及び分割画素を小さく形成する
必要があるため、TFTの動作不良の増加や、画素電極
の面積が小さくなり精細度が低下する。In the above-described liquid crystal active matrix display device according to the prior art, since one pixel is formed by a plurality of divided pixels, the number of TFTs and the number of divided pixels formed on the panel increases. If the size of one pixel is fixed, it is necessary to make the TFT and the divided pixel small, so that the malfunction of the TFT is increased and the area of the pixel electrode is reduced, and the definition is lowered.
【0005】また、n行m列の画素がマトリクス状に配
列されたマトリクスパネルの走査線はn本、信号線はm
本必要である。このため走査駆動回路,信号駆動回路の
出力本数は、夫々n本,m本となる。出力数がk本の駆
動回路を用いて駆動装置を構成する場合、全体の駆動回
路数UはU≧n/k+m/k個必要である。特にコンピ
ュータ等の端末装置のモニターに適用する場合、高精細
のマトリクスパネルが必要であり、この時の画素数は4
60万画素以上となって、駆動回路数が非常に多くな
る。また、カラー表示を行う場合、信号駆動回路は走査
駆動回路と比較して回路が複雑であるため回路面積が大
きくなる。以上従来技術により高精細のマトリクスパネ
ルを駆動すると駆動回路の規模が非常に大きくなり、表
示装置を小型化,軽量化することが難しくまた信頼性の
点でも問題があった。A matrix panel in which pixels of n rows and m columns are arranged in a matrix has n scanning lines and m signal lines.
I need a book. Therefore, the numbers of outputs of the scanning drive circuit and the signal drive circuit are n and m, respectively. When a drive device is configured using drive circuits having k outputs, the total number U of drive circuits must be U ≧ n / k + m / k. Especially when applied to a monitor of a terminal device such as a computer, a high-definition matrix panel is required, and the number of pixels at this time is 4
With more than 600,000 pixels, the number of drive circuits becomes very large. Further, in the case of performing color display, the circuit area of the signal drive circuit is large because the circuit is more complicated than the scan drive circuit. As described above, when a high-definition matrix panel is driven by the conventional technique, the scale of the drive circuit becomes very large, which makes it difficult to reduce the size and weight of the display device and has a problem in reliability.
【0006】本発明の目的は装置全体の駆動回路を小型
化し装置の簡素化,高信頼性化を達成することにある。An object of the present invention is to reduce the size of the drive circuit of the entire device and achieve simplification and high reliability of the device.
【0007】[0007]
【課題を解決するための手段】上記目的を達成するた
め、本発明は、n行,m列の画素からなるマトリクスパ
ネルにおいて各列行毎の隣接するTFT薄膜のドレイン
電極をt個単位(但し、tは任意)でまとめて共通に接
続して1本の信号線で形成すると共に共通に接続された
各々のTFTを独立に制御できるように各行毎につきt
本の走査線を形成する。In order to achieve the above object, the present invention provides a matrix panel consisting of pixels of n rows and m columns, in which the number of adjacent drain electrodes of the TFT thin film for each row is t (where , T are arbitrary) and connected in common to form a single signal line, and t in each row so that each commonly connected TFT can be independently controlled.
Form a scan line of a book.
【0008】[0008]
【作用】上記手段を用いることにより、走査線数が従来
例と比較してt倍となり、一方の信号線数が1/t倍と
なる。これによって装置全体の駆動回路数Uは、U≧
(t×n)/k+m/(t×k)となりn≦mの場合に
は駆動回路数は低減され表示装置全体の小型化を向上さ
せることが可能になる。また信号線数が1/tになるた
めに走査回路に比べて複雑な信号駆動回路の出力数も1
/tになり回路の規模を小さくできる。By using the above means, the number of scanning lines is t times that of the conventional example, and the number of one signal line is 1 / t times. As a result, the number U of drive circuits of the entire device is U ≧
In the case of (t × n) / k + m / (t × k), where n ≦ m, the number of drive circuits is reduced and the miniaturization of the entire display device can be improved. Further, since the number of signal lines is 1 / t, the number of outputs of the signal driving circuit, which is more complicated than that of the scanning circuit, is 1
Therefore, the circuit scale can be reduced.
【0009】[0009]
【実施例】本発明による液晶アクティブマトリクス表示
装置の構成例を図1に示す。FIG. 1 shows an example of the structure of a liquid crystal active matrix display device according to the present invention.
【0010】装置はTFT30,31,画素電極10,
11,走査線104,105,ゲート接続線106,1
07,信号線101の各部品で構成されたTFT群30
0がマトリクス状に配置されたTFT基板1と図示して
ないが共通電極6を設けた共通電極基板との間に液晶を
封入した液晶パネルと走査駆動回路2,信号駆動回路
3,フレームメモリ回路5で構成され、全体としてn行
m列の画素を持つマトリクス表示装置を成している。The device comprises TFTs 30, 31, pixel electrodes 10,
11, scanning lines 104 and 105, gate connection lines 106 and 1
07, TFT group 30 composed of signal line 101 parts
A liquid crystal panel in which liquid crystal is sealed between a TFT substrate 1 in which 0s are arranged in a matrix and a common electrode substrate (not shown) provided with a common electrode 6, a scanning drive circuit 2, a signal drive circuit 3, a frame memory circuit 5 to form a matrix display device having pixels of n rows and m columns as a whole.
【0011】以下、本実施例の特徴であるパネルの構成
を説明する。隣接する画素電極10及び11にTFT3
0及び31のソース電極Sを接続すると共に前記TFT
30及び31のドレイン電極Dの両方を信号線101に
接続する。また、前記TFT30のゲート電極を走査線10
4にゲート接続線106を介して接続すると共にTFT
31のゲート電極を走査線105にゲート接続線107
を介して接続する。このようにしてTFT群300を形
成し、同様にTFT群をパネル全体にマトリクス状に形
成する。この接続によりTFT群中の各々のTFTを独
立してON又はOFF状態に制御できる。次に各走査線
を走査駆動回路2の出力端子に接続し、各信号線を信号
駆動回路3の出力端子に接続する。以下同様にしてパネ
ル全体の走査線,信号線を駆動回路に接続する。こうす
ることにより走査線,信号線各々に独立した駆動電圧を
印加することができる。前記信号駆動回路3の入力端子
はフレームメモリ回路5の出力端子に接続され、前記フ
レーム回路5の入力端子は映像信号源4に接続する。フ
レームメモリ回路5はパソコン等の映像信号源4から出
力される映像信号を取り込み、映像信号のデータ出力順
番を変換して出力をおこなう。この変換方法を図2を用
いて説明を行う。図2に示すようにmが2の倍数(偶
数)の場合、1水平走査期間(1H)毎に1,2,3,
4,…,m−1,m列目データというように順次送られ
て来る映像信号をフレームメモリ回路によって変換し、
1H毎に奇数データを1,3,…,m−1列データを順
次1水平奇数列期間中(1/2水平走査期間)に出力
し、次に偶数列データを2,4,…,m列データを順次
1水平偶数列期間中(1/2水平走査期間)に出力す
る。この映像信号の変換を行うことで信号駆動回路3の
出力端子は1Hにおいて最初の1/2Hで奇数列の信号
電圧を発生し、次の1/2Hで偶数列画素の信号電圧を
出力することになる。この結果、フレームメモリ回路を
映像信号源と信号電圧駆動回路の間に設けることで本実
施例の液晶マトリクスパネルの各画素電極に所定の信号
電圧を印加することが可能となる。The configuration of the panel, which is a feature of this embodiment, will be described below. The TFT 3 is formed on the adjacent pixel electrodes 10 and 11.
The source electrodes S of 0 and 31 are connected and the TFT is
Both the drain electrodes D of 30 and 31 are connected to the signal line 101. In addition, the gate electrode of the TFT 30 is connected to the scanning line 10
4 via the gate connection line 106 and TFT
The gate electrode 31 is connected to the scanning line 105 and the gate connection line 107.
Connect through. In this way, the TFT group 300 is formed, and similarly, the TFT group is formed in a matrix on the entire panel. By this connection, each TFT in the TFT group can be independently controlled to be turned on or off. Next, each scanning line is connected to the output terminal of the scanning drive circuit 2, and each signal line is connected to the output terminal of the signal drive circuit 3. In the same manner, scan lines and signal lines of the entire panel are connected to the drive circuit. By doing so, independent drive voltages can be applied to the scanning lines and the signal lines. The input terminal of the signal drive circuit 3 is connected to the output terminal of the frame memory circuit 5, and the input terminal of the frame circuit 5 is connected to the video signal source 4. The frame memory circuit 5 takes in the video signal output from the video signal source 4 such as a personal computer, converts the data output order of the video signal, and outputs the data. This conversion method will be described with reference to FIG. As shown in FIG. 2, when m is a multiple of 2 (even number), 1, 2, 3, and 3 are obtained every horizontal scanning period (1H).
4, ..., m-1, m-th column data, such as sequentially transmitted video signals are converted by the frame memory circuit,
.., m-1 column data are sequentially output every 1H during one horizontal odd column period (1/2 horizontal scanning period), and then the even column data is 2, 4 ,. The column data is sequentially output during one horizontal even column period (1/2 horizontal scanning period). By converting this video signal, the output terminal of the signal drive circuit 3 generates the signal voltage of the odd-numbered column at the first 1 / 2H at 1H and outputs the signal voltage of the even-numbered column at the next 1 / 2H. become. As a result, by providing the frame memory circuit between the video signal source and the signal voltage drive circuit, it becomes possible to apply a predetermined signal voltage to each pixel electrode of the liquid crystal matrix panel of this embodiment.
【0012】次に本実施例の液晶マトリクスパネルの駆
動方法を図3を用いて説明する。Next, a method of driving the liquid crystal matrix panel of this embodiment will be described with reference to FIG.
【0013】例えば実施例におけるパネルの1列1行目
の液晶画素を駆動させるには走査線104に走査電圧V
G(104)を印加してTFT30を1/2Hの期間O
N状態にする。この状態で信号線101に信号電圧VD
(101)を印加して液晶画素を駆動させる。同様に走
査電圧VG(104)を印加したときにはすべての信号
線に信号電圧を印加し、1行目の全ての奇数列液晶画素
を駆動する。この時1行目の全ての偶数列液晶画素のT
FTはOFF状態であるため液晶画素に変化は生じな
い。For example, in order to drive the liquid crystal pixels in the first column and the first row of the panel in the embodiment, the scanning voltage V is applied to the scanning line 104.
G (104) is applied to turn on the TFT 30 for 1/2 H
Set to N state. In this state, the signal voltage VD is applied to the signal line 101.
(101) is applied to drive the liquid crystal pixels. Similarly, when the scanning voltage VG (104) is applied, the signal voltage is applied to all the signal lines to drive all the odd-numbered column liquid crystal pixels in the first row. At this time, the Ts of all the liquid crystal pixels in the first row
Since the FT is in the OFF state, no change occurs in the liquid crystal pixel.
【0014】次に走査線104に接続されているTF
T、つまり1行目の全ての奇数列液晶画素に接続された
TFTがOFF状態になったときに走査線105に走査
電圧VG(105)を印加して偶数列目のTFT31を
1/2Hの期間ON状態にする。この状態で信号線10
1に信号電圧VD(101)を印加して液晶画素を駆動
させる。同様に走査電圧VG(105)を印加したとき
にはすべての信号線に信号電圧を印加し、1行目の全て
の偶数列液晶画素を駆動する。この時1行目の全ての奇
数偶数列液晶画素のTFTはOFF状態であるため液晶
画素に変化は生じない。このようにして1Hの期間にお
いて1行目のすべての液晶画素を駆動する。以下パネル
の走査線に順次走査電圧を印加し全ての画素を駆動させ
る。Next, the TF connected to the scanning line 104
T, that is, when the TFTs connected to all the odd-numbered column liquid crystal pixels in the first row are turned off, the scanning voltage VG (105) is applied to the scanning line 105 to set the even-numbered TFTs 31 to 1 / 2H. Turn on for a period. In this state, the signal line 10
The signal voltage VD (101) is applied to the signal 1 to drive the liquid crystal pixels. Similarly, when the scanning voltage VG (105) is applied, the signal voltage is applied to all the signal lines to drive all the even-numbered column liquid crystal pixels in the first row. At this time, since the TFTs of all the odd-numbered and even-numbered liquid crystal pixels in the first row are in the OFF state, no change occurs in the liquid crystal pixels. In this way, all the liquid crystal pixels in the first row are driven in the period of 1H. Hereinafter, a scanning voltage is sequentially applied to the scanning lines of the panel to drive all pixels.
【0015】この結果、上記手段を用いることにより、
n行m列の画素をもつ液晶マトリクスパネルにおいて走
査線数が従来例と比較して2倍となり、一方の信号線数
が1/2倍となる。これによって装置全体の駆動回路数
Uは、1つの駆動回路の出力数をkとしたときにU≧
(2×n)/k+m/(2×k)となりn≦mの場合に
は駆動回路数は低減される。これにより表示装置全体の
小型化を向上させることが可能になる。また信号線数が
1/2になるために信号駆動回路の出力数も1/2にな
り回路の規模を小さくできる。As a result, by using the above means,
In the liquid crystal matrix panel having pixels of n rows and m columns, the number of scanning lines is doubled as compared with the conventional example, and the number of one signal line is halved. As a result, the number U of drive circuits of the entire device is U ≧ when the number of outputs of one drive circuit is k.
(2 × n) / k + m / (2 × k), and when n ≦ m, the number of drive circuits is reduced. This makes it possible to improve the miniaturization of the entire display device. Further, since the number of signal lines is halved, the number of outputs of the signal drive circuit is halved, and the circuit scale can be reduced.
【0016】この実施例においてはmは2の倍数(偶
数)であるがmが奇数の場合においては図4に示すよう
にm−1列目までの画素構成は前記実施例と同様である
が1行m列目の画素構成は画素電極28にTFT48の
ソース電極が接続され、そのTFT48のゲート電極は
走査線104に接続され、TFT48のドレイン電極は
信号線110に接続されている。同様に各行のm列目の
画素電極は信号線110に接続された構成をとるようにす
る。このように1行あたりに接続されているTFTの数
がすべての信号線において同じ必要はなく他の信号線と
1行あたり接続されるTFTが異なった信号線が配線さ
れる場合でもよい。In this embodiment, m is a multiple (even number) of 2, but when m is an odd number, as shown in FIG. 4, the pixel configuration up to the (m-1) th column is the same as that of the above embodiment. In the pixel configuration of the 1st row and the mth column, the source electrode of the TFT 48 is connected to the pixel electrode 28, the gate electrode of the TFT 48 is connected to the scanning line 104, and the drain electrode of the TFT 48 is connected to the signal line 110. Similarly, the m-th pixel electrode in each row is connected to the signal line 110. As described above, the number of TFTs connected per row does not have to be the same in all signal lines, and a signal line different from other signal lines in the TFT connected per row may be provided.
【0017】この図1の実施例においては走査線104
と105は画素電極30と31の上部に配線がなされて
いるために走査線104とTFT30のゲート電極を接
続するためにゲート接続線106が必要となる。このゲ
ート接続線106と走査線105が交差するため配線交
差108が生じる。しかし図5のように走査線104と1
05が画素電極30と31の上部と下部に配線を配置す
ることにより、ゲート接続線と走査線との配線交差の生
じない構造となり動作不良が低減できる。In the embodiment of FIG. 1, the scan line 104
Since wirings 105 and 105 are formed on the pixel electrodes 30 and 31, a gate connection line 106 is required to connect the scanning line 104 and the gate electrode of the TFT 30. Since the gate connection line 106 and the scanning line 105 intersect, a wiring intersection 108 occurs. However, as shown in FIG. 5, scan lines 104 and 1
By arranging wirings on the upper and lower portions of the pixel electrodes 30 and 31 in 05, a structure in which wiring crossing between the gate connection line and the scanning line does not occur can be achieved, and malfunctions can be reduced.
【0018】この図1のパネル構造を持つ実施例におい
て、画素電極は水平方向,垂直方向に配列された構造を
しているが図6に示すように例えば画素電極12が画素
電極10の真下ではなく、水平方向に半画素ずれて画素
電極10と11の斜め下に配置すようなデルタ配置をと
るパネル構造のものでも信号線101を蛇行させて配線
を行う場合でもよい。In the embodiment having the panel structure of FIG. 1, the pixel electrodes are arranged horizontally and vertically, but as shown in FIG. 6, for example, when the pixel electrode 12 is directly below the pixel electrode 10. Alternatively, a panel structure having a delta arrangement in which the pixel electrodes 10 and 11 are arranged diagonally below the pixel electrodes by being shifted by half a pixel in the horizontal direction may be used even when the signal line 101 is made to meander.
【0019】この図1における実施例においてパソコン
等の映像信号源から出力された映像信号をフレームメモ
リ回路を用いて実施例パネルを駆動できる映像信号に変
換を行っているが映像信号源そのものから実施例パネル
を駆動できる映像信号が出力され直接信号駆動回路に入
力する場合及び信号駆動回路に実施例パネルを駆動でき
る映像信号に映像信号を変換する機能を持たせた場合で
もよい。In the embodiment shown in FIG. 1, a video signal output from a video signal source such as a personal computer is converted into a video signal capable of driving the embodiment panel by using a frame memory circuit. For example, a video signal capable of driving the panel may be directly output to the signal drive circuit, or a signal drive circuit may have a function of converting the video signal into a video signal capable of driving the embodiment panel.
【0020】この図1における実施例においてはTFT
群は2個のTFTで成り立っているが図7に示すように
例えば3個のTFT220〜222が1本の信号線21
2に接続される場合、または、図示してないが1行あた
り4個以上のTFTからなるTFT群でパネルが形成さ
れた場合のものでもよい。その際、例えば図7のTFT
250が走査線201と接続し、TFT251が走査線
202と接続しTFT252が走査線203と接続され
ているように共通に1本の信号線に接続された各々のT
FTを独立に制御できるように各TFTのゲート電極は
それぞれ異なる走査線に接続しTFT群301が形成さ
れる。TFT群が4個以上のTFTから成り立つ場合でも
群中のTFTのソース電極が個々の画素電極に接続さ
れ、各ドレイン電極が1本の信号線に接続され、各ゲー
ト電極が別々の走査線に接続されていればよい。この際
フレームメモリ回路も出力状態が変わり、例えば3個の
TFTが1本の信号線に接続される場合は図8に示すよ
うにフレームメモリ回路の出力はmを3の倍数とすると
1H期間において1,4,7,…m−5,m−2列目デ
ータを最初の1/3H期間に出力し、2,5,8,…m
−4,m−1列目データを次の1/3H期間に出力、最
後の1/3H期間に3,6,9,…,m−3,m列目デ
ータと順次出力を行う。これにより図9に示すように各
走査線選択時にその走査線にTFTを介して接続された
画素電極に所定の信号を印加可能にすればよく、1行あ
たり3個以上のTFTが1本の信号線に接続される場合
でも同様である。このように1行あたり3個以上のTF
Tが1本の信号線に接続される場合においても映像信号
のデータ出力をフレームメモリ回路で変換し映像信号の
データ出力順番の並べ替えを行うことで走査線に薄膜ト
ランジスタを介して接続されている画素電極に所定の信
号電圧を印加することができる。In the embodiment shown in FIG. 1, the TFT is
Although the group is composed of two TFTs, as shown in FIG. 7, for example, three TFTs 220 to 222 include one signal line 21.
Alternatively, it may be connected to two or, although not shown, a panel is formed by a TFT group including four or more TFTs per row. At that time, for example, the TFT of FIG.
Each T connected in common to one signal line such that 250 is connected to the scanning line 201, TFT 251 is connected to the scanning line 202, and TFT 252 is connected to the scanning line 203.
The gate electrodes of each TFT are connected to different scanning lines so that the FT can be controlled independently, and a TFT group 301 is formed. Even when the TFT group consists of four or more TFTs, the source electrodes of the TFTs in the group are connected to individual pixel electrodes, each drain electrode is connected to one signal line, and each gate electrode is connected to a separate scanning line. It only needs to be connected. At this time, the output state of the frame memory circuit also changes. For example, when three TFTs are connected to one signal line, the output of the frame memory circuit is 1H period when m is a multiple of 3 as shown in FIG. 1, 4, 7, ... M-5, m-2 column data is output in the first 1 / 3H period, and 2, 5, 8 ,.
The −4, m−1th column data is output in the next 1 / 3H period, and in the last 1 / 3H period, the data of 3, 6, 9, ..., M−3, m columns are sequentially output. As a result, as shown in FIG. 9, when each scanning line is selected, a predetermined signal can be applied to the pixel electrode connected to the scanning line via the TFT. It is sufficient that one row has three or more TFTs. The same applies when connected to a signal line. Thus, 3 or more TFs per line
Even when T is connected to one signal line, the data output of the video signal is converted by the frame memory circuit, and the data output order of the video signal is rearranged to connect to the scanning line through the thin film transistor. A predetermined signal voltage can be applied to the pixel electrode.
【0021】[0021]
【発明の効果】以上詳述したように本発明によれば、マ
トリクス型液晶表示パネルを駆動する際に用いる駆動回
路の使用数を低減することにより表示装置全体の小型化
を可能にする。As described above in detail, according to the present invention, it is possible to reduce the size of the entire display device by reducing the number of drive circuits used for driving the matrix type liquid crystal display panel.
【図1】本発明によるマトリクス型液晶表示パネルの実
施例を示す図である。FIG. 1 is a diagram showing an embodiment of a matrix type liquid crystal display panel according to the present invention.
【図2】本発明によるフレームメモリ回路の映像信号変
換例を示す図である。FIG. 2 is a diagram showing an example of video signal conversion of a frame memory circuit according to the present invention.
【図3】本発明による駆動タイミング例を示す図であ
る。FIG. 3 is a diagram showing an example of drive timing according to the present invention.
【図4】本発明の変形例を示す図である。FIG. 4 is a diagram showing a modified example of the present invention.
【図5】本発明の変形例を示す図である。FIG. 5 is a diagram showing a modified example of the present invention.
【図6】本発明の変形例を示す図である。FIG. 6 is a diagram showing a modified example of the present invention.
【図7】本発明の応用例を示す図である。FIG. 7 is a diagram showing an application example of the present invention.
【図8】本発明の応用例に対するフレームメモリ回路の
映像信号変換例を示す図である。FIG. 8 is a diagram showing an example of video signal conversion of a frame memory circuit for an application example of the present invention.
【図9】本発明の応用例に対する駆動タイミング例を示
す図である。FIG. 9 is a diagram showing an example of drive timing for an application example of the present invention.
1…TFT基板、2…走査駆動回路、3…信号駆動回
路、4…映像信号源、5…フレームメモリ回路、6…共
通電極、10,11,28…画素電極、30,31,4
8,250,251,252…TFT、101,11
0,212…信号線、104,105,201,20
2,203…走査線、106,107…ゲート接続線、
108…配線交差、300,301…TFT群。DESCRIPTION OF SYMBOLS 1 ... TFT substrate, 2 ... Scan drive circuit, 3 ... Signal drive circuit, 4 ... Video signal source, 5 ... Frame memory circuit, 6 ... Common electrode, 10, 11, 28 ... Pixel electrode, 30, 31, 4
8,250,251,252 ... TFT, 101,11
0, 212 ... Signal lines, 104, 105, 201, 20
2, 203 ... Scan line, 106, 107 ... Gate connection line,
108 ... Wiring intersection, 300, 301 ... TFT group.
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.5 識別記号 庁内整理番号 FI 技術表示箇所 H01L 29/784 (72)発明者 筧 直文 茨城県日立市大みか町七丁目1番1号 株 式会社日立製作所日立研究所内─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. 5 Identification number Internal reference number FI Technical indication location H01L 29/784 (72) Inventor Naofumi Kakei 7-1, 1-1 Omika-cho, Hitachi-shi, Ibaraki Hitachi, Ltd. Hitachi Research Laboratory
Claims (3)
一方に共通電極、他方の基板上にマトリクス状に配列さ
れた薄膜トランジスタ、該薄膜トランジスタのソース電
極に一対一に接続された画素電極、各行毎の隣接する薄
膜トランジスタをt個単位(但し、tは任意)でまとめ
た薄膜トランジスタ群、前記薄膜トランジスタ群中の各
薄膜トランジスタのドレイン電極が共通に接続されてい
る信号線、前記薄膜トランジスタ群の各薄膜トランジス
タのゲート電極がそれぞれ別々に接続された各行毎にt
本設けられた走査線で少なくとも構成された液晶パネ
ル。1. A liquid crystal is enclosed in a pair of substrates, a common electrode is provided on one of the substrates, a thin film transistor is arranged in a matrix on the other substrate, and a pixel electrode is connected to a source electrode of the thin film transistor in a one-to-one relationship. A thin film transistor group in which adjacent thin film transistors in each row are grouped in t units (where t is arbitrary), a signal line to which the drain electrodes of the thin film transistors in the thin film transistor group are commonly connected, and thin film transistors in the thin film transistor group. For each row in which the gate electrodes of
A liquid crystal panel including at least scanning lines provided.
群の薄膜トランジスタの数により映像信号源から出力さ
れる映像信号データを取り込み映像信号のデータ出力順
番の並べ替えを変化させて出力を行うことを特徴とする
フレームメモリ回路。2. The video signal data output from a video signal source is taken in according to the number of thin film transistors of the thin film transistor group, and the data output order of the video signals is rearranged for output. Frame memory circuit to do.
ネルの走査線に接続された走査駆動回路、前記信号線に
映像信号を供給する信号駆動回路及び前記信号駆動回路
に接続された請求項2におけるフレームメモリ回路で少
なくとも構成されたことを特徴とするマトリクス型液晶
表示装置。3. The liquid crystal panel according to claim 1, a scan drive circuit connected to a scan line of the liquid crystal panel, a signal drive circuit for supplying a video signal to the signal line, and a signal drive circuit connected to the signal drive circuit. 2. A matrix type liquid crystal display device comprising at least the frame memory circuit in.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP29840392A JPH06148680A (en) | 1992-11-09 | 1992-11-09 | Matrix type liquid crystal display device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP29840392A JPH06148680A (en) | 1992-11-09 | 1992-11-09 | Matrix type liquid crystal display device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH06148680A true JPH06148680A (en) | 1994-05-27 |
Family
ID=17859258
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP29840392A Pending JPH06148680A (en) | 1992-11-09 | 1992-11-09 | Matrix type liquid crystal display device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH06148680A (en) |
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