JPH02214817A - Liquid crystal display device and its driving method - Google Patents

Abstract

PURPOSE:To obtain an excellent image quality at a large-screen, high-definition display by applying gate signals from both ends of each gate line of a liquid crystal panel or applying data signals from both ends of each data line, and shortening the propagation delay time of the gate line or data line. CONSTITUTION:Gate drivers 2 and 2' are connected to both ends of each gate line and in-phase gate pulses are inputted from both ends of each gate line. At this time, the longest propagation delay time is obtained at the center part of the screen, but the delay time can be shortened to <=1/4 time the time of a conventional driving method. Namely, VgL and VgR are applied to both ends of one gate line to reduce the parasitic capacity and wiring resistance effectively to 1/2 time that when a voltage is applied to one side and the delay time is shortened to 1/4 time. The same effect is obtained when signals are applied, but both are combined to shorten the propagation time more. Consequently, an excellent image screen can be formed at the large-screen, high-definition display device.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to an active matrix liquid crystal display device and a method for driving the same, and is particularly suitable for achieving good image quality in the case of high definition and large screens. The present invention relates to a liquid crystal display device and a driving method thereof.

[Conventional technology]

An active matrix liquid crystal display device is described in, for example, Japanese Patent Laid-Open No. 18886/1986 (US Pat. No. 29642).

FIG. 2 is an example of a conventional active matrix liquid crystal panel as described above.

In FIG. 2, 21 is a liquid crystal cell arranged in a matrix, 22 is a charge storage capacitor, and 23 is a thin film transistor connected to one electrode of each liquid crystal cell 21. It consists of Moreover, 24 is a plurality of (m) commonly connected to the data electrodes of the thin film transistors 23 for each column of the active matrix.
The data lines D1 to D, , 25 are a plurality of (n) gate lines 61 to Gn commonly connected to the gate electrodes of the thin film transistors 23 for each row of the active matrix.

Further, 26 is a gate scanning circuit (hereinafter referred to as gate driver) that sequentially applies scanning pulses to the gate lines, and 27 is a data scanning circuit (hereinafter referred to as data driver) that applies image signals for one horizontal scan to the data lines in parallel. ). Further, 28 is a transparent common electrode that is commonly connected to the other electrode of all the liquid crystal cells 21 formed on a substrate that faces the substrate on which the thin film transistor is formed and the liquid crystal interposed therebetween.

Next, driving of the above liquid crystal display device will be explained.

FIG. 3 schematically shows an example of a drive waveform of the prior art.

In FIG. 3, in synchronization with the application of the voltage VON that turns on the thin film transistor to the i-th gate line G,
An image signal vDJ is applied to the i-th data line Da. As a result, charges are accumulated in the storage capacitor and the liquid crystal capacitor in the pixel CId. This accumulation of charges is what is called writing of an image signal.

Writing of the image signal as described above starts at time TI and ends at t1+Δt, and at the same time the gate voltage becomes VOFF. Then, the voltage of the pixel C1 is held at vDJ until the signal is written again at time t s + T after one field period T.

Note that in line sequential scanning, the i-th gate line G1
The thin film transistors connected to the pixel Cik (k = 1 to m) are simultaneously driven, and the same signal writing as above is performed simultaneously in the pixel Cik (k = 1 to m), although the image signals are different.

Next, at time t I+ 1 = t i + Δt, the i+1th
A voltage VON that turns on the thin film transistor is applied to the gate line G1+, and the pixel Ct+Hh (k = 1
A signal is written to ~m). This signal writing ends at time t1+2Δt.

As described above, a voltage is sequentially applied to each gate line to turn on the thin film transistor line by line, thereby driving the pixels connected to the gate line.

[Problem to be solved by the invention]

The principle driving method for an active matrix liquid crystal display device is as described above, but in actual driving, propagation delays of gate voltage pulses and image signal voltage pulses must be taken into consideration.

This is the distortion of the drive waveform caused by the resistance of the gate wiring and data wiring and the parasitic capacitance thereof.

The above problem will be explained using FIG. 4.

FIG. 4 is a waveform diagram of the gate signal and the gate signal with propagation delay. In FIG. 4, even if the voltage applied to the gate line is a square wave (voltage waveform with zero or extremely short rise and fall times) on the gate driver 26 side, the voltage applied to the gate line is dependent on the wiring resistance and capacitance of the gate line itself. The waveform is distorted by
It becomes a waveform with t is. As a result, in the case of FIG. 4, the signal writing time is effectively shortened from the original Δt by at least jrg. In addition, if a similar propagation delay is observed on the data signal side, the signal writing time will be further shortened.

The value of the above propagation delay time can generally be estimated as follows.

FIG. 5 is an equivalent circuit diagram showing gate propagation delay in the i-th gate line GI.

In FIG. 5, C is the parasitic capacitance per pixel,
It is expressed as a composite capacitance of the capacitance at the intersection of the gate wiring and the data wiring, the parasitic capacitance of the thin film transistor, the storage capacitance of the pixel area, etc. Further, R is a wiring resistance that is predominantly determined by the wiring material. Using these and the number m of data lines in the horizontal direction, the propagation delay time can be estimated by the following equation.

jrg-m2C-R-(]-) Here, if the change in C based on the change in capacitance of the thin film transistor is considered, t□ can also be estimated from equation (1). The same applies to data signal delays.

Incidentally, amorphous silicon is often used in thin film transistors as switching elements.

This is because it is advantageous for increasing the area of the transistor matrix array and reducing costs. However, in the case of this amorphous silicon thin film transistor, MO using crystalline silicon
Its field effect mobility is considerably lower than that of an S transistor. Therefore, it is difficult to sufficiently write the image signal into the pixel portion within the writing time Δt-trg reduced by the propagation delay as shown in FIG.

In order to solve the above problem, it has been necessary to increase the transistor size or to
As described in No. 4, countermeasures such as shifting the gate signal and data signal were taken.

However, the above-mentioned measures are not sufficient to realize a display with a larger area and higher definition (m size), and there is also a problem that it causes a decrease in yield when manufacturing a substrate.

Furthermore, in addition to the propagation delay as described above, there has also been a problem in that the signal load per output of the gate driver increases.

An object of the present invention is to provide a liquid crystal display device and a method for driving the same that can reduce the influence of the propagation delay of the gate pulse or data signal without changing the size of the thin film transistor.

[Means to solve the problem]

In order to achieve the above object, the present invention is configured as described in the claims.

That is, the present invention reduces the propagation delay time in the gate lines by applying gate signals from both ends of each gate line of the liquid crystal panel.

Further, as another configuration of the present invention, the propagation delay time in the data lines is reduced by applying data signals from both ends of each data line of the liquid crystal panel.

Note that claim 1 describes a configuration for reducing the propagation delay time of a gate line, the second term describes a driving method thereof, the third term describes a configuration for reducing a data line propagation delay time, and the fourth term describes a driving method thereof. Items 5 and 6 of the method are applications of the liquid crystal display device and driving method thereof of the present invention.

[For production]

FIG. 6 is a gate pulse waveform diagram for explaining the present invention in detail.

Figure 6 shows the gate pulse Vgt applied to the left end of the first gate line and its delayed waveform at its right end, and the gate pulse Vgn applied to the right end of the same gate line and its delayed waveform at its left end. It is something.

When VgL and VOR are applied to both ends of the same gate line at the same time, the waveform becomes a superimposition of at least the above two waveforms.

At this time, although the propagation delay time is greatest at the center of the screen, the magnitude of the delay time can be reduced to 1/4 or less of that in the conventional driving method. In other words, by applying VgL and VaR to both ends of one gate line, the parasitic capacitance and wiring resistance are both effectively reduced to 1/2 compared to when voltage is applied to one side.
), the delay time is 1/4.

Note that the above explanation has been about driving the gate lines, but as another method, if signals are applied simultaneously from both ends of each data line, the propagation delay time of the data signal can be reduced to 1/1 of that of the conventional case. Since the number can be set to 4 or less, sufficient time for signal writing can be secured.

Therefore, the conventional problem of shortening the signal writing time is solved.

Further, by combining both the data line driving and gate line driving described above, the propagation delay time can be further shortened.

〔Example〕

(Example 1) FIG. 1 is a diagram showing a first embodiment of the present invention, in which (a) is a block diagram of a liquid crystal display device, (b) is a circuit diagram of a liquid crystal panel, and (c) and (d) are diagrams of a liquid crystal display device. It is a waveform diagram of a gate pulse.

In FIG. 1, a liquid crystal panel 1 has a matrix electrode formed of gate lines and data lines, as in FIG.
A thin film transistor is provided at each intersection. Further, 2 and 2' are gate drivers, which are respectively connected to both ends of each gate line. This gate driver 2
and 2' are constituted by shift registers having the same number of stages as the number of gate lines, and the output thereof is controlled by a clock signal generated by the control signal generating section 4.

Further, 3 is a data driver, which is composed of a shift register, a latch, and the like. Reference numeral 5 denotes an image signal generation section, which converts the image signal into a drive waveform matching the display and outputs it to the data driver 3.

The liquid crystal display device according to this embodiment differs from the conventional display device shown in FIG. 2 in that gate drivers 2 and 2' are connected to both ends of each gate line, and gate pulses of the same phase are inputted from both ends of each gate line. This is a feature.

FIG. 1(Q) is a diagram showing a pulse input to the first gate line. In this way, by applying in-phase pulses VgL and VgR from both ends of each gate line,
The propagation delay time of the gate pulse can be reduced to 1/4 or less of the conventional one.

Note that, regarding the pulses applied to the i-th gate line, the input pulse V &L (i) from the left end and the input pulse V+rR(i) from the right end do not necessarily need to be completely synchronized. That is, if the gate pulse propagation delay time is within a sufficiently small range, even if V++, (i) advances only with respect to vgR(i), as shown in Figure 1(d)l, or vice versa. Even if the timing is different, there is no problem with image display.

As mentioned above, it is preferable that VtL and VOR be in phase, but there is no practical problem even if they are slightly out of phase. In other words, it is sufficient that they are substantially synchronized after taking delay into consideration.

(Embodiment 2) FIG. 7 is a diagram showing a second embodiment of the present invention, and shows a block configuration diagram of a liquid crystal display device.

In this embodiment, - number of gate drivers 2 are used, and each output thereof is connected to both ends of each gate line. In this embodiment, the same effect as the first embodiment can be obtained without changing the number of gate drivers compared to the conventional one.

Such a configuration can realize the above-mentioned connections by using, for example, a flexible circuit board with two-layer wiring.

It goes without saying that the above-mentioned wiring can also be formed by patterning (that is, lamination) on the panel substrate.

(Embodiment 3) FIG. 8 is a diagram showing a third embodiment of the present invention, and shows a block configuration diagram of a liquid crystal display device.

This embodiment is characterized in that instead of using the gate driver 2, a gate signal generating section 6 is built on the same panel substrate as the liquid crystal panel. Here, the gate signal generating section 6 is composed of shift registers 1 to 1 using thin film transistors formed in the same process as the liquid crystal display section. According to this embodiment, the first embodiment described above can be achieved with a simpler drive circuit configuration.
It is possible to achieve a similar effect.

Note that the built-in Kate signal generating section 6 is, for example,
A vertical matrix addressing type drive circuit configuration as described in Japanese Patent Application Laid-Open No. 62-15599 may also be used.

(Embodiment 4) FIG. 9 is a diagram showing a fourth embodiment of the present invention, and shows a block configuration diagram of a liquid crystal display device.

In this embodiment, the structure of the gate driver is the same as in the first embodiment, but in addition, data drivers 3 and 3' are provided at both ends of the data line, and data signals of the same phase are sent from both ends of each data line. The feature is that it is configured to apply .

According to this configuration, in addition to being able to reduce the propagation delay time of the gate line, the propagation delay time of the data line can also be reduced to 1/4 or less, so that better image display can be achieved.

(Embodiment 5) FIG. 10 is a diagram showing a fifth embodiment of the present invention, and shows a block configuration diagram of a liquid crystal display device.

In this embodiment, the gate lli operation method uses only one gate driver as before, and three data drivers.
and 3" are arranged at the top and bottom of the panel as in the fourth embodiment. By inputting data signals of the same phase from both ends of each data line in this way, the propagation delay time can be reduced to 1/4 or less. Therefore, it is possible to improve the vertical resolution.

(Embodiment 6) FIG. 11 is a diagram showing a sixth embodiment of the present invention, and shows a block configuration diagram of a television receiver.

This example uses the liquid crystal display device of Example 1 to
This is for displaying a V image.

In FIG. 11, 7 is a standard drive circuit used in ordinary color TVs. Furthermore, if the input to the video signal processing circuit is a VTR signal, it can also be used as a video monitor.

Note that the liquid crystal display section used in this example is similar to that in Example 1.
It goes without saying that a color TV image can be obtained not only by using those described in Examples 2, 3, and 4.5.

Further, in this embodiment, the case where the liquid crystal display device of the present invention is used for displaying TV images has been explained, but the liquid crystal display device of the present invention is not limited to displaying TV images, but can of course be used as other displays. It is possible. In particular, if the present invention is applied, it is possible to realize a screen that is significantly better than that of the past in large-screen, high-definition display devices, and it is possible to clearly display precise figures and small characters, so information It is suitable as a display device such as a terminal device or a character and graphic display device.

〔Effect of the invention〕

As explained above, according to the liquid crystal display device and the driving method thereof according to the present invention, the gate propagation delay time can be reduced compared to the conventional one.
/4 or less, and furthermore,
In the configuration of the embodiment, the data propagation delay time is also reduced to 1/4.
It can be shortened to the following. Therefore, an excellent effect can be obtained in that good image quality can be realized on a large-screen, high-definition display.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a first embodiment of the present invention, (,) is a block diagram of a liquid crystal display device, (b) is a circuit diagram of a liquid crystal panel, (c) and (d) are waveform diagrams of gate pulses. , Figure 2 is an example of a conventional active matrix liquid crystal panel.
Figure 3 is a drive waveform diagram of a conventional panel, Figure 4 is a diagram showing the propagation delay of a gate pulse, Figure 5 is an equivalent circuit diagram showing the gate propagation delay due to wiring resistance and capacitance, and Figure 6 is a diagram showing the gate propagation delay due to wiring resistance and capacitance. Gate pulse waveform diagram for detailed explanation, FIG.
FIG. 8, FIG. 9, FIG. 10, and FIG. 11 are diagrams showing other embodiments of the present invention, respectively. <Explanation of symbols> 1...Liquid crystal matrix panel 2.2'...Gate driver 3.3'...Data driver 4...Control signal generation section 5...Image signal generation section 6... Panel built-in gate signal generator 7...Normal color TV drive circuit 21...Liquid crystal cell 22...Storage capacitor 23...Thin film transistor 24...Gate line 25...Data line 26...Gate Driver 27...data driver

Claims (1)

[Scope of Claims] 1. It has a plurality of data lines and a plurality of gate lines that intersect with the plurality of data lines, and a pixel electrode and the pixel electrode are driven at each intersection of the data line and the gate line. a first substrate on which a thin film transistor is formed; a second substrate on which a transparent conductor is formed; a liquid crystal layer sandwiched between the first substrate and the second substrate;
A liquid crystal display device comprising: means for inputting a gate drive voltage for driving the thin film transistor from both ends of each gate line. 2. The method for driving a liquid crystal display device according to claim 1, wherein the voltages inputted from both ends of each gate line are substantially synchronized for each gate line. 3. It has a plurality of data lines and a plurality of gate lines that intersect with the plurality of data lines, and a pixel electrode and a thin film transistor for driving the pixel electrode are formed at each intersection of the data line and the gate line. a first substrate; a second substrate formed with a transparent conductor; a liquid crystal layer sandwiched between the first substrate and the second substrate;
A liquid crystal display device comprising: means for inputting a data drive voltage for driving the thin film transistor from both ends of each data line. 4. The method for driving a liquid crystal display device according to claim 3, wherein the voltages input from both ends of the data lines are substantially synchronized for each data line. 5. A television image display device characterized in that the liquid crystal display device according to the above item 1 or 3 or the driving method according to the above item 2 or 4 is used as a display means. 6. An information terminal device or characters or figures, characterized in that the liquid crystal display device according to the above item 1 or 3 or the driving method according to the above item 2 or 4 is used as a display means. Display device.