JPH04280226A - Thin film transistor element array and driving method thereof - Google Patents

Abstract

PURPOSE:To shorten the delay time of a gate bus line by providing a shield electrode and an auxiliary bus line so as to cover the gate bus line. CONSTITUTION:A shield electrode 11 covering a gate bus line 2 is provided on the gate bus line 2 through an insulating film, and the gate bus line 2 is connected to the shield electrode 11 by through holes 12, 32 formed in the insulating film in the signal input side end part. In this case, the gate bus line 2 is connected to the shield electrode 11 by the through holes 12, 32 formed in the insulating film in two positions of the signal input side end part and the opposite side end part. Further, a second gate bus line 31 is provided on the gate bus line 2 through the insulating film, and the gate bus line 2 is connected to the second gate bus line 31 in plural positions through the contact holes 32 formed in the insulating film.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an active matrix liquid crystal display, and more particularly to wiring for scanning without delay in a large liquid crystal display having a diagonal of 20 inches or more.

0002

[Prior Art] Active matrix liquid crystal displays, in which thin-film field-effect transistors are arrayed on one glass substrate as switches for each pixel, are being actively researched and developed as thin panel displays such as wall-mounted color televisions. is being carried out. This active matrix type liquid crystal display is capable of full color display and has excellent display quality.
It is expected that a wall-mounted high-definition television of 0 inches or larger will be realized.

[0003] The maximum size that has been realized so far is 14
Inches. Even in a panel of this size,
Wiring delay time becomes a problem. For example, in order to non-interlace drive 480 scanning lines, 3
It is necessary to write a signal to the pixel in a time of 0 μs. During this write time, a scanning signal input from the outside propagates through the gate bus line and turns on the thin film transistor in the write pixel section. On the other hand, image signals must be propagated from orthogonal drain bus lines and written to display pixels through thin film transistors. At this time, the gate bus line has longer wiring than the drain bus line,
Moreover, since the parasitic capacitance of the transistor portion is large, wiring delay of the scanning signal becomes a problem.

Conventionally, wiring delay has been reduced by using a material with low resistance for the scanning line. For example, in small displays, chromium, which is suitable for the process, is used as a wiring material, but its resistivity is 26μΩ・c.
It is as large as m. When this chromium is used in a 14-inch panel, a delay time of 25 μs occurs. Therefore, for large displays of 10 inches or more, Al (aluminum) is used.
By using a low resistance material of about 3 μΩ·cm, such as copper or Cu, a signal delay of 3 μs can be achieved, and a good image display without crosstalk can be obtained.

[0005]

Problems to be Solved by the Invention In order to realize a large screen of 50 inches, the signal delay of the scanning line becomes large. Simply put, wiring delay is proportional to the square of the wiring length. In the case of high-definition, the number of scanning lines is approximately 1000, and the frequency is 60Hz.
If interlace driving is used, the writing time per scanning line is approximately 24 μs. Therefore, even if a low resistance wiring material such as aluminum or Cu is used, the wiring delay is approximately 38 μs, which is longer than the writing time.

[0006] The wiring delay time is determined by the product of wiring resistance and wiring capacitance. The wiring capacitance is limited by design rules, the aperture ratio of the array, etc., and the wiring capacitance cannot be changed significantly. On the other hand, in terms of the wiring resistance, the width of the wiring cannot be increased due to restrictions on the aperture ratio, so the only option is to increase the film thickness or use a material with low resistance. However, if the film thickness is too thick, the difference in level becomes large, and there is a strong possibility that the drain bus line, which is wired above with the insulating layer in between, will be disconnected. As mentioned above, the wiring material is Al, which has the lowest resistivity.
and Cu, so there is no room for improvement from the material standpoint.

[0007] The object of the present invention is to
The purpose of the present invention is to provide a wiring structure and driving method with less delay that can drive a large-screen display.

[0008]

[Means for Solving the Problems] A thin film transistor element array according to the first invention of the present application includes a gate bus line provided on a transparent insulating substrate, and a drain bus line provided to intersect with the gate bus line. In a thin film transistor element array having a thin film transistor provided at a portion where the gate bus line and the drain bus line intersect, a shield electrode is provided on the gate bus line and covers the gate bus line with an insulating film sandwiched therebetween. , and the gate bus line and the shield electrode are connected at a signal input side end through a through hole formed in the insulating film.

A thin film transistor array according to a second aspect of the present invention includes a gate bus line provided on a transparent insulating substrate, a drain bus line provided to intersect with the gate bus line, and a drain bus line provided to intersect with the gate bus line. In a thin film transistor element array having a thin film transistor provided at a portion where drain bus lines intersect, a shield electrode is provided on the gate bus line and covers the gate bus line with an insulating film interposed therebetween, and the gate bus line and The shield electrode is connected at two locations, a signal input side end and an opposite end, by through holes formed in the insulating film.

A thin film transistor element array according to a third aspect of the present invention includes a gate bus line provided on a transparent insulating substrate, a drain bus line provided to intersect with the gate bus line, and a drain bus line provided to cross the gate bus line. In the thin film transistor element array having a thin film transistor provided at a portion where the drain bus line intersects, an insulating film is sandwiched between the gate bus line and the second thin film transistor.
A gate bus line is provided, and the gate bus line and the second gate bus line are connected at a plurality of locations through contact holes formed in the insulating film.

[0011] A method for driving a thin film transistor element array according to a fourth invention of the present application is such that the scanning signal of the gate bus line of the thin film transistor element array according to the second or third invention is transmitted from both sides of the gate bus line of the thin film transistor element array. They are input at the same time.

0012

[Operation] The wiring delay of the gate line is determined by the resistance of the wiring and the size of the parasitic capacitance hanging from the wiring. FIG. 7 shows an equivalent circuit of the gate line. One pixel is represented by one equivalent circuit. In the figure, the wiring resistance of the gate bus line 2 is Rgl, the capacitance at the intersection of the gate bus line 2 and the drain bus line 3 is Ccrs, and the capacitance between the gate electrode and the drain or source electrode of the thin film transistor TFT is Cgd and Cgs, respectively. . Let Cgc be the capacitance between the gate bus line and the counter electrode. Let Clc be the capacitance between the pixel electrode and the counter electrode. The wiring resistance Rgl is simply determined by the resistivity determined by the wiring material and the wiring width and film thickness determined by the TFT array design. However, as mentioned above, even if aluminum or copper, which has the lowest resistivity among metals, is used and the wiring width and film thickness are made as large as possible, the delay of the gate bus line is large in a large-screen liquid crystal display of about 50 inches. Therefore, the wiring resistance Rgl cannot be reduced.

On the other hand, if the parasitic capacitance can be reduced, the delay time of the gate bus line can be reduced. As can be seen from the equivalent circuit in the figure, the parasitic capacitances are Ccrs, Cgd,
This corresponds to the parallel capacitance of Cgs and Ggc. Set pixel pitch to 0
．． Assuming that the size is 3 mm x 0.1 mm, the size of each capacitance is estimated to be 28, 20, 20, and 28 fF, respectively. Therefore, if the parasitic capacitance Cgc between the gate bus line 2 and the counter electrode can be ignored, the gate delay time can be reduced by about 30%. In the first invention of the present application, a shield electrode is formed between a gate bus line and a counter electrode, and this shield electrode is connected to a signal input portion of the gate bus line. Then, if the wiring resistance of the shield electrode is three times or less than the resistance of the gate bus line, the delay time due to Cgc can be ignored. In fact, it is easy to reduce the resistance of the shield electrode.

[0014] In a second invention, the shield electrode of the first invention is connected to the gate bus line at the end of the thin film transistor element array on the opposite side from the signal input part of the gate bus line. In this structure, the capacitance Cg between the counter electrode and
In addition to the compensation effect of c, since the scanning signal is also input from the opposite side of the gate bus line, the delay time is further reduced. Here, the shield electrode has the advantage that the film thickness can be increased because there is basically no problem with the step difference. In this structure, by sufficiently reducing the resistance of the shield electrode, the wiring delay can be reduced to about 1/5 compared to a conventional single gate bus line.

The third invention is a structure in which a low resistance second bus line is provided separately from the gate bus line to effectively reduce wiring resistance. The gate bus line and the second bus line are electrically connected to each other via contact holes at a plurality of locations to prevent signal delays from occurring on the gate bus line. By providing the second bus line above the drain bus line, there is no step problem and the film thickness can be made sufficiently thick. For example, if the film thickness of the auxiliary bus line can be formed to 1 micron, the resistance can be reduced to a fraction of that, and the wiring delay can be reduced.

A fourth aspect of the invention is to input signals from both sides of the thin film transistor element array. It is known that in a conventional relatively medium-sized LCD of about 14 inches, input can be made from both sides compared to when only the gate bus line is used, and gate delay can be prevented. In this conventional example, the delay time is reduced to 1/4 compared to when inputting on one side.

On the other hand, when the fourth invention is applied to the second invention, when inputting from both sides, when shield electrodes are formed, the delay time is reduced by 17% compared to when the conventional gate bus line is used alone. can be reduced to. Furthermore, by applying the third invention and forming a second gate bus line with sufficiently low resistance, the delay time of the gate bus line can be easily reduced to 10% or less compared to the conventional case of single-side input of a single gate. I can do that. Therefore, inputting signals on both sides to the structures of the second and third inventions is particularly effective in reducing image delay.

[0018]

[Embodiment] An embodiment of the first invention of the present application will be described. A plan view of the array structure is shown in FIG. Figure 2 shows XX in Figure 1.
FIG.

First, a glass substrate was used as the transparent insulating substrate 1. An aluminum film with a thickness of 200 nm and a Cr film with a thickness of 100 nm are formed thereon by sputtering. Here, a Cr film is used as a protective film for the aluminum film. The Cr film and aluminum film are patterned by wet etching to form a two-layer gate bus line 2.
form. Note that although the storage capacitor is omitted in FIG. 1, the image quality is better if it is formed.

Next, a silicon nitride film, a non-doped a-Si film (a-Si means amorphous silicon), and a high concentration n-type a-Si film were successively grown by plasma CVD. The thickness of the silicon nitride film is 400 nm. Here, the two-layer film of the high concentration n-type a-Si film and the non-doped a-Si film is dry-etched to form an island. After forming a drain bus line and a source electrode, the high concentration n-type a-Si film is etched using these as a mask to form a thin film transistor 4. Furthermore, I with a film thickness of 40 nm
TO is sputtered and patterned to form the pixel electrode 5. The process up to this point is equivalent to the manufacturing process of an active matrix LCD panel using ordinary thin film transistors.

Now, a silicon nitride film with a thickness of 400 nm is formed as an interlayer insulating film by plasma CVD. Next, a through hole 12 is formed in the signal input section. For etching, a dry etching method using trifluoromethane was used. Furthermore, aluminum is again formed to a thickness of 1 .mu.m by sputtering and patterned by a wet method to complete the shield electrode 11.

A cell is assembled with a gap thickness of 5 .mu.m between the TFT substrate thus prepared and the counter electrode, and finally, liquid crystal is injected to complete the panel. When we measured the wiring delay time of the gate bus line in this state, we found that the diagonal 2
In the case of 5 inches, it was 9 μs. This is 1000 scan lines
This is a value that allows HDTV display of about 100 yen.

Next, an embodiment of the second invention will be described. Figure 3 shows a plan view of the structure of a thin film transistor element array.
Shown below. FIG. 4 is a sectional view taken along the line X--X in FIG. 3. First, a glass substrate was used as the transparent insulating substrate 1. On top of this, a three-layer film of Ta/Cr/Ta is formed by sputtering with a thickness of 100 nm, 200 nm, and 100 nm, respectively.
A film, a Cr film, and a Ta film are deposited. Here, the lower Ta film is used to strengthen adhesion to the glass substrate, and the upper Ta film is used as a protective film for the aluminum film. This three-layer film is patterned to form a gate bus line 2 having a three-layer structure. Note that although the storage capacitor is omitted in FIGS. 3 and 4, the image quality is better if it is formed.

Next, a silicon nitride film, a non-doped a-Si film, and a high concentration n-type a-Si film were successively grown using a plasma CVD method. The thickness of the silicon nitride film is 400 nm. Here, the two-layer film of the high concentration n-type a-Si film and the non-doped a-Si film is dry-etched to form an island. After forming a drain bus line and a source electrode, the high concentration n-type a-Si film is etched using these as a mask to form a thin film transistor 4. Furthermore, the film thickness is 4
A pixel electrode 5 is formed by sputtering and patterning ITO with a thickness of 0 nm. The process up to this point is equivalent to the panel process of an active matrix LCD using ordinary thin film transistors.

Now, a silicon nitride film with a thickness of 400 nm is formed as an interlayer insulating film using the plasma CVD method. Next, through holes 22 are formed at the signal input section and at the ends of the thin film transistor element array. Therefore, through hole 21
are formed at two locations for one gate bus line. For etching, a dry etching method using trifluoromethane was used. Furthermore, an aluminum film with a thickness of 1 μm is formed again by sputtering and patterned by wet method, thereby completing the shield electrode 11.

A cell is assembled with a gap thickness of 5 μm between the TFT substrate and the counter electrode thus produced, and finally, liquid crystal is injected to complete the panel. In this state, when the wiring delay time of the gate bus line was measured by changing the width of the scanning pulse and measuring the transmittance of the pixel, it was found to be 12 μs in the case of a diagonal of 50 inches. This is a value that allows HDTV display with approximately 1000 scanning lines, demonstrating the effectiveness of the present invention.

Next, an embodiment of the third invention will be described. The structure of the thin film transistor element array is shown in FIGS. 5 and 6. 5 and 6, the gate bus line 2 uses a two-layer interconnection of an aluminum film and a Cr film. The film thicknesses are 200 nm and 100 nm, respectively. This laminated film is patterned by a wet method to form gate bus lines.

Next, a silicon nitride film, a non-doped a-Si film, and a high concentration n-type a-Si film were successively grown by plasma CVD. The thickness of the silicon nitride film is 400 nm. Here, the two-layer film of the high concentration n-type a-Si film and the non-doped a-Si film is dry-etched to form an island. After forming a drain bus line and a source electrode, the high concentration n-type a-Si film is etched using these as a mask to form a thin film transistor 4. Furthermore, the film thickness is 4
0 nm ITO is sputtered and patterned to form pixels. The process up to this point is equivalent to the panel process of an active matrix LCD using ordinary thin film transistors.

Now, a silicon nitride film with a thickness of 400 nm is formed as an interlayer insulating film by plasma CVD. Next, a through hole 32 is formed to electrically connect the second bus line to be formed in a subsequent step to the already formed gate bus line. In this embodiment, the through holes are formed at the signal input end, the middle part of one cell separated by each drain bus line, and the end of the thin film transistor element array. Note that one through hole may be formed for a plurality of cells, or a plurality of contact holes may be formed for one cell. This contact hole was etched using a dry etching method using trifluoromethane. Furthermore, an aluminum film is again formed with a thickness of 1.2 μm by sputtering and patterned by wet method to form the second gate bus line 31.
is completed.

A cell is assembled with a gap thickness of 5 μm between the TFT substrate thus prepared and the counter electrode, and finally liquid crystal is injected to complete the panel. In this state, when the wiring delay time of the gate bus line was measured by changing the width of the scanning pulse and measuring the transmittance of the pixel, it was found to be 8 μs in the case of a diagonal of 50 inches. This is a value that allows HDTV display with approximately 1000 scanning lines, demonstrating the effectiveness of the present invention.

Next, an embodiment of a method for driving a thin film transistor element array according to the fourth invention of the present application will be described. To drive the scanning side of the liquid crystal display, the output terminals of the drive IC formed by LSI are connected one by one to the gate bus lines formed on the glass substrate, and scanning signals are applied to the thin film transistor element array. . For connection, methods using anisotropic conductive rubber or tabs are known. Usually, this scanning drive IC is connected to only one side of the gate bus line.

In the present invention, drive ICs are connected to both sides of one gate bus line. These two I
By driving C in synchronization, scanning signals can be simultaneously input from both sides of the gate bus line.

Scanning drive ICs were connected to both sides of the thin film transistor element array provided with the shield electrode, which is the second invention of the present application, and were simultaneously driven. In this state, when the wiring delay time of the gate bus line was measured by changing the width of the scanning pulse and measuring the transmittance of the pixel, it was found to be 10 μm for a diagonal of 50 inches. This is a sufficiently small value for an HDTV display with approximately 1000 scanning lines, and the effectiveness of the present invention was demonstrated.

Regarding the thin film transistor element array provided with the second gate bus line, which is the third invention of the present application,
Scanning drive ICs were connected to both sides and driven simultaneously. In this state, by changing the width of the scanning pulse and measuring the transmittance of the pixel,
When the wiring delay time of the gate bus line was measured, it was 3 μs for a diagonal of 50 inches. This is scan line 10
This is a sufficiently small value for an HDTV display of approximately 0.000 lines, demonstrating the effectiveness of the present invention.

[0035]

Effects of the Invention In a large-screen liquid crystal display of 20 inches or more and about 50 inches, the delay time of the gate bus line can be shortened by providing a shield electrode or an auxiliary bus line to cover the gate bus line. Furthermore, in the thin-film transistor array having this structure, the delay time was further shortened by inputting scanning signals from both sides of the gate bus line, and a delay time that enabled high-definition display was realized.

[Brief explanation of the drawing]

FIG. 1 is a plan view showing an embodiment of the first invention of the present application.

FIG. 2 is a sectional view taken along line XX in FIG. 1;

FIG. 3 is a plan view showing an embodiment of the second invention of the present application.

FIG. 4 is a sectional view taken along the line XX in FIG. 3;

FIG. 5 is a plan view showing an embodiment of the third invention of the present application.

FIG. 6 is a sectional view taken along line XX in FIG. 6;

FIG. 7 is an equivalent circuit diagram of a liquid crystal display device using a thin film transistor element array.

[Explanation of symbols]

1 Transparent insulating substrate 2 Gate bus line 3 Drain bus line 4 Thin film transistor 5 Pixel electrode 11, 21 Shield electrode 12, 22, 32
Through hole 31 Second gate bus line

Claims (4)

[Claims] 1. A gate bus line provided on a transparent insulating substrate, a drain bus line provided to intersect with the gate bus line, and a portion where the gate bus line and the drain bus line intersect. In a thin film transistor element array having a thin film transistor provided, a shield electrode is provided on the gate bus line to cover the gate bus line with an insulating film sandwiched therebetween, and the gate bus line and the shield electrode are on a signal input side. A thin film transistor element array, characterized in that the end portions are connected by through holes formed in the insulating film. 2. A gate bus line provided on a transparent insulating substrate, a drain bus line provided to intersect with the gate bus line, and a portion where the gate bus line and the drain bus line intersect. In a thin film transistor element array having a thin film transistor provided therein, a shield electrode is provided on the gate bus line to cover the gate bus line with an insulating film sandwiched therebetween, and the gate bus line and the shield electrode are connected to a signal input side end. A thin film transistor element array, characterized in that the thin film transistor element array is connected at two locations, one at the end and the other at the opposite end, by through holes formed in the insulating film. 3. A gate bus line provided on a transparent insulating substrate, a drain bus line provided to intersect with the gate bus line, and a portion where the gate bus line and the drain bus line intersect. In a thin film transistor element array having a thin film transistor provided therein, a second gate bus line is provided on the gate bus line with an insulating film sandwiched therebetween, and the gate bus line and the second gate bus line are connected to the insulating film. A thin film transistor element array characterized in that the thin film transistor element array is connected at a plurality of locations via contact holes formed in the film. 4. Driving a thin film transistor element array, characterized in that scanning signals for the gate bus line of the thin film transistor element array according to claim 2 or 3 are simultaneously input from both sides of the gate bus line of the thin film transistor element array. Method.