KR100330096B1 - LCD Display - Google Patents

Abstract

On the transparent insulating substrate, a gate line formed of a horizontal gate line and a gate electrode and a common line formed of a plurality of common electrodes and a common electrode line connecting them are formed in a pixel area. A pixel connection portion extending from the data line and the drain electrode formed of a data line and a source and drain electrode defining a pixel crossing the gate line and crossing the gate line is formed on the gate insulating film covering the gate insulating film. In addition, a pixel electrode connected to the pixel connection part is alternately formed with the common electrode through a contact hole formed in the passivation layer, and an auxiliary gate line connected to the gate line is overlapped with the gate line through the contact hole formed in the passivation layer. Formed.

Description

Liquid crystal display

The present invention relates to a liquid crystal display device.

As the display device, in particular, the liquid crystal display, increases in size, wiring is used as a means for transmitting signals, and therefore, it is required to suppress signal delay and disconnection.

As a method of preventing signal delay, a material such as aluminum (Al) or aluminum alloy (Al alloy) or molybdenum or molybdenum alloy having low resistance should be used. However, since these materials are poor in acid resistance, they are easily eroded by the etching liquid or the cleaning liquid used in the manufacturing process or the cleaning process of the liquid crystal display device. In order to prevent this, the wiring, in particular the gate line to which the scan signal is applied, is formed to be covered with an amorphous silicon layer used as an insulating film or semiconductor layer made of silicon nitride or silicon oxide. However, when a defect occurs in the insulating film or the amorphous silicon layer, chemicals penetrate through the defect to corrode the gate line, which causes a problem that the gate line is disconnected.

An object of the present invention is to prevent disconnection of a gate line.

1 is a layout view of a liquid crystal display according to a first exemplary embodiment of the present invention.

2 and 3 are cross-sectional views taken along the line II-II including the thin film transistor unit in FIG. 1,

4 is a layout view illustrating a structure of a liquid crystal display according to a second exemplary embodiment of the present invention.

FIG. 5 is a cross-sectional view taken along the line V-V including the thin film transistor unit of FIG. 4.

6 is a cross-sectional view taken along the line VI-VI including the pixel unit in FIG. 4.

In the liquid crystal display substrate according to the present invention for solving the above problems, the gate lines overlap each other and are formed in parallel to each other.

In the thin film transistor for a liquid crystal display device according to the present invention, a gate line formed of a gate line formed on a substrate and a gate electrode connected to the gate line is covered with a gate insulating film. A data line is formed on the gate insulating layer, the data line including a source line and a drain electrode connected to the semiconductor layer, and a data line defining a pixel by crossing the gate line. In addition, a pixel electrode electrically connected to the drain electrode is formed on the passivation layer covering the data line and the semiconductor layer, and is connected to the gate line through the second contact hole formed in the passivation layer. The gate auxiliary line is formed in parallel with the gate line.

Next, embodiments of the liquid crystal display according to the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention.

In an embodiment of the present invention, a pixel electrode and a common electrode for driving liquid crystal molecules are formed on each substrate, and a TN method and a pixel electrode and a common electrode in which spirally twisted liquid crystal molecules are arranged in parallel to the substrate are provided. It will be described through the structure of the planar electric field driving method formed on the substrate. Of course, the embodiment of the present invention is not limited to the structure described above, and the same applies to the structure in which the liquid crystal molecules are oriented perpendicular to the substrate.

FIG. 1 is a layout view illustrating a structure of a thin film transistor substrate for a TN type liquid crystal display device according to a first embodiment of the present invention, and FIGS. 2 and 3 are along a line II-II including a thin film transistor unit in FIG. 1. It is a cut section. At this time, one unit pixel of the pixel electrode is integrally formed.

A gate wiring including a gate line 22 extending in the horizontal direction and a gate electrode 24 of a thin film transistor, which is a branch of the gate line 22, is formed on the insulating substrate 10. 2 illustrates a case in which gate wirings 22 and 24 are formed of a single layer of molybdenum or molybdenum alloy having good contact reliability with indium tin oxide (ITO), which is later formed as a pixel electrode, and FIG. In this case, the alloy film is formed of the upper films 222 and 242, and the chromium, molybdenum or molybdenum alloy is formed of the lower films 221 and 241.

The gate insulating film 30 made of silicon nitride (SiN _x ) covers the gate wirings 22 and 24 on the substrate 10, and the semiconductor layer 40 is disposed on the gate insulating film 30 on the gate wirings 22 and 24. These are formed, respectively. Contact layers 52 and 54 made of a material such as n + hydrogenated amorphous silicon doped with a high concentration of n-type impurities are formed on the semiconductor layer 40, respectively. Source and drain electrodes 62 and 64 made of Cr) or a molybdenum-tungsten alloy are formed. Here, the source electrode 62 is a branch of the data line 60 formed in the vertical direction and crossing the gate line 22 to define the pixel region.

A passivation layer 70 is formed on the data lines 60, 62, and 64 and the semiconductor layer 40 not covered by the data line, and the passivation layer 70 has contact holes in the drain electrode 64 and the gate line 22. (72, 74) are formed. As shown in FIG. 3, when the gate line 22 is formed of the double layers 221 and 222, the lower layer 221 is exposed through the contact hole 74.

On the passivation layer 70 of the pixel region, a pixel electrode 80 made of ITO, which is connected to the drain electrode 64 through a contact hole 72 and is formed of a transparent conductive material, is formed. Further, an auxiliary gate line 82 formed of ITO, overlapping with the gate line 22, and connected to the gate line 22 through the contact hole 74 is formed on the passivation layer 70.

As shown in FIG. 3, the auxiliary gate line 82 is in contact with the chromium, molybdenum or molybdenum alloy layer, which is the lower layer 221 of the gate line 22, and thus, an electrochemical reaction does not occur.

In addition, even if disconnection occurs in the gate line 22, the scan signal is transmitted through the auxiliary gate line 82.

In this case, the auxiliary gate line 82 may be formed to sufficiently cover the contact hole 74. The contact hole 74 formed on the gate line 22 may be formed for each pixel. One or more pixels may be formed as a unit.

Next, a structure in which a common electrode and a pixel electrode forming an electric field for driving liquid crystal molecules are formed on one substrate will be described in detail. At this time, one or more unit pixels of the common electrode and the pixel electrode are formed in parallel with each other.

4 is a layout view illustrating a structure of a liquid crystal display according to a second exemplary embodiment of the present invention. FIG. 5 is a cross-sectional view taken along a line VV including a thin film transistor unit in FIG. 4, and FIG. 6 is a pixel in FIG. 4. Sectional drawing taken along the line VI-VI containing the part.

4 to 6, the gate line 22 is formed in the horizontal direction on the lower transparent insulating substrate 10, and a part of the gate line 22 becomes the gate electrode 21. The common electrode line 24 is formed in parallel with the gate line 22, and a plurality of common electrodes 26 connected to the common electrode line 24 to receive a common signal from the common electrode line 24 in the pixel area are vertical. It is formed parallel to each other in the direction. Here, a variety of conductive materials may be used as the metals for the gate wirings 21 and 22 and the common wirings 24 and 26, and a single film such as chromium, molybdenum, and molybdenum alloys may be used, or aluminum and aluminum alloys may be used. It is also possible to form a double film combining these.

The gate insulating film 30 made of silicon nitride or the like is covered on the gate wirings 21 and 22 and the common wirings 24 and 26.

The semiconductor layer 40 of the thin film transistor made of amorphous silicon is formed on the gate insulating layer 30 on the gate electrode 21 in an island shape, and the amorphous silicon layer 40 is heavily doped with phosphorus (P) on the amorphous silicon layer 40. The ohmic contacts 51 and 52 made of silicon are formed on both sides of the gate electrode 21.

A source electrode 61 and a drain electrode 62 made of metal are formed on the ohmic contact layers 51 and 52, respectively, and the source electrode 61 is formed in the vertical direction on the gate insulating layer 30 to form the gate line 22. ) And the data line 60 defining the pixel area, and the drain electrode 62 is connected to the pixel connection part 64 extending in the horizontal direction in the pixel area.

In this case, the data wires 60, 61, and 62 and the pixel connection part 64 may be formed of a metal layer such as chromium, aluminum, an aluminum alloy, molybdenum, or molybdenum alloy.

The gate electrode 21, the gate insulating film 30, the amorphous silicon layer 40, the ohmic contact layers 51 and 52, the source and drain electrodes 61 and 62 form a thin film transistor, and the thin film transistor and the remaining data wirings. A protective film 70 covering the 60, 61, 62 and the pixel connection portion 64 is formed of silicon nitride or the like.

In the passivation layer 70, a contact hole 72 exposing the pixel connection part 64 is formed, and a contact hole 74 exposing the gate line 22 is formed together with the gate insulating layer 30.

The auxiliary gate line 80 is formed on the passivation layer 70 in the horizontal direction along the gate line 22 and connected to the gate line 22 through the contact hole 74 formed in the passivation layer 70. Formed. In addition, the passivation layer 70 is alternately formed with the common electrode 26, and the pixel electrodes 82 connected to the pixel connection unit 64 through the contact hole 72 are formed in parallel with each other.

Here, the gate auxiliary line 80 overlaps the gate line 22, but is bent so as not to overlap the thin film transistor.

In this structure, the scan signal applied to the gate line 22 is transmitted through the auxiliary gate line 80 even if the gate line 22 is disconnected.

The pixel electrode 82 and the auxiliary gate line 80 may be formed of a single film of chromium, molybdenum, molybdenum alloy, or ITO, or a plurality of films made thereof.

Here too, the contact between the chromium, molybdenum or molybdenum alloy film and the ITO film at the contact between the pixel electrode 82 and the pixel connection portion 64 or the drain electrode 62 and the contact between the auxiliary gate line 80 and the gate line 22. Avoid the electrochemical reaction at

In addition, it is advantageous to form the thickness of the pixel electrode 82 to about 1,000 mW or less in terms of preventing light leakage.

As in the embodiment of the present invention, it is possible to prevent the wires from being disconnected by the double gate lines and to minimize the delay of the signal applied to the gate lines.

Claims (5)

Board, A gate wiring formed on the substrate and comprising a gate line and a gate electrode connected to the gate line, A common wiring formed on the substrate, the common wiring including a common electrode line formed in parallel with the gate line and one or more common electrodes connected to the common electrode line and formed in a pixel; A gate insulating film covering the gate wiring and the common wiring on the substrate, A semiconductor layer formed on the gate insulating film on the gate electrode, An ohmic contact layer formed on both sides of the gate electrode on the semiconductor layer; A data line connected to the source and drain electrodes formed on the ohmic contact layer and the source electrode, and formed of a data line crossing the gate line to define the pixel; A protective film covering the data line and the semiconductor layer not covered by the data line, A liquid crystal display device including one or more pixel electrodes formed on the pixel on the passivation layer and electrically connected to the drain electrode through the first contact hole of the passivation layer and alternately arranged with the common electrode. Thin film transistor substrate. In claim 1, And an auxiliary gate line formed on the passivation layer so as to overlap the gate line, and connected to the gate line through the gate insulating layer and the second contact hole formed in the passivation layer. And the pixel electrode and the auxiliary gate line are formed of an ITO film. In claim 2, The gate wiring line includes a first conductive film made of aluminum or an aluminum alloy and a second conductive film made of chromium, molybdenum, or molybdenum alloy. In claim 3, The auxiliary gate line is in contact with the second conductive layer through the second contact hole. In claim 2, And one or more second contact holes formed in units of at least one pixel.