KR100635944B1 - a thin film transistor array panel for a liquid crystal display - Google Patents

Abstract

A gate wiring including a gate line, a gate electrode, and a gate pad is formed on an insulating substrate, and a gate insulating film is formed thereon. The semiconductor layer and the ohmic contact layer are sequentially formed thereon, and a data line including a data line, a source electrode, a drain electrode, and a data pad is formed on the gate insulating film. A protective film having contact holes for exposing the drain electrode, the gate pad, and the data pad, respectively, is formed on the data line. A drain electrode, a gate pad, and a pixel electrode, an auxiliary gate pad, and an auxiliary data pad respectively connected to the data layer are formed on the passivation layer. At this time, an interval between the auxiliary data pads is formed to be greater than or equal to the width of the auxiliary data pad, so that the interval between the auxiliary data pads is sufficiently wide. When the TCP in which the driving integrated circuit is mounted is connected to the thin film transistor substrate, even if misalignment of the TCP pad and the auxiliary data pad occurs, the TCP pad and the auxiliary data pad are electrically connected one by one without being short-circuited with the neighboring auxiliary data pad. In addition, when the dummy wires and the dummy pads are further formed, a gap between the dummy pads is formed to be greater than or equal to the width of the dummy pads so that the dummy pads and the TCP dummy pads may be electrically connected one by one.

Pad, misalignment, short circuit, TCP

Description

A thin film transistor array panel for a liquid crystal display}

1 is a view schematically showing a thin film transistor substrate for a liquid crystal display device according to the present invention;

FIG. 2 is a layout view illustrating the pixel region P of the thin film transistor substrate illustrated in FIG. 1 together with a pad.

3 is a cross-sectional view taken along line III-III of FIG. 2,

4 is a diagram illustrating a peripheral area and a TCP pad of a thin film transistor substrate for a liquid crystal display device.

5 is a layout view showing a portion of a TCP and a thin film transistor substrate,

FIG. 6 is an enlarged layout view of part VI of FIG. 5;

FIG. 7 is an enlarged cross-sectional view of an auxiliary data pad and a TCP pad in part VII of FIG. 4.

The present invention relates to a thin film transistor substrate for a liquid crystal display device.

The liquid crystal display is one of the most widely used flat panel display devices. The liquid crystal display includes two glass substrates on which electrodes are formed and a liquid crystal layer interposed therebetween. A display device for controlling the amount of light transmitted by rearranging them.

In one substrate of the liquid crystal display, a plurality of gate lines and data lines are insulated and intersected to form a plurality of pixel regions, and in the pixel region, a plurality of thin film transistors and pixel electrodes are formed. And a display area for displaying. In addition, a peripheral area outside the display area, in which a plurality of gate pads and data pads connected to the plurality of gate lines and data lines and receiving signals from outside are formed at regular intervals, respectively. A color filter and a common electrode are formed on a substrate facing the thin film transistor substrate, which is called a color filter substrate and is smaller in size than the thin film transistor substrate. Thus, when overlapping two substrates, part of the peripheral area is exposed.

Above and to the left of the liquid crystal panel formed by stacking these two substrates, a data PCB board and a gate PCB board are provided. Between the liquid crystal panel and the data PCB substrate, a data carrier package (TCP) for mounting a data driving integrated circuit for converting an electrical signal into a data signal and outputting the data signal to a data pad and a data line is connected. In addition, a gate TCP is mounted between the liquid crystal panel and the gate PCB substrate, in which a gate driving integrated circuit is mounted, which converts an electrical signal into a scan signal and outputs the result to a gate pad and a gate line.

The gate and data TCPs are connected to the exposed peripheral areas of the liquid crystal panel, that is, the gate pads and the data pads, through a thermocompression process using an anisotropic conducting film (ACF), respectively. Each pad of the substrate should be connected one by one.

However, as the liquid crystal display device becomes higher in size, the gap between pads becomes smaller, and thus, the TCP pad and the data pad are not properly connected, and thus there is a problem such as a short circuit between neighboring pads.

The technical problem to be achieved by the present invention is to prevent the short circuit of the pad when connecting the external driving integrated circuit.

In order to achieve such a problem, in the present invention, the distance between the pads is greater than or equal to the width of the pads.

According to the present invention, a plurality of first signal lines and a plurality of first pads connected to the first signal lines are formed on an insulating substrate. Also, a plurality of second signal lines and a plurality of second pads connected to the second signal line are formed to be insulated from and cross the first signal line to form a plurality of pixel areas. In the pixel area, a thin film transistor connected to the pixel electrode, the pixel electrode, the first signal line, and the second signal line is formed.

At this time, an interval between the first pads is greater than or equal to the width of the first pad, or an interval between the second pads is greater than or equal to the width of the second pad.

The thin film transistor substrate according to the present invention includes an insulating substrate, and includes a plurality of gate lines and gate electrodes connected to the gate lines on the substrate, and a gate including a plurality of gate pads connected to the gate lines to receive scan signals from the outside. Wiring is formed. The gate wiring is covered with a gate insulating film, on which a semiconductor layer is formed. A data line is formed on the semiconductor layer and the gate insulating layer including a plurality of data lines and source electrodes connected to the data lines, a drain electrode separated from the source electrodes, and a data pad connected to the data lines to receive image signals from the outside. have. A passivation film having a plurality of first to third contact holes respectively exposing the drain electrode, the gate pad, and the data pad is formed on the data line and the gate insulating film. On the passivation layer, a pixel electrode connected to the drain electrode through the first contact hole, an auxiliary gate pad covering the gate pad through the second contact hole, and an auxiliary data pad covering the data pad through the third contact hole are formed. Here, the spacing between the auxiliary data pads is greater than or equal to the width of the auxiliary data pad or the spacing between the auxiliary gate pads is greater than or equal to the width of the auxiliary gate pad.

In this case, the auxiliary gate pad and the auxiliary data pad are preferably formed of the same layer as the pixel electrode.

Here, a dummy pad connected to the dummy wire and the dummy wire may be further formed between the data wire and the gate pad. In this case, the distance between the dummy pads is preferably equal to or greater than the width of the dummy pad, and at least two dummy wires are connected to each other. It may be.

Meanwhile, the auxiliary gate pad and the auxiliary data pad may not be formed, and in this case, it is preferable that an interval between the third contact holes is greater than or equal to the width of the third contact hole or that an interval between the second contact holes is greater than or equal to the width of the second contact hole. Do.

The thin film transistor substrate for a liquid crystal display according to the present invention may further include an ohmic contact layer formed on the semiconductor layer.

In the present invention, even if the spacing between the auxiliary data pads is greater than or equal to the width of the auxiliary data pads, the pads of the external driving circuit and the auxiliary data pads may be misaligned.

Next, a thin film transistor substrate for a liquid crystal display according to an exemplary embodiment of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily implement the same.

1 to 3 will be described in detail including a pad with respect to the structure of a thin film transistor substrate according to an embodiment of the present invention.

1 is a view schematically illustrating a thin film transistor substrate for a liquid crystal display according to an exemplary embodiment of the present invention, FIG. 2 is a layout view illustrating a pixel region P of FIG. 1 including a pad, and FIG. It is sectional drawing cut along the III-III line | wire.

First, as shown in FIG. 1, a plurality of gate lines 20 are formed on the insulating substrate 10 in a horizontal direction, and a plurality of gate pads 22 connected to the gate lines 20 are formed. A plurality of data lines 60 are formed in the vertical direction and insulated from and cross the gate line 20, and a plurality of data pads 63 connected to the data lines 60 are formed. A plurality of pixel regions P are defined by crossing the gate line 20 and the data line 60, and a thin film transistor TFT connected to the gate line 20 and the data line 60 in the pixel region P. FIG. ) Is formed, and the pixel electrode PE connected to the thin film transistor TFT is also formed.

In this embodiment, the spacing between the pads 22 and 63 is equal to or greater than the widths of the pads 22 and 63.

The pixel region P of the thin film transistor substrate will be described in detail with reference to FIGS. 2 and 3.

2 and 3, on the insulating substrate 10, aluminum (Al) or aluminum alloy (Al alloy), molybdenum (Mo) or molybdenum-tungsten alloy (MoW), chromium (Cr), tantalum (Ta), etc. The gate wirings 20, 21, 22 made of metal or conductors are formed. The gate wiring is connected to the ends of the plurality of gate lines 20 extending in the horizontal direction, the gate electrode 21 which is a branch of the gate line 20, and the gate line 20, and receives a scan signal from the outside to receive the gate line 20. Gate pads 22).

The gate wirings 20, 21, 22 may be formed in a single layer, but may be formed in more than a double layer. In this case, it is preferable that one layer is formed of a material having a low resistance and the other layer is formed of a material having good contact properties with other materials. Examples thereof include a double layer of chromium and aluminum or a double layer of aluminum and molybdenum.

The gate wirings 20, 21, 22 are covered with a gate insulating film 30 made of silicon nitride (SiN _x ).

A semiconductor layer 40 made of a semiconductor such as amorphous silicon is formed on the gate insulating layer 30, and a resistance made of a semiconductor such as amorphous silicon doped with n-type impurities such as phosphorus (P) is formed on the semiconductor layer 40. The contact layers 51 and 52 are formed separated from both sides with respect to the gate electrode 21.

On the ohmic contacts 51 and 52 and the gate insulating film 30, data wires 60, 61, 62, and 63 made of a metal or a conductor such as aluminum or an aluminum alloy, molybdenum or molybdenum-tungsten alloy, chromium and tantalum are formed. It is. The data line intersects the gate line 20 and extends in the longitudinal direction, and the source electrode 61 centers around the source electrode 61 and the gate electrode 21 which are branches of the data line 60. ) And a drain electrode 62 facing the) and a data pad 63 connected to the data line 60 to receive an image signal from the outside and transmit the image signal to the data line 60.

The data lines 60, 61, 62, and 63 may also be formed in a single layer like the gate lines 20, 21, and 22, but may be formed in two or more layers.

Here, the gate electrode 21, the gate insulating film 30, the semiconductor layer 40, the ohmic contact layers 51 and 52, and the source and drain electrodes 61 and 62 form a thin film transistor TFT.

A protective film 70 made of silicon nitride is formed on the data wires 60, 61, 62, and 63, the semiconductor layer 40, and the gate insulating film 30. The protective film 70 has not only a contact hole 72 exposing the gate pad 22 with the gate insulating film 30, but also a contact hole 73 and a drain electrode 62 exposing the data pad 63. It has a contact hole 71.

The pixel electrode 80, the auxiliary gate pad 82, and the auxiliary data pad 83 made of a transparent conductive material such as indium tin oxide (ITO) or an opaque conductive material are formed on the passivation layer 70. The pixel electrode 80 is connected to the drain electrode 62 through the contact hole 71. The auxiliary gate pad 82 and the auxiliary data pad 83 are connected to the gate pad 22 and the data pad 63 through the contact holes 72 and 73 drilled in the passivation layer 70, and are connected to the external circuit device. It is not essential to serve to complement the adhesion and to protect the pads 22 and 63.

The manufacturing method of such a thin film transistor substrate is briefly described.

First, a gate wiring conductor layer is deposited on the substrate 10 and patterned to form gate wirings 20, 21, and 22. The gate insulating layer 30, the semiconductor layer, and the ohmic contact layer are sequentially deposited and patterned on the gate lines 20, 21, and 22 to form the semiconductor pattern 40 and the ohmic contact layer pattern. Subsequently, the data wiring conductor layer is deposited and patterned on the gate insulating layer 30 and the ohmic contact layer pattern to form the data wirings 60, 61, 62, and 63, and the resistivity exposed between the source and drain electrodes 61 and 62. The contact layer pattern is removed to separate the resistive contact layer patterns 51 and 52 and the semiconductor pattern 40 is exposed. Next, the passivation layer 70 is deposited and patterned to form contact holes 71, 72, and 73 that expose the drain electrode 62, the gate pad 22, and the data pad 63, respectively. Subsequently, a transparent conductive material such as ITO is deposited and patterned to form the pixel electrode 80, the auxiliary gate pad 82, and the auxiliary data pad 83.

When such a thin film transistor substrate is made, a driving integrated circuit for driving the liquid crystal display device after coupling with an opposing substrate, injecting a liquid crystal material, and electrically connecting the thin film transistor substrate must be electrically connected to the thin film transistor substrate.

Such a process will be described with reference to FIGS. 4 to 7. FIG. 4 is a diagram illustrating a TCP and a peripheral region of a thin film transistor substrate for a liquid crystal display, FIG. 5 is a layout view of a portion of the TCP and a thin film transistor substrate, and FIG. 6 is an enlarged view of part VI of FIG. 5. FIG. 7 is an enlarged cross-sectional view of an auxiliary data pad and a TCP pad in the Ⅶ portion of FIG. 4.

As shown in FIG. 4, when the thin film transistor substrate 10 and the color filter substrate 11 are overlapped with each other, the size of the color filter substrate 11 is small to expose the peripheral area of the thin film transistor substrate 10. Here, only the data pad area 6 is shown among the exposed peripheral areas. A data line 60 and an auxiliary data pad 83 are formed in the data pad region 6, and a dummy wiring 65 and a dummy pad (not shown) are formed. Independent signals such as a common signal are applied to the dummy wiring 65 and the dummy pad. An anisotropic conductive film 3 is formed in the data pad region 6, and TCP 1 is aligned on the anisotropic conductive film 3. The TCP 1 is equipped with a driving integrated circuit 2, which is radiated from the driving integrated circuit 2 and connected to the data line 60 and the printed circuit board (PCB) of the thin film transistor substrate 10, respectively. TCP wirings 13 and 12 are formed. In addition, the TCP dummy wiring 19 connected to the dummy wiring 65 is formed in TCP1.

The TCP 1 and the thin film transistor substrate 10 are enlarged and shown in FIG. 5.

As shown in FIG. 5, the driver integrated circuit 2 is mounted on the center of the TCP 1, and the TCP wirings 12 and 13 connected to the driver integrated circuit 2 are formed. TCP pads 14 and 4 are connected to ends of the TCP wires 12 and 13, respectively, TCP pads 14 are connected to the PCB, and TCP pads 4 are data pads of the thin film transistor substrate 10 (not shown). Not connected to the data line 60. TCP dummy wires 19 and TCP dummy pads 17 are also formed in the TCP 1, and the TCP dummy pads 17 are bonded to the dummy pads (not shown) of the thin film transistor substrate 10 and are commonly used. Independent signals such as signals may be applied.

Here, part VI of FIG. 5 is enlarged and shown in FIG. 6.

6 illustrates a dummy pad 85, an auxiliary data pad 83, a dummy wiring 65 and data of the thin film transistor substrate 10 bonded to the TCP dummy pad 17 and the TCP pad 4 of FIG. 5, respectively. Line 60 is shown. Here, the width v of the dummy pad 85 is wider than the width x of the auxiliary data pad 83.

0)이 되도록 보조 데이터 패드(83)의 간격(y)을 충분히 넓게 형성한다. 한편, 더미 패드(85)의 폭(v)과 더미 패드(85) 간의 간격(w) 또한, 1:(1+α)(α

0)이 되도록 더미 패드(85)의 간격(w)을 충분히 넓게 형성한다. 여기서, 더미 배선(65)은 연결부(66)를 통해 두 개 이상씩 서로 연결될 수도 있다.As shown in FIG. 6, the interval y between the width x of the auxiliary data pad 83 and the auxiliary data pad 83 is 1: (1 + α) (α

The interval y of the auxiliary data pads 83 is sufficiently wided to be 0). On the other hand, the distance w between the width v of the dummy pad 85 and the dummy pad 85 is also 1: (1 + α) (α

The space | interval w of the dummy pad 85 is formed wide enough so that it may become 0). Here, two or more dummy wires 65 may be connected to each other through the connection part 66.

Next, a process of connecting the auxiliary data pad 83 and the TCP pad 4 will be described with reference to FIG. 7.

As shown in FIG. 7, the anisotropic conductive film 3 is coated on the passivation film 70 on the substrate 10 and the auxiliary data pad 83 formed thereon. Here, the anisotropic conductive film 3 means that the crimping resin and the fine conductive sphere 5 are mixed. The TCP pads 4 are arranged on the anisotropic conductive film 3 so as to be connected with the auxiliary data pads 83 one by one. Subsequently, upon thermal compression, the anisotropic conductive film 3 is pressed and contacted by the conductive spheres 5 so that the TCP pad 4 and the auxiliary data pad 83 are connected to each other. In this way, a signal from the driver integrated circuit over TCP (1) can be transmitted to the liquid crystal panel.

Although not shown here, when the anisotropic conductive film 3 is also applied on the dummy pad 85, the TCP dummy pads 17 are aligned on the dummy pads 85, and thermally crimped, the dummy pads 85 and the TCP dummy pads 17 are electrically connected. Is connected.

In this case, the distance between the auxiliary data pads 83 and the dummy pads 85 is sufficiently wide, so that even if misalignment of the auxiliary data pads 83 and the TCP pads 4 occurs, the auxiliary data pads adjacent to each other during thermocompression bonding are generated. The short circuit with the 83 can be prevented, and even if misalignment of the dummy pad 85 and the TCP dummy pad 17 occurs, a short circuit between neighboring dummy pads 85 can be prevented at the time of thermocompression bonding.

Meanwhile, the auxiliary gate pad 82 and the auxiliary data pad 83 may not be formed on the gate pad 22 and the data pad 63.

In this case, the portion directly connected to the TCP pad 4 through the anisotropic conductive film 3 becomes the data pad 63, and the distance between the contact holes 73 is greater than the width of the contact hole 73 exposing the data pad 63. This should be large to prevent a short circuit due to misalignment of the data pad 63 and the TCP pad 4.

Therefore, the width of the contact hole 73 is equal to or smaller than the gap between the contact holes 73.

On the other hand, the spacing between the auxiliary gate pads 82 may be greater than or equal to the width of the auxiliary gate pads 82, and when the auxiliary gate pads 82 are not formed, the spacing between the contact holes 72 may be defined by the contact holes 72. It may be larger than the width.

As described above, in the present invention, the spacing between the auxiliary data pads is wider than the width of the auxiliary data pads, thereby preventing a short circuit between the pads due to misalignment during the thermocompression bonding process.

Claims (10)

Insulation board, A plurality of first signal lines formed on the same layer on the substrate, A plurality of first pads connected to the first signal line; A plurality of second signal lines insulated from and intersecting the first signal line to form a plurality of pixel regions and formed on the same layer; A plurality of second pads connected to the second signal line; A pixel electrode formed in the pixel region, A thin film transistor connected to the pixel electrode and the first and second signal lines Including; The width of the first pad is less than or equal to the gap between the first pads Thin film transistor substrate for liquid crystal display device. Insulation board, A gate wiring formed on the substrate, the gate wiring including a plurality of gate lines formed on the same layer, a gate electrode connected to the gate line, and a plurality of gate pads connected to the gate line to receive a scan signal from the outside; A gate insulating film covering the gate wiring, A semiconductor layer formed on the gate insulating film, A plurality of data lines formed on the semiconductor layer and the gate insulating layer and formed on the same layer, a source electrode connected to the data line, a drain electrode separated from the source electrode, and connected to the data line from outside. A data line including a plurality of data pads receiving an image signal, A passivation layer formed on the data line and the gate insulating layer and having a plurality of first to third contact holes respectively exposing the drain electrode, the gate pad, and the data pad; A pixel electrode connected to the drain electrode through the first contact hole on the passivation layer; A plurality of auxiliary gate pads covering the gate pads through the second contact holes on the passivation layer; A plurality of auxiliary data pads covering the data pads through the third contact holes on the passivation layer; Including; The distance between the auxiliary data pads is greater than or equal to the width of the auxiliary data pads. Thin film transistor substrate for liquid crystal display device. In claim 2, A thin film transistor substrate for a liquid crystal display device, wherein a distance between the auxiliary gate pads is equal to or greater than a width of the auxiliary gate pads. In claim 3, The auxiliary gate pad and the auxiliary data pad are formed on the same layer as the pixel electrode. In claim 2, And a dummy pad disposed between the data line and the gate pad and a dummy pad connected to the dummy wire. In claim 5, A thin film transistor substrate for liquid crystal display devices, wherein the gap between the dummy pads is equal to or greater than the width of the dummy pads. In claim 5, And at least two of the dummy wires are connected to each other. Insulation board, A gate wiring formed on the substrate and including a plurality of gate lines, a gate electrode, and a plurality of gate pads formed on the same layer; A gate insulating film covering the gate wiring, A semiconductor layer formed on the gate insulating film, A data line formed on the semiconductor layer and the gate insulating layer, the data line including a plurality of data lines, source and drain electrodes, and a plurality of data pads formed on the same layer; A passivation layer formed on the data line and the gate insulating layer and having a plurality of first to third contact holes respectively exposing the drain electrode, the gate pad, and the data pad; A pixel electrode connected to the drain electrode through the first contact hole on the passivation layer Including; The distance between the third contact holes is equal to or greater than the width of the third contact holes. Thin film transistor substrate for liquid crystal display device. In claim 8, A thin film transistor substrate for liquid crystal display devices, wherein the distance between the second contact holes is equal to or greater than the width of the second contact holes. In claim 8, And a ohmic contact layer formed between the semiconductor layer and the data line.

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