KR100277501B1 - LCD and its manufacturing method - Google Patents

Abstract

A gate line and a common line including a gate line, a gate electrode, a gate pad, and a gate line connection unit are formed on the substrate, and a gate insulating film is formed on the gate line and the common line. A semiconductor layer and an ohmic contact layer are formed on the gate insulating layer on the gate electrode, and data lines and pixel electrodes including source and drain electrodes, data lines, data pads, and data line connection parts are formed thereon. At this time, the thickness of the data line and the pixel electrode should be 500 Å or less. A protective film is formed on the data line and the pixel electrode, a redundancy data line is formed on the protective film, and a redundant gate pad and a redundant gate line connection part are formed. The redundant data line is electrically connected to the data line through a contact window formed in the passivation layer, and the redundant gate pad and the redundant gate line connection part are electrically connected to the gate pad and the gate line connection part through the contact window formed in the gate insulating film and the passivation layer. The redundant gate line connection unit and the redundant data line connection unit are connected to each other to short-circuit the gate and the data line on the substrate. After completing the substrate, the substrate is subjected to the usual manufacturing process such as alignment film printing and rubbing, and then the edge of the substrate is cut to remove the gate line connecting portion and the data line connecting portion.

Description

Liquid Crystal Display and Manufacturing Method Thereof

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device and a method for manufacturing the same, and more particularly, to a liquid crystal display device having an electrode structure for applying a horizontal electric field and a thin film transistor that is an electric field application means.

The prior art as a liquid crystal driving method by a horizontal electric field is shown in US Patent No. 5,598, 285.

However, the liquid crystal display device disclosed in US Pat. No. 5,598,285 has uneven rubbing in the process of rubbing an alignment layer formed on the electrode by a step between two electrodes for applying a horizontal electric field, that is, a common electrode and a pixel electrode. This leaking problem is occurring.

In order to solve this problem, Korean Patent Application No. 97-61456 of the applicant as a related application is proposed a method for reducing the step by forming a pixel electrode in a thin metal layer.

Meanwhile, the liquid crystal display device disclosed in US Pat. No. 5,598,285 has a structure in which both electrodes for forming a horizontal electric field are formed on one substrate, and thus have a structure vulnerable to static electricity introduced from the outside. There is a problem that a phenomenon occurs that is destroyed by.

To solve this problem, a method of electrically shorting the gate wiring and the data wiring during the process and separating them at the completion stage of the product is used. However, in this case, a process of connecting the wiring to each other is added, thereby increasing the number of processes.

An object of the present invention is to eliminate the light leakage phenomenon in the liquid crystal display device of the horizontal electric field drive method.

Another object of the present invention is to reduce the destruction of the thin film transistor by static electricity.

Another object of the present invention is to simplify the process of the liquid crystal display device of the horizontal electric field driving method.

Another object of the present invention is to reduce the disconnection of the wiring.

Another object of the present invention is to improve the mounting reliability by strengthening the contact force when mounting the drive driver.

1 is a layout view of an entire substrate for a liquid crystal display according to an exemplary embodiment of the present invention.

2 is a layout view illustrating a unit pixel, a gate, and a data pad unit of a substrate for a liquid crystal display according to an exemplary embodiment of the present invention;

3 to 6 are cross-sectional views taken along lines III-III ', IV-IV', V-V ', and VI-VI' of FIG. 2, respectively.

7 is a cross-sectional view illustrating a gate line connection unit of a liquid crystal display according to an exemplary embodiment of the present invention.

8A to 11E are cross-sectional views illustrating a manufacturing process of a liquid crystal display according to an exemplary embodiment of the present invention.

In order to solve the above technical problem, in the present invention, a gate wiring including a gate line, a gate electrode, a gate pad, and a gate line connecting portion is formed on a substrate, and a gate insulating film is formed on the gate wiring and the common wiring. A semiconductor layer and an ohmic contact layer are formed on the gate insulating layer on the gate electrode, and a data line including a source and drain electrode, a data line, a data pad, and a data line connection part and a pixel electrode are formed thereon as a first conductive layer. A protective film is formed on the data line and the pixel electrode, and a redundant data line including a redundancy data line, a redundant data pad, and a redundant data line connection part is formed as a second conductive layer on the protective layer. do. The redundant data line is electrically connected to the data line through a contact window formed in the passivation layer, and the redundant gate pad and the redundant gate line connection part are electrically connected to the gate pad and the gate line connection part through the contact window formed in the gate insulating film and the passivation layer. The redundant gate line connection unit and the redundant data line connection unit are connected to each other to short-circuit the gate and the data line on the substrate.

After completing the substrate, the substrate is subjected to the usual manufacturing process such as alignment film printing and rubbing, and then the edge of the substrate is cut to remove the gate line connecting portion and the data line connecting portion.

The pixel electrode may be formed in the process of forming the redundant data line using the second metal layer instead of forming the data line using the first metal layer, and the thickness of the pixel electrode may be 500 Å or less.

Embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

First, a structure of a liquid crystal display substrate according to an exemplary embodiment of the present invention will be described. 1 is a layout view briefly illustrating an overall configuration of a liquid crystal display according to an exemplary embodiment of the present invention.

As shown in FIG. 1, a plurality of gate lines 20 are formed in a horizontal direction on the substrate 100, and a plurality of common electrode lines 10 are formed in parallel with the gate line 20. Gate pads 22 connected to the gate drivers are formed at the ends of the gate lines 20, and the gate pads 22 are all connected by the gate line connectors 24. In the vertical direction, a plurality of data lines 60 are formed to intersect with the gate line 20 and the common electrode line 10, and a data pad 63 connected to a data driver at an end of the data line 60. Is formed, and the data pads 63 are also connected to each other by the data line connection unit 64. The gate line connecting portion 24 and the data line connecting portion 64 are connected to each other with a resistance therebetween so that the gate line 20 and the data line 60 of the entire substrate are short-circuited by the connecting portions 24 and 64. . The connection of all the wirings is to protect the thin film transistors by effectively dissipating static electricity generated during the manufacturing process of the liquid crystal display substrate. When the liquid crystal display substrate is completed, it is along the cutting line 200 indicated by a dotted line on the drawing. The outer portions of the pads 22 and 63 are cut to separate the wires from each other.

Each pixel is defined by the intersection of the gate line 20 and the data line 60, the substrate is divided into a plurality of pixels, and a linear pixel electrode and a common electrode are alternately formed in each pixel area.

Now, the structure of the unit pixel of the liquid crystal display according to the exemplary embodiment of the present invention will be described in detail. FIG. 2 is a layout view illustrating one pixel, a gate, and a data pad unit of the liquid crystal display as shown in FIG. 1, and FIGS. 3 to 6 are III-III ′, IV-IV ′, and V-V ′ of FIG. 2, respectively. , Sectional view along the line VI-VI '. 7 is a cross-sectional view of the gate line connection unit.

2 to 6, the gate line 20 is formed in the horizontal direction on the transparent insulating substrate 100, and the gate pad 22 is formed at the end of the gate line 20. Part of the gate line 20 becomes the gate electrode 21. The common electrode line 10 is formed in parallel with the gate line 20, and a plurality of common electrodes 11 are connected to the common electrode line 10 in the pixel area to receive a common signal from the common electrode line 10. ) Is formed. 1 and 7, a gate line connection part 24 connecting the gate pads 22 to each other is connected to the gate pads 22.

The gate insulating film 30 made of silicon nitride or the like is covered on the gate wirings 20, 21, 22, 24 and the common wirings 10, 11.

The semiconductor layer 40 of the thin film transistor made of amorphous silicon is formed on the gate insulating film 30 on the gate electrode 21, and the amorphous silicon doped with high concentration of phosphorus (P) or the like is formed on the amorphous silicon layer 40. The ohmic contacts 51 and 52 are formed on both sides of the gate electrode 21.

A source electrode 61 and a drain electrode 62 made of metal are formed on the ohmic contact layers 51 and 52, respectively, and the source electrode 61 is formed in the vertical direction on the gate insulating layer 30. 60, the drain electrode 62 is connected to the pixel electrode 65 that is linearly formed alternately with the common electrode 11 in the pixel area. A data pad 63 for receiving an image signal from the outside is formed at the end of the data line 60. As shown in FIG. 1, the data pads 63 are all connected by the data line connection unit 64.

The gate electrode 21, the gate insulating film 30, the amorphous silicon layer 40, the ohmic contact layers 51 and 52, the source and drain electrodes 61 and 62 form a thin film transistor, and the thin film transistor and the remaining data wirings. The protective film 70 covering the (60, 63, 64, 65) is made of silicon nitride or the like.

In the passivation layer 70, contact windows 71 and 73 are formed to expose portions of the data line 60 and the data pad 63, respectively. The passivation layer on the data line connecting portion 64 is not illustrated. A portion of 70 is also removed to reveal the data line connecting portion 64. A metal pattern is formed on the passivation layer 70 in the same manner as the data wirings 60, 63, and 64, and the data wirings 60, 63, and 64 are formed through the contact windows 71 and 73 formed on the passivation layer 70. They are connected to form redundant data wirings 80 and 83. The metal patterns 82 and 84 are also formed on the gate pads 22 and the gate line connecting portions 24 to form the gate pads through the contact windows 72 and 74 formed in the passivation layer 70 and the gate insulating layer 30. And a gate line connecting portion 24, respectively. On the other hand, the metal pattern 84 on the gate line connecting portion 24 and the metal pattern on the data line connecting portion 64, which is part of the redundant data wiring, are connected to each other so that both the gate line 20 and the data line 60 are electrically connected to each other. It is connected.

Now, a method of manufacturing a liquid crystal display substrate according to an embodiment of the present invention will be described. 8A to 11E are cross-sectional views illustrating a process of manufacturing a substrate for a liquid crystal display as shown in FIGS. 1 to 7. The manufacturing method according to the embodiment of the present invention is a manufacturing method using five masks, and the alphabets a to e shown in the reference numerals refer to a pixel region, a thin film transistor region, a gate pad region, a data pad region, It shows that the gate line connection portion is shown.

First, as shown in FIGS. 8A to 8E, a metal layer having a thickness of about 3000 μs is deposited on a transparent insulating substrate 100 such as glass, and patterned using a first mask to form a gate line 20 and a gate electrode 21. The gate pad 22, the gate line connection part 24, the common electrode 11, and the common electrode line 10 are formed. In this case, various conductive materials may be used as the gate wiring metal, and chromium, aluminum, aluminum alloy, molybdenum, or the like may be used, or the gate wiring may be formed by a double layer combining these metals.

Next, as shown in FIGS. 9A to 9E, an insulating gate insulating film 30 such as silicon nitride or an organic insulating film is formed on the entire surface of the substrate to a thickness of 3,000 to 5,000 GPa, and an amorphous silicon layer having a thickness of about 500 to 2,000 GPa ( 40) and an amorphous silicon layer 50 heavily doped with impurities such as phosphorous having a thickness of about 500 GPa are sequentially deposited. The doped amorphous silicon layer 50 and the amorphous silicon layer 40 are patterned together using a second mask to form an island shape on the gate electrode 21.

As shown in FIGS. 10A to 10E, a metal layer such as chromium, an aluminum alloy, or molybdenum is deposited at about 500 GPa or less and patterned using a third mask to pattern the data line 60 crossing the gate line 20. Source and drain electrodes 61 and 62, a data pad 63, a data line connector 64, and a pixel electrode 65 are formed. Next, the doped amorphous silicon layer 50 is etched by etching the doped amorphous silicon layer 50 using the source electrode 61 and the drain electrode 62 as a mask, and the resistive contact layer 51 is separated from each other by the gate electrode 21. , 52).

A protective film 70 having a thickness of 1,500 to 2,500 Å is formed on the entire surface of the substrate using silicon nitride or an organic insulating film, and is patterned by using a fourth mask to expose the data line 60 and the data pad 63, respectively. 73 is formed, and the contact insulating films 72 and 74 are formed by removing the gate insulating film 30 and the protective film 70 on the gate pad 22 and the gate line connection part 24.

Finally, as shown in FIG. 3 to FIG. 7, a single film or a plurality of films of molybdenum, molybdenum alloy, or aluminum alloy is deposited to a thickness of 2,000 to 2,500 Pa, and patterned using a fifth mask to form a data line 60. ), Redundant redundancy data lines 80, 83, 82, 84 similar to the data pad 63, the gate pad 22, and the gate line connecting portion 24 are formed. Although not shown in the drawing, the data line connection part is also formed on the passivation layer 70 in a similar pattern, and is electrically connected to the data line connection part through the contact window and formed in a double.

Thereafter, an alignment layer is formed on the surface of the substrate and subjected to a rubbing process to give the orientation of the liquid crystal material. Finally, the gate line connection unit and the data line connection unit and the connection unit for electrically connecting them are separated and removed.

In the liquid crystal display according to the exemplary embodiment of the present invention, the pixel electrode is reduced as much as possible to about 500 kHz, thereby reducing the step difference between layers and suppressing the uneven alignment generated in the rubbing process, thereby reducing the light leakage phenomenon, and the redundant data wiring part is the pixel. The portion other than the region has a smaller thickness limit than the pixel electrode layer, so that it is formed thicker to about 2,000-2,500 kHz, thereby lowering the resistance of the wiring. In addition, since the redundant data wiring portion constitutes the pad portion, it is preferable to use a material having high contact reliability when mounting the driver integrated circuit.

In the above embodiment, the redundancy data line may be first formed, the passivation layer may be formed, the contact window may be formed on the passivation layer, and the pixel electrode, the data line, and the source / drain electrode may be formed. In this case, it is advantageous to form the thickness of the pixel electrode at about 500 mW or less in terms of preventing light leakage. On the other hand, in this case, since the metal forming the pixel electrode forms the pad portion, it is preferable to form the pixel electrode with chromium, molybdenum, molybdenum alloy or the like which can have reliability as the pad portion.

Unlike in the embodiment of the present invention, when the indium tin oxide (ITO) is used as the redundant data wiring or when the upper layer is formed of ITO with another metal layer underneath, the contact reliability with the driver can be further improved.

In addition, unlike the embodiment of the present invention in which a part of the passivation layer on the data line is removed and electrically connected to the redundant data line, when the passivation layer formed on the data line is removed and the redundant data line is formed thereon, the data wiring and the redundant data The contact resistance between the wirings is reduced, and redundant data wirings enter the space between the protective films, thereby reducing the step difference.

In the exemplary embodiment of the present invention, both the gate line connection part and the data line connection part are formed in double, and the redundant gate line connection part and the redundant data line connection part are connected to each other to short the gate line and the data line. Instead of forming one or both of the data line connecting portions, a pattern for connecting the data line connecting portion and the gate line connecting portion may be formed when the redundant data wiring is formed.

As in the embodiment of the present invention, by using five masks to form a horizontal field drive type liquid crystal display device having redundant data wiring, the light leakage phenomenon of the liquid crystal display device is removed, and the thin film transistor is effectively protected from static electricity. The process can be simplified. In addition, disconnection of the wiring can be reduced by redundant data wiring, and the mounting reliability can be improved by enhancing the contact force when mounting the drive driver in the pad portion.

Claims (32)

A plurality of gate lines formed parallel to each other on a transparent substrate, A plurality of data lines insulated from and intersecting the gate lines; A pixel region in which a common electrode and a pixel electrode are formed to face each other at a predetermined interval in an area defined by the intersection of the gate line and the data line; A thin film transistor having a gate electrode, a source electrode, and a drain electrode connected to the gate line, the data line, and the pixel electrode; An insulating film formed below or above the data line and having a first contact window; And a redundant data line formed side by side with the data line and the insulating layer interposed therebetween and electrically connected to the data line through the first contact window. In claim 1, A data pad formed at an end of the data line, Further comprising a redundant data pad made of a conductive material layer, such as the redundant data line, The insulating layer has a second contact window, and the data pad and the redundant data pad are electrically connected to each other through the second contact window. In claim 2, The upper layer of the data pad and the redundant data pad includes a layer made of ITO. In claim 1, A gate pad formed at an end of the gate line, And a redundant gate pad made of the same metal layer as the redundant data line and electrically connected to the gate pad. In claim 4, And a layer formed above the gate pad and the redundant gate pad includes a layer made of ITO. In claim 1, A gate line connection part connecting the plurality of gate lines to each other; A data line connection unit connecting the plurality of data lines to each other; A redundant gate line connection part formed of the same metal layer as the redundant data line and electrically connected to the gate line connection part; And a redundant data line connection part formed of the same metal layer as the redundant data line and electrically connected to the data line connection part. And the redundant gate line connection unit and the redundant data line connection unit are connected to each other. In claim 1, And at least one of the data line and the redundant data line is formed of the same layer as the pixel electrode. In claim 7, The pixel electrode has a thickness of 500 kPa or less. Board, A gate line formed on the substrate and a gate electrode connected to the gate line; A linear common electrode formed separately from the gate line on the substrate, A gate insulating film covering the gate line, the gate electrode, and the common electrode, A semiconductor layer formed on the gate insulating film on the gate electrode, An ohmic contact layer formed on both sides of the gate electrode on the semiconductor layer; Source and drain electrodes respectively formed on the ohmic contact layer; A data line formed on the gate insulating layer and connected to the source electrode; A linear pixel electrode alternately formed with the common electrode on the gate insulating layer of the pixel region defined by the intersection of the gate line and the data line, and connected to the drain electrode; A passivation layer covering the source and drain electrodes, the data line, and the pixel electrode and having a first contact window exposing the data line; A redundancy data line formed on the passivation layer and electrically connected to the data line through the first contact window; And at least one pixel electrode and at least one common electrode in each pixel area. In claim 9, A data pad formed at an end of the data line, Further comprising a redundant data pad made of a conductive material layer, such as the redundant data line, The passivation layer has a second contact window such that the data pad and the redundant data pad are electrically connected through the second contact window. In claim 10, The redundant data pad includes a layer made of ITO. In claim 9, A gate pad formed at an end of the gate line, Further comprising a redundant gate pad made of the same metal layer as the redundant data line, And the gate insulating layer and the passivation layer have a third contact window exposing the gate pad so that the gate pad and the redundant gate pad are electrically connected through the third contact window. In claim 12, The redundancy gate pad includes a layer made of ITO. In claim 9, A gate line connection part connecting the gate pads to each other; Further comprising a redundant gate line connecting portion made of a metal layer such as the redundant data line, The gate insulating layer and the passivation layer have a fourth contact window exposing the gate line connection part, and the gate line connection part and the redundant gate line connection part are electrically connected through the fourth contact window. The method of claim 14, A data line connection unit connecting the data pads to each other; Further comprising a redundant data line connection portion made of the same metal layer as the redundant data line, The passivation layer has a fifth contact window exposing the data line connection part, the data line connection part and the redundant data line connection part are electrically connected through the fifth contact window, and the redundant data line connection part is the redundant gate line. Liquid crystal display connected to the connection. In claim 9, The pixel electrode has a thickness of 500 kPa or less. Forming a common wiring and a gate wiring including a gate line, a gate electrode, a gate pad, and a gate line connecting portion on the substrate, Forming a gate insulating film covering the gate wiring and the common wiring; Forming a semiconductor layer and an ohmic contact layer on the gate insulating layer; Forming a data line and a pixel electrode including a source and drain electrode, a data line, a data pad, and a data line connection part using the first metal layer; Depositing a passivation layer on the first metal layer; Forming first and second contact windows on the passivation layer to expose the data line and the data pad, respectively; And forming a redundant data line including a redundant data line, a redundant data pad, and a redundant data line connection part using the second metal layer on the passivation layer. The method of claim 17, Forming a first contact window on the passivation layer to form third and fourth contact windows that respectively expose the gate pad and the gate line connection part by etching the gate insulating layer together; And forming a redundant gate pad and a redundant gate line connection part in the forming of the redundant data line. The method of claim 18, The pixel electrode is a substrate manufacturing method for a liquid crystal display device to be formed to 500 GHz or less. Forming a common wiring and a gate wiring including a gate line, a gate electrode, a gate pad, and a gate line connecting portion on the substrate, Forming a gate insulating film covering the gate wiring and the common wiring; Forming a semiconductor layer and an ohmic contact layer on the gate insulating layer; Forming a data line including a source and drain electrode, a data line, a data pad, and a data line connection part using the first metal layer; Depositing a passivation layer on the first metal layer; Forming first and second contact windows on the passivation layer to expose the data line and the data pad, respectively; Forming a redundant data line and a pixel electrode on the passivation layer with a second metal layer. The method of claim 20, Forming first and second contact windows on the passivation layer to etch the gate insulating layer together to form third and fourth contact windows respectively exposing the gate pad and the gate line connection part, And forming a redundant gate pad and a redundant gate line connection part in the forming of the redundant data line. The method of claim 21, The pixel electrode is a substrate manufacturing method for a liquid crystal display device to be formed to 500 GHz or less. A plurality of gate lines formed parallel to each other on a transparent substrate, Gate pads connected to ends of the gate lines, respectively. A plurality of data lines insulated from and intersecting the gate lines; A data pad connected to each end of the data line, A pixel region in which a common electrode and a pixel electrode are formed to face each other at a predetermined interval in an area defined by the intersection of the gate line and the data line; A thin film transistor having a gate electrode, a source electrode, and a drain electrode connected to the gate line, the data line, and the pixel electrode; An insulating film formed on the data line, the data pad, the gate line, and the gate pad; And a redundancy pad formed on the data pad or the gate pad and connected to the data pad or the gate pad through a first contact window of the insulating layer. The method of claim 23, Consists of a conductive material layer such as redundant pad, And a redundant data line formed in parallel with the data line and connected to the data line through a second contact window of the insulating layer. The method of claim 24, The redundant pad includes a layer made of ITO. The method of claim 25, And a layer formed above the gate pad and the redundant gate pad includes a layer made of ITO. The method of claim 26, And at least one of the data line and the redundant data line is formed of the same layer as the pixel electrode. The method of claim 27, The pixel electrode has a thickness of 500 kPa or less. Board, A gate line formed on the substrate, a gate electrode connected to the gate line, and a gate pad connected to an end of the gate line; A linear common electrode formed separately from the gate line on the substrate; A gate insulating film covering the gate line, the gate electrode, and the common electrode, A semiconductor layer formed on the gate insulating film over the gate electrode, An ohmic contact layer formed on both sides of the gate electrode on the semiconductor layer; Source and drain electrodes respectively formed on the ohmic contact layer; A data pad formed on the gate insulating layer and connected to the source electrode and a data pad connected to an end of the data line; A linear pixel electrode alternately formed with the common electrode on the gate insulating layer of the pixel region defined by the intersection of the gate line and the data line, and connected to the drain electrode; A protective film covering the source and drain electrodes, the data line, and the pixel electrode, and having a first contact window for drawing the gate pad together with the data pad or the gate insulating film; A redundancy pad formed on the passivation layer and connected to the data pad or the gate pad through the first contact window; And at least one pixel electrode and at least one common electrode in each pixel area. The method of claim 29, Further comprising a redundant data line made of the same conductive layer as the redundant pad, The passivation layer has a second contact window that exposes the data line, and the data line and the data line are electrically connected through the second contact window. The method of claim 30, The redundant pad includes a layer made of ITO. The method of claim 31, The pixel electrode has a thickness of 500 kPa or less.