KR100552298B1 - Liquid crystal display device and substrate manufacturing method for liquid crystal display device - Google Patents

Abstract

A gate line and a common line including a gate line, a gate electrode, a gate pad, and a gate line connection unit are formed on the substrate, and a gate insulating film is formed on the gate line and the common line. A semiconductor layer, an ohmic contact layer, and a light blocking film are formed on the gate insulating film on the gate electrode, and the gate insulating film is patterned to expose the gate pad and the gate line connection part. Next, the first conductive layer is stacked and patterned thereon to form source and drain electrodes, a data line, a data pad, a data line including a data line connection part, a pixel electrode, and a first redundant gate pad, followed by a second conductive layer. Are stacked and patterned to form redundant data lines, redundant data pads, and second redundant gate pads that overlap the light blocking film. At this time, the thickness of the data line and the pixel electrode should be 1,000 Å or less. A protective film is formed on the redundant data wiring, the data wiring and the pixel electrode, and the protective film is patterned to expose the redundant data pad and the second redundant gate pad. Here, the redundant data wiring and the second redundant gate pad are formed of a double layer of a lower layer made of ITO and an upper layer made of molybdenum, molybdenum alloy or aluminum and aluminum alloy, and the lower ITO layer is exposed on the pad portion to mount the driver integrated circuit. Improve contact reliability

Description

Liquid crystal display device and substrate manufacturing method for liquid crystal display device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device and a method for manufacturing the same, and more particularly to a liquid crystal display device having a thin film transistor which is an electrode structure for applying a horizontal electric field and an electric field application means.

The prior art as a liquid crystal driving method by a horizontal electric field is shown in US Patent No. 5,598, 285.

However, the liquid crystal display device disclosed in US Pat. No. 5,598,285 has uneven rubbing in the process of rubbing an alignment layer formed on the electrode by a step between two electrodes for applying a horizontal electric field, that is, a common electrode and a pixel electrode. This leaking problem is occurring.

In order to solve this problem, Korean Patent Application No. 97-61456 of the applicant as a related application is proposed a method for reducing the step by forming a pixel electrode in a thin metal layer.

Meanwhile, the liquid crystal display device disclosed in US Pat. No. 5,598,285 has a structure in which both electrodes for forming a horizontal electric field are formed on one substrate, and thus have a structure vulnerable to static electricity introduced from the outside. There is a problem that a phenomenon occurs that is destroyed by.

To solve this problem, a method of electrically shorting the gate wiring and the data wiring during the process and separating them at the completion stage of the product is used, but in this case, a process of connecting the wiring to each other is added, thereby increasing the number of processes.

In addition, a coupling effect occurs between the data line applying the voltage to the pixel electrode and the common electrode, and light leaks, thereby causing a cross talk.

An object of the present invention is to eliminate the light leakage phenomenon in the liquid crystal display device of the horizontal electric field drive method.

Another object of the present invention is to reduce the destruction of the thin film transistor by static electricity.

Another object of the present invention is to simplify the process of the liquid crystal display device of the horizontal electric field driving method.

Another object of the present invention is to reduce the disconnection of the wiring.

Another object of the present invention is to improve the mounting reliability by strengthening the contact force when mounting the drive driver.

In order to solve the above technical problem, in the present invention, a gate wiring including a gate line, a gate electrode, a gate pad, and a gate line connecting portion is formed on a substrate, and a gate insulating film is formed on the gate wiring and the common wiring. On the gate insulating film on the gate electrode, a light blocking film is formed at the boundary between the semiconductor layer, the ohmic contact layer, and the pixel region, and the gate insulating film is etched to expose the gate pad and the gate connection part. Subsequently, a first conductive layer defines a source and a drain electrode, a gate line and a pixel region, a data line overlapping the light blocking layer, a data line including a data pad and a data line connection unit, a pixel electrode and a gate pad connected to the drain electrode. A redundancy gate pad connected to the redundancy gate pad is formed, and a redundancy data line including a redundancy data line, a redundant data pad, and a redundant data line connection unit is formed as a second conductive layer. Next, a protective film is formed, and the protective film is patterned to expose the second redundant gate pad and the redundant data pad. Here, the first and second redundant gate pads are electrically connected to the gate pads through a contact window formed in the gate insulating layer, and the data line connection part and the redundant data line connection part are electrically connected to the gate line connection part through the contact window formed in the gate insulating film. To be connected. The gate line connection part, the data line connection part, and the redundant data line connection part are connected to each other to short-circuit the gate and the data wire on the substrate.

After the substrate is completed, the substrate is subjected to a usual manufacturing process such as alignment film printing and rubbing, and then the edge of the substrate is cut to remove the gate line connecting portion, the data line, and the redundant data line connecting portion.

The pixel electrode may be formed in the process of forming the redundant data line using the second conductive layer instead of forming the data line using the first conductive layer, and the thickness of the pixel electrode may be 1,000 Å or less. It is good.

Embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

First, a structure of a liquid crystal display substrate according to an exemplary embodiment of the present invention will be described. 1 is a layout view briefly illustrating an overall configuration of a liquid crystal display according to an exemplary embodiment of the present invention.

As shown in FIG. 1, a plurality of gate lines 20 are formed in a horizontal direction on the substrate 100, and a plurality of common electrode lines 10 are formed in parallel with the gate line 20. Gate pads 22 connected to the gate drivers are formed at the ends of the gate lines 20, and the gate pads 22 are all connected by the gate line connectors 24. In the vertical direction, a plurality of data lines 60 are formed to intersect with the gate line 20 and the common electrode line 10, and a data pad 63 connected to a data driver at an end of the data line 60. Is formed, and the data pads 63 are also connected to each other by the data line connection unit 64. The gate line connecting portion 24 and the data line connecting portion 64 are connected to each other with a resistance therebetween so that the gate line 20 and the data line 60 of the entire substrate are short-circuited by the connecting portions 24 and 64. . The connection of all the wirings is to protect the thin film transistors by effectively dissipating static electricity generated during the manufacturing process of the liquid crystal display substrate. When the liquid crystal display substrate is completed, it is along the cutting line 200 indicated by a dotted line on the drawing. The outer portions of the pads 22 and 63 are cut to separate the wires from each other.

Each pixel is defined by the intersection of the gate line 20 and the data line 60, the substrate is divided into a plurality of pixels, and a linear pixel electrode and a common electrode are alternately formed in each pixel area.

Now, the structure of the unit pixel of the liquid crystal display according to the exemplary embodiment of the present invention will be described in detail. FIG. 2 is a layout view illustrating one pixel, a gate, and a data pad unit of the liquid crystal display as shown in FIG. 1, and FIGS. 3 to 6 are III-III ′, IV-IV ′, and V-V ′ of FIG. 2, respectively. , Sectional view along the line VI-VI '. 7 is a cross-sectional view of the gate line connection unit.

2 to 6, the gate line 20 is formed in the horizontal direction on the transparent insulating substrate 100, and the gate pad 22 is formed at the end of the gate line 20. Part of the gate line 20 becomes the gate electrode 21. The common electrode line 10 is formed in parallel with the gate line 20, and a plurality of common electrodes 11 are connected to the common electrode line 10 in the pixel area to receive a common signal from the common electrode line 10. , 12) is formed. 1 and 7, a gate line connection part 24 connecting the gate pads 22 to each other is connected to the gate pads 22.

A gate insulating film 30 made of silicon nitride or the like is covered on the gate wirings 20, 21, 22, and 24 and the common wirings 10, 11, and 12. The gate insulating film 30 includes a gate pad 22 and a gate. Contact holes 32 and 34 are formed to expose the line connecting portion 24.

The semiconductor layer 40 of the thin film transistor made of amorphous silicon is formed on the gate insulating film 30 on the gate electrode 21, and the amorphous silicon doped with high concentration of phosphorus (P) or the like is formed on the amorphous silicon layer 40. The ohmic contacts 51 and 52 are formed on both sides of the gate electrode 21. In addition, on the gate insulating layer 30 at the unit pixel region boundary, an edge portion of the common insulating layer 12 overlaps with the common electrode 12, and an undoped amorphous silicon layer 411 and a doped amorphous silicon layer ( A light blocking film 41 made of 412 is formed.

A source electrode 61 and a drain electrode 62 made of metal are formed on the ohmic contact layers 51 and 52, respectively, and the source electrode 61 is formed in the vertical direction on the gate insulating layer 30. The drain electrode 62 is connected to the pixel electrode 65 which is linearly formed alternately with the common electrodes 11 and 12 in the pixel area. In addition, a first redundant gate pad 66 connected to the gate pad 22 through the contact hole 32 is formed on the gate insulating layer 30 of the gate pad 22. A data pad 63 for receiving an image signal from the outside is formed at the end of the data line 60. As shown in FIG. 1, the data pads 63 are all connected by the data line connection unit 64.

Here, the gate electrode 21, the gate insulating film 30, the amorphous silicon layer 40, the ohmic contact layers 51 and 52, the source and drain electrodes 61 and 62 form a thin film transistor, as shown in FIG. 7. The data line connector 64 is connected to the gate line connector 24 through the contact hole 34 of the gate insulating layer 30.

The redundant data 80 and the redundant data pad 83 are formed on the data line 60 and the data pad 63, and the second redundant gate pad 86 is formed on the first redundant gate pad 66. The redundant data line connection part 84 is formed also in the upper part of the data line connection part 64. As shown in FIG. Here, the redundant data wirings 80, 83, 84, and the second redundant gate pad 86 each include a lower film 801, 831, 841, 861 made of ITO, which is a transparent conductive film, and molybdenum, molybdenum alloy, aluminum, or aluminum. Top films 802, 832, 842, and 862 made of an alloy or the like.

A protective film 70 made of silicon oxide or silicon nitride is formed on the redundant data wirings 80, 83, 84, the second redundant gate pad 86, and the substrate 100 not covered by the redundant data wirings 80, 83, 84. In the passivation layer 70, contact holes 72 and 73 are formed to expose the ITO lower layer 861 of the second redundant gate pad 86 and the ITO lower layer 831 of the redundant data pad 83. 1 and 7, the gate line connection unit 24 is electrically connected to the data line connection unit 64 and the redundant data line connection unit 84, which are part of the redundant data line, so that the gate line 20 and the data line are electrically connected to each other. The 60 and redundant data lines 80 are shorted to each other.

Now, a method of manufacturing a liquid crystal display substrate according to an embodiment of the present invention will be described. 8A to 11E are cross-sectional views illustrating a process of manufacturing a substrate for a liquid crystal display as shown in FIGS. 1 to 7. The manufacturing method according to the embodiment of the present invention is a manufacturing method using six masks, and the alphabets a to e shown in the reference numerals are each a pixel region, a thin film transistor region, a gate pad region, a data pad region, It shows that the gate line connection portion is shown.

First, as shown in FIGS. 8A to 8E, a metal layer having a thickness of about 3000 μs is deposited on a transparent insulating substrate 100 such as glass, and patterned using a first mask to form a gate line 20 and a gate electrode 21. ), The gate pad 22, the gate line connection part 24, the common electrodes 11 and 12, and the common electrode line 10 are formed. In this case, various conductive materials may be used as the gate wiring metal, and chromium, aluminum, aluminum alloy, molybdenum, or the like may be used, or the gate wiring may be formed by a double layer combining these metals.

Next, as shown in FIGS. 9A to 9E, an insulating gate insulating film 30 such as silicon nitride or an organic insulating film is formed on the entire surface of the substrate to a thickness of 3,000 to 5,000 GPa, and an amorphous silicon layer having a thickness of about 500 to 2,000 GPa ( 40) and an amorphous silicon layer 50 heavily doped with impurities such as phosphorous having a thickness of about 500 GPa are sequentially deposited. The doped amorphous silicon layer 50 and the amorphous silicon layer 40 are patterned together using a second mask to form an island shape on the gate electrode 21, and the doped amorphous silicon layer 411 and the doped The light blocking film 41 made of the amorphous silicon layer 412 is formed. Subsequently, contact holes 32 and 34 exposing the gate pad 22 and the gate line connection part 24 are formed by patterning the gate insulating film 30 using a third mask.

As shown in FIGS. 10A to 10E, a metal layer such as chromium, an aluminum alloy, or molybdenum is deposited at about 1,000 GPa or less, patterned using a fourth mask, and intersected with the gate line 20 to cross the unit pixel region. The data line 60, the source and drain electrodes 61 and 62, the data pad 63, the data line connector 64, the pixel electrode 65, and the first redundant gate pad 66 are formed. Next, the doped amorphous silicon layer 50 is etched by etching the doped amorphous silicon layer 50 using the source electrode 61 and the drain electrode 62 as a mask, and the resistive contact layer 51 is separated from each other by the gate electrode 21. , 52). In this case, the doped amorphous silicon layer 411 of the light blocking layer 41 remains only under the data line 60, and the undoped amorphous silicon layer 412 is not etched and overlaps with the common electrode 12. .

Next, as shown in FIGS. 11A to 11E, a single film or a plurality of films of ITO and molybdenum, molybdenum alloy or aluminum and aluminum alloy, which are low resistance metals, are deposited and patterned using a fifth mask to form a data line 60. Forming redundant data wires 80, 83, 84 similar to the data pad 63, the data line connection 64, and a second redundant gate pad 86 similar to the first redundant gate pad 66. do. Here, the lower layers 801, 831, 841, 861 and the upper layers 802, 832, 842, and 862 of the redundant data wirings 80, 83, 84, and the second redundant gate pad 86 are formed of ITO and molybdenum, respectively. Alternatively, when the molybdenum alloy is formed, the upper layer and the lower layer may be etched at one time with an etchant for ITO.

Finally, as shown in FIGS. 2 to 7, a protective film 70 having a thickness of 1,500 to 2,500 100 is formed on the entire surface of the substrate 100 using silicon nitride or an organic insulating film, and is patterned using a sixth mask. Contact holes 72 and 73 are formed to expose the redundant gate pad 86 and the data pad 63, respectively. At this time, patterning is performed continuously to expose the ITO of the lower layers 861 and 831 of the second redundant gate pad 86 and the redundant data pad 83.

Thereafter, an alignment layer is formed on the surface of the substrate and subjected to a rubbing process to give the orientation of the liquid crystal material. Finally, the gate line connection unit and the data line connection unit and the connection unit for electrically connecting them are separated and removed.

In the liquid crystal display device according to the embodiment of the present invention, the pixel electrode is as low as possible to 1,000 Å or less, thereby reducing the step difference between layers and suppressing the uneven alignment generated in the rubbing process, thereby reducing the light leakage phenomenon, redundant data wiring The portion is a portion other than the pixel region, and the thickness is less than that of the pixel electrode layer, so that the portion is formed thicker to about 2,000-2,500 GHz to lower the resistance of the wiring. In addition, since the redundant data wiring portion including the ITO constitutes the pad portion, it is preferable to use a material having high contact reliability when mounting the driver integrated circuit.

In the above embodiment, the redundancy data lines may be first formed by changing the data process order, and then the pixel electrodes, the data lines, and the source / drain electrodes may be formed. In this case, it is advantageous to form the thickness of the pixel electrode at about 1,000 GPa or less in terms of preventing light leakage. On the other hand, in this case, since the metal forming the pixel electrode forms the pad portion, it is preferable to form the pixel electrode with chromium, molybdenum, molybdenum alloy or the like which can have reliability as the pad portion.

As in the embodiment of the present invention, it is possible to further increase the contact reliability with the driver by using indium tin oxide (ITO) in the redundant data wiring and exposing the lower layers 861 and 831 made of ITO in the pad portion.

In addition, by forming the redundant data wirings 80 and 83 directly on the data wirings 60 and 63, the contact resistance between the data wiring and the redundant data wiring can be reduced, and the wiring can be formed twice to prevent disconnection of the wiring. .

In addition, crosstalk can be prevented by forming the light blocking film 41 so as to overlap between the data line 60 and the redundant data line 80 and the common electrode 12.

As in the embodiment of the present invention, by using the six masks to form a horizontal field drive type liquid crystal display device having redundant data wiring and light blocking film, light leakage phenomenon and cross talk of the liquid crystal display device are eliminated, and the process is performed. Can be simplified. In addition, the disconnection of wiring can be reduced by redundant data wiring, and the mounting reliability can be improved by strengthening the contact force when mounting the driving driver in the pad part, and the gate line and the data line are shorted through the gate line and the data line connection part. This can effectively protect the thin film transistor from static electricity.

1 is a layout view of an entire substrate for a liquid crystal display according to an exemplary embodiment of the present invention.

2 is a layout view illustrating a unit pixel, a gate, and a data pad unit of a substrate for a liquid crystal display according to an exemplary embodiment of the present invention;

3 to 6 are cross-sectional views taken along lines III-III ', IV-IV', V-V ', and VI-VI' of FIG. 2, respectively.

7 is a cross-sectional view illustrating a gate line connection unit of a liquid crystal display according to an exemplary embodiment of the present invention.

8A to 11E are cross-sectional views illustrating a manufacturing process of a liquid crystal display according to an exemplary embodiment of the present invention.

Claims (19)

A plurality of gate lines formed parallel to each other on a transparent substrate, A plurality of data lines insulated from and intersecting the gate lines; A pixel region in which a common electrode and a pixel electrode are formed to face each other at a predetermined interval in an area defined by the intersection of the gate line and the data line; A thin film transistor having a gate electrode, a source electrode, and a drain electrode connected to the gate line, the data line, and the pixel electrode; A redundant data line formed to overlap the data line; A liquid crystal including a layer made of at least amorphous silicon between the common electrode and the data line or the redundant data line adjacent to the data line and the redundant data line and between the common electrode and the data line or the redundant data line Display device. In claim 1, A data pad formed at an end of the data line, Further comprising a redundant data pad made of a conductive material layer, such as the redundant data line, And the data pad and the redundant data pad are in contact with each other. In claim 2, And a layer in contact with a driver among the data pad and the redundant data pad is made of ITO. In claim 1, A gate pad formed at an end of the gate line, And a redundant gate pad formed of the same metal layer as the data line or the redundant data line and electrically connected to the gate pad. In claim 4, The layer connected to the driver among the gate pad and the redundant gate pad is made of ITO. In claim 1, And at least one of the data line and the redundant data line is formed of the same layer as the pixel electrode. In claim 6, The pixel electrode has a thickness of more than 0 and less than 1,000 GPa. Board, A gate line formed on the substrate in a horizontal direction and a gate electrode connected to the gate line; A plurality of linear common electrodes on the substrate, the plurality of linear common electrodes being separated from the gate lines and formed in the pixel region; A gate insulating film covering the gate line, the gate electrode, and the common electrode, A semiconductor layer formed on the gate insulating film on the gate electrode, An ohmic contact layer formed on both sides of the gate electrode on the semiconductor layer; A light blocking film formed on a boundary of the pixel region on the gate insulating layer, overlapping with the common electrode, and formed of amorphous silicon; Source and drain electrodes respectively formed on the ohmic contact layer; A data line formed on the gate insulating layer and connected to the source electrode and defining the pixel area by crossing the gate line; A linear pixel electrode formed alternately with the common electrode on the gate insulating layer and connected to the drain electrode; And a redundant data line formed along the data line and covering the data line. In claim 8, A data pad formed at an end of the data line, And a redundant data pad formed at an end of the redundant data line. And the data pad and the redundant data pad are connected to each other. In claim 9, And the redundant data line and the redundant data pad include a double layer of a lower layer made of ITO and an upper layer made of molybdenum, molybdenum alloy, aluminum, or aluminum alloy. In claim 8, A gate pad formed at an end of the gate line, And a redundant gate pad made of a metal layer such as the data line or the redundant data line. And the gate insulating layer has a first contact hole exposing the gate pad so that the gate pad and the redundant gate pad are electrically connected to each other through the first contact hole. In claim 11, The redundant gate pad may include a double layer of a lower layer made of ITO and an upper layer made of molybdenum, molybdenum alloy, aluminum, or aluminum alloy. The method of claim 10 or 12, And a passivation layer covering the redundant data line, the redundant data pad, and the redundant gate pad. The passivation layer has second and third contact holes exposing the redundant data pad and the redundant gate pad. In claim 13, And the ITO lower layers of the redundancy gate and the data pad are exposed to the second and third contact holes, respectively. In claim 8, The pixel electrode has a thickness of more than 0 and less than 1,000 GPa. Forming a gate wiring including a gate line, a gate electrode, a gate pad, and a gate line connecting portion on the substrate and a common wiring including a common electrode line and a common electrode, Forming a gate insulating film covering the gate wiring and the common wiring; Stacking an amorphous silicon layer and a doped amorphous silicon layer on the gate insulating film, Patterning the doped amorphous silicon layer and the amorphous silicon layer to form a semiconductor layer, an ohmic contact layer, and a dummy amorphous silicon layer, Patterning the gate insulating film to expose the gate pad, Forming a data line including a source and drain electrode, a data line, a data pad, and a data line connecting portion, a pixel electrode, and a first redundant gate pad as a first conductive layer; Forming a redundant data line including a redundant data line over the data line, a redundant data pad over the data pad, and a redundant data line connection part as a second conductive layer, and a second redundant gate pad over the first redundant gate pad. step, Depositing a protective film on the first and second conductive layers, Exposing the redundant data pad and the second redundant gate pad to the passivation layer, respectively. Substrate manufacturing method for a liquid crystal display device comprising a. The method of claim 16, And exposing the gate line connection part to expose the gate pad. The method of claim 17, The pixel electrode is a substrate manufacturing method for a liquid crystal display device formed to be more than 0 to 1,000 kHz. The method of claim 18, The second conductive layer is formed of a lower layer made of ITO and an upper layer made of molybdenum, molybdenum alloy or aluminum, aluminum alloy, Exposing the redundant data pad and the second redundant gate pad, respectively, exposing the ITO underlayer.