JPH06268222A - Liquid crystal display device and manufacture thereof - Google Patents

Abstract

PURPOSE:To prevent the breaking of wire caused by the adhesion of foreign substance and the residue of resist by a method wherein a laminated structure consisting of three or more layers of a plurality of materials having a high selectivity ratio of etching method with each other. CONSTITUTION:After formation of a scanning wiring and a gate electrode 2 on an insulated substrate 1, an insulating layer 7 and semiconductor layers 8 and 9 are deposited, the first layer of conductive material is deposited on the semiconductor layers 8 and 9 without conducting a photoetching process, and a photoetching treatment is conducted. Then, the insulating layer 7, on the lower part of the first conductive layer 13, and the semiconductor layers 8 and 9 are etched using the first layer of conductive layer 13 as a mask. Then, the second layer of conductive material is deposited on the upper part of the first conductive layer 13, and the second conductive layer 14 only is photoetched. Besides, the third layer of conductive material 15 only is photoetched. In other words, the deposition of a conductive material and a photoetching process are repeated, and a signal wire consisting of a three or more layer structure is obtained.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film semiconductor device,
In particular, the structure of signal wiring, drain electrode and source electrode used in an active matrix liquid crystal display device,
And the manufacturing method thereof.

[0002]

2. Description of the Related Art Currently, the signal wiring of mass-produced thin film transistor liquid crystal display devices (hereinafter referred to as TFT-LCD) includes
A single layer structure mainly composed of metals such as Cr, Ti and Al,
Alternatively, a two-layer structure of Mo / Al, Cr / Al or the like is adopted. The signal wiring having a two-layer structure is considered in terms of prevention of disconnection due to strengthening of wiring, low resistivity, adhesion to an indium oxide (hereinafter referred to as ITO) film which is a display pixel electrode, and the like. Conventionally, in order to form such a two-layer signal wiring, in the case of a thin film transistor (hereinafter referred to as TFT) having an inverted stagger structure, the following method is used. First, a scanning wiring and a gate electrode are formed on an insulating substrate by a sputtering method and a photo-etching step, and a CVD method and a photo-etching step are repeated thereon to pattern an insulating layer and a semiconductor layer, and then a signal wiring, a drain electrode and a source. Each conductive material that constitutes the main composition of each layer of the electrode, that is, Mo and C mentioned above
metals such as r and Al are continuously deposited by the sputtering method,
After patterning the photoresist, each metal layer is separately or collectively etched with an etching solution for each metal, and then the photoresist is removed to form a desired pattern. At this time, it is obvious that further strengthening of the wiring and improvement of reliability can be expected if the signal wiring is not limited to two layers and is further multilayered.

By the way, the TFT-LCD is a very expensive display device at present, but the reason therefor is that the manufacturing process usually includes 6 to 8 times of photoetching process, and the manufacturing yield is low. Therefore,
To reduce the price of TFT-LCD, it is essential to simplify the manufacturing process and improve the manufacturing yield. If attention is paid only to the yield reduction, the cause is the disconnection of the signal wiring. The disconnection of the signal wiring is mainly divided into a disconnection due to the step shape of the pattern formed in the process before the wiring metal deposition, a foreign matter such as dust adhered, and a disconnection due to the lack of photoresist. The former is a technical factor, and is a factor that can be dealt with by optimizing the process design conditions, such as relaxing the taper angle of the step, reducing the step, and increasing the metal film thickness deposited on the step. is there. On the other hand, the latter is a force majeure factor due to the cleanliness of the clean room,
In order to prevent the latter from disconnecting the signal wiring, at present,
The width of the signal wiring is widened so that even if the signal wiring pattern is etched and lost due to adhesion of foreign matter or lack of photoresist, a part of the wiring is barely left.

[0004]

However, in designing a high-definition liquid crystal display device, improvement of the aperture ratio is one of the important issues, and as the pixel pitch becomes higher, the rate of occurrence of wire breakage is reduced as in the conventional case. It is a design problem to keep the signal wiring width wide in order to reduce the width.

Inverse stagger structure TFT-LC by the conventional method
When D is manufactured, the mechanism of wire breakage due to the adhesion of foreign matter and the lack of photoresist is as follows.

First, one or two photo-etching steps are required to form an insulating layer, a semiconductor layer and an impurity semiconductor layer before depositing a conductive material forming the signal wiring, the drain electrode and the source electrode. Therefore, it is highly possible that foreign matter such as dust adheres to the substrate surface. When the adhered portion of the foreign matter corresponds to the formation place of the signal wiring, the drain electrode, and the source electrode, the conductive material is deposited on the upper portion of the foreign matter, it is difficult to remove the foreign matter in the subsequent etching step, and unevenness occurs on the surface. If the foreign matter is extremely thicker than the thickness of the conductive layer, the conductive layer is pierced through, and even if the second and third conductive materials are deposited on the conductive layer, the step caused by the foreign matter is caused by the second and third layers. Since the eyes cannot be covered, the wiring breaks.

Secondly, after the signal wiring conductive material is deposited, adhesion of foreign matter and missing of the photoresist pattern in the photoresist patterning step cannot be stochastically avoided because the cleanliness of the clean room is limited. In this case, even the conductive layer in the portion where the photoresist is missing during the etching of the conductive layer is etched, and the wiring is broken.

Therefore, an object of the present invention is to suppress the signal wiring width to a necessary minimum and increase the number of photo-etching steps to use the conductive material used in the conventional process, to attach foreign matters and resist residue. This is to prevent disconnection of the signal wiring due to.

[0009]

According to the present invention, a signal wiring, a drain electrode and a source electrode of a liquid crystal display device having an inverted staggered structure TFT as a switching element have a layered structure of three or more layers to form a layered structure. In selecting more than one kind of conductive material, each conductive material should have a high etching selection ratio with respect to other conductive materials.

In forming the above-mentioned layer structure, after forming the scanning wiring and the gate electrode on the insulating substrate, the insulating layer and the semiconductor layer are deposited, and the photo-etching step is not performed. The conductive material of the first layer is deposited by the sputtering method and photoetched. Next, the insulating layer and the semiconductor layer under the first conductive layer are etched using the first conductive layer as a mask. Next, a second layer is formed on the first conductive layer.
A conductive material for the second layer is deposited and only the second conductive layer is photoetched. Further, a third layer conductive material is deposited on the second conductive layer, and only the third conductive layer is photoetched. That is, the steps of depositing the conductive material and photo-etching are repeated,
The signal wiring having a layered structure of three layers or more is obtained.

For etching the insulating layer and the semiconductor layer,
After patterning the second conductive layer, the second layer may be used as a mask.

[0012]

According to the present invention, since the photo-etching step of the insulating layer and the semiconductor layer before the deposition of the conductive material of the signal wiring, the drain electrode and the source electrode is omitted, the foreign matter adhering to the surface of the substrate before the deposition of the conductive material is eliminated. The amount can be reduced. Therefore, it is possible to suppress the occurrence of irregularities on the surface of the conductive layer and the breakage of the conductive layer due to the adhesion of foreign matter, and to prevent the disconnection of the wiring.

As a second function, it is possible to prevent the disconnection of the wiring due to the lack of photoresist which occurs during the photo etching of the signal wiring, the drain electrode and the source electrode. This is because it is extremely unlikely that the same portion of each conductive layer pattern of the signal wiring, the drain electrode and the source electrode will be broken. Therefore, if the second conductive layer is deposited after photoetching the first conductive layer, Since the generated disconnection portion is covered by the second layer, the disconnection of the first layer can be relieved. Moreover, when the second layer is etched due to the lack of the photoresist of the second conductive layer, a disconnection occurs, and the first layer is exposed to the etching solution of the second conductive layer that has penetrated from the disconnection portion. Since the etching selectivity of the eye is high, the wiring is not broken because the first layer is not etched. Furthermore, even if a disconnection occurs at the same location of the first and second conductive layers, the third conductive layer can repair the disconnection as described above. Further, since the etching solution for the third conductive layer has a high selection ratio with respect to the first and second layers, the wiring in the lower layer is not etched and is not broken. Therefore, according to the multilayer signal wiring manufacturing method of the present invention,
The occurrence of wire breakage is extremely low because wire breakage occurs only when foreign matter adheres to the same location and the photoresist is lost during the layer formation process.

As a third action, in the present invention, a photo-etching step is required to form the signal wiring, the drain electrode and the source electrode by the number of layers constituting the wiring.
Although it is more complicated than the conventional manufacturing method if only the manufacturing of the wiring is considered, the photo-etching process of the insulating layer and the semiconductor layer can be reduced by patterning the insulating layer and the semiconductor layer using the wiring layer as a mask. The total number of manufacturing processes does not increase.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT An embodiment of the present invention is shown in FIG. Figure 1
FIG. 2A is an enlarged plan view and a sectional view of a TFT of a substrate on which a switching element array of a liquid crystal display device is formed. In FIG. 1, 1 is an insulating substrate, 2 is a scanning wiring and a gate electrode portion, 3 is an anodized film which is an insulating layer, 4 is a signal wiring and drain electrode portion, 5 is a source electrode portion, and 6 is a display pixel electrode. Part, 7 is an insulating layer, 8 is a semiconductor layer, 9 is an n-type semiconductor layer, 1
Reference numeral 0 is the signal wiring and drain electrode first conductive layer, 11 is the same second conductive layer, 12 is the same third conductive layer, 13 is the source electrode first conductive layer, 14 is the same second conductive layer, and 15 is the same. Similarly, it is the third conductive layer.

A method of manufacturing the TFT of the present invention will be described with reference to FIG. FIG. 5 is a cross-sectional view taken along the line CC ′ of FIG. 1, showing the TFT cross-sectional shape in each step.

A scanning wiring and a gate electrode 2 are formed by depositing a conductive material containing Al as a main component on the insulating substrate 1 by a sputtering method and performing a photoetching process (FIG. 5).
(A)). By the anodization method, except the scanning wiring terminal part,
An Al ₂ O ₃ film 3 is formed on the wiring surface (FIG. 5B). C
The insulating layer SiN7, the semiconductor layer amorphous silicon (hereinafter a-Si) 8, and the n + amorphous silicon (hereinafter n + a-Si) layer 9 are successively deposited by the VD method or the like. Subsequently, the source electrode first conductive layer 13 is deposited by the sputtering method (FIG. 5C). After the first conductive layer 13 is formed into a desired pattern by a photo-etching process, the first conductive layer 13 is used as a mask to dry the SiN7, a-Si film or the like.
8 and n + a-Si9 are collectively etched (FIG. 5).
(D)). The source electrode second conductive layer 14 is formed by the sputtering method.
Are deposited (FIG. 5E). A pattern is formed by the photoetching process so that the second conductive layer 14 covers only the upper part of the first conductive layer 13 or the upper part and the side wall part (FIG. 5F). The source electrode third conductive layer 15 is deposited by the sputtering method (FIG. 5G). By the photo-etching process, the third conductive layer 15 is formed only on the upper part of the second conductive layer 15,
Alternatively, a pattern is formed so as to cover the upper portion and the side wall portion (FIG. 5 (h)). Second conductive layer 14, third conductive layer 15
Is used as a mask to etch the first conductive layer 13 above the gate electrode, and then using the first conductive layer 13, the second conductive layer 14 and the third conductive layer 15 as a mask, n + a above the gate electrode is used as a mask.
-Si9 is etched to separate n + a-Si9 into a drain side and a source side.

The second manufacturing method of the present invention is shown in FIG. 6A to 6C are the same as FIG. In FIG. 6, after patterning the first conductive layer 13 (FIG. 6D),
The second conductive layer 14 is deposited without etching n + a-Si9, a-Si8 and SiN7 (FIG. 6).
(E)). After patterning the second conductive layer 14, n + a-Si9, a-Si8 and SiN7 are etched using the second conductive layer 14 as a mask (FIG. 6 (f)). After that,
Depositing the third conductive layer 15 (FIG. 6G), the third conductive layer 15
By photo-etching (FIG. 6 (h)), using the third conductive layer as a mask, the second conductive layer 14, the first conductive layer 13, and n + a-Si.
9 is etched (FIG. 6 (i)).

Next, a method for preventing disconnection of signal wiring according to the present invention will be described with reference to FIG. FIG. 7 shows DD ′ of FIG.
The cross section shows the cross-sectional shape of the signal wiring in each step. As described in the method of manufacturing a thin film transistor, SiN7, a-Si8, n + a-Si are formed after forming the scanning wiring, the gate electrode 2, and the anodized film 3 on the insulating substrate 1.
9, signal wiring and drain electrode first conductive layer 10 is deposited (FIG. 7A). Here, since there is no photo-etching step of SiN 7, a-Si 8 and n + a-Si 9 before the deposition of the first conductive layer 10, the probability that foreign matter will adhere to the substrate surface is low. Therefore, the surface of the first conductive layer 10 is flat and is unlikely to be pierced by foreign matter. A photoresist is coated on the first conductive layer 10, and a desired photoresist pattern 16 is formed through a developing process. At this time, a missing portion is formed in the photoresist pattern 16 due to adhesion of foreign matter such as dust (FIG. 7).
(B)). In the etching process of the first conductive layer 10, the etching liquid penetrates through this missing portion, causing a disconnection in the first conductive layer 10 (FIG. 7C). When the signal wiring and the drain electrode second conductive layer 11 are deposited on this, a step is formed,
The second conductive layer 11 is also embedded in the disconnection portion of the first conductive layer 10 to relieve the disconnection of the wiring (FIG. 7D). A photoresist pattern 16 is formed on the second conductive layer 11 by applying a photoresist and a developing process, but a missing portion is formed as in the first layer (FIG. 7E). In the etching process of the second conductive layer 11, the etching liquid penetrates from the missing portion of the photoresist pattern 16 to cause a disconnection in the second conductive layer 11. At this time, the etching liquid penetrates into the first conductive layer 10 through the disconnection portion of the second conductive layer, but the disconnection does not occur in the first conductive layer 10 because the selectivity of the etching liquid is high (FIG. 7 (f)). Therefore, the disconnection of the signal wiring does not occur unless the disconnection portions of the first layer and the second layer match. Even if the disconnection portions of the first layer and the second layer coincide with each other, the signal wiring and the drain electrode third conductive layer 12 that are subsequently deposited are buried in the disconnection portion, and the disconnection can be repaired (FIG. 7 (g)). . Although the photoresist pattern of the third conductive layer 12 has a missing portion (see FIG. 7).
(H)), because the etching liquid has a high selectivity,
The layers are not etched. The first layer, the second layer and the third layer
The probability that the disconnection portions of the layers will coincide is extremely low. Therefore,
The disconnection due to the lack of photoresist generated in each layer can be repaired in another layer, and the possibility of disconnection is almost eliminated when viewed as the entire signal wiring.

In the above method, a plurality of conductive materials having different etching liquid selection ratios, such as Cr and A, are used.
l, ITO is used. In this case, the second cerium ammonium nitrate is used as Cr, the mixed solution of phosphoric acid, nitric acid and acetic acid is used as Al, and the mixed solution of hydrochloric acid, nitric acid and water is used as ITO for the etching solution. As the combination of layers, the first layer is A
When the first layer is Cr, the second layer is Cr, and the third layer is ITO, the first layer may be Cr, the second layer is Al, and the third layer is ITO.

FIG. 2 shows a second embodiment manufactured by the above method, which is a sectional structure of a signal wire and a source electrode.

FIG. 3 shows a third embodiment, in which, in the multilayer structure, the metal of the upper layer covers the surface and the side wall of the metal of the lower layer in consideration of the adhesiveness of each metal layer.

FIG. 4 shows a fourth embodiment, in which the signal wiring and the source electrode have a multilayer structure of four layers. In this case, considering the adhesion with the ITO film, the first conductive layer 1
0, 13 is Cr, second conductive layers 11, 12 are ITO, third
Cr for the conductive layers 12, 15 and Al for the fourth conductive layers 17, 18
To use. Further, it is possible in principle to increase the number of layers, but since the photoetching step is required by the number of layers, up to four layers are practical considering the manufacturing cost and throughput.

[0024]

According to the present invention, in a liquid crystal display device, adhesion of foreign matter,
It is possible to prevent disconnection of the signal wiring due to the lack of the photoresist, and it is possible to improve the manufacturing yield.

[Brief description of drawings]

1A and 1B are a plan view and a cross-sectional view of a thin film transistor of the present invention.

FIG. 2 is a diagram showing a second embodiment of the multilayer wiring structure of the present invention.

FIG. 3 is a diagram similarly showing a third embodiment.

FIG. 4 is a diagram similarly showing Example 4.

FIG. 5 is a diagram showing a method of manufacturing a thin film transistor according to the present invention.

FIG. 6 is a diagram showing a method 2 for manufacturing a thin film transistor according to the present invention.

FIG. 7 is a diagram showing a method for manufacturing a multilayer wiring for explaining the effect of the present invention.

[Explanation of symbols]

1 ... Insulating substrate, 2 ... Scan wiring and gate electrode, 3 ... Signal wiring and drain electrode, 4 ... Insulating layer, 5 ... Semiconductor layer,
6 ... Source electrode, 7 ... Display electrode, 8 ... Anodized film formation, 9 ...
n-type semiconductor layer, 10 ... Signal wiring and drain electrode first conductive layer, 11 ... Signal wiring and drain electrode second conductive layer, 1
2 ... Signal wiring and drain electrode third conductive layer, 13 ... Source electrode first conductive layer, 14 ... Source electrode second conductive layer, 15
Source electrode third conductive layer 16, photoresist pattern 17, signal wiring and drain electrode fourth conductive layer 18,
... Source electrode fourth conductive layer.

Claims (4)

[Claims] 1. A structure of a liquid crystal display device comprising a plurality of scanning wirings and signal wirings arranged on an insulating substrate, and a thin film transistor serving as a switching element and a display pixel electrode near an intersection of the scanning wirings and the signal wirings. In the above, the signal wiring and the drain electrode, and the source electrode for supplying signal data from the thin film transistor to the display pixel electrode have a laminated structure of three or more layers made of a plurality of conductive materials having a high etching method selection ratio. Characteristic liquid crystal display device. 2. The process of depositing a conductive material composing each layer, applying photoresist, patterning photoresist, etching, and removing photoresist for each layer in the laminated structure of the signal wiring, the drain electrode, and the source electrode according to claim 1. A method of manufacturing a liquid crystal display device, which comprises repeatedly forming a laminated structure of three or more layers. 3. The liquid crystal display device according to claim 1, wherein a semiconductor layer, an insulating layer, and a gate electrode are located below the signal line, the drain electrode, and the source electrode.
After depositing the insulating layer and the semiconductor layer, subsequently depositing a conductive layer that constitutes the signal wiring, the drain electrode, and the source electrode, and after photoetching, using the conductive layer as a mask,
A method for manufacturing a liquid crystal display device, which comprises etching the semiconductor layer and the insulating layer below. 4. The layer structure of three or more layers of the signal wiring, the drain electrode and the source electrode according to claim 1, wherein the layer formed on the upper side covers the surface and the side wall of the layer formed on the lower side. A liquid crystal display device characterized by being formed in.