KR20010056591A - Liquid crystal display and method for fabricating the same - Google Patents

Abstract

PURPOSE: A liquid crystal display device and a manufacturing method thereof are provided to reduce the time of manufacturing by reducing the number of mask process times, to prevent the deterioration of productivity due to mis-alignment, and to prevent the breakage of an insulation film. CONSTITUTION: The liquid crystal display device having a horizontal gate line(102), a vertical data line(120), and a pixel area additionally comprises a thin film transistor(110), a pixel electrode(118), and an anti-short circuit part(160). The thin film transistor consists of a gate electrode formed in the last gate line, a source electrode(112) projected from the last data line to overlap a part of the gate electrode, and a drain electrode(114) disposed to correspond to the source electrode. The pixel electrode contacts with the drain electrode of the thin film transistor, and overlaps the last gate line. The anti-short circuit part is formed in an overlapped portion between the last gate line and the pixel electrode. Since a capacitor electrode(150) is formed in a projection of the pixel electrode, thereby the anti-short circuit part prevents the short circuit between the gate line and the capacitor electrode. By adopting the anti-short circuit part, only four times of mask process is required in the manufacturing method for the liquid crystal display device.

Description

Liquid crystal display device manufacturing method and a liquid crystal display device according to the manufacturing method {Liquid crystal display and method for fabricating the same}

The present invention relates to an image display device, and more particularly, to a manufacturing method of a liquid crystal display (LCD) including a thin film transistor (TFT) and a liquid crystal display device according to the manufacturing method. will be.

In particular, the present invention relates to a method of manufacturing by reducing the number of masks used in manufacturing a liquid crystal display, and a liquid crystal display manufactured by the method.

The driving principle of the liquid crystal display device uses the optical anisotropy and polarization property of the liquid crystal. Since the liquid crystal is thin and long in structure, the liquid crystal has directivity in the arrangement of molecules, and the direction of the molecular arrangement can be controlled by artificially applying an electric field to the liquid crystal.

Accordingly, when the molecular arrangement direction of the liquid crystal is arbitrarily adjusted, the molecular arrangement of the liquid crystal is changed, and light is refracted in the molecular arrangement direction of the liquid crystal due to optical anisotropy to express image information.

Currently, the active matrix liquid crystal display (AM-LCD) in which the above-described thin film transistor and pixel electrodes connected to the thin film transistor are arranged in a matrix manner has attracted the most attention due to its excellent resolution and ability to implement video.

In general, the structure of a liquid crystal panel, which is a basic component of a liquid crystal display, will be described.

1 is a cross-sectional view showing a cross section of a general liquid crystal panel.

In the liquid crystal panel 20, two substrates 2 and 4 having various kinds of elements are formed to correspond to each other, and the liquid crystal layer 10 is interposed between the two substrates 2 and 4. .

The liquid crystal panel 20 includes an upper substrate 4 having a color filter representing a color and a lower substrate 2 having a switching circuit capable of converting a molecular arrangement direction of the liquid crystal layer 10.

The upper substrate 4 includes a color filter layer 8 for implementing colors and a common electrode 12 covering the color filter layer 8. The common electrode 12 serves as one electrode for applying a voltage to the liquid crystal 10. The lower substrate 2 has a thin film transistor S serving as a switching function and a pixel electrode 14 serving as an electrode for receiving a signal from the thin film transistor S and applying a voltage to the liquid crystal 10. It is composed of

The portion where the pixel electrode 14 is formed is called the pixel portion P. FIG.

In order to prevent leakage of the liquid crystal 10 injected between the upper substrate 4 and the lower substrate 2, sealants (sealant) is formed at the edges of the upper substrate 4 and the lower substrate 2. It is sealed with).

Referring to the operation and configuration of the lower substrate 2 in Figure 2 showing a plan view of the lower substrate 2 shown in FIG. 1 as follows.

The pixel electrode 14 is formed on the lower substrate 2, and the data line 24 and the gate line 22 are formed in the vertical and horizontal alignment directions of the pixel electrode 14, respectively.

In the active matrix liquid crystal display device, a thin film transistor S, which is a switching element for applying a voltage to the pixel electrode 14, is formed at one portion of the pixel electrode 14. The thin film transistor S includes a gate electrode 26, source and drain electrodes 28 and 30, and a portion of the gate wire 22 defines a portion of the gate electrode 26, and the source electrode 28. ) Is connected to the data line 24.

In addition, data pads 23 and gate pads 21 are formed at one ends of the data line 24 and the gate line 22, respectively, to drive the thin film transistor S and the pixel electrode 14, respectively. It is connected to a driving circuit (not shown).

The drain electrode 30 is electrically connected to the pixel electrode 14 through the drain contact hole 30 ′.

In addition, a storage capacitor C _st is formed in a portion of the gate line 22 to store charge together with the pixel electrode 14.

The operation of the active matrix liquid crystal display device described above is as follows.

When a voltage is applied to the gate electrode 26 of the switching thin film transistor S, the data signal is applied to the pixel electrode 14, and when the signal is not applied to the gate electrode 26, the voltage is applied to the pixel electrode 14. This is not authorized.

The manufacturing process of the liquid crystal panel constituting the liquid crystal display device is a complex process of several complex steps. In particular, the lower substrate on which the thin film transistor S is formed must go through several mask processes.

The performance of the final product is determined by this complex manufacturing process. Preferably, the simpler the process, the less likely it is that defects will occur. That is, since a number of major elements that determine the performance of the liquid crystal display are formed on the lower substrate, the manufacturing process should be simplified.

In general, the manufacturing process of the lower substrate is often determined by what material is used for each device to be made or designed according to the specification.

For example, in the past, a small liquid crystal display was not a problem, but in the case of a large area liquid crystal display of 12 inches or more, the resistivity value of the material used for the gate wiring is an important factor in determining the superiority of the image quality. Therefore, in the case of a large area liquid crystal display element, it is preferable to use a metal with low resistance, such as aluminum or an aluminum alloy.

In general, the structure of a thin film transistor used in a liquid crystal display is an inverted staggered structure. This is because the structure is simple and the performance is excellent.

In addition, the reverse staggered thin film transistor is divided into a back channel etch type (EB) and an etch stopper type (ES) according to a channel forming method, and a simple back channel etch type structure is applied. The liquid crystal display device manufacturing process will be described.

Hereinafter, a manufacturing process of a conventional active matrix liquid crystal display device will be described with reference to FIGS. 3A to 3E. 3A to 3E are cross-sectional views taken along cut lines A-A and B-B of FIG. 2 for ease of description.

First, a foreign material or an organic material is removed from the substrate 1, and the metal film is deposited by sputtering after cleaning to improve the adhesion between the metal film of the gate material to be deposited and the glass substrate. .

3A is a step of forming a gate electrode 26 and a capacitor first electrode 22 by patterning with a first mask after the metal film deposition. The gate electrode 26 material, which is important for the operation of the active matrix liquid crystal display, is mainly composed of aluminum having low resistance to reduce the RC delay, but pure aluminum has low chemical resistance to corrosion and is healed in subsequent high temperature processes. Since wiring defects are caused by the formation of a hillock, an aluminum wiring may be used in the form of an alloy or a laminate structure may be applied. The gate electrode 26 and the capacitor first electrode 22 may have the same pattern. And a part corresponding to the gate wiring, and is functionally referred to as the gate electrode 26 and the capacitor first electrode 22.

Next, referring to FIG. 3B, after forming the gate electrode 26 and the capacitor first electrode 22, an insulating film 50 is deposited over the top and the entire exposed substrate. In addition, amorphous silicon (a-Si: H: 52), which is a semiconductor material, and amorphous silicon (n ⁺ a-Si: H: 54) containing impurities are deposited on the gate insulating film 50 in succession.

After the semiconductor material is deposited, the semiconductor layer is patterned with a second mask to form an active layer 55 and a semiconductor island 53 having the same shape as the active layer.

The amorphous silicon 54 containing the impurity is to reduce the contact resistance between the metal layer to be formed later and the active layer 55.

Thereafter, as shown in FIG. 3C, a metal layer is deposited and patterned with a third mask to form a source electrode 28 and a drain electrode 30. The data line 24 connected to the source electrode 28 is formed at the same time as the source and drain electrodes 28 and 30.

In addition, the capacitor second electrode 58 is formed on the capacitor first electrode 22 so as to overlap with a portion of the capacitor first electrode 22. In other words, the data line 24, the source electrode 28, the drain electrode 30, and the capacitor second electrode 58 are formed in the third mask process.

The ohmic contact layer existing between the source electrode 28 and the drain electrode 30 is removed using the source and drain electrodes 28 and 30 as a mask. If the ohmic contact layer between the source electrode 28 and the drain electrode 30 is not removed, a serious problem may occur in the electrical characteristics of the thin film transistor S, and a great problem may occur in performance.

Careful attention is required to removing the ohmic contact layer. In actual etching of the ohmic contact layer, since there is no etch selectivity with the active layer formed thereunder, the active layer is overetched by about 50 to 100 nm. Etching uniformity directly affects the characteristics of the thin film transistor S. Crazy

Thereafter, as shown in FIG. 3D, an insulating film is deposited and patterned with a fourth mask to form a protective film 56 to protect the active layer 55. The passivation layer 56 may adversely affect the characteristics of the thin film transistor due to the unstable energy state of the active layer 55 and the residual material generated during etching, so that the inorganic silicon nitride layer (SiN _x ) or silicon oxide layer (SiO ₂ ) It is formed of organic BCB (Benzocyclobutene).

The passivation layer 56 requires high light transmittance, properties of a moisture resistant and durable material.

A process of forming a contact hole during patterning of the passivation layer 56 is added. The data pad contact hole 23, the drain contact hole 30 ′, and the storage contact hole 58 ′ are respectively formed.

The data pad contact hole 23 is for contact between the transparent conductive film to be formed in a later process and the data line 42. The drain contact hole 30 ′ and the storage contact hole 58 ′ are pixel electrodes. For contact with

The process illustrated in FIG. 3E is a process of forming a pixel electrode 14 by depositing a transparent conductive oxide (TCO) and patterning it with a fifth mask. ITO (Indium Tin Oxide) is mainly used as the transparent conductive material. The pixel electrode 14 is in contact with the capacitor second electrode 58 and is in electrical contact with the drain electrode 30 through the drain contact hole 30 ′.

By the above-described process, the thin film transistor substrate of the liquid crystal display device is completed.

4 is a flowchart illustrating a manufacturing process of FIGS. 3A to 3E.

ST200 uses a glass substrate (1) to prepare a substrate. In addition, the process of cleaning the glass substrate 1 is included. Cleaning is aimed at enhancing the adhesion of the thin film to be deposited and improving the characteristics of the thin film transistor, in addition to the basic concept of removing impurities and particles in the substrate or film surface during the initial process to prevent defects.

ST210 is a step of depositing a metal film, and is formed by depositing aluminum or molybdenum. Then, using a lithography technique, the gate electrode and the capacitor first electrode are formed so that the metal film has a tapered shape.

ST220 deposits an insulating film, amorphous silicon, and amorphous silicon containing impurities. The insulating film deposits a silicon nitride film or a silicon oxide film with a thickness of about 3000 Å. After deposition of the insulating film, an amorphous silicon film and an amorphous silicon film containing impurities are successively deposited.

ST230 is a step of depositing and patterning a metal such as chromium or chromium alloy to form a source electrode and a drain electrode.

ST240 is a step of forming a channel by removing the impurity semiconductor layer using the source and drain electrodes formed in ST230 as a mask.

ST250 is a step of forming a protective film for protecting the devices. The protective film is made of a material resistant to moisture or external impact. In the process, a contact hole is formed as a medium connected to each device.

ST260 is a step of forming a pixel electrode by depositing and patterning ITO with a transparent conductive electrode (TCO). Each pad electrode is formed in the above process.

The manufacturing method of the active matrix liquid crystal display described above is a five mask method used basically.

However, when the gate electrode is used as an aluminum-based metal (aluminum alloy) in the process of forming a thin film transistor, problems due to hillock on the aluminum surface may occur.

That is, referring to FIG. 5, which is an enlarged cross-sectional view of the Z portion (storage capacitor portion) of FIG. 3E, is as follows.

If the capacitor first electrode 22 is an aluminum metal, a hillock (H) may occur on the surface of the capacitor first electrode 22. The hillock H interferes with the growth of the insulating film 50 formed in a later process.

That is, the insulating film 50 of the portion where the hillock H is generated is abnormally grown. Accordingly, the capacitor second electrode 58 and the capacitor first electrode 22 formed on the abnormally grown insulating film 50 are shorted by the heel lock H, thereby causing defects. May occur.

Accordingly, at least two masks are needed because anodization process must be added to the capacitor first electrode to solve the problem caused by the hillock. Therefore, at least five to six mask processes are required to construct the thin film transistor substrate.

The mask process used in manufacturing a thin film transistor substrate used in a liquid crystal display device involves various processes such as cleaning, deposition, baking, and etching. Therefore, even if the mask process is shortened once, the manufacturing time is considerably reduced, which is advantageous in terms of production yield and manufacturing cost.

Accordingly, an object of the present invention is to provide a method for shortening the number of mask processes used in manufacturing a liquid crystal display device and to improve the production yield of a product.

1 is a cross-sectional view showing a cross section corresponding to one pixel portion of a general liquid crystal display device.

2 is a plan view illustrating a plane corresponding to one pixel part of a general liquid crystal display;

3A to 3E are process diagrams showing a process of cross sections along cut lines A-A and B-B of FIG.

4 is a flowchart showing a process of a general liquid crystal display.

5 is an enlarged view of a portion Z of FIG. 3E;

6 is a plan view illustrating a plane corresponding to the pixel portion of the liquid crystal display according to the exemplary embodiment of the present invention.

7A to 7D are process drawings showing the manufacturing process of the cross section along the cut line VIII-VIII of FIG.

Fig. 8A and Fig. 8B are cross-sectional views illustrating a cross section along cut line VIII-VIII in Fig. 6.

9 and 10 are plan views showing another example of the present invention.

<Explanation of symbols for the main parts of the drawings>

101: gate electrode 102: gate wiring

106: gate pad 107: gate pad electrode

108: gate pad contact hole 112: source electrode

114: drain electrode 118: pixel electrode

150 capacitor electrode 200 gate insulating film

202: active layer 122: protective film

In order to achieve the above object, the present invention includes N gate wirings formed in a horizontal direction, M data wirings formed while crossing the N gate wirings in a vertical direction, and the gate wirings and data wirings. A liquid crystal display comprising a pixel region composed of a matrix of x M, comprising: 1) a gate electrode formed on an n-th gate wiring, 2) a source electrode overlapping a predetermined area with the gate electrode, and protruding from the m-th data wiring; 3) an n x m th thin film transistor including a drain electrode formed in a direction corresponding to the source electrode; a (n + 1) xmth pixel electrode in contact with the drain electrode of the (n + 1) xmth thin film transistor and overlapping the nth gate wiring; An array substrate of a liquid crystal display device including a short circuit prevention part interposed in an overlapping portion of the (n + 1) × m-th pixel electrode and the n-th gate line is provided.

In the present invention, the substrate; A thin film transistor formed on the substrate, covered with a protective film, and having a gate wiring, a gate electrode defined in the gate wiring, a gate insulating film, an active layer, a source and a drain electrode; A pixel electrode in contact with a drain electrode of the thin film transistor and overlapping a portion of the gate wiring; A storage capacitor having the gate wiring as one electrode, the pixel electrode overlapping the gate wiring as another electrode, and a gate insulating film interposed between the gate wiring and the pixel electrode overlapping the gate wiring as a dielectric layer; An array substrate of a liquid crystal display device including an active layer formed in a stepped portion of a gate wiring overlapped with the pixel electrode and a protective film formed thereon is provided.

In addition, the present invention comprises the steps of providing a substrate; Depositing a first metal layer on the substrate and patterning with a first mask to form a gate wiring; A gate insulating film, a pure semiconductor layer, an impurity semiconductor layer, and a second metal layer are sequentially deposited over the entire surface of the substrate on which the gate wiring is formed, and patterned with a second mask to form data wirings, source and drain electrodes, and pixels to be formed later. Forming a short circuit prevention portion and a channel in a portion of the gate wiring to overlap with the electrode; Depositing an insulating film over the entire surface of the patterned second metal layer, covering the channel portion, the data line, the source and drain electrodes, and the short circuit prevention portion with a third mask, and having a drain contact hole exposing a portion of the drain electrode; Forming a protective film; Depositing a transparent conductive electrode over the entire surface of the substrate including the data line and the source and drain electrodes, and forming a storage capacitor so as to overlap the transparent conductive electrode with a gate wiring formed with the short circuit prevention portion using a fourth mask, and It provides a method of manufacturing an array substrate of a liquid crystal display device comprising the step of forming a pixel electrode to contact.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

6 is a plan view illustrating a plane of a liquid crystal display according to an exemplary embodiment of the present invention.

As shown in FIG. 6, the liquid crystal display according to the exemplary embodiment of the present invention includes a gate wiring 102 extending in one direction and a gate pad 106 formed at an edge of the gate wiring 102. do. The gate pad 106 is in contact with the gate pad electrode 107 covering the gate pad.

In addition, the data line 120 extends in a direction perpendicular to the gate line 102 extending in one direction, and a data pad 105 is formed at an edge of the data line 120. The data pad 105 is in contact with the data pad electrode 109 formed on the data pad 105.

In addition, at a predetermined position of the data line 120, a source electrode 112 protruding and extending from the data line 120 to a predetermined length is formed, and the drain electrode is spaced apart from the source electrode 112 at a predetermined interval. 114) is formed.

In addition, a gate electrode 101 sharing the function with the gate wiring 102 is formed in the gate wiring 102, and the thin film transistor is formed as the gate electrode 101 and the source and drain electrodes 112 and 114. 110 is configured.

A drain contact hole 116 is formed on the drain electrode 114 of the thin film transistor 110, and the pixel electrode 118 contacting the drain electrode 114 through the drain contact hole 116 is formed. Is formed.

In addition, a portion of the gate wiring 102 except for the portion where the thin film transistor 110 is formed, the capacitor electrode 150 extending from the pixel electrode 118 is formed, the capacitor electrode 150 and the gate wiring A short circuit prevention portion 160 is formed at an intersection portion of the 102 to prevent a short circuit between the gate wiring 102 and the capacitor electrode 150 in a cross-sectional structure.

In addition, the passivation layer 122 covers the data line 120 and the source and drain electrodes 112 and 114. The drain contact hole 116 is formed on the passivation layer 122 on the drain electrode 114.

In addition, the passivation layer 122 may be formed smaller than the width of the data line 120.

Hereinafter, a manufacturing process of the liquid crystal display according to the present invention of FIG. 6 will be described with reference to FIGS. 7A to 7D, which are process drawings of a cross section taken along the cutting line VII-Ⅶ of FIG. 6.

First, a manufacturing process of the liquid crystal display according to the present invention will be described in detail with reference to FIG. 7A.

7A illustrates the steps of depositing a first metal and forming a gate electrode 101 using a first mask.

As the first metal used to form the gate electrode 101, chromium (Cr), molybdenum (Mo), and the like, which are generally used, may be used. Preferably, an aluminum metal is used. The aluminum metal is aluminum-nedium (AlNd).

FIG. 7B is a diagram illustrating a step of forming the data line 120 and the source and drain electrodes 112 and 114.

That is, the gate insulating film 200, the semiconductor layer 202, and the second metal layer are sequentially deposited on the gate electrode 101 illustrated in FIG. 7A, and then patterned with a second mask to form the source electrode 112 and the second electrode. The drain electrode 114 is formed. Subsequently, a portion of the semiconductor layer 202 is etched using the patterned second metal layer as a mask to form a channel. The semiconductor layer 202 is formed of a stack of a pure semiconductor layer 202a and an impurity semiconductor layer 202b. Here, the semiconductor layer etched when the channel is formed becomes the impurity semiconductor layer 202b.

7C is a diagram illustrating a step of forming the protective film 122 as a third mask.

The passivation layer 122 covers the data line 120 and the source and drain electrodes 112 and 114. In this case, a drain contact hole 116 through which a portion of the drain electrode 114 is exposed is formed in the passivation layer 122.

Thereafter, as shown in FIG. 7D, the transparent electrode is deposited over the entire surface of the substrate 1 on which the passivation layer 122 is formed, and the pixel electrode 118 is formed by the fourth mask.

The pixel electrode 118 contacts the drain electrode 114 exposed through the drain contact hole 116.

FIG. 8A is a cross-sectional view taken along the line VII-VII of FIG. 6, and illustrates a cross-sectional view of the storage capacitor of the liquid crystal display according to the present invention.

As shown in FIG. 8A, the storage capacitor of the liquid crystal display according to the present invention uses the gate wiring 102 as one electrode and the capacitor electrode 150 extending from the pixel electrode 118 as the other electrode. do. The gate insulating film 200 formed on the gate wiring 102 is used as the dielectric layer.

Here, a short circuit prevention portion 160 is formed in the stepped portion T where the edge of the gate wiring and the capacitor electrode cross each other, thereby preventing a short circuit between the capacitor electrode 150 and the gate wiring 102.

The stepped portion T has a structure that is susceptible to stress unbalance of the gate wiring 102 and breakdown of the gate insulating layer 200.

In order to compensate for the structural shortcomings of the storage capacitor of the liquid crystal display manufactured by the weak four masks as described above, in the present invention, the short circuit prevention portion 160 is formed in the stepped portion T to overcome the structural defects.

The short circuit prevention unit 160 includes a semiconductor layer 202 made of pure semiconductor and impurity semiconductor, and a second metal layer 113 and a protective film 112 used to form the source and drain electrodes 112 and 114. .

Here, the second metal layer 113 may be removed from the structure of the short circuit prevention unit 160.

That is, when the short circuit prevention portion 160 is formed in such a manner that the second metal layer 113 is removed, the structure may be a stack of the pure semiconductor layer 202a and the protective film 112. The impurity semiconductor layer 202b does not exist here because the impurity semiconductor layer 202b is removed during channel formation (see FIG. 8B).

9 and 10 illustrate an example in which a short circuit prevention part is configured in another form in the storage capacitor part.

That is, as shown in FIG. 9, the short circuit prevention part 160 is not formed at the intersection of the gate wiring 102 and the capacitor electrode 150 but is formed at the overlapping part. As described above, when the short-circuit prevention portion 160 is randomly generated at a portion where the gate electrode 102 and the capacitor electrode 150 overlap each other, it may occur on the surface of the gate wiring 102 formed of aluminum-based metal. The breakdown of the gate insulating film due to hillock can be greatly reduced.

In FIG. 10, the short circuit prevention part 160 is formed over the stepped portions and the overlapping portions of the gate electrode 102 and the capacitor electrode 150. When the short circuit prevention unit 160 is formed as described above, defects due to insulation breakdown of the insulating layer due to the hillock generated on the stepped portion of the gate wiring 102 and the surface of the gate wiring 102 can be eliminated.

As described above, the liquid crystal display according to the exemplary embodiment of the present invention may be manufactured using only four masks.

In addition, a short circuit prevention portion is formed at a portion where the edge of the gate wiring intersects with the capacitor electrode to prevent a short circuit between the gate wiring and the capacitor electrode.

When the liquid crystal display is manufactured by the embodiments of the present invention described above has the following characteristics.

First, when the liquid crystal display device is manufactured by the method of manufacturing the liquid crystal display device according to the embodiments of the present invention, the manufacturing time is shortened because only four mask processes may be manufactured.

Second, since the thin film transistor substrate can be configured with four masks, it is possible to prevent a decrease in yield due to misalignment.

Third, there is an advantage of reducing the breakdown of the insulating film due to the heel lock that may be generated on the surface of the gate wiring in the storage capacitor unit by employing a short circuit prevention unit.

Claims (8)

N pixel wirings formed in a horizontal direction, M data wirings formed intersecting the N gate wirings in a vertical direction, and the gate wirings and data wirings, each pixel region including an N × M matrix. As a liquid crystal display device, 1) a gate electrode formed on the n-th gate wiring; 2) a source electrode overlapping the predetermined area with the gate electrode, and protruding and extending from the m-th data wiring; and 3) a drain electrode formed in a direction corresponding to the source electrode. An n x m th thin film transistor; a (n + 1) × m-th pixel electrode in contact with the drain electrode of the (n + 1) × m-th thin film transistor and overlapping the n-th gate wiring; A short circuit prevention portion interposed at an overlapping portion of the (n + 1) × m th pixel electrode and the n th gate wiring. Array substrate of a liquid crystal display comprising a. The method according to claim 1, The thin film transistor further includes a passivation layer formed thereon, wherein the drain electrode and the pixel electrode contact a portion of the passivation layer drain electrode formed on the thin film transistor through an exposed drain contact hole. Array substrate. The method according to claim 1, And the short circuit prevention portion is formed in a stepped portion of an n-th gate line and a (n + 1) × m-th pixel electrode. The method according to claim 1, And a plurality of short-circuit preventing portions formed in a portion where an n-th gate line and an (n + 1) x m-th pixel electrode overlap each other. The method according to claim 1, And the short circuit prevention portion is formed in the entire portion where the n-th gate wiring and the (n + 1) × m-th pixel electrode overlap. A substrate; A thin film transistor formed on the substrate, covered with a protective film, and having a gate wiring, a gate electrode defined in the gate wiring, a gate insulating film, an active layer, a source and a drain electrode; A pixel electrode in contact with the drain electrode of the thin film transistor and overlapping a part of the gate wiring at the front end or the rear end; A storage capacitor having the gate wiring as one electrode, the pixel electrode overlapping the gate wiring as another electrode, and a gate insulating film interposed between the gate wiring and the pixel electrode overlapping the gate wiring as a dielectric layer; A short circuit prevention portion comprising an active layer formed on a stepped portion of the gate wiring overlapping the pixel electrode and a protective film formed thereon Array substrate of a liquid crystal display comprising a. The method according to claim 6, And the short circuit prevention part further comprises the same metal as the source and drain electrodes interposed between the passivation layer and the active layer. Providing a substrate; Depositing a first metal layer on the substrate and patterning with a first mask to form a gate wiring; A gate insulating film, a pure semiconductor layer, an impurity semiconductor layer, and a second metal layer are sequentially deposited over the entire surface of the substrate on which the gate wiring is formed, and patterned with a second mask to form data wirings, source and drain electrodes, and pixels to be formed later. Forming a short circuit prevention portion and a channel in a portion of the gate wiring to overlap with the electrode; Depositing an insulating film over the entire surface of the patterned second metal layer, covering the channel portion, the data line, the source and drain electrodes, and the short circuit prevention portion with a third mask, and having a drain contact hole exposing a portion of the drain electrode; Forming a protective film; Depositing a transparent conductive electrode over the entire surface of the substrate including the data line and the source and drain electrodes, and forming a storage capacitor so as to overlap the transparent conductive electrode with a gate wiring formed with the short circuit prevention portion using a fourth mask, and Forming pixel electrodes to be in contact Array substrate manufacturing method of the liquid crystal display device comprising a.