KR100333270B1 - Liquid crystal display and method for fabricating the same - Google Patents

Abstract

The present invention provides a liquid crystal display device which receives an external signal and represents an image in order to reduce the manufacturing process of the liquid crystal display device, comprising: a substrate; A gate electrode and a gate wiring formed on the substrate in a two-layer structure of a transparent conductive material and an opaque metal; A pixel electrode spaced apart from the gate electrode at a predetermined interval and formed of the same layer and the same material as the transparent conductive material; A three-layer semiconductor layer formed of an insulating film, pure amorphous silicon, and amorphous silicon containing impurities and covering the gate electrode and the gate wiring; A source electrode formed on the three-layer semiconductor layer on the gate electrode and a drain electrode in contact with the pixel electrode; A first gate electrode is formed as a first storage electrode, and includes a second storage electrode on the first storage electrode, the second storage electrode being smaller than the gate wiring width, and formed between the first and second storage electrodes. Disclosed is a liquid crystal display including a storage capacitor including a dielectric layer having a cutting groove exposed at both edges of the first storage electrode.

Description

Liquid crystal display device manufacturing method and a liquid crystal display device according to the manufacturing method {Liquid crystal display and method for fabricating the same}

The present invention relates to an image display device, and more particularly, to a manufacturing method of a liquid crystal display (LCD) including a thin film transistor (TFT) and a liquid crystal display device according to the manufacturing method. will be.

In particular, the present invention relates to a method of manufacturing by reducing the number of masks used in manufacturing a liquid crystal display, and a liquid crystal display manufactured by the method.

The driving principle of the liquid crystal display device uses the optical anisotropy and polarization property of the liquid crystal. Since the liquid crystal is thin and long in structure, the liquid crystal has directivity in the arrangement of molecules, and the direction of the molecular arrangement can be controlled by artificially applying an electric field to the liquid crystal.

Accordingly, when the molecular arrangement direction of the liquid crystal is arbitrarily adjusted, the molecular arrangement of the liquid crystal is changed, and light is refracted in the molecular arrangement direction of the liquid crystal due to optical anisotropy to express image information.

Currently, the active matrix liquid crystal display (AM-LCD) in which the above-described thin film transistor and pixel electrodes connected to the thin film transistor are arranged in a matrix manner is attracting the most attention because of its excellent resolution and ability to implement video.

In general, the structure of a liquid crystal panel, which is a basic component of a liquid crystal display, will be described.

1 is a cross-sectional view showing a cross section of a general liquid crystal panel.

In the liquid crystal panel 20, two substrates 2 and 4 on which various kinds of elements are formed are attached to each other, and the liquid crystal layer 10 is sandwiched between the two substrates 2 and 4.

The liquid crystal panel 20 includes an upper substrate 4 having a color filter representing a color and a lower substrate 2 having a switching circuit capable of converting a molecular arrangement direction of the liquid crystal layer 10.

The upper substrate 4 has a color filter layer 8 that implements color, and a common electrode 12 covering the color filter layer 8. The common electrode 12 serves as one electrode for applying a voltage to the liquid crystal 10. The lower substrate 2 has a thin film transistor S serving as a switching function and a pixel electrode serving as an electrode that receives a signal from the thin film transistor S and applies a voltage to the liquid crystal 10. 14).

The portion where the pixel electrode 14 is formed is called the pixel portion P. FIG.

In order to prevent leakage of the liquid crystal 10 injected between the upper substrate 4 and the lower substrate 2, sealants are formed at edges of the upper substrate 4 and the lower substrate 2. It is sealed.

Referring to the operation and configuration of the lower substrate 2 in Figure 2 showing a plan view of the lower substrate 2 shown in FIG. 1 as follows.

The lower substrate 2 has pixel electrodes 14 formed thereon, and data lines and gate lines are formed in the vertical and horizontal alignment directions of the pixel electrodes 14, respectively.

In the active matrix liquid crystal display device, a thin film transistor S, which is a switching element for applying a voltage to the pixel electrode 14, is formed at one portion of the pixel electrode 14. The thin film transistor S includes a gate electrode 26, source and drain electrodes 28 and 30, the gate electrode 26 is connected to the gate line 22, and the data line 24. Is connected to.

The drain electrode 30 is electrically connected to the pixel electrode 14.

The operation of the active matrix liquid crystal display device described above is as follows.

When the switching thin film transistor is turned on to apply a data signal to the pixel electrode, and no signal is applied to the gate wiring 22, no voltage is applied to the pixel electrode.

The manufacturing process of the liquid crystal panel constituting the liquid crystal display device is a complex process of several complex steps. In particular, the lower substrate on which the thin film transistor is formed must go through several mask processes. The performance of the final product is determined by this complex manufacturing process. Preferably, the simpler the process, the less likely it is that defects will occur. That is, since a number of major elements that determine the performance of the liquid crystal display are formed on the lower substrate, the manufacturing process should be simplified. In general, the manufacturing process of the lower substrate is often determined by what material is used for each device to be made or designed according to the specification.

For example, in the past, a small liquid crystal display was not a problem, but in the case of a large area liquid crystal display of 12 inches or more, the intrinsic resistance of the material used for the gate wiring is an important factor in determining the superiority of the image quality. Therefore, in the case of a large area liquid crystal display element, it is preferable to use a metal with low resistance, such as aluminum or an aluminum alloy.

Hereinafter, a manufacturing process of a conventional active matrix liquid crystal display will be described in detail with reference to FIGS. 3A to 3E.

In general, the structure of a thin film transistor used in a liquid crystal display is an inverted staggered structure. This is because the structure is the simplest and the performance is excellent. In addition, the reverse staggered thin film transistor is divided into a back channel etch (EB) and an etch stopper (ES), and a process of manufacturing a liquid crystal display device having a back channel etch structure is described. do.

First, cleaning is performed to remove foreign matters or organic substances on the substrate 1 and to improve the adhesion between the metal thin film of the gate material to be deposited and the glass substrate, and then the metal film is deposited by sputtering.

3A is a step of forming a gate electrode 30 and a storage electrode 32 by patterning with a first mask after the deposition of the metal film. The gate electrode 30 material, which is important for the operation of the active matrix liquid crystal display, is mainly composed of aluminum having low resistance in order to reduce the RC delay, but pure aluminum has low chemical resistance to corrosion, and is healed in subsequent high temperature processes. In the case of aluminum wiring, it is used in the form of an alloy or a laminated structure is applied because it causes a wiring defect problem due to the formation of the hi-lock.

After the gate electrode 30 and the storage electrode 32 are formed, a gate insulating film 34 is deposited over the top and the entire exposed substrate. In addition, amorphous silicon (a-Si: H), which is a semiconductor material, and amorphous silicon (n ⁺ a-Si: H), which contains impurities, are sequentially deposited on the gate insulating layer 34.

After deposition of the semiconductor material, a pattern is formed using a second mask to form an active layer 36 and an ohmic contact layer 38 having the same size as the active layer.

The ohmic contact layer 38 is intended to reduce contact resistance between a metal layer to be formed later and the active layer 36 (FIG. 3B).

The process illustrated in FIG. 3C is a process of depositing a transparent conducting oxide (TCO) and patterning it with a third mask to form the pixel electrode 40. ITO (Indium Tin Oxide) is mainly used as the transparent conductive material. The pixel electrode 40 is configured to overlap with the storage electrode 32 to form a storage capacitor together with the storage electrode 32.

Thereafter, as shown in FIG. 3D, a metal layer is deposited and patterned with a fourth mask to form a source electrode 42 and a drain electrode 44. The drain electrode 44 is configured to contact the pixel electrode 40 at a predetermined position.

The ohmic contact layer existing between the source electrode 42 and the drain electrode 44 is removed using the source and drain electrodes 42 and 44 as a mask. If the ohmic contact layer between the source electrode 42 and the drain electrode 44 is not removed, a serious problem may occur in the electrical characteristics of the thin film transistor S, and a great problem may occur in performance.

Careful attention is required to remove the ohmic contact layer 38. When the ohmic contact layer 38 is actually etched, since there is no etching selectivity with the active layer 36 formed thereunder, the active layer 36 is overetched by about 50 to 100 nm. The etching uniformity is a thin film. It directly affects the characteristics of the transistor S.

Finally, as shown in FIG. 3E, an insulating film is deposited and patterned with a fifth mask to form a protective layer 46 to protect the active layer 36. The passivation layer 46 may adversely affect the characteristics of the thin film transistor due to the unstable energy state of the active layer 36 and the residual material generated during etching, so that the inorganic silicon nitride layer (SiN _x ) or silicon oxide layer (SiO ₂ ) or the like may be adversely affected. It is formed of inorganic BCB (BenzoCycloButene).

In addition, the passivation layer 46 may have high light transmittance, moisture resistance, and durability in order to protect the channel region and the main portion of the pixel region P of the thin film transistor S from moisture or scratch resistance that may occur during subsequent processing. This material is deposited.

By the above-described process, the thin film transistor substrate of the liquid crystal display device is completed.

4 is a flowchart illustrating a manufacturing process of FIGS. 3A to 3E.

ST200 uses a glass substrate (1) to prepare a substrate. In addition, the process of cleaning the glass substrate 1 is included. Cleaning is aimed at enhancing the adhesion of thin films to be deposited and improving the characteristics of thin film transistors, in addition to the basic concept of removing defects and particles in the substrate or film surface during the initial process to prevent defects.

ST210 is a step of depositing a metal film, and is formed by depositing aluminum or molybdenum. The gate electrode 30 and the storage electrode 32 are formed to have a tapered shape by using a lithography technique.

The ST220 is a step of depositing the insulating film 34, amorphous silicon, and amorphous silicon containing impurities. The insulating film 34 deposits a silicon nitride film or a silicon oxide film with a thickness of about 3000 Å. After deposition of the insulating film 34, the amorphous silicon film 36 and the amorphous silicon film 38 containing impurities are successively deposited.

ST230 is a step of forming a pixel electrode 40 by depositing and patterning ITO with a transparent conductive electrode (TCO).

The ST240 is a step of depositing and patterning a metal such as chromium or chromium alloy to form a source electrode 42 and a drain electrode 44.

ST250 is a step of forming a channel by removing the impurity semiconductor layer using the source and drain electrodes 42 and 44 formed in ST240 as a mask.

ST260 is a step of forming a protective film 46 to protect the devices. The protective layer 46 is made of a material resistant to moisture or external impact.

The manufacturing method of the active matrix liquid crystal display described above was a five mask method used basically. However, when the gate electrode is used as aluminum in the process of forming the thin film transistor, at least two masks are required to solve the problem of hillock that may occur on the aluminum surface. Thus, at least seven to eight mask processes have been required to construct a thin film transistor substrate.

The mask process used in manufacturing a thin film transistor substrate used in a liquid crystal display device involves various processes such as cleaning, deposition, baking, and etching. Therefore, even if the mask process is shortened once, the manufacturing time is considerably reduced, which is advantageous in terms of production yield and manufacturing cost.

Accordingly, an object of the present invention is to provide a method for shortening the number of mask processes used in manufacturing a liquid crystal display device, and to improve the production yield of a product.

1 is a cross-sectional view showing a cross section corresponding to one pixel portion of a general liquid crystal display device.

2 is a plan view illustrating a plane corresponding to one pixel part of a general liquid crystal display;

3A to 3E are process drawings showing the process of the section along the cutting line II-II 'of FIG.

4 is a flowchart showing a process of a general liquid crystal display.

5 is a plan view corresponding to one pixel portion of a liquid crystal display according to an exemplary embodiment of the present invention.

6A to 6D are process diagrams illustrating a process of a cross section along the cutting line VI-VI ′ of FIG. 5.

FIG. 7 is a cross-sectional view taken along a cut line VII-VII 'of FIG. 5. FIG.

FIG. 8 is a cross-sectional view taken along a cut line VII-VII 'of FIG. 5. FIG.

<Explanation of symbols for the main parts of the drawings>

50: gate wiring 52: cutting groove

56 gate electrode 62 source electrode

64 drain electrode 66 pixel electrode

70: insulating film 72: pure amorphous silicon

74: amorphous silicon containing impurities

In the present invention to achieve the above object and the substrate; A gate electrode and a gate wiring formed on the substrate in a two-layer structure of a transparent conductive material and an opaque metal; A pixel electrode spaced apart from the gate electrode at a predetermined interval and formed of the same layer and the same material as the transparent conductive material; A three-layer semiconductor layer formed of an insulating film, pure amorphous silicon, and amorphous silicon containing impurities and covering the gate electrode and the gate wiring; A source electrode formed on the three-layer semiconductor layer on the gate electrode and a drain electrode in contact with the pixel electrode; A first gate electrode is formed as a first storage electrode, and includes a second storage electrode on the first storage electrode, the second storage electrode being smaller than the gate wiring width, and formed between the first and second storage electrodes. Disclosed is a liquid crystal display including a storage capacitor including a dielectric layer having a cutting groove exposed at both edges of the first storage electrode.

In addition, in the present invention, a liquid crystal display including a storage capacitor electrically connected to a pixel electrode formed on a substrate, wherein the storage capacitor is formed of a two-layer structure of a substantially transparent conductive material and a substantially opaque metal on the substrate. A first storage electrode; A dielectric layer having a three-layer structure of an insulating film formed on the first storage electrode, pure amorphous silicon, and amorphous silicon containing impurities; A liquid crystal display including a second storage electrode connected to the pixel electrode on the dielectric layer is disclosed.

In addition, the present invention comprises the steps of providing a substrate; Continuously depositing and patterning a transparent conductive metal and an opaque conductive metal on the substrate to form a gate electrode and a pixel electrode each having a two-layer structure; A three-layer semiconductor layer formed of a stack of an insulating film, pure amorphous silicon, and an amorphous silicon containing impurities on the entire surface of the gate electrode and the pixel electrode and the exposed substrate, and subsequently patterning the semiconductor layer to cover the gate electrode of the two layers. Forming an active layer and removing the opaque conductive metal layer to form a single layer structure of a transparent conductive metal by removing the opaque conductive metal layer; Depositing and patterning metal on the active layer and the pixel electrode to form a source electrode on the active layer on the gate electrode and a drain electrode spaced apart from the source electrode and in contact with the pixel electrode; A method of manufacturing a liquid crystal display device comprising depositing a protective layer on the source and drain electrodes, the exposed three active layers, and the pixel electrode is disclosed.

Hereinafter, with reference to the accompanying drawings will be described in detail the configuration of the present invention.

5 is a plan view corresponding to one pixel unit according to the present invention, in which a gate electrode 56 connected to the N-th gate line 50 in the horizontal direction is formed.

A storage electrode 53a is formed on the Nth gate line 50 and the N + 1th pixel electrode, and the cutting groove 52 crossing the gate line 50 near both edges of the storage electrode 53a. Is formed. The storage electrode 53a is formed to overlap a portion of the N-th gate line 50 and the N + 1-th pixel electrode to form the storage capacitor 53.

Hereinafter, the names of the gate wirings to the storage capacitors are referred to as the gate wirings 50 and the storage capacitors 53 regardless of the order of the N to N + 1th order.

The structure of the storage capacitor 53 will be described in detail with reference to FIGS. 7 to 8.

Cutting grooves 52 that cross the gate wiring 50 are positioned near both sides of the storage capacitor 53 positioned on the gate wiring 50. Description of the cutting groove 52 will be described in detail in FIG.

The semiconductor layer 58 is covered on the gate wiring 50 and the gate electrode 56. The semiconductor layer 58 has a structure of an impurity semiconductor / semiconductor / insulating film, which will be described in detail with reference to FIG. 6B.

In addition, a source electrode 62 connected to the source wiring 60 and the source wiring 60 in the vertical direction and overlapping the gate electrode 56 is formed, and is positioned at a position corresponding to the source electrode 62. A drain electrode 64 spaced apart by a predetermined distance and overlapping the gate electrode 56 is formed. The drain electrode 64 is electrically connected to the pixel electrode 66.

Referring to FIGS. 6A to 6D, which are cross-sectional views taken along line VI-VI ′ of FIG. 5, a manufacturing process of a thin film transistor substrate according to the present invention will be described.

First, referring to FIG. 6A, a transparent conductive material and an opaque metal material are deposited on the substrate 1 and patterned with a first mask to form the gate electrode 56 and the pixel electrode 66. In this case, the metal layer 66 ′ on the pixel electrode 66 is removed in a later process.

As described above, when the gate electrode 56 is formed in the two-layer structure of the gate electrode 56a of the transparent conductive material and the metal gate electrode 56b, defective pixels may not be generated due to disconnection of the metal gate electrode 56b. There is no advantage. That is, the gate electrode 56a of the transparent conductive material serves as an auxiliary electrode of the metal gate electrode 56b.

FIG. 6B illustrates forming an active layer over the gate electrode 56, and over the entire surface of the gate electrode 56, the upper metal layer 66 ′ of the pixel electrode 66, and the exposed substrate 1. The semiconductor layer of the layer is successively deposited and patterned with a second mask to form an active layer 58. First, the active layer 58 of the three layers includes a gate insulating layer 70 formed on the metal gate electrode 56b, an amorphous silicon layer 72 on the gate insulating layer 70, and an upper portion of the amorphous silicon layer 72. Is formed of an amorphous silicon layer 74 containing impurities.

The three active layers 58 are formed to cover the gate electrodes 56a and 56b. The metal layer 66 ′ on the pixel electrode 66 is removed by the second mask.

In the second mask process, the active layer 58 and the pixel electrode 66 are formed. That is, in the embodiment of the present invention, since the transparent conductive electrode is first deposited on the substrate 1, the pixel electrode 66 is formed in the second mask process.

FIG. 6C illustrates a process of forming source and drain electrodes, in which an opaque metal is deposited and patterned with a third mask to include a portion of the active layer 58 to overlap a predetermined portion with the gate electrode 56. The drain electrode 64 is formed on the amorphous silicon 74 to be in contact with the source electrode 62 and the pixel electrode 66.

Thereafter, the source and drain electrodes 62 and 64 are used as masks to remove the amorphous silicon 74 containing impurities in region A, which is a back channel portion of the active layer 58. At this time, it should be noted that when removing the amorphous silicon 74 containing the impurity, the etching time should be well adjusted so as not to be etched to the amorphous silicon region 72 below. Inevitably, in a liquid crystal display device employing a back channel etching thin film transistor, amorphous silicon 72 is overetched in the back channel portion A by about 50 to 100 nm. This is because there is no etching selectivity between the amorphous silicon 74 containing impurities and the pure amorphous silicon 72. Therefore, considerable care must be taken in etching the back channel portion A. FIG.

Finally, as shown in FIG. 6D, an insulating film is deposited and patterned with a fourth mask to form a protective film 76 to protect the active layer 58. Since the passivation layer 76 may adversely affect the characteristics of the thin film transistor due to the unstable energy state of the back channel portion A of the active layer 58 and residual materials generated during etching, the passivation layer 76 may be formed of an inorganic silicon nitride layer (SiN _x ). It is formed of a silicon oxide film (SiO ₂ ) or organic BCB (BenzoCycloButene).

In addition, the passivation layer 76 has a high light transmittance, moisture resistance, and durability in order to protect the channel region and the main portion of the pixel region P of the thin film transistor S from moisture or scratch resistance defects that may occur during subsequent processes. This material is deposited.

In addition, a connection hole (not shown) for forming the cutting groove 52 and various connection parts shown in FIG. 5 is formed as a fourth mask.

FIG. 7 is a cross-sectional view taken along the line VII-VII 'of FIG. 5. That is, the configuration of the cutting groove 52 in detail is as follows.

First, a gate wiring 50 having a two-layer structure of a transparent gate wiring 50b and an opaque metal gate wiring 50a is formed on the substrate 1, and three layers of semiconductors are formed on the gate wiring 50. The floor is located. The three semiconductor layers have the same structure as the three semiconductor layers 58 shown in Fig. 6B.

The storage electrode 53a is formed on the three-layer semiconductor layer. In addition, cutting grooves 52 are formed near both ends of the storage electrode 53a. The function of the cutting groove 52 is that the charge stored in the storage capacitor 53 increases as the potential of the storage electrode 53a increases, and thus, amorphous silicon 74 containing impurities below the storage electrode 53a. This is to prevent the leakage of charge through). The cutting groove 52 is formed up to an upper portion of the gate wiring 50 including amorphous silicon containing impurities of a three-layer semiconductor layer at positions spaced apart from the storage electrode 53a by a predetermined distance.

FIG. 8 is a diagram illustrating a relationship between the storage capacitor 53, the storage electrode 53a, and the gate wiring 50, and is a cross-sectional view taken along the cutting line ′-′ ′ of FIG. 5.

As illustrated in FIG. 8, three semiconductor layers are formed on the gate line 50, and a storage electrode 53a covering the three semiconductor layers and a part of the pixel electrode 66 is formed. Here, the capacitance of the storage capacitor 53 substantially becomes a portion where the gate wiring 50 and the storage electrode 53a overlap. In addition, the three semiconductor layers formed between the gate wiring 50 and the storage electrode 53a serve as a dielectric of the storage capacitor 53.

In addition, a passivation layer 76 is formed on the pixel electrode 66, the storage electrode 53a, and the semiconductor layer to protect the devices.

In the above-described embodiment of the present invention, the transparent conductive material and the opaque metal are continuously deposited in a stacked structure on the substrate, and the gate wiring, the gate electrode, and the pixel electrode can be formed by only two mask processes, and finally, four masks. The thin film transistor substrate could be formed by the step.

In addition, by manufacturing the thin film transistor substrate using only four masks, a decrease in yield due to misalignment can be prevented in advance.

In addition, by forming the gate wiring and the gate component of the gate electrode in a two-layer structure, it is possible to prevent the short circuit or disconnection of the electrode that may occur during the patterning of the gate component.

When manufacturing a liquid crystal display according to the embodiment of the present invention described above has the following features.

First, since the thin film transistor substrate can be manufactured with four masks, the manufacturing time is shortened.

Second, since the thin film transistor substrate can be configured with four masks, it is possible to prevent a decrease in yield due to misalignment.

Third, there is a cost reduction effect due to the reduction of the manufacturing process of the liquid crystal display device.

Fourth, by forming the gate electrode of the thin film transistor in a two-layer structure, when forming the gate electrode, there is an advantage that can reduce the defective pixels due to disconnection of the gate electrode.

Claims (7)

A substrate; A gate electrode and a gate wiring formed on the substrate in a two-layer structure of a transparent conductive material and an opaque metal; A pixel electrode spaced apart from the gate electrode at a predetermined interval and formed of the same layer and the same material as the transparent conductive material; A three-layer semiconductor layer formed of an insulating film, pure amorphous silicon, and amorphous silicon containing impurities and covering the gate electrode and the gate wiring; A source electrode formed on the three-layer semiconductor layer on the gate electrode and a drain electrode in contact with the pixel electrode; A first gate electrode is formed as a first storage electrode, and includes a second storage electrode on the first storage electrode, the second storage electrode being smaller than the gate wiring width, and formed between the first and second storage electrodes. A storage capacitor including a dielectric layer having a cutting groove exposing the first storage electrode near both edges Liquid crystal display comprising a. The method according to claim 1, The opaque metal is a liquid crystal display, characterized in that the material selected from the group consisting of chromium, aluminum, aluminum alloy, molybdenum, tantalum, tungsten, antimony. The method according to claim 1, And the transparent conductive material is ITO. A liquid crystal display comprising a storage capacitor electrically connected to a pixel electrode formed on a substrate. The storage capacitor includes: a first storage electrode formed on the substrate in a two-layer structure of a substantially transparent conductive material and a substantially opaque metal; A dielectric layer having a three-layer structure of an insulating film formed on the first storage electrode, pure amorphous silicon, and amorphous silicon containing impurities; A second storage electrode connected to the pixel electrode on the dielectric layer Liquid crystal display comprising a. The method according to claim 4, The pixel electrode is the same material as the transparent conductive material of the first storage electrode. Providing a substrate; Continuously depositing and patterning a transparent conductive metal and an opaque conductive metal on the substrate to form a gate electrode and a pixel electrode each having a two-layer structure; A three-layer semiconductor layer formed of a stack of an insulating film, pure amorphous silicon, and an amorphous silicon containing impurities on the entire surface of the gate electrode and the pixel electrode and the exposed substrate, and subsequently patterning the semiconductor layer to cover the gate electrode of the two layers. Forming an active layer and removing the opaque conductive metal layer to form a single layer structure of a transparent conductive metal by removing the opaque conductive metal layer; Depositing and patterning metal on the active layer and the pixel electrode to form a source electrode on the active layer on the gate electrode and a drain electrode spaced apart from the source electrode and in contact with the pixel electrode; Depositing a protective layer on the source and drain electrodes, the exposed three active layers and the pixel electrode Liquid crystal display manufacturing method comprising a. The method according to claim 6, And etching the amorphous silicon containing impurities formed under the spaced apart portions of the source electrode and the drain electrode using the source and drain electrodes as masks.