JP2003156764A - Manufacturing method for thin-film transistor array substrate and liquid crystal display unit equipped with the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve the problem that since gate wires are formed separately, one by one, by a conventional manufacturing method for a thin-film transistor array substrate, static electricity enters a gate wire in subsequent processes and thin-film transistor characteristics deteriorate to cause a decrease in yield. SOLUTION: A plurality of gate wires, a gate wire connection part which connects the plurality of gate wires, and a gate electrode are provided on an insulating substrate and a 1st insulating film is provided thereupon; and a 2nd insulating film is provided on the gate wire connection part, a source electrode, a drain electrode, and a channel formation area, and a contact hole is provided on the gate wire and drain electrode. At this time, the 1st insulating film and 2nd insulating film on the gate wire connection part are etched away and the exposed gate wire connection part is etched away to part the connected gate wires.

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to a method of manufacturing a thin film transistor array substrate. In particular, a substrate having an inverted staggered thin film transistor is used as one substrate, and a thin film transistor array substrate manufacturing method and a thin film transistor array substrate manufactured by such a method relating to measures against display defects due to deterioration of thin film transistor characteristics due to static electricity during the manufacturing process are used. Liquid crystal display device.

[0002]

2. Description of the Related Art FIG. 4 is a sectional view showing a manufacturing process of a thin film transistor array substrate having an inverted staggered thin film transistor, a gate wiring, a source wiring and the like in a conventional thin film transistor type liquid crystal display device, and FIG. In the thin film transistor type liquid crystal display device of FIG. 3, there is shown a plan view showing a manufacturing process of a thin film transistor array substrate including an inverted staggered thin film transistor, a gate wiring, a source wiring and the like.

In such a thin film transistor array substrate, as shown in FIG. 4, gate wirings 1 and source wirings 2 are arranged in a matrix on a transparent insulating substrate 5 made of glass or the like. The region surrounded by the gate line 1 and the source line 2 becomes one pixel electrode 3, and the thin film transistor 4 is provided for each pixel.

As for the thin film transistor 4, a gate electrode 6 drawn from the gate wiring 1 is provided on a transparent insulating substrate 5, and a gate insulating film 7 is provided so as to cover the entire gate electrode 6. Amorphous silicon (a-S) is formed on the gate insulating film 7 above the gate electrode 6.
The semiconductor film 8 made of i) is provided, and n of phosphorus or the like is provided.
Amorphous silicon (a-Si:
The source electrode 10 and the drain electrode 1 drawn from the source wiring 2 from the semiconductor film 8 to the gate insulating film 7 via the ohmic contact layer 9 made of n ⁺ ).
1 is provided.

A passivation film 12 is provided to cover the thin film transistor 4 composed of the source electrode 10, the drain electrode 11, the gate electrode 6 and the like.
A contact hole 13 is provided in the passivation film 12 on the drain electrode 11.

Further, a pixel electrode 14 made of a transparent conductive film such as indium tin oxide (hereinafter referred to as “ITO”) electrically connected to the drain electrode 11 through the contact hole 13 is provided. Has been.

The right side portion of FIG. 4 shows the sectional structure of the gate terminal pad portion 15 and the source terminal pad portion 16 at the end of the gate wiring 1 located outside the display area. As shown in FIG. 4, the gate insulating film 7 and the passivation film 12 are formed on the lower pad layer 17 made of the gate wiring material on the transparent insulating substrate 5, and the passivation film is formed on the lower pad layer 18 made of the source wiring material. Contact holes 19 and 20 respectively penetrating 12 are provided, and the gate upper pad layer 21 and the source upper pad are electrically connected to the gate lower pad layer 17 and the source lower pad layer 18 through the contact holes 19 and 20, respectively. A layer 22 is provided. The upper pad layers 21 and 22 are made of the same transparent conductive film as the pixel electrode 14.

In manufacturing this thin film transistor array substrate, first, a conductive film is formed on the transparent insulating substrate 5, and the conductive film is patterned to form the gate electrode 6 and the gate wiring 1. Further, the lower pad layer 17 is formed on the gate terminal pad portion 15.

Next, after forming a gate insulating film 7 for covering the gate electrode 6 and the gate wiring 1, an a-Si film 8,
a-Si: n ⁺ film 9 will sequentially deposited, these a-Si film 8, a-Si using a single photomask: by patterning collectively n ⁺ layer 9, Figure 4 As shown, an island portion is formed on the gate electrode 6 with the gate insulating film 7 interposed therebetween.

Further, after forming a conductive film on the entire surface, the drain electrode 11 made of a conductive film is formed by patterning the conductive film.
The source electrode 10 and the source wiring 2 are formed, and a-
The a-Si: n ⁺ film 9 on the channel portion of the Si film 8 is removed to form an ohmic contact layer made of the a-Si: n ⁺ film 9.

Next, a passivation film 12 is formed on the entire surface and patterned to form a passivation film 12 and a gate insulating film 7 on the lower gate pad layer 17, a drain electrode 11 and a lower source pad layer 1.
8, a part of the passivation film 12 is opened, and a contact hole 13 for electrically connecting the drain electrode 11 and the pixel electrode 14 and a gate mounting terminal portion 15 and a source mounting terminal portion 16 are electrically connected. Contact holes 19 and 20 for forming are formed respectively.

Finally, an ITO film is formed on the entire surface and is patterned to form the pixel electrode 14, the gate upper pad layer 21 and the source upper pad layer 22 as mounting electrodes. A conventional thin film transistor array substrate is completed through these steps.

[0013]

However, according to the method of manufacturing the thin film transistor array substrate as described above, since the gate wirings are formed separately for each wiring, subsequent island portion formation, source / drain Electrode formation, contact hole formation, film formation during pixel electrode formation,
In the photolithography, etching and resist stripping process, static electricity invades the gate wiring to deteriorate the characteristics of the thin film transistor, resulting in an extremely high probability of display failure, resulting in a decrease in yield.

In order to solve the above-mentioned problems, the present invention is formed by connecting gate wirings to make it difficult for static electricity to enter the gate wirings in the subsequent steps, and to end the gate electrodes when the pixel electrodes are formed. To provide a method for manufacturing a thin film transistor array substrate capable of preventing characteristic deterioration of a thin film transistor due to static electricity in a process of manufacturing a thin film transistor array substrate by dividing wiring, and a thin film transistor array manufactured by the method. An object is to provide a liquid crystal display device using a substrate.

[0015]

In order to achieve the above object, a method of manufacturing a thin film transistor array substrate according to the present invention comprises a plurality of gate wirings on an insulating substrate and a gate wiring connecting each of the plurality of gate wirings. A step of providing a gate electrode drawn from the connection portion and the gate wiring,
Providing a first insulating film on the insulating substrate, the gate wiring, the gate wiring connecting portion and the gate electrode; providing a semiconductor layer above the first insulating film; A step of providing a source electrode and a drain electrode so as to face each other in a portion other than the channel formation region immediately above the electrode, and the insulating substrate, at least the gate wiring connection portion, the source electrode, the drain electrode, and the channel formation A step of forming a second insulating film on the region, and etching the first insulating film and the second insulating film on the gate wiring connection portion when forming a contact hole on the gate wiring and the drain electrode. A step of removing and exposing at least a part of the gate wiring connecting portion, and a step of forming a pixel electrode above the contact hole, The exposed gate wiring connection portion is removed by etching, characterized in that it and a step of dividing the connected gate wiring.

With this structure, the gate wiring is connected until after the pixel electrode is formed, and it is possible to prevent the characteristic deterioration of the thin film transistor due to static electricity from after the gate wiring is formed until when the pixel electrode is formed.

That is, compared with the conventional manufacturing process, since the connected gate wiring can be divided in the pixel electrode process without increasing the number of photomasks, the characteristics of the thin film transistor due to static electricity can be increased without increasing the manufacturing cost. It is possible to prevent deterioration.

Further, in the method of manufacturing the thin film transistor array substrate according to the present invention, it is preferable that the gate wiring, the gate wiring connecting portion, and the gate electrode are made of a material which can be etched by a wet method.

The pixel electrode is of a transmissive type, a reflective type or a semi-transmissive type.

In order to achieve the above object, a liquid crystal display device according to the present invention is a liquid crystal display device in which a liquid crystal material is sandwiched between two insulating substrates facing each other. As one of the insulating substrates, a thin film transistor array substrate manufactured by the method of manufacturing a thin film transistor array substrate as described above is used.

[0021]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A thin film transistor array substrate according to embodiments of the present invention will be described below with reference to the drawings. The method of manufacturing the thin film transistor array substrate according to the present embodiment uses a two-layer film of aluminum alloy and molybdenum tungsten as a gate material and a three-layer film of titanium, aluminum and titanium as a source material in an inverted stagger type thin film transistor. In this example, the manufacturing process is a five-mask process.

1 and 3 are cross-sectional views showing a manufacturing process of a thin film transistor array substrate, which is one of the substrates facing each other with a liquid crystal layer sandwiched in the liquid crystal display device using the thin film transistor array substrate according to the present embodiment. FIG. 2 is a plan view showing a manufacturing process of a thin film transistor array substrate which is one of the substrates facing each other with a liquid crystal layer interposed therebetween in the liquid crystal display device using the thin film transistor array substrate according to the present embodiment.

The thin film transistor array substrate according to the present embodiment has a glass substrate 5 as shown in FIGS.
The gate wirings 1 and 1'are connected between the mounting portion and the thin film transistor forming portion, and the gate electrodes 6 drawn out from the respective gate wirings are provided on the upper portion.
A gate insulating film 7 made of SiNx is provided so as to cover the. In the present embodiment, all of the plurality of gate wirings are connected by the gate wiring connecting portion, and a two-layer film of aluminum alloy and molybdenum tungsten is used as the gate wiring material.

Further, the gate insulating film 7 above the gate electrode 6
A semiconductor film 8 made of amorphous silicon (a-Si) is provided on the semiconductor film 8 via an ohmic contact layer 9 made of amorphous silicon (a-Si: n ⁺ ) containing an n-type impurity such as phosphorus. A source electrode 10 and a drain electrode 11 drawn from the source wiring 2 are provided in the. The source wiring 2, the source electrode 10 and the drain electrode 11 are formed of a three-layer film of titanium, aluminum and titanium.

Then, a passivation film 12 made of SiNx is provided to cover the thin film transistor 4 composed of the source electrode 10, the drain electrode 11, the gate electrode, etc., and the passivation film 12 on the drain electrode 11 is provided.
Is provided with a contact hole 13. Further, a pixel electrode 14 made of ITO electrically connected to the drain electrode 11 through the contact hole 13 is provided.

The right part of FIG. 1 shows the cross-sectional structure of the gate terminal pad portion 15 and the source terminal pad 16 at the end of the gate wiring 1, 1 ′ located outside the display area. As shown in FIG. 1, a contact hole 1 penetrating a gate insulating film 7 and a passivation film 12 on a lower pad layer 17 made of a gate wiring material on a glass substrate 5.
9 is provided, and an upper pad layer 21 made of ITO electrically connected to the lower pad layer 17 through the contact hole 19 is provided. The source terminal pad portion is also provided with a contact hole 20 penetrating the passivation film 12 on the gate insulating film 7 on the glass substrate 5 and the lower pad layer 18 made of a source wiring material. An upper pad layer 22 made of ITO electrically connected is provided. Further, the rightmost portion 23 in FIG. 1 shows a sectional structure of a cut portion of the gate wiring connection portion of the gate wirings 1 and 1 ′ located outside the display region.

In manufacturing this thin film transistor array substrate, first, as shown in FIGS. 1 and 2, a two-layer film of an aluminum alloy and molybdenum tungsten is continuously formed on a glass substrate 5, and this is formed into an ordinary film. The gate electrode 6 and the gate wiring 1 are formed by patterning using the photolithography technique. Further, the lower pad layer 17 is formed on the gate terminal pad portion 15.

Next, the SiNx film 7 and a-S are formed so as to cover the gate electrode 6, the gate wiring connection portion and the gate wiring 1.
Three layers, i film 8 (semiconductor film) and a-Si: n ⁺ film 9 (impurity semiconductor film), are continuously formed on the entire surface of the substrate. On this occasion,
Continuous film formation is performed in the same vacuum atmosphere using the same film forming apparatus, and this is patterned by using a normal photolithography technique to form an a-Si: n ⁺ film 9 and an a-Si film 8.

Next, a three-layer film made of titanium, aluminum and titanium is continuously formed on the entire surface, and the film is patterned by using a normal photolithography technique to form the drain electrode 11, the source electrode 10, and the source wiring 2, and a-S
An ohmic contact layer made of i: n ⁺ film 9 is formed.

Next, a SiNx film is formed on the entire surface to form the passivation film 12, and the two-layer film of the passivation SiNx film 12 and the gate insulating SiNx film 7 is etched by using a normal photolithography technique.

When the passivation film 12 is etched in this step, part of the passivation film 12 on the drain electrode 11, the gate terminal pad portion 15 and the lower pad portion 16 of the source terminal pad portion is partially removed. A contact hole 1 for opening and electrically connecting the drain electrode 11 and the pixel electrode 14
3. Contact holes 19 and 20 for electrically connecting the lower pad layer 17 and the upper pad layer 18 are formed.

Further, as shown in FIG. 3A, in the dividing portion 23 between the gate wiring connecting portions 1 and 1 ', the two-layer film of the passivation film 12 and the gate insulating film 7 is etched to expose the gate wiring 24. .

Next, an ITO film is formed on the entire surface, and the ITO film is patterned using a normal photolithography technique to form the pixel electrode 14 and the gate terminal pad portion 15.
The upper pad layers 21 and 22 of the source terminal pad portion 16 are formed. At this time, hydroiodic acid, hydrochloric acid and hydrobromic acid are used as the etching solution for the ITO film.

Further, the gate wiring dividing portion 23 is shown in FIG.
As shown in, the ITO film can be etched in this step, and the gate electrode 24 of the gate wiring dividing portion 23 can be etched and removed at the same time. At this time, if 24 etching of the gate electrode is incomplete, I
If the etching is performed with a phosphorous nitrate acetic acid-based etching solution before removing the resist after etching the TO film, the etching can be easily removed.

Through these steps, a thin film transistor array substrate as shown in FIG. 3C can be manufactured. Then, the thin film transistor array substrate and a counter substrate on which a common electrode is formed are prepared, and liquid crystal is sealed between these substrates to complete the liquid crystal display device having the above-described configuration.

In the method of manufacturing the thin film transistor array substrate according to the present embodiment and the liquid crystal display device using the thin film transistor array substrate manufactured by the method, all the gate wirings are connected until after the pixel electrodes are formed. It is possible to prevent the characteristic deterioration of the thin film transistor due to static electricity from thereafter on until the pixel electrode is formed.

That is, by using all the gate wirings that can be wet-etched and connected, the gate wiring connection portions exposed in the step of providing the pixel electrodes above the contact holes are removed by wet etching, and all the connected gate wirings are removed. Divide. All the gate wirings are connected until after the pixel electrode is formed, and it is possible to prevent the characteristic deterioration of the thin film transistor due to static electricity from after the gate wiring is formed until when the pixel electrode is formed. Since the gate wiring can be divided in the pixel electrode process without increasing the number of photomasks, it is possible to prevent the characteristic deterioration of the thin film transistor due to static electricity without increasing the manufacturing cost.

[0038]

As described above, according to the method of manufacturing the thin film transistor array substrate of the present invention, it is possible to prevent the characteristic deterioration of the thin film transistor due to static electricity from after the gate wiring is formed until the pixel electrode is formed. That is, as compared with the conventional manufacturing process, since all the gate wirings connected to each other can be divided in the pixel electrode process without increasing the number of photomasks, the characteristic deterioration of the thin film transistor due to static electricity can be prevented without increasing the manufacturing cost. Can be prevented.

[Brief description of drawings]

FIG. 1 is a sectional view of a manufacturing process of a thin film transistor array substrate according to an embodiment of the present invention.

FIG. 2 is a plan view of a thin film transistor array substrate according to an embodiment of the present invention.

FIG. 3 is a detailed sectional view of the manufacturing process of the thin film transistor array substrate according to the embodiment of the present invention.

FIG. 4 is a sectional view of a manufacturing process of a conventional thin film transistor array substrate.

FIG. 5 is a plan view of a conventional thin film transistor array substrate.

[Explanation of symbols]

1 gate wiring 2 source wiring 3 and 14 pixel electrode 4 thin film transistor 5 transparent insulating substrate (glass substrate) 6 gate electrode 7 gate insulating film 8 semiconductor film 9 a-Si: n ⁺ film 10 source electrode 11 drain electrode 12 passivation film ( Insulating film) 13, 19, 20 Contact hole 15 Gate terminal pad section 16 Source terminal pad section 17 Gate lower pad layer 18 Source lower pad layer 21 Gate upper pad layer 22 Source upper pad layer 23 Gate wiring dividing section 24 Gate wiring dividing section Gate electrode 25 resist

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) H01L 29/786 H01L 29/78 623A 612A (72) Inventor Atsushi Mitsuo 1006 Kadoma, Kadoma-shi, Osaka Matsushita Electric Industrial Co., Ltd. (72) Inventor Atsushi Imai 1006 Kadoma, Kadoma City, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. F term (reference) 2H092 JA26 JB01 JB79 MA13 MA18 MA48 NA14 5C094 AA42 AA43 AA48 BA03 BA43 CA19 DA13 DB01 DB04 EA04 EA05 EA06 EA10 FA01 FA02 FB12 FB14 FB15 GB10 5F043 AA27 BB18 GG10 5F110 AA16 AA22 BB01 CC07 DD02 EE06 EE14 FF03 GG02 GG15 HK03 HK04 HK09 HK16 BB16 H15 BB14H16H12 BB16H12Q15H12H15B12H16A12A17A02

Claims (4)

[Claims] 1. A step of providing a plurality of gate wirings, a gate wiring connecting portion for connecting each of the plurality of gate wirings, and a gate electrode drawn from the gate wirings on an insulating substrate, the insulating substrate, Forming a first insulating film on the gate line, the gate line connecting portion and the gate electrode; forming a semiconductor layer above the first insulating film; and forming a channel immediately above the gate electrode. A step of providing a source electrode and a drain electrode so as to face each other in a portion other than the region; and a second step on the insulating substrate, at least the gate wiring connection portion, the source electrode, the drain electrode, and the channel formation region. The step of providing the insulating film, and the step of connecting the gate wiring when the contact hole is provided on the gate wiring and the drain electrode. A step of exposing at least a portion of the first insulating film and the second insulating film above is removed by etching the gate wiring connection portion, when providing the upper to the pixel electrode of the contact hole,
A step of removing the exposed gate wiring connection portion by etching to divide the connected gate wiring. 2. The gate wiring, the gate wiring connecting portion,
The method of manufacturing a thin film transistor array substrate according to claim 1, wherein the gate electrode is made of a material that can be etched by a wet method. 3. The method of manufacturing a thin film transistor array substrate according to claim 1, wherein the pixel electrode is one of a transmissive type, a reflective type and a semi-transmissive type. 4. A liquid crystal display device in which a liquid crystal material is sandwiched between two insulating substrates facing each other, wherein one of the insulating substrates is formed of one of the insulating substrates. A thin film transistor array substrate manufactured by the method for manufacturing a thin film transistor array substrate according to the item 1.