JP3272873B2 - Liquid crystal display - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display.

[0002]

2. Description of the Related Art In recent years, liquid crystal display devices are characterized by being thin and light, capable of being driven at a low voltage, and being easily colored, and have recently been used in personal computers, word processors and the like. Is used as a display device. Among them, an active matrix type liquid crystal display device using a thin film transistor (TFT) as a switching element (hereinafter simply referred to as a liquid crystal display device) has no deterioration in contrast, response and the like even with a large number of pixels, and also has a halftone display. Since it is possible, it is expected as a display device for a full-color television or OA.

FIG. 13 is a perspective view showing a configuration of an array substrate of a conventional liquid crystal display device. FIG. 14 is a schematic diagram showing the configuration of the array substrate. In FIG. 13, 10
Reference numeral 1 denotes a light-transmitting insulating substrate, on which a pixel portion 102 is provided. The pixel portion 102 is roughly divided, as shown in FIG. 14, from a pixel electrode 104 arranged in a matrix and a TFT 105 as a switching element provided for each pixel electrode.

Around the pixel section 102, as shown in FIG. 13, a TFT driving IC 103 which is a dedicated IC for driving the TFT is provided. This TFT driving I
C103 is connected to the TFT via an extraction electrode provided around the pixel portion 102. That is, FIG.
As shown in FIG. 2, the gate driving IC connected to the scanning line in the driving IC 103 is connected to the gate of the TFT 105 via the gate extracting electrode 106, and the driving IC
The signal line driving IC of C103 connected to the signal line is connected to the source / drain of the TFT 105 via the signal line extracting electrode 107. This source / drain is the one of the two sources / drain that is not connected to the pixel electrode 104.

[0005] As a method of connecting the driving IC 103 to the extraction electrode, COG (Chip On Glass) mounting is performed by TAB.
(Tape Automated Bonding). This is because there are advantages in that the number of components for connection can be reduced, connection at a fine pitch can be performed, and the thickness of the entire array substrate including the driving IC can be reduced.

FIG. 15 shows an inverted stagger type TFT as a TFT.
FIG. 3 is a cross-sectional view illustrating a configuration of an array substrate when using the substrate.
The basic structure of this inverted stagger type TFT is a light-transmitting insulating substrate 1
01, a gate electrode 111, a gate insulating film 112, an active layer 113, an ohmic contact layer 11
4 and source / drain electrodes 117 and 118. Reference numeral 115 denotes a channel protective film, and 119 denotes a TFT protective film.

The gate electrode 111 extends to a gate electrode take-out portion provided around the pixel portion. A gate take-out electrode 118b is provided on the gate electrode 111 of the gate electrode take-out portion. The gate extraction electrode 118b is formed of the same conductive film as the source / drain electrodes 117 and 118. The source / drain electrode 118 extends to a signal line electrode take-out portion provided around the pixel portion. The source / drain electrode of this signal line electrode take-out portion is a signal line take-out electrode 118.
a.

FIG. 16 shows that the signal line driving IC 103a is
It is sectional drawing which shows the principal part of the array board which carried out OG mounting. In order to mount the signal line driving IC 103a by COG, it is necessary to form the electrodes 121 and the bumps 122 on the signal line driving IC 103a by using a plating method, an evaporation method, or the like. In a method such as a plating method or a vapor deposition method, a photolithography technique is required to form the bump 122. Here, the bump 122 is generally high. Therefore, formation (patterning) of bump 122 by photolithography technology
And the reliability of the bump 122 is reduced.

Further, the signal line driving IC 103a on which the electrodes 121 and the bumps 122 are formed is connected to the signal line taking out electrodes 11a.
8a for the signal line drive during the crimping process for connecting to
Due to the load applied to C103a, cracks may occur in the electrodes such as the signal line extraction electrode 118a and the bump 122. Such cracks cause poor connection and lower reliability. Such a problem is caused by the gate drive IC.
There is also about.

[0010]

As described above, in a conventional liquid crystal display device, a driving IC is mounted on an array substrate with a CO.
In order to mount G, it was necessary to form a bump on the driving IC. However, bumps are generally tall and difficult to make. For this reason, there has been a problem that the reliability is reduced due to the bumps.

Further, in the pressure bonding step when connecting the driving IC to the array substrate, a load is applied to the driving IC, so that cracks occur in the electrodes such as the bumps and the electrodes for taking out the signal lines, thereby lowering the reliability. There was a problem.

The present invention has been made in consideration of the above circumstances, and an object of the present invention is to prevent a decrease in reliability that may occur when a control unit such as a driving IC for controlling a TFT is mounted. It is to provide a liquid crystal display device.

[0013]

In order to achieve the above object, a liquid crystal display device according to the present invention (claim 1) is provided with pixel electrodes arranged in a matrix on an insulating substrate and provided on each pixel electrode. A pixel portion including an inverted staggered thin film transistor as a switching element, and a source / drain of the inverted staggered thin film transistor provided on the insulating substrate around the pixel portion. and a signal line electrode <br/> extraction unit is connected to one electrode, the via the signal line electrode extraction portion Gyakusu
Control means for controlling the inverted staggered thin film transistor connected to the tag type thin film transistor, wherein the signal line electrode extraction portion includes a signal line extraction electrode;
Consists of a stacked portion provided in the lower portion of the signal line extraction electrode, the signal line extraction electrode is formed from the source and drain electrodes of the same conductive film of the inverted staggered thin <br/> film transistor The stacking portion is formed of the same conductive film as the gate electrode of the inverted staggered thin film transistor;
Same insulation as gate insulating film of staggered thin film transistor
Film, the same as the active layer of the inverted staggered thin film transistor
Semiconductor layer, ohmic of the inverted staggered thin film transistor
The same low-resistance semiconductor layer as the contact layer,
The same insulating film as the channel protective film of the GaAs thin film transistor
And at least one of the same conductive films as the pixel electrodes is formed of the same material .

[0014]

[0015]

In the present invention, an electrode comprising a first extraction electrode and a second extraction electrode is employed as an extraction electrode, and the second extraction electrode comprises a gate insulating film of a thin film transistor, Further, it is formed of the same intermediate film as the conductive film or the semiconductor film constituting the thin film transistor between the gate insulating film and the insulating substrate. Alternatively, the second extraction electrode is formed of a gate insulating film of a thin film transistor, and an intermediate film that is the same as at least one of a conductive film, a semiconductor film, and an insulating film forming the thin film transistor between the gate insulating film and the source electrode. (Claim 2).

That is, the extraction electrode of the present invention has a first extraction electrode having the same structure as that of the conventional extraction electrode, and has a multi-layered structure including a gate insulating film and an intermediate film, which has not been conventionally provided. And two extraction electrodes.

Therefore, according to the present invention, the load applied to the extraction electrode at the time of mounting the control means is effectively absorbed and dispersed by the second extraction electrode. A possible decrease in reliability can be prevented.

In addition, by using the second extraction electrode having a multilayer structure, the height of the extraction electrode becomes higher than in the conventional case, and thus, for example, when the control means is mounted by COG, A bump with a low height can be used, and a decrease in reliability due to the bump can be prevented.

[0019]

Embodiments will be described below with reference to the drawings. FIG. 1 is a sectional view of an array substrate of a liquid crystal display according to a first embodiment of the present invention. This array substrate is roughly divided into a gate electrode extraction portion, a pixel portion, and a signal line electrode extraction portion.

The pixel section is composed of pixel electrodes 16 arranged in a matrix on the translucent insulating substrate 1 and an inverted staggered TFT 2 as a switching element provided for each pixel electrode.

The inverted stagger type TFT 2 is composed of a transparent insulating substrate 1
The gate electrode 11 and the gate insulating film 1 sequentially provided on the
2, an active layer 13, an ohmic contact layer 14, and source / drain electrodes 17, 18. Note that reference numeral 15 denotes a channel protection film, and 19 denotes a TFT protection film.

The gate electrode 11 extends to the gate electrode take-out portion.
A first gate extraction electrode 18b formed of the same conductive film as the drain electrodes 17 and 18 and a second gate extraction electrode as a stacking unit described later are provided.

The signal line electrode take-out portion includes a first signal line take-out electrode 18a formed of the same conductive film as the source / drain electrodes 17 and 18, and a second signal line take-out portion as a stacking portion described later. Electrodes are provided.

The second signal line lead-out electrode is made of the same conductive film 11a as the gate electrode 11, the same insulating film 12a as the gate insulating film 12, and the same semiconductor layer 13 as the active layer 13.
a, the same low-resistance semiconductor layer 14a as the ohmic contact layer 14, and the same insulating film 15a as the channel protective film 15.
And the same conductive film 16 a as the pixel electrode 16.

Similarly, the second gate extraction electrode includes the same conductive film 11b as the gate electrode 11, the same insulating film 12b as the gate insulating film 12, the same semiconductor layer 13b as the active layer 13, and the ohmic contact layer. 14, the semiconductor layer 14b is formed of the same low-resistance semiconductor layer 14b, the same insulating film 15b as the channel protective film 15, and the same conductive film 16b as the pixel electrode 16.

FIG. 2 is a process sectional view showing a method of manufacturing the array substrate of FIG. First, as shown in FIG.
A gate electrode 11, a conductive film 11a constituting a part of a second signal line extraction electrode (hereinafter, referred to as a signal line stacking portion) and a second gate extraction electrode (hereinafter, gate) are formed on the transparent insulating substrate 1. After forming a MoTa alloy film to be the conductive film 11b constituting a part of the stacked portion),
The gate electrode 11 and the conductive layers 11a and 11b are formed by patterning the oTa alloy film. The MoTa alloy film is formed by, for example, a sputtering method, and its thickness is, for example, 200 nm. Al instead of MoTa alloy film
A metal film such as a film or an alloy film such as a MoW film may be used.

[0027] Next, as shown in FIG. 2 (b), the entire surface of the gate insulating film, the signal line stacked part and CVD insulating film 12 ₀ of thickness 400nm constituting a part of the gate stacked portion
It is formed by a method. As the insulating film ₁₂₀ , for example, a silicon oxide film or a silicon nitride film is used.

[0028] Subsequently, the active layer on the insulating film 12 _0, the semiconductor layer 13 ₀ thick 50nm as a semiconductor layer constituting a part of the semiconductor layer and the gate stacked unit constituting a part of the signal line stacked unit It is formed by a CVD method. Semiconductor layer 1
3 The _0, for example, using an amorphous silicon film.

[0029] Subsequently, an insulating film 15 that constitutes a part of the semiconductor layer 13 ₀ channel protection film 15 on the signal line stacked unit
a and the insulating film 15 forming a part of the gate stacking portion
After forming an insulating film having a thickness of 200 nm to be b by the CVD method, the insulating film is patterned to form the channel protective film 15 and the insulating films 15a and 15b. Incidentally, the insulating film 15, 15a, 15b, the insulating film 12 ₀ and the semiconductor layer 13 ₀ may be continuously formed by a film formation method other than CVD method.

Next, as shown in FIG. 2C, the ohmic contact layer 14, the semiconductor layer 14a forming a part of the signal line stacking portion, and the semiconductor layer 14b forming a part of the gate stacking portion are formed on the entire surface. A low-resistance semiconductor layer, for example, an n ⁺ -type amorphous silicon film
After forming the VD method, this and the semiconductor layer 13 ₀ is patterned, the semiconductor layer constituting the ohmic contact layer 14, the active layer 13, a part of the signal line stacked unit 1
3a, 14a and semiconductor layers 13b, 14b constituting part of the gate stacking portion are formed.

Next, as shown in FIG. 2D, the pixel electrode 16 and the conductive film 1 forming a part of the signal line stacking portion are formed on the entire surface.
6a and the conductive film 1 forming a part of the gate stacking portion
After forming an ITO film having a thickness of, for example, 150 nm by sputtering, the insulating film ₁₂₀ is patterned to form a pixel electrode 16, a gate insulating film 12, and a conductive film 16a constituting a part of a signal line stacking portion. And insulating film 1
2a (= 12), and a conductive film 16b and an insulating film 12b which form part of the gate stacking portion are formed.

Next, as shown in FIG.
After a metal film such as Mo or Mo is formed to a thickness of 400 nm by a sputtering method, this is patterned and the source / drain electrodes 17 and 18, the conductive film 18a constituting a part of the signal line stacking portion, and the gate stacking portion are formed. The conductive film 18b constituting a part is formed.

Finally, after the ohmic contact layer 14 on the channel protective film 15 is removed, an insulating film such as a silicon nitride film is deposited on the entire surface, and is patterned to form a TFT.
By forming the protective film 19, the basic structure of the array substrate is completed.

FIG. 3 shows a signal line drive I on the array substrate.
It is a schematic diagram which shows the state which mounted C20 by COG. An electrode 21 and a bump 22 are formed on the signal line driving IC 20.

In this embodiment, the same conductive film 11a as the gate electrode 11, the same insulating film 12a as the gate insulating film 12, the same semiconductor layer 13a as the active layer 13, the ohmic contact Since a signal line stacking portion including the same low-resistance semiconductor layer 14a as the layer 14, the same insulating film 15a as the channel protective film 15, and the same conductive film 16a as the pixel electrode 16 is provided, the signal line driving IC 20 The load 23 applied to the signal line extraction electrodes 18a and the bumps 22 when COG is mounted by COG is absorbed or dispersed by various layers and films constituting the signal line stacking portion.

Therefore, according to the present embodiment, it is possible to prevent a connection failure due to cracks in the electrodes such as the signal line extraction electrode 18a and the bumps 22 due to the above-mentioned load, and a reduction in reliability due to the connection failure.

In the case of the present embodiment, since the cross-sectional shape of the signal line stacking portion is trapezoidal, the step coverage of the signal line extraction electrode 18a is good, and
Thus, it is possible to prevent a decrease in reliability due to disconnection of the signal line extraction electrode 18a.

Further, since the height of the bumps 22 can be made lower than that of the prior art by the signal line stacking portion, the formation of the bumps 22 by photolithography (for example,
2 patterning step) becomes easy. Such an effect can be obtained also in the gate electrode extraction portion.

Therefore, according to the present embodiment, the driving I
Even if C (TFT driving IC, signal line driving IC) is mounted on the array substrate by COG, a liquid crystal display device which does not cause a decrease in reliability can be obtained.

FIG. 4 is a sectional view of an array substrate of a liquid crystal display device on which a signal line driving IC according to a second embodiment of the present invention is mounted by COG. Note that portions corresponding to the array substrate on which the signal line driving IC of FIG. 3 is mounted by COG are denoted by the same reference numerals as in FIG. 3, and detailed description thereof will be omitted.

This embodiment is different from the previous embodiment in that instead of forming the electrodes 21 and the bumps 22 on the signal line driving IC 20, the signal line driving IC has connection electrodes having the same structure as the signal line stacking portion. Has been formed.

That is, the conductive film 11a 'and the insulating film 12a
′, Semiconductor layer 13a ′, semiconductor layer 14a ′, insulating film 15
A connection electrode having the same structure as the signal line stacking portion composed of a ′ and the conductive film 16a ′ is provided on the signal line driving IC 20.

Also in this embodiment, similarly to the previous embodiment, it is possible to prevent a decrease in reliability due to cracks. Furthermore, according to the present embodiment, since bumps are not required, various problems caused by the bumps can be solved.

FIG. 5 is a sectional view of an array substrate of a liquid crystal display device on which a signal line driving IC according to a third embodiment of the present invention is mounted by COG. This embodiment is different from the first embodiment in that only the electrodes 21 are formed on the signal line driving IC instead of forming the electrodes 21 and the bumps 22 on the signal line driving IC 20. Also in this case, no bump is required, and the same effect as in the second embodiment can be obtained.

FIG. 6 is a sectional view of an array substrate of a liquid crystal display according to a fourth embodiment of the present invention. This embodiment is different from the first embodiment in that a coplanar TFT is used instead of the inverted staggered TFT. In addition,
Parts corresponding to the array substrate in FIG. 1 are denoted by the same reference numerals as in FIG. In the drawing, reference numeral 24 denotes an interlayer insulating film.

According to the present embodiment, since the various films constituting the coplanar type TFT and the stacked portions formed of the same films and layers as the various layers are formed, the same effects as those of the first embodiment can be obtained. .

The same effect as in the first embodiment can be obtained by using a staggered TFT instead of the coplanar TFT. In the second and third embodiments, a coplanar TFT or a staggered TFT may be used instead of the inverted staggered TFT.

FIG. 7 is a perspective view of a liquid crystal panel of a liquid crystal display according to a fifth embodiment of the present invention. Also,
FIG. 8 is a sectional view of the liquid crystal panel of FIG. On the array substrate 31, a counter substrate 32 is connected. A driving IC 33 is provided on the array substrate 31 around the counter substrate 32. The driving IC 33 is connected to the array substrate 31 via the bump 34.

The array substrate 31 is, as in the previous embodiment,
It is formed from a glass substrate, pixel electrodes arranged in a matrix on the glass substrate, and TFTs as switching elements provided for each pixel electrode. Driving IC3
Reference numeral 3 is formed of a glass substrate and a semiconductor element formed thereon. 0.3mm thick glass substrate
~ 1.5 mm is common, but often 0.5 mm ~
It is manufactured in a range of 1.1 mm. In this embodiment, the thickness H _A of the driving IC 33 is 0.9 mm, the thickness H _B of the opposing substrate 32 is 0.9 mm, and the thickness H _IC of the semiconductor element is 1.1 mm.

In this embodiment, as described above, the driving IC 33 having the semiconductor element formed on the glass substrate is used. That is, the substrate material of the driving IC 33 and the substrate material of the array substrate 31 are the same. For this reason, the array substrate 31 and the driving IC
Since the expansion and contraction of the 33 are substantially the same, the thermal distortion applied to the array substrate 31, the bump 34, and the driving IC 33 is reduced.

Therefore, according to the present embodiment, the connection between the array substrate 31 and the bumps 34, the connection between the driving IC 33 and the bumps 34, and the breaks inside the bumps 34 can be prevented, and the reliability can be improved. The improvement can be achieved.

Further, by determining the thickness of the driving _IC 33 so that H _IC ≤ H _A or H _IC ≤ H _B , it is possible to prevent the driving IC 33 from being damaged.

FIG. 9 is a developed view of a liquid crystal panel of a liquid crystal display according to a sixth embodiment of the present invention. The main difference between the liquid crystal panel of the present embodiment and that of the fifth embodiment is that one driving IC 40 is mounted on each of the source side and the gate side around the pixel section.

In order to prevent damage caused by the drive IC 40 protruding from the liquid crystal panel, an H _IC
The thickness of the driving IC 40 is determined so that ≦ H _B. Specifically, the thickness _HA of the array substrate 41 is set to 1.1 m.
m, the thickness H _B of the opposing substrate 42 was also 1.1 mm, and the thickness H _IC of the driving _IC 40 was also 1.1 mm.
The pixel area is 5.6 inches diagonally.

In the case of this embodiment, since the driving IC is one on each side, the driving IC itself becomes large, and it is necessary to consider the strength. However, the thickness H _IC of the driving _IC 40 is set to 1.1 mm.
(H _IC ≦ H _B ), so damage can be prevented.

The assembling is performed by mounting the drive I on the array substrate 41.
After mounting the C40, the printed circuit board 44 and the flexible printed circuit board 45 are connected to the C40, and subsequently, are fitted into the mold frame 46. Finally, the shield case 43 is fitted from above and below.

FIG. 10 is a sectional view of a liquid crystal panel of a liquid crystal display according to a seventh embodiment of the present invention. This embodiment is an example of a liquid crystal display device using a simple dot matrix panel.

In the simple dot matrix panel, wiring made of a transparent conductive film such as ITO is formed on the array substrate 31 and the counter substrate 35, and the wiring of the array substrate 31 and the wiring of the counter substrate 35 are orthogonal to each other. As described above, the array substrate 31 and the counter substrate 35 are overlaid.
The driving IC 33 is connected to the wiring of the array substrate 31 and the counter substrate 35, and satisfies the relations of H _IC ≦ H _A and H _IC ≦ H _B.

In the simple dot matrix panel, the thicknesses of the array substrate 31 and the counter substrate 35 may be the same as in the case of the active matrix panel described above, and are 0.9 mm in this embodiment. The thickness of the driving IC 33 was 0.7 mm. Of course, the thickness of the array substrate 31 and the thickness of the opposing substrate 35 may be different.
mm, and the thickness of the counter substrate 35 may be 0.9 mm.
In this case, the thickness of the driving IC 33 is, for example, 0.7 m
m.

FIG. 11 is a sectional view of a liquid crystal panel of a liquid crystal display according to an eighth embodiment of the present invention. The feature of this embodiment is that the end surface of the glass substrate constituting the driving IC 50 is chamfered. By chamfering the end surface of the glass substrate, breakage due to cleavage from the end surface of the glass substrate can be prevented, and the reliability can be further improved. In addition, the chamfering of the end face of the glass substrate is performed by setting the end face to R
The same effect can be obtained by making the shape.

Next, a method of manufacturing a main part of the driving IC will be described. That is, a method for forming a semiconductor element on a glass substrate as a substrate will be described. Here, a coplanar TFT will be described as an example of the semiconductor element.

First, as shown in FIG. 12A, after a polysilicon film to be an active layer 62 is formed on a light-transmitting insulating substrate 61, the polysilicon film is patterned by photolithography to obtain a predetermined shape.・ Dimensional active layer 62
Get.

Here, as the translucent insulating substrate 61, for example, a substrate made of quartz or glass, or a substrate whose surface is coated with insulation is used. The thickness of the active layer 62 is, for example, 50 nm. Examples of the film formation method include a method of forming a polycrystalline silicon film from an amorphous silicon film by solid phase growth, and a method of plasma CVD.
, An amorphous silicon film is formed by a CVD method such as the LPCVD method, and then the amorphous silicon film is crystallized by laser annealing to form a polysilicon film, or a method of forming a SiH ₄ , SiF ₄ , H ₂
There is a method in which a polysilicon film is directly formed by a plasma CVD method using such as a raw material gas.

Next, as shown in FIG. 12B, after forming a gate insulating film 63 on the entire surface, a gate electrode 64 is formed. Here, as the gate insulating film 63, for example, an oxide film such as a silicon oxide film or a nitride film such as a silicon nitride film is used, and its thickness is, for example, 100 nm.

As a method of forming the gate insulating film 63, for example, an APCVD method, a plasma CVD, an ECR-CVD
A CVD method such as a CVD method is used. Alternatively, after the polysilicon film is formed, a part thereof may be thermally oxidized.

The thickness of the gate electrode 64 is, for example, 250
nm. As a material of the gate electrode 64, for example, a metal such as Al, W, Mo, Ta, an alloy or silicide of these metals, or polysilicon doped with an impurity is used.

Next, as shown in FIG. 12C, for example,
Using the gate electrode 64 as a mask, phosphorus (P) is dosed at a dose of 5
The source region 62a and the drain region 62b are formed by ion implantation under the condition of × 10 ¹⁵ cm ⁻³ . Thereafter, activation of impurities (phosphorus) is performed by thermal annealing or excimer laser annealing.

Next, as shown in FIG. 12D, after an interlayer insulating film 65 having a thickness of about 350 nm is formed on the entire surface, the source region 62a and the drain region 62 are formed on the interlayer insulating film 65.
Open a contact hole for b.

Next, an aluminum film having a thickness of about 400 nm serving as a source electrode 66 and a drain electrode 67 is formed on the entire surface by sputtering, and then the aluminum film is patterned to form a source electrode 66 and a drain electrode 67. Note that a source electrode 66 and a drain electrode 67 made of gold, copper, silver, platinum, and palladium may be formed instead of aluminum.

Finally, as shown in FIG. 12E, after forming a protective film 68 made of an insulating film such as a silicon oxide film or a silicon nitride film, a drain electrode 67 is formed on the protective film 68.
Then, a contact hole for taking out the light is opened, and the basic structure of the coplanar TFT is completed. Thus, a structure in which the uppermost layer electrode (drain electrode 67) is exposed is obtained.

Although only the TFT has been described here, an active semiconductor element (for example, a bipolar transistor or a CMOS) can be similarly formed. Next, a method for forming a bump of the semiconductor element (coplanar TFT) of the driving IC will be described.

After cleaning the surface of the uppermost layer electrode (drain electrode 67), a titanium layer (lower layer) / nickel layer (lower layer) having a role of an adhesive layer or a barrier layer and a role of a base electrode for plating on the surface. Middle layer / palladium layer (upper layer) 3
A layer laminated film is formed by a sputtering method.

Next, a gold bump is formed on the palladium layer. As a method of forming a gold bump, there is a method of forming a metal film to be a gold bump and then patterning the same by photolithography, a thin film forming method, a printing method, a transfer method, and the like. In addition, here, gold is used as the material of the bump, but solder, copper, nickel, aluminum, or the like may be used instead. The resist used in the method of forming a bump by photolithography may be either a positive resist or a negative resist.

Next, a method of connecting the driving IC to the array substrate will be described. As described above, the bumps are formed on the semiconductor elements of the driving IC, while the wirings are formed on the array substrate. The wiring may be a material having conductivity, but generally, a material used in a liquid crystal panel manufacturing process is desirable.

More specifically, in the manufacturing process of the liquid crystal panel, a transparent conductive film such as ITO or SnO ₂ , aluminum, molybdenum, tantalum, chromium, nickel, tungsten, titanium, panadium, palladium, zirconium, niobium, platinum, A simple metal such as cobalt or an alloy of the above simple metals such as molybdenum-tungsten is used. Among them, ITO, aluminum, molybdenum, molybdenum-tungsten, and tantalum are frequently used, and among them, aluminum and ITO are most frequently used.

The connection method between the driving IC and the array substrate is as follows.
Various selections can be made depending on the wiring material and bump material. For example,
When the bump material is gold and the wiring material is ITO, a method of connecting on the gold bump via a conductive paste such as silver base, a method of connecting via an anisotropic conductive adhesive, or a method of directly insulating There is a method of connecting only through a conductive resin.

If the bump material is gold and the wiring material is aluminum, for example, solid phase diffusion connection is used. In this case, for example, the semiconductor element is heated to 350 ° C., the liquid crystal panel is heated to 80 °, and 15 g per bump is used.
It is good to press-contact with a load of 1 second.

When the array substrate and the driving IC were connected by the above-described process, and the operation of the liquid crystal panel was examined by displaying an image, it was confirmed that the liquid crystal panel was operating as specified. In this embodiment, the connection between the semiconductor element (drive IC) on which the bumps are formed and the array substrate has been described. However, since the periphery of the general semiconductor element electrode is protected by passivation or the like, It is slightly concave. For this reason, it is necessary to newly form a bump which is an electrode on the protrusion. However, when the electrode is convex, the semiconductor element may be directly connected to the array substrate without forming a bump. Instead of forming bumps, fine conductive particles may be selectively arranged and used as bumps.

The present invention is not limited to the embodiment described above. For example, the above embodiments may be appropriately combined. In addition, without departing from the gist of the present invention,
Various modifications can be made.

[0080]

As described above in detail, according to the present invention, when the control means is mounted, the load applied to the extraction electrode is the second.
Is effectively absorbed / dispersed by the extraction electrode, so that it is possible to prevent a decrease in reliability that may occur when the control means is mounted.

Further, by using the second extraction electrode having a multilayer structure, the height of the extraction electrode is made higher than in the conventional case, and thus, for example, when the control means is mounted by COG, A bump with a low height can be used, and a decrease in reliability due to the bump can be prevented.

[Brief description of the drawings]

FIG. 1 is a sectional view of an array substrate of a liquid crystal display device according to a first embodiment of the present invention.

FIG. 2 is a sectional view showing a step of the method for manufacturing the array substrate of FIG. 1;

FIG. 3 is a schematic diagram showing a state where the signal line driving IC 20 is mounted on the array substrate by COG.

FIG. 4 is a sectional view of an array substrate of a liquid crystal display device on which a signal line driving IC according to a second embodiment of the present invention is mounted by COG;

FIG. 5 is a sectional view of an array substrate of a liquid crystal display device on which a signal line driving IC according to a third embodiment of the present invention is mounted by COG.

FIG. 6 is a sectional view of an array substrate of a liquid crystal display according to a fourth embodiment of the present invention.

FIG. 7 is a perspective view of a liquid crystal panel of a liquid crystal display according to a fifth embodiment of the present invention.

FIG. 8 is a sectional view of the liquid crystal panel of FIG. 7;

FIG. 9 is a development view of a liquid crystal panel of a liquid crystal display device according to a sixth embodiment of the present invention.

FIG. 10 is a sectional view of a liquid crystal panel of a liquid crystal display device according to a seventh embodiment of the present invention.

FIG. 11 is a sectional view of a liquid crystal panel of a liquid crystal display device according to an eighth embodiment of the present invention.

FIG. 12 is a process cross-sectional view illustrating the method of manufacturing the driving IC.

FIG. 13 is a perspective view showing a configuration of an array substrate of a conventional liquid crystal display device.

FIG. 14 is a schematic view showing a configuration of an array substrate of a conventional liquid crystal display device.

FIG. 15 is a cross-sectional view showing the configuration of a conventional array substrate when an inverted staggered TFT is used as a switching element.

FIG. 16 is a sectional view showing a main part of an array substrate on which a signal line driving IC is mounted by COG;

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Translucent insulating substrate, 2 ... Inverted stagger TFT, 11 ... Gate electrode, 12 ... Gate insulating film, 13 ... Active layer, 14 ... Ohmic contact layer, 15 ... Channel protective film, 16 ...
Pixel electrodes, 17, 18, source / drain electrodes, 19 ...
TFT protective film, 20: signal line driving IC, 21: electrode,
22 ... Bump

Continuation of the front page (72) Inventor Masayuki Saito 33, Shinisogo-cho, Isogo-ku, Yokohama-shi, Kanagawa Prefecture Inside Toshiba Production Technology Laboratory Co., Ltd. (56) References JP-A-62-297820 (JP, A) 29829 (JP, U) (58) Field surveyed (Int. Cl. ⁷ , DB name) G02F 1/1345 G02F 1/1368

Claims (2)

(57) [Claims] 1. A pixel section comprising a matrix of pixel electrodes arranged on an insulating substrate, an inverted staggered thin film transistor as a switching element provided on each pixel electrode, and a pixel section surrounding the pixel section on the insulating substrate. Provided, said
Source and drain electrodes of the inverted staggered thin film transistor
And a signal line electrode extraction portion connected contrast to, via the signal line electrode extraction portion connected to the inverted staggered thin film DOO <br/> transistor, and a control means for controlling the inverted staggered thin film transistor becomes, the signal wire electrode take-out portions is composed of a signal line extraction electrode, a stacked portion formed in the lower portion of the signal line extraction electrode, the signal line extraction electrodes, the inverted staggered thin film Trang < br /> formed from the source and drain electrodes of the same conductive film register, the stacked unit, the same conductive film as the gate electrode of the inverted staggered thin film transistor, the inverted staggered thin film Trang
The same insulating film as the gate insulating film of the transistor, the inverted stagger type
The same semiconductor layer as the active layer of the thin film transistor;
Same as ohmic contact layer of tag type thin film transistor
One low resistance semiconductor layer, the inverted staggered thin film transistor
The same insulating film as the channel protective film of the pixel and the pixel electrode
A liquid crystal display device formed of the same material as at least one of the same conductive films . Wherein said control means is a liquid crystal display device according to claim 1, wherein a signal line electrode extraction portion driving IC is COG-mounted on <br/>.