JP3231487B2 - Active matrix type liquid crystal display - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an active matrix type liquid crystal display device, and more particularly to a structure of a liquid crystal display device in which a transparent electrode film serving as a pixel electrode is disposed above a thin film transistor serving as a switching element with an insulating film interposed therebetween.

[0002]

2. Description of the Related Art In recent years, liquid crystal display devices have great advantages such as thin and light weight and low power consumption.
It is frequently used for display devices of the A-apparatus, and at the same time, there is a strong demand for improvement of manufacturing techniques and display characteristics of liquid crystal display devices. In particular, an active matrix type comprising a TFT array substrate in which a three-terminal device such as a thin film transistor (hereinafter referred to as a TFT) is connected to each pixel electrode as a switch, and a counter substrate having a counter electrode. The liquid crystal display device is easy to obtain a large screen,
Attention has been paid to the fact that conventional semiconductor manufacturing technology can be applied to manufacturing.

In an active matrix type liquid crystal display device, a TFT on a TFT array substrate and a transparent pixel electrode made of ITO or the like are electrically connected by metal wiring or the like. In making electrical connection, a TFT array substrate structure in which a signal line for transmitting a screen display signal to a TFT and ITO are not arranged on the same layer, but ITO is arranged on the signal line via an insulating film. It has been proposed in recent years for the following reasons.

One of them is to form an ITO film on an upper layer of a signal line via an interlayer insulating film and to etch the same, thereby forming an IT.
This is to prevent a cross short between the signal line and the ITO due to the residual at the time of O etching. The two are TFT
Is a polysilicon TFT, in order to maintain consistency between the TFT process and the film quality of the ITO, after the TFT process is completely completed, an insulating film is formed on the TFT, a contact hole is opened, and then the ITO is formed. Is formed and etched to form a pixel electrode.

A conventional liquid crystal display having the above-described structure will be described with reference to FIG. In the sectional view of the conventional TFT array substrate shown in FIG. 2, the TFT was a coplanar structure N-type polysilicon TFT. A polysilicon layer 2 serving as an active layer is formed on a quartz substrate 1 by a chemical vapor deposition (CVD) method and is etched in an island shape.
The polysilicon layer 2 is oxidized at a high temperature in an oxygen atmosphere to form a thermal oxide film serving as the gate insulating layer 3. Then, the gate electrode 4 is formed again by the CVD method and etching is performed. In this state, arsenic (As) is implanted into the polysilicon layer 2 by an ion implantation method using the gate electrode 4 as a self-alignment mask, and then arsenic (As) is activated by high-temperature annealing, so that the polysilicon layer 2 has a high concentration. Impurity regions 5 and 6 are formed. Next, after the first interlayer insulating layer 7 is formed by the CVD method, the drain side contact hole 8 is opened by etching the first interlayer insulating layer 7 and the gate insulating layer 3. Next, a metal such as an aluminum (Al) alloy is formed by a sputtering method. At this time, the Al alloy contacts the high-concentration impurity region 5 and forms the signal line 9 by etching. At this time, the external terminal connection pads 10 are formed simultaneously with the signal lines 9. Further, by performing a hydrogen passivation process using a plasma CVD device or the like, the N-type polysilicon T
FT is completed.

Subsequently, after forming the second interlayer insulating layer 11 again by the CVD method or the like, the source side contact hole 12 is etched by etching the second interlayer insulating layer 11, the first interlayer insulating layer 7, and the gate insulating layer. To open. Next, ITO serving as a pixel electrode is formed by a sputtering method. At this time, the ITO makes contact with the high-concentration impurity region 6 and forms the pixel electrode 13 by etching. Further, the pad contact holes 14 are opened by etching the second interlayer insulating layer 11, and the entire array process is completed.

[0007]

However, in the above-described structure, three different types of insulating layers, a thermal oxide layer, a first interlayer insulating layer, and a second interlayer insulating layer, are etched to form a source-side contact hole. Must be opened. For this reason, a step is likely to occur at the interface between different insulating layers during etching, and it is difficult to open a contact hole having a normal shape. Furthermore, since the aspect ratio of the contact hole becomes large, ITO
The margin of the coverage in the film formation is reduced. As a result, physical contact between the ITO and the high-concentration impurity region becomes difficult, and there is a problem that a failure due to the disconnection of the ITO is likely to occur.

In addition, the method of obtaining electrical contact by directly contacting ITO with a high-concentration region in which impurities are donors has a problem that electrical contact becomes difficult due to a large contact resistance of several kilohms. Furthermore, in the above-mentioned conventional example, there is a problem that it is extremely difficult to selectively etch the underlying Al alloy when opening the contact hole in the pad portion.

Regarding the improvement of contact resistance, ITO
And a high-concentration impurity region through a contact metal. The method will be described with reference to FIG. In this method, the steps up to the hydrogen passivation process are the same as those in the above-described conventional example, and the subsequent steps will be described. The drawing numbers are the same. After the hydrogen passivation process is completed, the second interlayer insulating layer 11 is formed again by the CVD method or the like, and then the second interlayer insulating layer 11, the first interlayer insulating layer 7, and the gate insulating layer 3 are etched to form a source side contact. A hole 12 is opened. Here, a contact metal is formed by a sputtering method. At this time, the contact metal 15 is formed by making contact with the high-concentration impurity region 6 and etching. In addition, chromium (Cr), tantalum (Ta), titanium (Ti),
Refractory metals such as molybdenum (Mo) and tungsten (W) and silicides thereof such as tungsten silicide (WSi) are used. Next, ITO as a pixel electrode is formed by a sputtering method. Then I
The TO forms contact with the contact metal 15 and forms the pixel electrode 13 by etching. Further, the pad contact hole 14 is opened by etching the second interlayer insulating layer 11, and the entire array process is completed. With such a structure, the resistance is provided via the contact metal, so that the contact resistance between the TFT and the pixel electrode is several hundred Ω or less.

In this case, however, the electrical contact is improved, but the physical contact is not. That is, there is a problem in that it is difficult to perform etching at the time of opening the source-side contact hole, and a defect is likely to occur due to disconnection of the contact metal. Furthermore, the problem that the selective etching with the underlying Al alloy is very difficult when opening the contact hole in the pad portion has not been solved. In addition, as compared with the conventional example shown in FIG. 2, there is a problem that the number of steps for forming and etching the contact metal increases and the manufacturing cost increases.

The present invention has been made in view of such a problem, and the connection between a TFT and a pixel electrode can be made with low-resistance electrical contact and physical contact having a large process margin without increasing the number of steps. It is another object of the present invention to provide a liquid crystal display device provided with a TFT array having a structure in which a contact hole of a pad portion can be selectively etched with a base.

[0012]

The liquid crystal display device of the present invention comprises a substrate, a plurality of thin film transistors arranged in a matrix on the substrate, a signal line transmitting a screen display signal to the thin film transistor, and an external connection. As an element
Pads and is disposed through the upper insulating layer before Symbol thin film transistor and the signal line, and an active matrix type liquid crystal display device having a thin film transistor array substrate having a pixel electrode respectively electrically connected to the thin film transistor Wherein the electrical resistivity between the thin film transistor and the pixel electrode is at least 5 × 10
^-6 Ωcm or less is electrically connected via a multilayer wiring layer including one wiring layer selected from a metal or an alloy wiring layer thereof, and the electrical connection is such that the uppermost layer of the multilayer wiring layer is connected to the pixel electrode. And the lowermost layer is formed between the high concentration impurity region of the thin film transistor and the uppermost layer of the multilayer wiring layer is a conductive layer other than the metal or its alloy layer, and the metal or its alloy layer selectively made of conductive layers which may be etched, said pad wherein
The multilayer wiring layer on the pad surface formed of a multilayer wiring layer
Is removed to expose the metal or its alloy layer
It is characterized by doing.

The electrical resistivity according to the present invention is 5 × 10 ^-6 Ωcm
The following metals are metals having a low resistivity required for a wiring layer, and are used for the active matrix type liquid crystal display device.
A metal that can be used as a wiring layer of an FT array substrate.
Including those alloys. Specifically, gold (Au; ρ = 2.35)
× 10 ⁻⁶ Ωcm), silver (Ag; ρ = 1.59 × 10 ⁻⁶ Ωcm), copper (Cu; ρ = 1.67 × 10 ⁻⁶ Ωcm), aluminum (Al;
ρ = 2.65 × 10 ⁻⁶ Ωcm). Among these, Al which is easy to handle and can reduce the sheet resistance of the wiring is particularly preferable. Examples of these alloys include alloys of these metals and silicides.

A multilayer wiring layer including at least one wiring layer selected from a metal or an alloy wiring layer having an electrical resistivity of 5 × 10 ⁻⁶ Ωcm or less includes at least one of the above-described metal layers,
It is a multi-layer wiring layer combining other conductive layers. Materials that can be used as other conductive layers include tantalum (Ta), molybdenum (Mo), titanium (Ti), and tungsten (W).
Such as high melting point metal and tungsten silicide (WS
These silicides and the like can be used. Further, the uppermost layer of the multilayer wiring layer is a metal other than the above-mentioned metal layer, and is a conductive layer that can be selectively etched with this metal or its alloy layer. Here, “selectively etching” means that the etching rate of the metal or its alloy layer and the conductive layer can be arbitrarily selected by optimizing the etching conditions. With such a structure, the electrical connection with the ITO becomes good, and the opening of the contact hole in the pad portion becomes extremely easy. It is preferable that the lowermost layer of the multilayer wiring layer is made of a material having a high adhesion strength to polysilicon or the like and capable of preventing Al from diffusing into polysilicon.

This multilayer wiring layer can also be used as a signal line for transmitting a screen display signal to the TFT. The same structure of the multilayer wiring layer and the signal line shortens the manufacturing process and improves physical properties. It is more preferable that electrical contact or the like can be obtained. That is, a first interlayer insulating layer is formed on a TFT formed on a transparent substrate such as a quartz substrate, a contact hole is opened, and a signal line and a contact line are formed in the same step by the above-described multilayer wiring layer. I do. A second interlayer insulating layer is formed thereon, a contact hole is opened, and ITO is formed.
Is formed, the electrical contact between the TFT and the pixel electrode is obtained between the TFT, the multilayer wiring layer, and the ITO, and at the same time, the uppermost layer of the multilayer wiring layer can be used as a barrier when the pad portion contact hole is opened. it can.

The TFT substrate according to the present invention can be applied to TFTs having various structures such as a planar structure TFT. Also,
The active layer can be made of polysilicon, amorphous silicon, single crystal silicon, or the like.
Type or P type.

The active matrix type liquid crystal display device of the present invention can be obtained by attaching a driving circuit to the above-mentioned TFT substrate, facing the opposite substrate, and sandwiching the liquid crystal composition therebetween.

[0018]

By interposing the above-mentioned multilayer wiring layer, a low-resistance electrical contact and a physical contact having a large process margin can be obtained in the connection between the TFT and the pixel electrode. Further, the opening of the pad contact hole can be formed by selective etching.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail with reference to the drawings. Embodiment 1 FIG. 1 is a sectional view of an N-type polysilicon TFT array substrate having a coplanar structure used in an active matrix type liquid crystal display device of the present invention. A polysilicon layer 2 serving as an active layer is formed on a quartz substrate 1 by a chemical vapor deposition (CVD) method and is etched in an island shape. The polysilicon layer 2 is oxidized at a high temperature in an oxygen atmosphere to form a thermal oxide film serving as the gate insulating layer 3. Then, the gate electrode 4 is formed again by the CVD method and etching is performed. In this state, arsenic (As) is implanted into the polysilicon layer 2 by an ion implantation method using the gate electrode 4 as a self-alignment mask, and then arsenic (As) is activated by high-temperature annealing, so that the polysilicon layer 2 has a high concentration. Impurity regions 5 and 6 are formed.

Next, after the first interlayer insulating layer 7 is formed by the CVD method, the first interlayer insulating layer 7 and the gate insulating layer 3 are etched to form the drain side contact hole 8.
And the first source side contact hole 16 are simultaneously opened. Next, an aluminum alloy such as Al-Si or Al-Si-Cu is used as a lower layer film, tungsten silicide (WSi).
Is formed as the upper layer film by sputtering. At this time, the Al alloy which is the lower layer film of the two-layer metal wiring comes into contact with the high-concentration impurity regions 5 and 6 at the same time. By etching the two-layer metal wiring, the signal line 9, the external terminal connection pad 10, and the contact wiring 17 having the two-layer metal wiring are formed.

Further, an N-type polysilicon TF is formed by performing a hydrogen passivation process using a plasma CVD device or the like.
T is completed.

Subsequently, after the second interlayer insulating layer 11 is formed again by the CVD method or the like, the second source side contact hole 1 is formed.
8 is opened by etching only the second interlayer insulating layer 11. Here, ITO serving as a pixel electrode is formed by a sputtering method. At this time, the ITO makes contact with the upper layer film WSi of the contact wiring 17 and etches to form the pixel electrode 13. Further, a pad contact hole 14 is opened by etching the second interlayer insulating layer 11. By making the second interlayer insulating layer of SiO ₂ or SiN _X , this insulating layer becomes CHF ₃
And it can be etched with a mixed gas of O ₂ but, WSi becomes etched difficult etching stopper at the top of the external terminal connection pad 10. Therefore, etching of the second interlayer insulating layer at the time of forming the pad contact hole is suppressed on the WSi surface. If the WSi remaining on the pad portion is etched and stripped by CDE using an F-based gas, the Al alloy under the pad is not etched, and the pad surface as an external connection terminal is not damaged. The alloy is exposed.
As a result, the external connection terminals are wire-bonded, T
AB or the like can be easily bonded. Thus, all the steps of the TFT array are completed.

In this TFT array, the pixel electrode 13
In this case, it is only necessary to cover ITO with respect to the thickness of the second interlayer insulating layer 11. Further, since the opening of the second source-side contact hole 18 is an opening of only the single layer of the second interlayer insulating layer 11, a step which is easily generated at an interface between different insulating layers does not occur. Therefore, the disconnection failure can be remarkably improved, and the process margin in physical contact can be increased.

On the other hand, regarding the electrical contact, the high-concentration impurity region 6 and the ITO as the pixel electrode 13 are connected via the contact wiring 17. The contact resistance in this case is 1
8 Ω. On the other hand, the contact resistance between the high-concentration impurity region 6 and the ITO in the conventional TFT array shown in FIG. 2 was 3 to 5 KΩ. The conventional TFT shown in FIG.
When the array is improved and the high-concentration impurity region 6 and the ITO are connected via the contact metal, the contact resistance becomes 48
Ω.

With respect to the number of manufacturing steps of the TFT array, the first source-side contact hole 16 is opened at the same time as the drain-side contact hole 8, and the contact wiring 17 is formed and etched at the same time as the signal line 10. The number of manufacturing steps does not increase as compared with a TFT array having a structure.

Further, in this embodiment, the second interlayer insulating layer 11 and the external terminal connection pad 10 can be selectively etched when the pad contact hole is opened, and the external terminal connection pad underlayer can be formed. It is also possible to make the pad surface an Al alloy by selective etching with the Al alloy.

Using the obtained TFT array, an active matrix type liquid crystal display device is assembled by a conventional method, and when lit, there is no point defect or line defect, and there is no display unevenness. The device was obtained.

[0028]

According to the active matrix type liquid crystal display device of the present invention, at least one wiring selected from a low resistivity metal such as Al or an alloy wiring layer thereof is formed between the TFT and the pixel electrode of the TFT array substrate. Electrical connection is made via a multilayer wiring layer including the layers, and the electrical connection is made between the uppermost layer of the multilayer wiring layer and the pixel electrode, and between the lowermost layer and the high concentration impurity region of the TFT, And the uppermost layer is other than a low resistivity metal such as Al or its alloy layer, and
And so on, the connection having electrical contact with low contact resistance and physical contact with large process margin is T
It is obtained between the FT and the pixel electrode. Further, it is possible to open the pad contact hole while maintaining the selectivity with the alloy such as Al constituting the external terminal connection pad. Further, since the contact wiring and the signal line can be formed simultaneously, the number of manufacturing steps of the TFT array substrate is not increased. As a result, an active matrix type liquid crystal display device having no display defect and no line defect and excellent display quality without display unevenness can be obtained.

[Brief description of the drawings]

FIG. 1 is a diagram showing a cross section of a TFT array substrate obtained by a method according to an embodiment.

FIG. 2 is a diagram showing a cross section of a conventional TFT array substrate.

FIG. 3 is a diagram showing a cross section of a conventional TFT array substrate in which contact resistance between a TFT and a pixel electrode is improved.

[Explanation of symbols]

1 ... quartz substrate, 2 ... polysilicon layer, 3 ...
Gate insulating layer, 4 ... Gate electrode, 5, 6 ... High-concentration impurity region, 7 ... First interlayer insulating layer, 8 ... Drain side contact hole, 9 ... Signal line, 10 ... ......
External terminal connection pad, 11... Second interlayer insulating layer, 1
2 ... source side contact hole, 13 ... pixel electrode, 14 ... pad contact hole, 15 ...
Contact metal, 16... First source side contact hole, 17... Contact wiring, 18... Second source side contact hole.

──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G02F 1/1368 G02F 1/1345 G09F 9/30 338 H01L 29/786

Claims (2)

(57) [Claims] 1. A substrate, a plurality of thin film transistors arranged in a matrix on the substrate, a signal line transmitting a screen display signal to the thin film transistor, and an external connection element
A pad as a child, is disposed through an insulating layer on top of the previous SL thin film transistor and the signal line, and an active matrix type having a thin film transistor array substrate having a respective electrically connected to a pixel electrode of the thin film transistor In the liquid crystal display device, between the thin film transistor and the pixel electrode, a multilayer wiring layer including at least one wiring layer selected from a metal or an alloy wiring layer having an electric resistivity of 5 × 10 ⁻⁶ Ωcm or less is interposed. The uppermost layer of the multilayer wiring layer is connected to the pixel electrode, the lowermost layer is connected to the high-concentration impurity region of the thin film transistor, and the multilayer wiring layer is electrically connected. Is a conductive layer other than the metal or its alloy layer, and is selectively etched with the metal or its alloy layer. Made of conductive layers which can, said pad being formed in the multilayer wiring layer and the path
The uppermost layer of the multilayer wiring layer on the pad surface is removed and the gold layer is removed.
An active matrix type liquid crystal display device, wherein a metal or an alloy layer thereof is exposed . 2. The active matrix type liquid crystal display device according to claim 1, wherein said electric resistivity is 5 × 10 ^−6.
An active matrix liquid crystal display device, wherein the metal or its alloy layer of Ωcm or less is aluminum or an aluminum alloy wiring layer.