JP2006154034A - Electronic device with electrostatic discharge protection - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a desirable TFT array structure with electrostatic discharge protection for forming an electronic device equipped with electrostatic discharge protection. <P>SOLUTION: An array substrate with electrostatic discharge protection comprises; a substrate; a plurality of conductive lines overlying the substrate along a first direction; and at least one conductive segment overlying the substrate between every two conductive lines, wherein each conductive segment is electrically isolated from the conductive lines. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to an electronic device, and more particularly to an electronic device having an array substrate having an electrostatic discharge (ESD) protection function.

  Electrostatic discharge (ESD) damage is a well-known event that affects the fabrication of thin film transistor (TFT) arrays. The electrostatic discharge mainly occurs because the TFT is formed on an insulating substrate such as glass, and the source and drain electrodes formed of a conductive material are charged to a very high voltage. Furthermore, since the peripheral circuit to which the TFT array is to be connected is not normally formed on the same substrate as the TFT array, the gate and source lines are connected to the TFT array through the wire bonding pads. In order to make the connection, it must be fully extended from the TFT array. The static electricity charged by the gate and the source line is transmitted not only to the intersection of the gate and the source line where the static electricity is held, but also to the gate and the source electrode of the TFT. If the static electricity reaches a sufficiently high level, the dielectric gate insulating layer between the gate and the source electrode may be destroyed. Even if this breakdown can be prevented, the voltage difference between the gate and the source electrode or the gate and the drain electrode caused by the held static electricity converts the threshold voltage of the TFT to either the positive or negative direction. There is a possibility to make it.

  Recently, particular attention has been directed to problems arising from electrostatic discharge damage in active matrix flat panel displays such as LCDs. Now, electrostatic discharge damage is also expected to be caused by equipment related to problems during manufacture, handling and testing of these types of devices. In addition to the use of high-speed mass processing equipment equipped with high-speed substrate processing, the trend toward miniaturization that reduces the metal line width during the manufacturing process and the parasitic capacitance of the TFT also reduces the electrostatic discharge resistance.

  Therefore, a more preferable TFT array structure having an electrostatic discharge protection function for forming an electronic device having an electrostatic discharge protection function is required.

  In accordance with various embodiments, an array substrate with electrostatic discharge protection is provided. The array substrate is provided on the substrate, the substrate, at least one of which is disposed between the two conductors of the plurality of conductors, and each includes a plurality of conductive portions that are electrically insulated from the conductors.

  In accordance with various embodiments, a display device with electrostatic discharge protection is provided. The display device includes a display panel and a controller connected to and driven by the display panel, and displays an image according to an input. The display panel is a substrate, a plurality of conductors on the substrate along a first direction, and on the substrate, at least one of which is installed between every two conductors of the plurality of conductors, Includes a plurality of conductive portions that are electrically insulated from the conducting wire.

  In accordance with various embodiments, a method for manufacturing an array substrate with electrostatic discharge protection is provided. The method includes providing a substrate and forming a plurality of gate lines connected by a first conductor on the substrate. An interlayer insulating film is subsequently formed on the gate line and the first conductive line, and a plurality of contact holes are subsequently formed on the interlayer insulating film on the first conductive layer. The portion of the underlying first conductive line between the gate lines is exposed. Next, a conductive layer is formed on the substrate and the contact hole. Subsequently, the conductive layer and the first conductive line under the contact hole are defined, and a plurality of the conductive layer on the gate line and at least one conductive part on the substrate between the two gate lines. A data line is formed.

  According to the electronic device having an array substrate having an electrostatic discharge (ESD) protection function of the present invention, electrostatic discharge damage can be prevented, and undesirable mura phenomenon caused in the TFT device in the pixel region due to electrostatic discharge damage can be reduced. be able to.

  In order that the objects, features, and advantages of the present invention will be more clearly understood, embodiments will be described below in detail with reference to the drawings. In addition, for example, the expression “on the substrate”, “on the layer”, or “on the film” is used in this specification to refer to the relative position with respect to the surface of the base layer regardless of the presence of the interlayer insulating film. It merely shows the relationship. Thus, these expressions may indicate not only the direct contact of the layers, but also the non-contact state of one or more stacks.

  FIG. 1 is a partial top view of an array substrate 1 having an electrostatic discharge (ESD) protection function according to an embodiment of the present invention. Here, the array substrate 1 is shown as an active matrix array substrate having a configuration of a liquid crystal display (LCD) device or an electroluminescent (EL) display device, but is not limited thereto.

  The array substrate 1 can include a plurality of pixel regions 12 formed on the substrate 10. A plurality of gate lines 14 on the substrate 10 in the column direction and a plurality on the substrate 10 in the row direction. Defined by the data line 16. Here, the pixel region 12 can be formed in the display region D, and each pixel region 12 can include a thin film transistor (TFT) region 18 electrically connected to the gate line 14 and the display region 20. In general, but not necessarily, a common electrode 22 can be formed between two adjacent gate lines 14 under each display area 20 along the column direction. The portion of the common electrode 22 below the pixel region 12 functions as a bottom electrode and can form a storage capacitor (not shown).

  Further, the conductive portion 24 can be formed on the substrate 10 between two adjacent gate lines 14 in the non-display region ND, and is insulated by the opening OP formed therebetween. The conductive portion 24 can also be formed on the substrate 10 between the common electrode 22 and its adjacent gate lines 14 that are substantially aligned. In addition, each gate line 14 and each common electrode 22 in the non-display region ND can include a pair of conductive fins 14a and 22a, respectively. As seen in FIG. 1, the pair of conductive fins 14 a may include a first fin extending from the first side of each gate line 14 and a second fin extending from the second side of each gate line 14. . Similarly, as shown in FIG. 1, the pair of conductive fins 22 a includes a first fin extending from the first side of the common electrode 22 and a second fin extending from the second side of the common electrode 22. be able to. The conductive fins 14a and 22a and the conductive portion 24 therebetween can be substantially aligned and insulated by the opening OP formed therebetween. As shown in FIG. 1, the conductive fins 14 a and 22 a and the conductive portion 24 therebetween provide an electrostatic discharge protection function during the manufacture of the pixel region 12 and the TFT region 18, and the TFT region 18 and the display region 20. Ensure the functionality of the device.

  The manufacture of the conductive fins 14a, 22a of FIG. 1 and the conductive portion 24 capable of providing an electrostatic discharge protection function is further illustrated in FIGS. 2a-2d in a cross-sectional view along line AA ′ of FIG. It is. 3A to 3D, a cross-sectional view taken along line A-A 'in FIG. 1 is shown, and a manufacturing process of the thin film transistor in the TFT region 18 is shown.

  2a and 3a, for example, a transparent substrate of the substrate 10 is provided. For example, a buffer layer 102 of silicon nitride, silicon oxide, or a combination thereof can be subsequently formed on the substrate 10. Next, the active layer 104 can be formed on the buffer layer 102 in the TFT region 18 by successive deposition and patterning of, for example, an amorphous silicon layer or a polysilicon layer. Subsequently, an insulating layer 106 on one side can be formed on the substrate 10 and the buffer layer 102 and the active layer 104 in the underlying TFT region 18 can be covered. Next, the patterned conductive layer 108 can be formed by continuous deposition and patterning a layer of conductive material, such as molybdenum (Mo) or aluminum (Al), on the substrate 10. Therefore, the gate line 14 and the common electrode 22 are formed on the substrate (see FIG. 1). Next, using the conductive layer 108 as an implantation mask, ion implantation (not shown) for implanting an appropriate dopant into the active layer 104 can be performed on the substrate 10. Therefore, the source region 104a and the drain region 104b to which an appropriate dopant is added are thus formed in the active layer 104, and the channel region 104c can also be formed therebetween. In FIG. 3a, the conductive layer 108 can function as the gate electrode of the thin film transistor, thus producing the thin film transistor.

  In FIG. 2a, the conductive layer 108 can function as a conductor connecting to the gate line 14 and the common electrode 22 (see FIG. 1) and can be connected to it during manufacture of the TFT, thus providing additional conductivity. Provides a path to diffuse the electrostatic discharge accumulated during device manufacture. The portion of the conductive line formed by the conductive layer 108 can also function as part of the gate line and the common electrode.

  Subsequently, in FIGS. 2b and 3b, an interlayer dielectric 110 can be formed on the substrate 10 and patterned to form a plurality of openings OP and contact openings OP '. In FIG. 2b, the opening OP exposes a portion of the underlying conductive layer. In FIG. 3b, the contact openings OP 'expose portions of the source region 104a and the drain region 104b, respectively.

  Subsequently, in FIGS. 2 c and 3 c, the opening OP, the source region 104 a and the drain region 104 b can be covered with the second conductive layer 112. The second conductive layer 112 can cover the contact opening OP ′ and fill the opening OP, and can be electrically connected to the source region 104 a, the drain region 104 b, and the conductive layer 108, respectively. The second conductive layer 112 can be a single conductive layer or a plurality of conductive layers such as, for example, a Mo—Al—Mo three layer. In various embodiments, the second conductive layer 112 can include the same material as the material of the underlying conductive layer 108.

  2d and 3d, the second conductive layer 112 is patterned to form a data line (see data line 16 in FIG. 1), a gate line and a common electrode (gate line 14 and common electrode 22 in FIG. 1). And the source / drain regions 104a / 104b of the TFT can be covered. Thus, in FIG. 3d, patterned second conductive layers 112a and 112b can be formed that are electrically connected to the source region 104a and the drain region 104b. The second conductive layer 112a can connect data lines (not shown) adjacent to the source region 104a, and the second conductive layer 112b can be connected to a display region (not shown) formed continuously with the drain region 104b. ) Can be connected.

  In the pattern of the second conductive layer 112, the second conductive layer 112 in the non-display area ND can be completely removed, and over-etching also leaves a conductive residue on the surface of the ILD layer 110 in the non-display area ND. Can be done to not. Here, during the above-described over-etching, the portion of the conductive wire 108 in the opening OP is also removed, so that the conductive fin 24 and the conductive fin extending along both sides of the gate line and the common electrode 22 as shown in FIG. 14a and 22a are left. Therefore, the purpose of the electrostatic discharge protection function during the manufacture of the TFT device is achieved. The possibility of a short circuit between two adjacent gate lines or between the common electrode and its adjacent gate lines can be eliminated by forming at least two openings OP between them.

  As shown in FIG. 1, the gate line 14 and the common electrode 22 of the above-described embodiment can be conducted by a conductive layer (not shown) before the data line 16 is formed. Provides additional electrostatic discharge protection to counter static build-up during manufacturing. A portion of the conductive layer is exposed and subsequently cut off during formation of the data line, thus leaving the conductive portion 24 and the conductive fins 14a or 22a extending along both sides of the gate line and the common electrode 22, The opening OP can be formed between them to prevent a short circuit. Electrostatic discharge damage prior to pixel formation can be prevented by the methods and structures provided by the above-described embodiments, thus reducing undesirable mura phenomenon caused to the TFT device in the pixel region by electrostatic discharge damage.

  In addition, other conventional electrostatic discharge protection features, such as contact pads or shorting bars, can be further combined with the methods and structures provided by the previous embodiments and are not limited by the embodiments.

  Furthermore, the array substrate 1 can be used for manufacturing a display panel 200 such as an LCD panel or an OLED panel, and the display panel 200 can be connected to a controller 202. As shown in FIG. Form. Further, the display panel 200 can include an opposite substrate (not shown) installed on the opposite side of the array substrate 1. The controller 202 may include a source and gate driving circuit (not shown) and controls the display panel 200 for operation of the display device 204.

  FIG. 5 is a schematic diagram showing an electronic device in which the display device 204 shown in FIG. 4 is combined. Input device 206 can be connected to controller 202 of display device 204 shown in FIG. 4 to form electronic device 208. The input device 206 may include a processor or the like, and inputs data to the controller 202 and displays an image. In various embodiments, the electronic device 208 can be a portable device such as a PDA, notebook computer, tablet computer, mobile phone, or display monitor device, or a non-portable device such as a desktop computer.

  The preferred embodiments of the present invention have been described above, but this does not limit the present invention, and a few changes and modifications that can be made by those skilled in the art without departing from the spirit and scope of the present invention. It is possible to add. Accordingly, the scope of the protection claimed by the present invention is based on the scope of the claims.

It is a top view of an array substrate provided with an electrostatic discharge (ESD) protection function of an embodiment of the present invention. FIG. 2 is a cross-sectional view taken along line A-A ′ of FIG. 1 illustrating a method of manufacturing an array substrate having an electrostatic discharge (ESD) protection function according to an embodiment of the present invention. FIG. 2 is a cross-sectional view taken along line A-A ′ of FIG. 1 illustrating a method of manufacturing an array substrate having an electrostatic discharge (ESD) protection function according to an embodiment of the present invention. FIG. 2 is a cross-sectional view taken along line A-A ′ of FIG. 1 illustrating a method of manufacturing an array substrate having an electrostatic discharge (ESD) protection function according to an embodiment of the present invention. FIG. 2 is a cross-sectional view taken along line A-A ′ of FIG. 1 illustrating a method of manufacturing an array substrate having an electrostatic discharge (ESD) protection function according to an embodiment of the present invention. FIG. 2 is a cross-sectional view taken along line B-B ′ of FIG. 1 illustrating a method of manufacturing an array substrate thin film transistor according to an embodiment of the present invention. FIG. 2 is a cross-sectional view taken along line B-B ′ of FIG. 1 illustrating a method of manufacturing an array substrate thin film transistor according to an embodiment of the present invention. FIG. 2 is a cross-sectional view taken along line B-B ′ of FIG. 1 illustrating a method of manufacturing an array substrate thin film transistor according to an embodiment of the present invention. FIG. 2 is a cross-sectional view taken along line B-B ′ of FIG. 1 illustrating a method of manufacturing an array substrate thin film transistor according to an embodiment of the present invention. It is the schematic which shows the display apparatus which combined the controller of the Example of this invention. It is the schematic which shows the electronic device which combined the display apparatus of the Example of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Array substrate 10 Substrate 12 Pixel area 14 Gate line 16 Data line 18 Thin film transistor (TFT) area 20 Display area 22 Common electrode 24 Conductive portion 14a Conductive fin 22a Conductive fin ND Non-display area OP Opening OP'Contact opening 102 Buffer layer 104 Active Layer 104a source region 104b drain region 106 insulating layer 108 conductive layer 110 dielectric layer 112 second conductive layer 112a second conductive layer 112b second conductive layer 200 display panel 202 controller 204 display device 206 input device 208 electronic device

Claims (20)

substrate,
A plurality of conductors on the substrate along a first direction, and on the substrate, at least one of which is installed between two conductors of the plurality of conductors, each electrically from the conductors An array substrate provided with electrostatic discharge protection including a plurality of conductive portions insulated by each other.   Each of the plurality of conductive wires includes a pair of conductive fins, the first conductive fins of the pair of conductive fins extend toward the first side, and the second conductive fins of the pair of conductive fins move to the second side. The array substrate according to claim 1, which extends toward the surface.   The array substrate according to claim 2, wherein the plurality of conductive fins and the plurality of conductive portions are arranged along a second direction different from the first direction.   The array substrate according to claim 2, wherein the second direction is substantially perpendicular to the first direction.   A plurality of common electrodes on the substrate, wherein each of the plurality of common electrodes is disposed between two of the plurality of conductive wires, and the common electrode is electrically insulated from the conductive portion; The array substrate according to claim 3.   Each of the plurality of common electrodes includes a pair of conductive fins, the first conductive fins of the pair of conductive fins extend toward the first side, and the second conductive fins of the pair of conductive fins toward the second side. The array substrate according to claim 5, which extends toward the surface.   The array substrate according to claim 6, wherein the pair of conductive fins of each of the plurality of common electrodes, the pair of conductive fins of each of the plurality of conductive wires, and the conductive portion are arranged substantially in a line.   The array substrate according to claim 1, wherein the conductive wire is a gate line connected to a gate electrode of a thin film transistor disposed on the substrate. substrate,
A plurality of conductors on the substrate along a first direction;
On the substrate, at least one of which is installed between two conductors of the plurality of conductors, each of which is electrically insulated from the conductors, and is connected to the display panel, A display device with electrostatic discharge (ESD) protection including a display panel including a controller that drives and displays an image according to input.   The display device according to claim 9, wherein the display panel is a liquid crystal display (LCD) panel.   The display device according to claim 9, wherein the display panel is an electroluminescent display panel including an electroluminescent layer.   The display device of claim 11, wherein the electroluminescent layer comprises a polymer material, and the electroluminescent display panel is a polymer light emitting diode (PLED) display.   The display device of claim 11, wherein the electroluminescent layer includes an organic material, and the electroluminescent display panel includes an organic light emitting diode (OLED) display. Providing a substrate;
Forming a plurality of gate lines connected by conductive wires on the substrate;
Forming an interlayer insulating film on the plurality of gate lines and the conductive wires;
A plurality of contact holes are formed in the interlayer insulating film on the conductive layer, and the plurality of contact holes expose a portion of the underlying conductive line between two gate lines of the plurality of gate lines. Step to do,
Forming a conductive layer on the substrate and the plurality of contact holes; and defining the conductive layer and the conductive line under the plurality of contact holes, the plurality of gate lines, and the plurality of gate lines A method of manufacturing an array substrate comprising electrostatic discharge protection, comprising forming a plurality of data lines on at least one conductive part on the substrate between every two gate lines.   During the step of forming the plurality of gate lines, a common electrode is formed on the substrate between every two gate lines of the plurality of gate lines, and the common electrode is electrically connected to the plurality of gate lines. 15. The method of claim 14, wherein:   The method of claim 14, wherein during the step of forming the plurality of gate lines, a gate electrode of a thin film transistor is formed on the substrate, and the gate electrode is connected to the plurality of gate lines.   The source electrode and the drain electrode of the thin film transistor are formed on the interlayer insulating film during the step of forming the plurality of gate lines, and the source electrode is electrically connected to the plurality of data lines. The method described.   The method according to claim 14, wherein the conductive layer is defined by a dry etching process that is continuous with a photolithography process.   The method of claim 18, wherein the dry etching includes an over-etching process. The method of claim 18, wherein the conductive layer covering the first conductor is completely removed during the definition.