CN110854175B

CN110854175B - Array substrate, preparation method thereof and display panel

Info

Publication number: CN110854175B
Application number: CN201911175504.6A
Authority: CN
Inventors: 刘军; 闫梁臣; 周斌; 宋威; 倪柳松; 程磊磊; 罗标; 桂学海
Original assignee: BOE Technology Group Co Ltd; Hefei Xinsheng Optoelectronics Technology Co Ltd
Current assignee: BOE Technology Group Co Ltd; Hefei Xinsheng Optoelectronics Technology Co Ltd
Priority date: 2019-11-26
Filing date: 2019-11-26
Publication date: 2022-11-25
Anticipated expiration: 2039-11-26
Also published as: CN110854175A

Abstract

The disclosure provides an array substrate, a preparation method thereof and a display panel, and belongs to the technical field of display. The array substrate comprises a substrate, an interlayer dielectric layer and a source drain layer which are sequentially stacked; the source-drain layer comprises two adjacent conductive structures, the interlayer dielectric layer is provided with two grooves for accommodating the two conductive structures in a one-to-one correspondence mode, and the thickness of any conductive structure is smaller than the depth of the corresponding groove. The array substrate can improve the yield.

Description

Array substrate, preparation method thereof and display panel

Technical Field

The disclosure relates to the technical field of display, and in particular relates to an array substrate, a preparation method thereof and a display panel.

Background

With the development of display technology, the requirements for the size and resolution of the display panel are higher and higher. Large size high resolution display panels require thicker wires, higher wire density and narrower wire spacing to balance the requirements of the display panel in terms of voltage drop, retardation and resolution.

However, the large-size high-resolution display panel is easily affected by particles in the environment when the source/drain layer leads are prepared, so that a metal material is left between two adjacent source/drain layer leads to short circuit, and the yield of the display panel is reduced.

The above information disclosed in the background section is only for enhancement of understanding of the background of the present disclosure and therefore it may contain information that does not constitute prior art that is known to a person of ordinary skill in the art.

Disclosure of Invention

The present disclosure provides an array substrate, a method for manufacturing the same, and a display panel, which can improve the yield of the array substrate.

In order to achieve the purpose, the technical scheme adopted by the disclosure is as follows:

according to a first aspect of the present disclosure, an array substrate is provided, which includes a substrate, an interlayer dielectric layer, and a source drain layer, which are sequentially stacked; wherein,

the source-drain layer comprises two adjacent conductive structures, the dielectric layer between the layers is provided with two grooves for accommodating the two conductive structures in a one-to-one correspondence mode, and the thickness of any one conductive structure is smaller than the depth of the corresponding groove.

In an exemplary embodiment of the disclosure, an included angle between any one of the trenches close to a sidewall of the other trench and a surface of the interlayer dielectric layer away from the substrate base plate is not greater than 95 °.

In an exemplary embodiment of the disclosure, a distance between a surface of any one of the conductive structures, which is far away from the substrate base plate, and a surface of the interlayer dielectric layer, which is far away from the substrate base plate, is not less than 0.1 micrometer.

In an exemplary embodiment of the present disclosure, a distance between two of the trenches is not greater than 12 micrometers.

In an exemplary embodiment of the present disclosure, a distance between two of the trenches is not greater than 8 micrometers.

In an exemplary embodiment of the present disclosure, the array substrate further includes a gate layer disposed between the substrate base and the interlayer dielectric layer; the orthographic projection of any one of the conductive structures on the substrate is completely not coincident with the orthographic projection of the gate layer on the substrate.

In an exemplary embodiment of the present disclosure, the trench penetrates the interlayer dielectric layer.

According to a second aspect of the present disclosure, a display panel is provided, which includes the array substrate.

According to a third aspect of the present disclosure, there is provided a method of manufacturing an array substrate, including:

providing a substrate base plate;

forming an interlayer dielectric layer on one side of the substrate, wherein the interlayer dielectric layer is provided with two adjacent grooves;

forming a source drain layer on one side of the interlayer dielectric layer, which is far away from the substrate, wherein the source drain layer comprises two adjacent conductive structures, and the two conductive structures are accommodated in the two grooves in a one-to-one correspondence manner; the thickness of any one of the conductive structures is smaller than the depth of the corresponding groove.

In one exemplary embodiment of the present disclosure, the forming of the interlayer dielectric layer at one side of the substrate base plate includes:

forming an interlayer dielectric material layer on one side of the substrate base plate;

and patterning the interlayer dielectric material layer to form two adjacent grooves, wherein an included angle between the side wall of one groove close to the other groove and the surface of the interlayer dielectric layer far away from the substrate base plate is not more than 95 degrees.

and patterning the interlayer dielectric material layer to form two adjacent grooves, wherein the distance between the two grooves is not more than 12 microns.

In an exemplary embodiment of the present disclosure, forming a source drain layer on a side of the interlayer dielectric layer away from the substrate includes:

forming a source drain material layer on one side of the interlayer dielectric layer, which is far away from the substrate, and enabling the thickness of the source drain material layer to be at least 0.1 micrometer smaller than the depth of the groove;

and carrying out patterning operation on the source drain material layer to form two adjacent conductive structures.

In an exemplary embodiment of the present disclosure, the method of manufacturing an array substrate further includes:

forming a gate layer on one side of the substrate before forming the interlayer dielectric layer;

forming an interlayer dielectric layer on one side of the substrate base plate includes:

and forming the interlayer dielectric layer on one side of the gate layer far away from the substrate, wherein the orthographic projection of any groove on the substrate is completely not overlapped with the orthographic projection of the gate layer on the substrate.

In one exemplary embodiment of the present disclosure, the forming of the interlayer dielectric layer at one side of the substrate base further includes:

an interlayer dielectric layer is formed on one side of the substrate base plate, and the groove penetrates through the interlayer dielectric layer.

In the array substrate, the preparation method thereof and the display panel provided by the disclosure, the conductive structure is arranged in the groove, and the thickness of the conductive structure is smaller than the depth of the groove, so that a certain height difference exists between the surface of the conductive structure and the surface of the interlayer dielectric layer. Therefore, even if the source and drain metal material is left on the interlayer dielectric layer between the two trenches, the left source and drain metal material cannot be electrically connected with the conductive structure, and the problem that the left source and drain metal material causes short circuit between the two adjacent conductive structures is solved. Therefore, in the array substrate disclosed by the invention, even if the source and drain metal materials between the two conductive structures cannot be completely removed due to the reasons of particles in the environment and the like, the two conductive structures cannot be short-circuited, so that the defect that the two adjacent conductive structures are short-circuited due to the residual source and drain metal materials of the array substrate is avoided, and the yield of the array substrate is improved.

Drawings

The above and other features and advantages of the present disclosure will become more apparent by describing in detail exemplary embodiments thereof with reference to the attached drawings.

Fig. 1 is a schematic partial sectional structure view of an array substrate according to an embodiment of the present disclosure.

Fig. 2 is a schematic partial top view structure diagram of an array substrate according to an embodiment of the present disclosure.

Fig. 3 is a partial cross-sectional structural diagram of an array substrate with an element drain metal material left according to an embodiment of the disclosure.

Fig. 4 is a schematic partial top view structure diagram of the residual metal material of the array substrate according to the embodiment of the disclosure.

Fig. 5 is a partial cross-sectional structural schematic view of forming a patterned first photoresist layer in accordance with an embodiment of the present disclosure.

Fig. 6 is a schematic diagram of a partial top view structure of forming a patterned first photoresist layer in an embodiment of the disclosure.

Fig. 7 is a partial cross-sectional structural schematic view of forming a patterned interlayer dielectric layer of an embodiment of the present disclosure.

Fig. 8 is a schematic partial top view structure of forming a patterned interlayer dielectric layer in accordance with an embodiment of the present disclosure.

Fig. 9 is a partially cross-sectional structural schematic view of an interlayer dielectric layer according to an embodiment of the present disclosure.

Fig. 10 is a schematic diagram of a partial top view structure of an interlayer dielectric layer according to an embodiment of the present disclosure.

Fig. 11 is a schematic partial cross-sectional structural diagram of forming a source/drain material layer according to an embodiment of the disclosure.

Fig. 12 is a schematic partial top view structure diagram of a source/drain material layer formed according to the embodiment of the disclosure.

Fig. 13 is a schematic partial top view structure diagram of forming a passivation layer according to an embodiment of the disclosure.

Fig. 14 is a schematic top view structure diagram of a source-drain lead according to an embodiment of the present disclosure.

Fig. 15 is a schematic cross-sectional structure view of an array substrate according to an embodiment of the present disclosure.

Fig. 16 is a schematic flow chart illustrating a method for manufacturing an array substrate according to an embodiment of the present disclosure.

The reference numerals of the main elements in the figures are explained as follows:

100. a substrate base plate; 200. a gate layer; 300. an interlayer dielectric layer; 301. a layer of interlayer dielectric material; 302. a first photoresist layer; 310. a trench; 311. a first side wall; 312. a second side wall; 320. a pair of trenches; 400. a source drain layer; 401. a source drain material layer; 410. a source drain lead; 411. a conductive structure; 412. a pair of conductive structures; 420. residual source drain metal material; 501. a metal light shielding layer; 502. a buffer layer; 503. an active layer; 504. a gate insulating layer; 505. a passivation layer; 506. a planarization layer; 601. a pixel electrode layer; 602. a pixel defining layer; 603. an organic light-emitting layer; 604. a common electrode layer; 605. and (7) packaging the layer.

Detailed Description

Example embodiments will now be described more fully with reference to the accompanying drawings. Example embodiments may, however, be embodied in many different forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a thorough understanding of embodiments of the disclosure.

In the drawings, the thickness of regions and layers may be exaggerated for clarity. The same reference numerals in the drawings denote the same or similar structures, and thus a detailed description thereof will be omitted.

The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a thorough understanding of embodiments of the disclosure. One skilled in the relevant art will recognize, however, that the embodiments of the disclosure can be practiced without one or more of the specific details, or with other methods, components, materials, and so forth. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring the primary technical ideas of the disclosure.

When a structure is "on" another structure, it may mean that the structure is integrally formed with the other structure, or that the structure is "directly" disposed on the other structure, or that the structure is "indirectly" disposed on the other structure via another structure.

The terms "a," "an," "the," and the like are used to denote the presence of one or more elements/components/parts; the terms "comprising" and "having" are intended to be inclusive and mean that there may be additional elements/components/etc. other than the listed elements/components/etc. The terms "first" and "second", etc. are used merely as labels, and are not limiting on the number of their objects.

The present disclosure provides an array substrate, as shown in fig. 1, the array substrate includes a substrate 100, an interlayer dielectric layer 300, and a source drain layer 400, which are stacked in sequence; as shown in fig. 2, the source/drain layer 400 includes two conductive structures 411 arranged adjacently; as shown in fig. 1 and 9, the interlayer dielectric layer 300 is provided with two trenches 310 that accommodate two conductive structures 411 in a one-to-one correspondence, and the thickness of any conductive structure 411 is smaller than the depth of the corresponding trench 310.

In the array substrate provided by the present disclosure, since the conductive structure 411 is disposed in the trench 310 and has a thickness smaller than the depth of the trench 310, a certain height difference d exists between the surface of the conductive structure 411 and the surface of the interlayer dielectric layer 300. Therefore, as shown in fig. 3 and fig. 4, even if the source-drain metal material 420 remains on the interlayer dielectric layer 300 between the two trenches 310, the remaining source-drain metal material 420 cannot be electrically connected to the conductive structure 411, thereby avoiding the problem that the remaining source-drain metal material 420 causes a short circuit between two adjacent conductive structures 411. Thus, in the array substrate of the present disclosure, even if the source-drain metal material 420 between the two conductive structures 411 cannot be completely removed due to the particles in the environment and other reasons, the two conductive structures 411 cannot be short-circuited, which avoids the defect that the two adjacent conductive structures 411 are short-circuited due to the residual source-drain metal material 420 of the array substrate, improves the yield of the array substrate, and is particularly suitable for a large-size display panel.

The array substrate of the present disclosure is further explained and illustrated with reference to the drawings.

The base substrate 100 may be an inorganic base substrate 100 or an organic base substrate 100. For example, in one embodiment of the present disclosure, the substrate 100 may be made of soda-lime glass (soda-lime glass), quartz glass, sapphire glass, or other glass materials, or may be made of stainless steel, aluminum, nickel, or other metal materials. In another embodiment of the present disclosure, the material of the substrate 100 may be Polymethyl methacrylate (PMMA), polyvinyl alcohol (PVA), polyvinyl phenol (PVP), polyether sulfone (PES), polyimide, polyamide, polyacetal, polycarbonate (PC), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), or a combination thereof. The substrate 100 may also be a flexible substrate 100, for example, in one embodiment of the present disclosure, the material of the substrate 100 may be Polyimide (PI).

The material of the interlayer dielectric layer 300 may be silicon oxide, silicon nitride, silicon oxynitride, or other insulating materials, and may be selected according to actual requirements. For example, if the thin film transistor of the array substrate is an oxide thin film transistor, the material of the interlayer dielectric layer 300 may be silicon oxide.

As shown in fig. 1, the thickness of the interlayer dielectric layer 300 should be greater than the thickness of the source and drain layers 400 to ensure that the interlayer dielectric layer 300 can be provided with the trench 310 having a depth greater than the thickness of the source and drain layers 400. Optionally, the thickness of the interlayer dielectric layer 300 is at least 0.1 micrometer greater than the thickness of the source drain layer 400, i.e. d is not less than 0.1 micrometer in fig. 1, so that the distance d between any conductive structure 411 far away from the surface of the substrate 100 and the surface of the interlayer dielectric layer 300 far away from the substrate 100 is not less than 0.1 micrometer. In one embodiment of the present disclosure, the thickness of the interlayer dielectric layer 300 is 0.8 to 0.9 micrometers.

In the present disclosure, when describing the thickness of a film layer or a structure, it refers to the dimension of the film layer or the structure in a direction perpendicular to the plane of the substrate base plate 100; in other words, a virtual straight line perpendicular to the plane of the substrate 100 may pass through the film or the structure, and the length of the portion where the virtual straight line and the film or the structure overlap is the thickness of the film or the structure. Accordingly, when describing the depth of the trench 310 or via, it refers to the dimension of the trench 310 or via in a direction perpendicular to the plane of the substrate base 100; in other words, a virtual straight line perpendicular to the plane of the substrate 100 may pass through the space defined by the trench 310 or the space defined by the via, and the length of the overlapping portion of the virtual straight line and the space defined by the trench 310 or the via is the depth of the trench 310 or the via.

In the present disclosure, as shown in fig. 7, the trenches 310 for respectively accommodating two adjacently disposed conductive structures 411 constitute a trench pair 320. As shown in fig. 9, any one of the trenches 310 includes a first sidewall 311 and a second sidewall 312, wherein, in a trench pair 320, the first sidewall 311 of one trench 310 is close to the other trench 310, and the second sidewall 312 of one trench 310 is far from the other trench 310. In one trench pair 320, either trench 310 is adjacent to the sidewall of the other trench 310, and makes an angle of not more than 95 ° with the surface of the interlayer dielectric layer 300 away from the substrate base plate 100. In other words, an included angle between the surface of the interlayer dielectric layer 300 away from the substrate base plate 100 and the first sidewall 311 of the trench 310 is a first included angle θ 1, and the first included angle θ 1 is an obtuse angle and is not greater than 95 °. As shown in fig. 11 and 12, when the source-drain metal material is deposited on the side of the interlayer dielectric layer 300 away from the substrate 100 to form the source-drain material layer 401, since the first sidewall 311 is close to the normal direction of the substrate 100 and the thickness of the formed source-drain material layer 401 is smaller than the depth of the trench 310, the source-drain metal material cannot be effectively deposited continuously on the first sidewall 311, which makes the portion of the source-drain material layer 401 located at the bottom of the trench 310 discontinuous from the portion located between two trenches 310, that is, the source-drain material layer 401 is discontinuous at the AB dashed line and the CD dashed line. This ensures that the portions of the source/drain material layer 401 located in the two trenches 310 cannot be electrically connected to each other through the portion located between the two trenches 310, as shown in fig. 4, and further ensures that the two adjacent conductive structures 411 cannot be electrically connected through the source/drain metal material 420 remaining between the two trenches 310.

Alternatively, as shown in fig. 7 and 9, in any groove pair 320, two groove sidewalls of the two grooves 310 far away from each other, i.e., the second sidewall 312 of the groove 310, may exhibit a steeper slope or a shallower slope. To avoid the side wall slope being too gentle and thus oversizing the groove 310, the slope of the two mutually distant side walls may be not less than 40 °. In other words, an angle between the surface of the interlayer dielectric layer 300 away from the substrate base plate 100 and the second sidewall 312 is a second angle θ 2, and the second angle θ 2 is an obtuse angle and is not less than 140 °.

The interlayer dielectric layer 300 may be formed by a photolithography process. For example, as shown in fig. 5 to 10, an interlayer dielectric material layer 301 may be formed on one side of the substrate 100; the interlayer dielectric material layer 301 is then subjected to a patterning operation to form two trenches 310 disposed adjacently and other pattern structures.

In the following, a method of patterning the interlayer dielectric material layer 301 is exemplarily provided:

as shown in fig. 5, a first photoresist layer 302 is formed on a side of the interlayer dielectric material layer 301 away from the base substrate 100, and the thickness of the first photoresist layer 302 may be 2.5 to 3.0 micrometers.

Then, as shown in fig. 5 and 6, the first photoresist layer 302 is exposed through a mask plate and then developed, so as to obtain a patterned first photoresist layer 302. In the patterned first photoresist layer 302, two exposure holes corresponding to the two trenches 310 are provided, and the slope angle of the sidewall where the two exposure holes are close to each other is not less than 85 °, in other words, the included angle between the sidewall where the two exposure holes are close to each other and the surface of the first photoresist layer 302 away from the substrate 100 is not more than 95 °. The slope angle of the sidewalls of the two exposure holes away from each other is not less than 40 °, in other words, the angle between the sidewalls of the two exposure holes away from each other and the surface of the first photoresist layer 302 away from the substrate 100 is not more than 140 °. A half-tone mask process may be used such that the slope angles of both sidewalls of the exposure hole are different. Alternatively, the width of the exposure hole may be 2 to 3 micrometers greater than the width of the corresponding conductive structure 411. Here, the width of the exposure hole or the conductive structure 411 refers to a dimension of the exposure hole or the conductive structure 411 in an orthogonal projection of the substrate base 100 along a direction perpendicular to an extending direction of the orthogonal projection.

Then, as shown in fig. 7 and 8, the exposed interlayer dielectric material layer 301 is etched using dry etching to form a desired trench 310, forming an interlayer dielectric layer 300. Optionally, the etching is performed with carbon tetrafluoride and oxygen, wherein the flow of carbon tetrafluoride may be 1000-1400 sccm and the flow of oxygen may be 1500-1900 sccm, using a high bias and high power setting. In this way, the profile of the etched trench 310 matches the profile of the exposed hole to obtain the desired trench 310.

Finally, as shown in fig. 9 and 10, the first photoresist layer 302 is removed. The first photoresist layer 302 may be removed by wet stripping.

As shown in fig. 1 and fig. 2, the source/drain layer 400 includes two conductive structures 411 disposed adjacently, where any other conductive structure 411 made of a source/drain metal material is not disposed between the two conductive structures 411 disposed adjacently. Of course, it is understood that, as shown in fig. 3 and fig. 4, a source drain metal material 420 may remain between two adjacent conductive structures 411, and these remaining source drain metal materials 420 do not intentionally remain according to design, but accidentally remain uncontrollably due to the limitation of the manufacturing process. The array substrate provided by the present disclosure has an advantage that even if the source-drain metal material 420 is uncontrollably remained between the two adjacent conductive structures 411, it can be ensured that no short circuit occurs between the two conductive structures 411. Another advantage of the array substrate provided by the present disclosure is that, as shown in fig. 1, since two adjacent conductive structures 411 are separated by the interlayer dielectric layer 300, the risk of mutual short circuit between the two conductive structures 411 is avoided.

As shown in fig. 1, two adjacent conductive structures 411 form a conductive structure pair 412, and a plurality of conductive structure pairs 412 may be disposed on the array substrate. In the array substrate of the present disclosure, some or all of the pairs of conductive structures 412 may adopt the arrangement of the trenches 310. When a conductive structure pair 412 is disposed in the manner of the trench 310, the interlayer dielectric layer 300 is disposed with the trench pair 320 corresponding to the conductive structure pair 412, such that the two conductive structures 411 of the conductive structure pair 412 are disposed in the two trenches 310 of the trench pair 320, respectively. In one embodiment of the present disclosure, any pair of conductive structures 412 is provided with a trench 310.

It can be understood that the source drain metal material 420 is easily remained between the two conductive structures 411 due to the shielding of exposure or etching by particles in the environment or particles generated in the manufacturing process. When the distance between the adjacent conductive structures 411 is smaller, the remaining source-drain metal material 420 may cause a short between the adjacent conductive structures 411 to be more likely. Because the conductive structures 411 of the array substrate of the present disclosure are disposed in the trenches 310, the two adjacent conductive structures 411 are necessarily separated from the source-drain metal material 420 remaining therebetween, and thus it is structurally ensured that no short circuit occurs between the two adjacent conductive structures 411 due to the remaining source-drain metal material 420. Therefore, the smaller the distance between two adjacent conductive structures 411 is, especially the higher the resolution of the display panel is, the more significantly the yield is improved when the array substrate of the present disclosure is used.

Optionally, in the pair of conductive structures 412, a distance between orthographic projections of the two conductive structures 411 on the substrate base plate 100 is not greater than 12 microns. In this way, in the array substrate with higher resolution, especially in the array substrate with 2K or more, even if the source-drain metal material 420 remains between the two adjacent conductive structures 411, short circuit failure does not occur between the two conductive structures.

Further, in the pair of conductive structures 412, the distance between the orthographic projections of the two conductive structures 411 on the substrate base plate 100 is not more than 8 micrometers, so that the array base plate can be suitable for 4K, 8K or other higher-resolution display panels; thus, the array substrate significantly improves the yield of the high-resolution display panel, and overcomes the defect caused by the residual active drain metal material 420 due to the narrow spacing between the adjacent conductive structures 411.

The source-drain layer 400 may be provided with a source-drain layer structure such as a source electrode of a thin film transistor, a drain electrode of the thin film transistor, and a source-drain lead (e.g., a data line, a power supply line), and may also be provided with other required source-drain layer structures such as an electrode plate of a storage capacitor, a pad, an electrostatic breakdown prevention (ESD) structure, and the like, which are formed by patterning the source-drain material layer 401, as shown in fig. 11. Any conductive structure 411 in the pair of conductive structures 412 may be one of the above-mentioned source-drain layer structures or a part of a certain source-drain layer structure; any source/drain layer structure may be disposed on one or more conductive structures 411, which is not limited in this disclosure.

For example, as shown in fig. 14, in an embodiment of the present disclosure, a local distance between two adjacent source/drain leads 410 is smaller, and portions of the two source/drain leads 410 close to each other are two conductive structures 411 in one conductive structure pair 412, and the two conductive structures 411 are respectively accommodated in two trenches 310, so as to ensure an electrical disconnection between the two conductive structures 411, and thus ensure an electrical disconnection between the two source/drain leads 410.

Optionally, as shown in fig. 14, a plurality of mutually close local regions exist between two source/drain lead lines 410 that are adjacently disposed, a conductive structure pair 412 may be formed in any mutually close local region, and two conductive structures 411 in the conductive structure pair 412 may be disposed on the two source/drain lead lines 410, respectively.

Optionally, in order to reduce the sheet resistance of the source drain lead 410, the source drain layer 400 may use a conductive material with higher conductivity, for example, copper. Further, the source drain layer 400 may further have a protective metal layer, such as a molybdenum layer or a molybdenum-niobium layer, disposed on at least one side of the copper layer. For example, in one embodiment of the present disclosure, the source-drain layer 400 includes a molybdenum niobium layer, a copper layer, and a molybdenum niobium layer, which are sequentially stacked. For another example, in another embodiment of the present disclosure, the source/drain layer 400 includes a molybdenum niobium layer and a copper layer sequentially stacked, where the molybdenum niobium layer is disposed on a side of the copper layer close to the substrate 100.

Alternatively, in order to reduce the sheet resistance of source drain wires 410, source drain layer 400 may have a larger thickness, for example, the thickness of source drain layer 400 may be not less than 0.6 μm. Further, the thickness of the source drain layer 400 may be 0.7 to 0.8 μm. For example, in one embodiment of the present disclosure, the source/drain layer 400 includes a molybdenum niobium layer and a copper layer sequentially stacked, where the molybdenum niobium layer is disposed on a side of the copper layer close to the substrate 100, the thickness of the molybdenum niobium layer may be 0.03 to 0.04 micrometers, and the thickness of the copper layer may be 0.7 to 0.8 micrometers.

Optionally, in order to increase the pixel density of the array substrate, the width of the source/drain wiring 410 may be smaller, for example, smaller than 10 μm. The width of the source-drain lead 410 can be determined according to actual requirements, so as to meet the requirements of the array substrate in the aspects of sheet resistance, voltage drop and delay. For example, in a 55-inch 8K array substrate, the width of the source/drain leads 410 may be 4 to 5 microns, the minimum distance between two adjacent source/drain leads 410 may be 5 to 8 microns, and the thickness of the copper layer may be greater than 0.7 micron.

Alternatively, the source and drain layers 400 may be formed by a photolithography process. For example, as shown in fig. 11 and fig. 12, a source/drain material layer 401 may be deposited on a side of the interlayer dielectric layer 300 away from the substrate 100, and then the source/drain material layer 401 may be patterned to obtain the source/drain layer 400. When forming the source/drain material layer 401, the source/drain material layer 401 may cover the surface of the interlayer dielectric layer 300 away from the substrate 100 and cover the trench 310; due to the structure of the trenches 310, the source drain material layer 401 is discontinuous at the first sidewalls 311 of both trenches 310. The source drain material layer 401 may be patterned by the following method:

forming a second photoresist layer on one side of the source drain material layer 401 away from the substrate 100, wherein the thickness of the second photoresist layer can be 1.5-1.8 micrometers, and the second photoresist layer is made of positive photoresist;

then, exposing the second photoresist layer through a mask plate, and then developing to obtain a patterned second photoresist layer;

then, the exposed source/drain material layer 401 is partially etched by wet etching. The etching liquid can contain hydrogen peroxide.

And finally, after the etching is finished, removing the second photoresist layer to obtain the source drain layer 400.

The array substrate can also comprise other film layers to form a driving circuit layer of the array substrate. A plurality of driving circuits may be formed in the driving circuit layer, any driving circuit may include a thin film transistor, a storage capacitor, or other devices, and the thin film transistor may be an LTPS-TFT (low temperature polysilicon-thin film transistor) or an oxide-TFT (oxide-thin film transistor), for example, an IGZO-TFT, which is not limited in this disclosure. The thin film transistor may be a top gate type or a bottom gate type, and the disclosure is not limited thereto. As shown in fig. 15, devices such as a thin film transistor and a storage capacitor may be formed through each of the layers of the driving circuit, and the layers may include at least an interlayer dielectric layer 300 and a source drain layer 400 according to the present disclosure, and may further include an active layer 503, a gate insulating layer 504, and a gate layer 200. The hierarchical relationship of these layers can be determined according to the type of the thin film transistor. For example, if the thin film transistor is a top gate type, the gate insulating layer 504 is disposed on the active layer 503 on a side away from the substrate 100, and the gate layer 200 is disposed on the gate insulating layer 504 on a side away from the substrate 100. If the thin film transistor is a bottom gate type, the gate insulating layer 504 is provided on the active layer 503 on the side closer to the base substrate 100, and the gate electrode layer 200 is provided on the gate insulating layer 504 on the side closer to the base substrate 100.

Alternatively, as shown in fig. 15, the gate layer 200 is provided between the substrate 100 and the interlayer dielectric layer 300; an orthogonal projection of any of the conductive structures 411 on the substrate 100 is completely misaligned with an orthogonal projection of the gate layer 200 on the substrate 100. Therefore, the conductive structure 411 on the source-drain layer 400 and each gate layer structure on the gate layer 200 can be prevented from forming an excessive parasitic capacitance or being short-circuited.

Further, when the interlayer dielectric layer 300 is patterned, a via hole exposing the active layer 503 may also be formed so that the source and drain electrodes of the thin film transistor are electrically connected with the active region of the thin film transistor. In order to simplify the patterning process, as shown in fig. 7 and 8, the trench 310 may penetrate the interlayer dielectric material layer 301 when the trench 310 is formed, and thus, the trench 310 and the via may be simultaneously formed in one etching using the same process. Since the conductive structure 411 and the gate layer 200 do not overlap, the penetration of the trench 310 through the interlayer dielectric layer 300 does not cause a short circuit of the conductive structure 411 and the gate layer 200. Here, in the present disclosure, the trench 310 penetrates the interlayer dielectric layer 300, which means that the trench 310 penetrates the interlayer dielectric layer 300 in a normal direction of the substrate base plate 100.

Optionally, as shown in fig. 13, the driving circuit layer of the array substrate may further include a passivation layer 505, where the passivation layer 505 is formed on a side of the source and drain layer 400 away from the substrate to protect the source and drain layer.

Optionally, the driving circuit layer of the array substrate may further include a metal light shielding layer 501, a buffer layer 502, a planarization layer 506, and other film layers, which are not described in detail in this disclosure.

Optionally, the array substrate may further include an organic light emitting layer 603 disposed on a side of the driving circuit layer away from the substrate 100, and the organic light emitting layer 603 can emit light under the control of the driving circuit layer to display a picture.

Hereinafter, an array substrate is exemplarily provided to further explain and explain the principles, structures and effects of the array substrate of the present disclosure.

In an exemplary array substrate, as shown in fig. 15, the array substrate includes an underlying substrate 100, a metal light-shielding layer 501, a buffer layer 502, an active layer 503, a gate insulating layer 504, a gate layer 200, an interlayer dielectric layer 300, a source-drain layer 400, a passivation layer 505, a planarization layer 506, a pixel electrode layer 601, a pixel definition layer 602, an organic light-emitting layer 603, a common electrode layer 604, and an encapsulation layer 605, which are sequentially stacked. Wherein,

the substrate 100 may be a glass substrate.

The metal light shielding layer 501 is disposed on one side of the substrate 100 and is used for providing a light shielding environment for the thin film transistor, especially for an active region of the thin film transistor. The material of the metal light shielding layer 501 may be molybdenum, titanium, molybdenum-niobium alloy, or other metal materials, and the thickness of the metal light shielding layer 501 may be 0.1 to 0.15 μm. Alternatively, the metal light shielding layer 501 may be formed by: a layer of metal material is deposited on one side of the base substrate 100 to form a light-shielding material layer, and then the light-shielding material layer is patterned to form the metal light-shielding layer 501, and wet etching may be performed using mixed acid during the patterning operation.

The buffer layer 502 is disposed on a side of the metal light-shielding layer 501 away from the substrate 100, covering the display region and the peripheral region of the array substrate, i.e., covering the metal light-shielding layer 501 and the exposed substrate 100. The buffer layer 502 may be made of silicon oxide and may have a thickness of 0.3 to 0.5 μm. The buffer layer 502 may be formed by a deposition method.

The active layer 503 is arranged on one side of the buffer layer 502 far away from the substrate base plate 100; the material of the active layer 503 may be an oxide semiconductor, and may be IGZO, for example; the thickness of the active layer 503 may be 0.05 to 0.1 micrometers. The active layer 503 may be formed with an active region of a thin film transistor and may also be formed with one electrode plate of a storage capacitor. Alternatively, the active layer 503 may be formed by the following method: an oxide semiconductor layer is deposited on the buffer layer 502 at a side away from the substrate 100 to form an active material layer, and then the active material layer is patterned to form an active layer 503, and wet etching may be used when the patterning is performed.

The gate insulating layer 504 is disposed on a side of the active layer 503 away from the substrate base plate 100, and covers a portion of the oxide semiconductor layer. The material of the gate insulating layer 504 may be silicon oxide, and the thickness may be 0.1 to 0.2 μm. The gate layer 200 is disposed on a side of the gate insulating layer 504 away from the substrate 100; an orthogonal projection of the gate layer 200 on the substrate 100 overlaps with an orthogonal projection of the oxide semiconductor layer on the substrate 100, and the gate layer 200 is isolated from the oxide semiconductor layer by the gate insulating layer 504. In this way, the gate layer 200 may be formed with a gate of a thin film transistor, and the gate layer 200 may be formed with a gate structure such as a gate lead, a pad, and the like. The gate layer 200 may include a mo-nb layer and a cu layer sequentially stacked, wherein the mo-nb layer is disposed on a side of the cu layer adjacent to the substrate 100. The thickness of the molybdenum niobium layer can be 0.03 to 0.04 microns, and the thickness of the copper layer can be 0.7 to 0.8 microns.

The gate insulating layer 504 and the gate layer 200 may be formed by: depositing a layer of silicon oxide on the side of the active layer 503 away from the substrate 100 to form a gate insulating material layer; a layer of molybdenum niobium and a layer of copper are sequentially deposited on the side of the gate insulating material layer away from the substrate base plate 100 to form a gate material layer. A patterned third photoresist layer is formed on a side of the gate material layer away from the substrate 100, and the exposed gate material layer is etched by using a mixed acid (for example, a solution of nitric acid, acetic acid, and phosphoric acid in a certain ratio) to form the gate layer 200. And performing dry etching on the exposed gate insulating material layer to form a gate insulating layer 504, wherein the flow rate of carbon tetrafluoride in the dry etching is 2000-2500 sccm, the flow rate of oxygen is 1000-1500 sccm, and high source power and high bias power are adopted in the dry etching. The exposed active layer 503 is conducted with a conductimetric action, which may be performed using ammonia or helium gas, to improve the conductivity of the surface of the exposed active layer 503. And performing ashing treatment on the third photoresist layer, wherein the flow of oxygen in the ashing treatment is 10000-12000 sccm. And after the third photoresist layer is subjected to ashing treatment, carrying out wet stripping to completely remove the third photoresist layer.

The interlayer dielectric layer 300 is disposed on a side of the gate layer 200 away from the substrate 100, and may be made of silicon oxide and have a thickness of 0.8-0.9 μm. The interlayer dielectric layer 300 may be formed by:

a layer of silicon oxide is deposited on the side of the gate layer 200 remote from the substrate 100 to form an interlayer dielectric material layer 301.

A first photoresist layer 302 is formed on the side of the interlayer dielectric material layer 301 away from the substrate base plate 100, and the thickness of the first photoresist layer 302 is 2.5-3.0 micrometers. Patterning the first photoresist layer 302 using a halftone mask; in the patterned first photoresist layer 302, two exposure holes are provided in one-to-one correspondence with the two trenches 310, the slope angle of the side wall where the two exposure holes are close to each other is not less than 85 °, and the slope angle of the side wall where the two exposure holes are far from each other is not less than 40 °; the patterned first photoresist layer 302 may also include other exposure holes for forming other patterns on the interlayer dielectric layer 300. Optionally, in order to locate the conductive structure 411 in the groove, the width of the exposure hole corresponding to the groove is 2 to 3 micrometers greater than the width of the conductive structure 411.

The exposed interlayer dielectric material layer 301 is etched by dry etching to form a desired groove. In the dry etching, high bias and high power setting is adopted, wherein the flow rate of carbon tetrafluoride can be 1000-1400 sccm, and the flow rate of oxygen can be 1500-1900 sccm. In this way, in the obtained groove pair, an angle between the sidewall of one of the trenches 310 close to the sidewall of the other trench 310 and the surface of the interlayer dielectric layer 300 away from the substrate 100 is not more than 95 °, and slopes of the two sidewalls away from each other may be not less than 40 °. To form a via exposing a portion of the active region in a dry etch, a dry etch may cause the trench 310 to penetrate the interlayer dielectric material layer 301; in order to avoid short-circuiting between the gate layer 200 and the source/drain layers 400, the orthographic projection of any of the trenches 310 on the substrate 100 does not overlap with the orthographic projection of the gate layer 200 on the substrate 100.

Optionally, in order to electrically connect the source-drain layer 400 and the metal light-shielding layer 501, the time of dry etching may be further prolonged or wet etching may be further adopted, so as to etch a via hole on the buffer layer 502, which exposes the metal light-shielding layer 501.

The first photoresist layer 302 is wet stripped.

The source-drain layer 400 is arranged on one side of the interlayer dielectric layer 300 far away from the substrate 100, the material of the source-drain layer 400 is copper, and the thickness of the source-drain layer 400 is 0.7-0.8 micrometers. Optionally, a molybdenum niobium layer with a thickness of 0.03 to 0.04 micrometers may be further disposed on the side of the copper layer close to the substrate 100. The source and drain layers 400 are electrically connected to the active region through the via hole such that the source and drain layers 400 are formed with a source and a drain of the thin film transistor. The source-drain layer 400 may also be electrically connected to the metal light-shielding layer 501 through a via hole on the buffer layer 502, and may also be formed with another electrode plate of the storage capacitor. The pair of conductive structures 412 in the source-drain layer 400 corresponds to the pair of trenches 320 in the interlayer dielectric layer 300 one by one, and the two conductive structures 411 of the pair of conductive structures 412 are respectively disposed in the two trenches 310 of the pair of trenches 320. Since the thickness of the source-drain layer 400 is smaller than the depth of the trench 310, the two conductive structures 411 of the conductive structure pair 412 cannot be electrically connected through the source-drain metal material 420 remaining therebetween, thereby reducing the risk of short circuit between the two due to the fact that the source-drain metal material 420 between the two cannot be completely removed by the manufacturing process.

The passivation layer 505 is disposed on a side of the source/drain layer 400 away from the substrate 100 for protecting the source/drain layer 400. The passivation layer 505 may be silicon oxide and may have a thickness of 0.5 to 0.6 microns. A layer of silicon oxide may be deposited on the side of the source and drain layers 400 away from the substrate 100 to form a passivation layer 505.

A planarization layer 506 is provided on the surface of the passivation layer 505 remote from the substrate base plate 100 to provide a flat surface for the pixel electrode. The pixel electrode layer 601 is disposed on a surface of the planarization layer 506 away from the substrate 100, and includes a plurality of pixel electrodes. Any pixel electrode is electrically connected with the source drain layer 400 through a metalized via, and particularly electrically connected with the drain electrode of the thin film transistor through a metalized via. Any one of the pixel electrodes is provided with a light emitting region. The pixel defining layer 602 is provided on a surface of the pixel electrode layer 601 away from the substrate 100, and covers a region other than the light-emitting region. The organic light emitting layer 603 is disposed on a side of the pixel defining layer 602 away from the substrate 100, and covers light emitting regions of the exposed respective pixel electrodes. The common electrode layer 604 is provided on a surface of the organic light-emitting layer 603 away from the base substrate 100, and covers the organic light-emitting layer 603. The encapsulation layer 605 is disposed on a side of the common electrode layer 604 away from the substrate 100 to protect the organic light emitting layer 603.

The present disclosure also provides a method for manufacturing an array substrate, as shown in fig. 16, the method for manufacturing an array substrate includes:

step S110, providing a substrate 100;

step S120, forming an interlayer dielectric layer 300 on one side of the substrate 100, wherein the interlayer dielectric layer 300 is provided with two trenches 310 arranged adjacently;

step S130, forming a source/drain layer 400 on a side of the interlayer dielectric layer 300 away from the substrate base plate 100, where the source/drain layer 400 includes two conductive structures 411 arranged adjacently, and the two conductive structures 411 are accommodated in the two trenches 310 in a one-to-one correspondence manner; the thickness of any conductive structure 411 is less than the depth of the corresponding trench 310.

The method for manufacturing the array substrate provided by the present disclosure can manufacture any one of the array substrates described in the above array substrate embodiments, and therefore, the method has the same or similar beneficial effects, and the details of the present disclosure are not repeated herein.

Step S120 may be implemented by:

forming an interlayer dielectric material layer 301 on one side of the base substrate 100;

the interlayer dielectric material layer 301 is subjected to a patterning operation.

Alternatively, in an embodiment of the present disclosure, by performing a patterning operation on the interlayer dielectric material layer 301, two trenches 310 disposed adjacently may be formed, and an included angle between any one trench 310 and a surface of the interlayer dielectric layer 300 away from the substrate 100 is not greater than 95 ° near a sidewall of the other trench 310.

Alternatively, in another embodiment of the present disclosure, by performing a patterning operation on the interlayer dielectric material layer 301, two trenches 310 adjacently disposed may be formed such that a distance between the two trenches 310 is not greater than 12 micrometers.

Step S130 may be implemented by a method such as:

forming a source-drain material layer 401 on one side of the interlayer dielectric layer 300 far away from the substrate 100;

the source drain material layer 401 is patterned to form two conductive structures 411 disposed adjacently.

Alternatively, when forming the source/drain material layer 401, the thickness of the source/drain material layer 401 may be at least 0.1 μm smaller than the depth of the trench 310.

Alternatively, before step S120, a gate layer 200 may be further formed on one side of the substrate 100; in step S120, an interlayer dielectric layer 300 may be formed on a side of the gate layer 200 away from the substrate 100, and an orthographic projection of any one of the trenches 310 on the substrate 100 is completely misaligned with an orthographic projection of the gate layer 200 on the substrate 100.

Further, in step S120, the trench 310 may be made to penetrate the interlayer dielectric layer 300.

Details, principles and effects of the method for manufacturing an array substrate of the present disclosure have been discussed in detail in the above embodiments of the array substrate, or can be reasonably derived according to the details described in the above embodiments of the array substrate, and are not repeated herein.

Embodiments of the present disclosure also provide a display panel including any one of the array substrates described in the above array substrate embodiments. The display panel may be an OLED display panel, an LCD display panel, a QD-OLED display panel, or other type of display panel. Since the display panel has any one of the array substrates described in the above embodiments of the array substrate, the display panel has the same advantageous effects, and the disclosure is not repeated herein.

Embodiments of the present disclosure also provide a display device including any one of the display panels described in the above display panel embodiments. The display device may be a cell phone screen, a computer monitor, a television, or other type of display device. Since the display device has any one of the display panels described in the above display panel embodiments, the display device has the same beneficial effects, and the disclosure is not repeated herein.

It is to be understood that the disclosure is not limited in its application to the details of construction and the arrangements of the components set forth in the specification. The present disclosure is capable of other embodiments and of being practiced and carried out in various ways. The foregoing variations and modifications are within the scope of the present disclosure. It should be understood that the disclosure disclosed and defined in this specification extends to all alternative combinations of two or more of the individual features mentioned or evident from the text and/or drawings. All of these different combinations constitute various alternative aspects of the present disclosure. The embodiments of this specification illustrate the best mode known for carrying out the disclosure and will enable those skilled in the art to utilize the disclosure.

Claims

1. The array substrate is characterized by comprising a substrate, an interlayer dielectric layer and a source drain layer which are sequentially stacked; wherein,

the source-drain layer comprises two adjacent conductive structures, the interlayer dielectric layer is provided with two grooves for accommodating the two conductive structures in a one-to-one correspondence manner, and the thickness of any conductive structure is smaller than the depth of the corresponding groove;

wherein the two adjacently arranged conductive structures form a conductive structure pair; the source-drain layer is provided with source-drain leads, and the parts, close to each other, of the two adjacent source-drain leads are two conductive structures in one conductive structure pair respectively; the source drain layer comprises a molybdenum niobium layer and a copper layer which are sequentially stacked, the molybdenum niobium layer is arranged on one side, close to the substrate, of the copper layer, the thickness of the molybdenum niobium layer is 0.03-0.04 micrometer, and the thickness of the copper layer is 0.7-0.8 micrometer; the width of the source drain lead is 4 to 5 micrometers, and the minimum distance between two adjacent source drain leads is 5 to 8 micrometers; the interlayer dielectric layer is made of silicon oxide, and the thickness of the interlayer dielectric layer is 0.8 to 0.9 micrometer; wherein, any one groove is close to the side wall of the other groove, and the included angle between the groove and the surface of the interlayer dielectric layer far away from the substrate base plate is not more than 95 degrees; an included angle between the side wall of any one groove far away from the other groove and the surface of the interlayer dielectric layer far away from the substrate base plate is an obtuse angle and is smaller than 140 degrees; the distance between the surface of any conductive structure far away from the substrate and the surface of the interlayer dielectric layer far away from the substrate is not less than 0.1 micrometer.

2. The array substrate of claim 1, further comprising a gate layer disposed between the substrate and the interlayer dielectric layer; the orthographic projection of any conductive structure on the substrate is completely not overlapped with the orthographic projection of the gate electrode layer on the substrate.

3. The array substrate of claim 2, wherein the trench penetrates the interlayer dielectric layer.

4. A display panel comprising the array substrate according to any one of claims 1 to 3.

5. A preparation method of an array substrate is characterized by comprising the following steps:

providing a substrate base plate;

forming an interlayer dielectric layer on one side of the substrate, wherein the interlayer dielectric layer is provided with two adjacent grooves; wherein, any one groove is close to the side wall of the other groove, and the included angle between the groove and the surface of the interlayer dielectric layer far away from the substrate base plate is not more than 95 degrees; an included angle between the side wall of any one groove far away from the other groove and the surface of the interlayer dielectric layer far away from the substrate base plate is an obtuse angle and is smaller than 140 degrees; the interlayer dielectric layer is made of silicon oxide, and the thickness of the interlayer dielectric layer is 0.8 to 0.9 micrometer;

forming a source drain layer on one side, far away from the substrate, of the interlayer dielectric layer, wherein the source drain layer comprises two adjacent conductive structures, and the two conductive structures are accommodated in the two grooves in a one-to-one correspondence manner; the thickness of any conductive structure is smaller than the depth of the corresponding groove; wherein the two adjacently arranged conductive structures form a conductive structure pair; the source-drain layer is provided with source-drain leads, and the parts, close to each other, of the two adjacent source-drain leads are two conductive structures in one conductive structure pair respectively; the source drain layer comprises a molybdenum niobium layer and a copper layer which are sequentially stacked, the molybdenum niobium layer is arranged on one side, close to the substrate, of the copper layer, the thickness of the molybdenum niobium layer is 0.03-0.04 micrometer, and the thickness of the copper layer is 0.7-0.8 micrometer; the width of the source drain lead is 4 to 5 micrometers, and the minimum distance between two adjacent source drain leads is 5 to 8 micrometers; the distance between the surface of any conductive structure far away from the substrate and the surface of the interlayer dielectric layer far away from the substrate is not less than 0.1 micrometer;

wherein forming an interlayer dielectric layer on one side of the substrate base plate includes:

forming a first photoresist layer on one side of the interlayer dielectric material layer far away from the substrate base plate; the thickness of the first photoresist layer is 2.5 to 3.0 micrometers;

patterning the first photoresist layer using a halftone mask to form a patterned first photoresist layer; the patterned first photoresist layer is provided with two exposure holes corresponding to the two grooves one by one, the slope angle of the side wall of the two exposure holes close to each other is not less than 85 degrees, and the slope angle of the side wall of the two exposure holes far away from each other is not less than 40 degrees;

etching the exposed interlayer dielectric material layer by dry etching to form the trench; in the dry etching, the flow rate of carbon tetrafluoride is 1000 to 1400sccm, and the flow rate of oxygen is 1500 to 1900sccm;

and carrying out wet stripping on the first photoresist layer.

6. The method for manufacturing an array substrate according to claim 5, further comprising:

7. The method of claim 6, wherein forming an interlayer dielectric layer on one side of the substrate base further comprises: