JPS62286271A - Manufacture of thin-film transistor substrate - Google Patents

Abstract

PURPOSE:To decrease the number of masks, by etching a semiconductor layer and an insulating layer in the same pattern, forming a pattern, which is isolated with the double layers of the semiconductor layer and the insulating layer, using a part where the double layers do not remain, and providing a connecting part with a display electrode and a lead-out part for a gate electrode bus. CONSTITUTION:ITO and Cr on a glass substrate 10 are etched so that a picture element shape comprising a transparent gate electrodes 11b and Cr 12 remains. Patterns of the Cr electrodes 12a and 12b are formed. An SiNx layer 13 as an insulating film and an aSi layer 14 as a semiconductor layer sector are formed by a plasma CVD method. Etching is performed, and an aSi island region, which is to become a gate insulating layer and a channel region, is formed. Al is deposited by a DC sputtering method. Al is etched by using a third mask so that an Al source electrode 15a and an Al drain electrode 15b are made to remain in the pattern. The ITOs 11a and 11b are formed beneath 12a and 12b, and the gate insulating film 13 is formed beneath the aSi 14 in the same pattern. Thus the number of the masks can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION 3. DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a method for manufacturing an active matrix display substrate using thin film transistors (TPT), and particularly to a method for manufacturing a substrate for a liquid crystal display.

Background Art Displays using active matrix type display substrates using TPT have been actively researched because they provide higher image quality than simple matrix type display devices. T.P.
The active matrix display device using T is the 10th
This is the configuration shown in the figure.

A source (or drain) electrode busbar 21 and a gate electrode busbar 22 formed on a transparent substrate 20, a display substrate 25 supporting a TFT 23 and a picture element electrode 24, and a counter electrode 2.
6 and a counter substrate 27 having a substrate 25.27.
A liquid crystal is sealed in between. Active matrix display substrates using TPT have the disadvantage that they require more steps and are more expensive than simple matrix display devices, and methods have been proposed to reduce the number of steps. for example,
JP-A No. 59-501562 discloses a method of reducing the mask operation to two steps, but the TPT of this method is a staggered type in which an insulator is formed on a semiconductor, and it is difficult to obtain a high-quality TPT. is difficult.

On the other hand, an inverted staggered TF that forms a semiconductor on an insulator
Although high-quality TPT can be obtained with T, six steps of mask operation are required for use as a matrix display substrate. This method will be explained with reference to FIG.

The TFT consists of an Or gate 31, a Si, 5N5 insulating layer 32, and a three-layer ASI layer deposited on an insulating substrate 30.Table 4A':/
- It is formed by a drain 36 and a drain 36.

The picture element electrode 38 is made of Indium-Tin-Ox
ide). The TFT and picture element electrode 38 are coupled to a drain 36 that follows a contact hole 42 formed in the insulating layer 32. The following pattern forming step is required to form this structure.

(1) Etching ITO to form the picture element electrode 38.

(2) Etching the gate metal to form the gate electrode bus bar 31
form.

(3) An opening 42 is provided in the insulating layer 32. (Also forms a peripheral gate electrode busbar extraction portion.) (4) Etch the semiconductor 34 to form an island pattern.

(5) Etching the source/drain metal to form a drain 36 connected to the picture element electrode 38 via the source electrode bus line 35 and contact hole 42 .

This method requires 6 masks. In the above-described manufacturing method, a doped n-aSi layer is not formed to provide ohmic relationship between the source/drain electrodes and the semiconductor layer. In order to add the step of depositing this n+-asi layer, the n''-aSi layer is removed in the source/drain pattern, and the aSi layer (as described above in the patterning process) is removed in advance to prevent the aSi layer of the semiconductor layer from being etched. of (2
) and (3))) A step of forming a channel protective layer is required. In this case, six masks are required.

Problems to be Solved by the Invention As mentioned above, after depositing an insulating layer, a semiconductor layer is deposited. In order to obtain an active matrix display substrate using high quality TFTs, 6 to 6 masks are required and the process is time-consuming. There were many.

Means for Solving the Problems The present invention provides a method for manufacturing an active matrix display substrate in which each picture element includes a thin film transistor and a display picture element electrode as constituent elements, the method comprising: depositing a conductive layer on an insulating substrate; a first step of patterning the conductive layer using a first mask operation to form an electrode busbar; a second step of depositing an insulating layer and a semiconductor layer; and a second step of patterning the conductive layer using a first mask operation to form an electrode busbar. Leaving the semiconductor layer and the insulating layer at the intersection of the bus line and the source (or drain) electrode bus line and at the part where the thin film transistor is formed, the semiconductor layer and the insulating layer at least at the peripheral extraction part of the gate electrode bus line and the display electrode part. a third step of removing the insulating layer;
Provided is a method for manufacturing a display substrate, which includes the following steps.

Function: In the present invention, the process of forming the opening 42 in the insulating layer 32 and the process of etching the semiconductor 34 to form an island-like pattern shown in the prior art are performed using the same mask, thereby reducing the number of masks.

That is, the semiconductor layer and the insulating layer are etched in the same pattern to form a pattern separated by a double layer of the semiconductor layer and the insulating layer, and a part of the part where the double layer does not remain is used to connect the display electrode and the gate electrode. This is used as a take-out part for the bus bar.

EXAMPLES Below, examples will be explained using plan views and sectional views.

(Example 1) FIG. 2 is a plan view explaining the process, and FIG. 1 is a sectional view.

(1) A transparent electrode ITO of 100 OA and an Or metal layer of 1000 layers are deposited on the glass substrate 10 by DC sputtering.

(2) Etching is performed to leave ITO and Or in the form of a gate electrode formed of ITOlla, Cr12&, and a pixel electrode formed of TO11b and Cr12b.

In FIG. 2a, a pattern of Or electrodes 12&, 12b is formed, and ITOlla, 11b are formed below this.

(3) Next, SiNx was formed as an insulating layer by plasma CvD method.
Layer 13 is 40oO, and 4 layers are formed on the aSiSi layer as a semiconductor layer.
ooO people accumulate.

(4) Etching is performed in a photolithography process using a second mask so that layers 13 and 14 are left in the pattern shown in Figure 1, forming a gate insulating layer and a channel region.
A Si island region is formed.

(6) Next, 7,000 layers are deposited by DC sputtering.

(6) Etching is performed by a photolithography process using a third mask so as to leave the source (or drain) electrode 15a1 in the shape of the drain (or source) electrode 15b in the pattern shown in FIG. 2C. A-person/, B-s/ in Fig. 2 of the completed active matrix substrate
A cross-sectional view of the line portion is shown in Figure 1a.

Shown in b. Although not shown in FIG. 2, 12
a, xTolla under 12b.

11b, and a gate insulating layer 13 is formed under the aSi 14 in the same pattern.

In this embodiment, an active matrix substrate can be formed using three masks. Since the portion of the Or picture element electrode 12b remains on the picture element electrode, it can be used for a reflective liquid crystal display or the like. Note that a liquid crystal display device can be obtained by placing the substrate shown in FIG. 1.2 and another glass substrate (on which a color filter is formed in the case of color) facing each other and sealing liquid crystal between them.

(Example 2) This example is almost the same as Example 1. Omit explanations of common processes. FIG. 4 is a plan view of the substrate formed in this step, and FIGS. 3a and 3b are taken along the line CC/ in FIG. 4.

A cross section taken along the line DD' is shown. Following (1) and 12) of Example 1, (3) SiN as an insulating layer was formed by plasma CvD method.
The x layer 13 is deposited with a thickness of 4,000, the asi layer 14 is deposited with a thickness of 100 OA as a semiconductor layer, and the n+a Si layer 16 is deposited with a thickness of 500.

(4) Etch layers 13, 14, 16 to leave them in the same pattern as shown in Figure 2.

(5) 50OA of DC sputtering MoSi2, 1 person
7,000 people.

(6) Selectively etching the MoSi□ and forming the source (or drain) of the pattern shown in Fig. 4
Electrode 16a9 drain (or source) electrode 15b.

Etch to leave in the form of λg gate backup metal 150. The MoSi217 under the person is
1]&, 1ab, 15Ct7) n aSi 16 of the exposed part not covered by the pattern
and etching a part of &SiN. Another 161L
By etching the Or metal 12b on the gate electrode and picture element electrode that are not covered with ~158,141L, a transparent pattern 11a is formed as shown in FIGS. 4 and 3.
, 11b can be exposed, and the picture element electrode becomes a transparent electrode.

A cross-sectional view taken along line CC' and DD' of the active matrix substrate shown in FIG. 4 thus completed is shown in FIGS. 3&b. In this embodiment, an active matrix substrate can be formed using three masks.

Since the picture element electrode is transparent, it is used in transmissive liquid crystal displays and the like.

(Example 3) This example is a case where a channel protective layer is provided, and the fifth
This is a method for realizing an active matrix substrate having picture element units (indicated by broken lines) of the equivalent circuit shown in the figure. 101 is a gate line, 152L is a source line (or drain line), 15d is a common electrode, 104 is a transistor, 1
06 is a load capacitor such as a liquid crystal, and 106 is an auxiliary capacitor connected to the common electrode. The process will be explained using the final plan view in FIG. 7 and the process sectional view in FIG. X in FIG. 8 is a cross-sectional process of the lead-out portion of the gate electrode busbar in the periphery, although the seventh step is not shown.

Steps (1) and (2) of Example 1 are common. Following this step, (3) SiNx layer 1 as an insulating layer by plasma CVD method.
3 to 4000 people, aSi layer 14 as a semiconductor layer to 600
A, 1000 SiNx layers 18 are deposited.

(4) Etch the layer 18 which will become the channel protection layer so as to leave it in the shape of the pattern 11a shown in FIG. (Figure 8b) (5) Impurity-doped naSi using plasma CVD method
Deposit layer 16 by 500 people. (Fig. 8C) (6) Layers 16, 14, 13.12 are etched by etching the hatched pattern 5o and the gate electrode extraction part in Fig. 7.
11 is exposed. (FIG. 8d) At this time, ITOlld is exposed at the extraction portion of the gate electrode.

(7) DCC Nisbatate MO5i217 SOO person,
Deposit Ad15 by 7000 people.

(s) The layers 1s and 17 are arranged as a source (
Etching is performed so as to leave the patterns of the drain (or drain) electrode 15a, the drain (or source) electrode 15b, and the common electrode 15d. Further 16a.

Etch the exposed layer 18.14 not covered by 15kl, 15d, 181L. (FIG. 8e) The active matrix substrate thus completed can be completed using four masks.

(Example 4) This example is also a case where a channel protective layer is provided, and the sixth
This is a method of realizing an active matrix circuit having picture element units (indicated by broken lines) of the equivalent circuit shown in the figure. 111 is a gate line, 112 is a source line (or gate line), 113 is a gate line of the next stage, 114 is a transistor, 116 is a load capacitor such as a liquid crystal, and 116 is an auxiliary capacitor connected to the next stage gate line. The process of an active matrix circuit for realizing this is shown in the plan view of FIG.

In this embodiment, an active matrix substrate using TFTs can be realized using four masks.

In the above embodiment, the gate electrode is formed using a double layer of ITO and Cr, and the gate electrode bus line and the display pixel electrode are patterned at the same time. However, it is possible to form the gate electrode bus line and the display pixel electrode using different materials. Needless to say, the manufacturing method of the present invention can be applied even if patterning is performed by an independent process.

In addition, the pattern in the third step of etching the semiconductor layer and the insulating layer in the same pattern is to leave the semiconductor layer and the insulating layer at the minimum at the intersection of the gate electrode bus line and the source (or drain) electrode bus line and at the TPT area. However, it is not necessarily necessary to cover the gate electrode bus and the source (or drain) electrode bus as shown in the embodiment.

Further, in the above embodiment, an example was shown in which an Or gold metal gate wiring was formed on ITO, but a transparent electrode may be used instead of ITO, such as 5n02, CdO, ZnO, etc. The metal on the transparent electrode should be selected from a material that can withstand the etching agent of the semiconductor layer and the insulating layer.
, Mo, silicide, etc. Furthermore, metal is person 4 and M
It may be composed of two or more layers such as oSi2, human e and T1. In addition, as an insulating layer, SiNx is used as an insulating layer. Ta205. There is no particular choice of material such as Ae205, and what about the semiconductor layer? Although Lsi is used, GdSe, Te, polysi, etc. may also be used.

Either wet etching or dry etching (reactive ion etching, chemical dry etching) may be used for etching.

Effects of the Invention By using the process according to the present invention, the number of masks for an active matrix substrate using TPT with a reverse star type, which conventionally requires 5 to 6 stages of masks, can be reduced by one. By adding another devised process, the number of masks can be reduced to 3 to 4 stages, and a structure and manufacturing method have been disclosed that greatly contribute to cost reduction and yield improvement.

[Brief explanation of drawings]

1 and 2 are cross-sectional views and plan views explaining the steps of Example 1 of the present invention, FIGS. 3 and 4 are plan views and cross-sectional views explaining the steps of Example 2 of the present invention, 5 and 6 are equivalent circuit diagrams of Embodiment 3 and Embodiment 4, FIG. 7 and 8 are plan views and cross-sectional views explaining the steps of Embodiment 3 of the present invention, and FIG. 10 is an exploded view of a display device using a TPT, and FIG. 11 is a diagram illustrating a conventional process using an inverted staggered TPT. 11...Transparent electrode, 12...Metal layer,
12 &... Gate pass line pattern, 12b
...Picture element electrode pattern. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure Al source compliance Figure 3//λ Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11

Claims (2)

[Claims] (1) A source (or drain) electrode bus that transmits a display signal, a gate electrode bus that transmits a scanning signal, a thin film transistor at the intersection of the source (or drain) electrode bus and the gate electrode bus, and a drain of the thin film transistor. (or source) and a display pixel electrode connected to the substrate, the method includes depositing a conductive layer on an insulating substrate and patterning the conductive layer using a first mask operation. The first electrode that forms the gate electrode busbar
a second step of depositing an insulating layer and a semiconductor layer; and a second step of depositing an insulating layer and a semiconductor layer, and a second mask operation to remove at least the intersection of the gate electrode bus and the source (or drain) electrode bus and the portion where the thin film transistor is to be formed. A method for manufacturing a thin film transistor substrate, comprising: a third step of removing the semiconductor layer and the insulating layer at least in the peripheral extraction portion of the gate electrode busbar and the display electrode portion, while leaving the semiconductor layer and the insulating layer. (2) The thin film transistor substrate according to claim 1, wherein in the third step, the semiconductor layer and the insulating layer are formed separately corresponding to each picture element on the gate electrode bus line. Production method.