JP4034376B2 - Manufacturing method of active matrix type liquid crystal display device - Google Patents

Manufacturing method of active matrix type liquid crystal display device Download PDF

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JP4034376B2
JP4034376B2 JP10525597A JP10525597A JP4034376B2 JP 4034376 B2 JP4034376 B2 JP 4034376B2 JP 10525597 A JP10525597 A JP 10525597A JP 10525597 A JP10525597 A JP 10525597A JP 4034376 B2 JP4034376 B2 JP 4034376B2
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基鉉 柳
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エルジー フィリップス エルシーディー カンパニー リミテッド
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66765—Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78663—Amorphous silicon transistors
    • H01L29/78669—Amorphous silicon transistors with inverted-type structure, e.g. with bottom gate
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device

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  • Power Engineering (AREA)
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  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Liquid Crystal (AREA)
  • Thin Film Transistor (AREA)

Description

【０００１】
【発明の属する技術分野】
本発明はアクティブマトリクス方式の液晶表示装置の製造方法に関する。
【０００２】
【従来の技術】
一般のアクティブマトリクス液晶表示装置（以下には、「AMLCD」と称する）には、各々画素の駆動及び制御のため、スイッチング素子として薄膜トランジスタ（以下には、「TFT」と称する）のような能動素子が用いられている。
図１のようにTFTアレイを具備した一般の液晶表示装置は、透明ガラス基板上に大略長方形の画素電極４７が行、列で近接して配列されている。ゲートバス配線（アトレスライン）13は画素電極47の各行配列に沿って近接して形成されており、ソースバス配線（データライン）14は画素電極４７の各列配列に沿って近接して形成されている。
【０００３】
図２は図１の液晶表示素子の一部の拡大平面図であり、透明ガラス基板（図示せず）上にゲート電極の形成部33（図３）を有するゲートバス配線13が形成されている。絶縁層35（図４参照）が前記ゲートバス配線13及びゲート電極33を覆い、該絶縁層上にゲートバス配線13と交差する多数の平行なソースバス配線14が形成されている。又、前記ゲートバス配線13とソースバス電極14の交差部の近傍に、半導体層37（図４参照）が該ゲートバス配線及びゲート電極を覆っている絶縁層上に形成されている。該半導体層上にソース電極43a及びゲート電極43bが対向するように互いに離間して形成されて、能動素子としてのTFTが構成される。
【０００４】
従来のAMLCDの製造方法について、図２の２ー２線に沿って切断した切断面である図３〜図７を参照して説明する。
【０００５】
透明ガラス基板31上に第１金属層を被着した後、パータニングを行ってゲートバス配線13の拡張部であるゲート電極33を形成する（図３）。
基板の全面にSiNxから成る第１絶縁層（ゲート絶縁層）35と，ａ−Ｓｉから成る半導体層37及びSiNxから成る第２絶縁層とを順次被着する。
図４に示すように、前記第２絶縁層のパターニングを行ってエッチストッパ40を形成し、n+型a-Siから成る不純物がドープされた半導体39層を基板の全面に被着した後、該不純物半導体層39と半導体層37とを同時にパターニングする（図５）。
【０００６】
第２金属層43が次に前記基板の全面に被着され、その後、第２金属層をパターニングして、ソースバス配線及びソースバス配線から分岐するソース電極43aと、ドレイン電極43bとを形成する。次に、図６に示すように、前記ソース、ドレイン電極をマスクとして用いて不純物半導体層39の露出されている部分をエッチングする。
【０００７】
第１絶縁層と前記ソース電極43a及びドレイン電極43bが形成されている基板全面に窒化シリコン層を被着して保護絶縁層45を形成する。次に保護絶縁層をエッチングしてコンタクトホ−ルを形成する。続いて、前記基板の全面の絶縁保護層上にスパッタリング法でＩＴＯ層を被着して、前記ＩＴＯ層をパターニングして画素電極47を形成する。画素電極はコンタクトホ−ルを通じてドレイン電極43bと電気的に接触する（図７）。
【０００８】
【発明が解決しようとする課題】
従来のTFTの製造方法は、非常に複雑である。また、AMLCDの各々パターン形成の工程においては、マスクパターンの形成、正確なパターニングを行うための高度のマスクの位置合わせ、フォトレジストの塗布及び現象等の工程で時間がたくさん必要であり、又、不良の発生で歩留まりの低減等の問題点がある。
【０００９】
【課題を解決するための手段】
本発明はAMLCDの製造工程で第２金属層と半導体層との同時パターニングを行い、パターン形成のためのマスク工程の数を減らすことを目的とする。又、保護絶縁層をマスクとして用いて第２金属層と不純物を含む第２半導体層とを同時にエッチングしてソース電極及びドレイン電極を形成する。
【００１０】
特に、前述した目的を達成するために本発明は、次の方法で製造する。透明ガラス基板上に第１金属層を被着した後、パターニングしてゲートバス配線及びゲート電極を形成する。前記ゲートバス配線及びゲート電極が形成された前記透明ガラス基板上にゲート絶縁層、第１半導体層及びエッチング防止（絶縁）層を順次被着する。前記エッチング防止絶縁層をパターニングしてエッチストッパを形成し、前記エッチストッパ及び前記第１半導体層上に不純物ドープの第２半導体層を被着する。前記不純物ドープの第２半導体層上に第２金属層を被着し、前記第２金属層、不純物ドープの第２半導体層及び第１半導体層をパターニングする。
【００１１】
パターニングされた第２金属層とゲート絶縁層上に保護絶縁層を被着する。前記保護絶縁層のパターニングを行ってコンタクトホールを形成し、前記エッチストッパ上の第２金属層の一部を露出させる。前記露出された第２金属層及び保護絶縁層上に透明導電膜を形成する。前記コンタクトホールを通じて第２金属層と電気的に接続するように前記透明導電膜をパターニングして画素電極を形成する。そして、前記保護絶縁層をマスクとして用いて、前記第２金属層の一部と、不純物ドープの第２半導体層の一部とをエッチングして、ソース電極とドレイン電極とを形成する。
【００１２】
従って、本発明によるAMLCDは、透明ガラス基板と、該透明ガラス基板上に形成されたゲートバス配線及びゲート電極と、該ゲートバス配線とゲート電極が形成されている基板上に形成されたゲート絶縁層と、該ゲート絶縁層上に形成された第１半導体層と、前記第１半導体層の一部分上に形成されたエッチストッパと、前記エッチストッパ上に二領域に分離された不純物ドープの第２半導体層と、分離されて形成された前記不純物ドープの第２半導体層上の各部分に形成されたソース電極及びドレイン電極と、前記ソース電極及びドレイン電極上に形成され、コンタクトホールを有する保護絶縁層と、前記コンタクトホールを通じて前記ドレイン電極に電気的に接続され、前記保護絶縁層上に形成された画素電極とから成る構造を有する。
【００１３】
【発明の実施の形態】
以下、本発明のAMLCDの製造方法の実施の形態を図面を参照して説明する。
まず、透明ガラス基板131の一面にAl、又は、Al系合金のAl-Pd、Al-Si、Al-Si-Ti、Al-Si-Cu等から成る第１金属層をスパッタリング法で被着する。写真食刻法で第１金属層を選択的にエッチングしてゲート電極133を形成する（図８）。
もし必要であれば、耐化学性、耐熱性、特に、続いて形成するゲート絶縁層との接着性等の向上のため、ゲート電極133を陽極酸化させ、陽極酸化層を形成するようにしてもよい。該陽極酸化層は続いて形成されるゲート絶縁層の窒化シリコンと共に絶縁層として機能してゲート電極133と近接の信号線間の電気的絶縁性を
向上させる役割を果たす。
【００１４】
ゲート電極が形成された前記透明ガラス基板131上に第１絶縁層（ゲート絶縁層）135、不純物がドープされていないa-Si半導体層137及び窒化シリコンから成る第２絶縁層140を順次被着する（図９）。
【００１５】
図１０から分かるように、第２絶縁層をエッチングしてエッチストッパ140を形成し、エッチストッパ140及び半導体層137上にプラスマCVD装置で水素ガス及びホスフィンガスを使って、Ｎ+半導体層139を被着する（図１１）。
【００１６】
続いて、図１２に示すように、Pd、Al-Si、Al-Si-Ti及びAl-Si-Cuのいずれかの一つの金属から成る第２金属層143をスパッタリング法で被着し、次に第２金属層143上に感光膜（図示せず）を塗布する。そして感光膜の選択された部分を露光し、現象して、第２金属層143の選択された部分を露出する。次に、前記現象されたパターンで、第２金属層143、Ｎ+半導体層139及び半導体層137を除去する。図１３ように、第２金属層143、Ｎ+半導体層139及び半導体層137は所望の形態にパターニングされる。
【００１７】
ゲート絶縁層135及びパターニングされた第２金属層143の上にプラスマCVD装置でアンモニアガス、シランガス、水素ガスを使って、窒化珪素層から成る保護絶縁層145を被着する。
そして、エッチストッパ140上の開口と、第２金属層143の一部分が露出するコンタクトホールを形成するように保護絶縁層145をパターニングする（図１４）。
【００１８】
図１５に示すように、画素電極147を形成する。そして、パターニングによりコンタクトホールを通じて第２金属層143とが電気的に接続するようにコンタクトホールの中と保護絶縁層145上にＩＴＯ層を被着する。
そして、図１６に示されるように、保護絶縁層145をマスクとして用いて、露出された第２金属層の部分143とＮ+半導体層139とをエッチングして、ソース電極143aとドレイン電極143bを形成する。
前記第２金属層143とＮ+半導体層139のエッチングの前に、保護絶縁層145にコンタクトホールを形成して、その後に前記画素電極147を形成する理由は、前記画素電極147は、コンタクトホールを介して露出された第２金属層143をエッチングされることを防ぐ役割をするためである。従って、製造工程の順序が重要である。それで、第２金属層143及びＮ+半導体層139は単一の工程でエッチングされる。これに対して、前記の従来の工程によると、エッチングストッパ140上に形成される各層は各々別々の工程でエッチングされる。
【００１９】
上述した方法で製造されたAMCLDは、以下に述べる構造を有している。透明ガラス基板131上に形成されたゲートバス配線及びゲート電極133と、該ゲートバス配線及びゲート電極133が形成されている基板上に形成されたゲート絶縁層135と、該ゲート絶縁層135上に形成された半導体層137と、半導体層137上のゲート電極133の位置に合わせて形成されたエッチストッパ140と、エッチストッパ140及び半導体層137の各々を覆う二領域に離間した不純物Ｎ+半導体層139と、前記不純物Ｎ＋半導体層139の一領域上に形成されたソース電極143aと、他の一領域上に形成されたドレイン電極143bと、前記ゲート絶縁層、ソース電極143a及びドレイン電極143bを覆っている保護絶縁層と、前記保護絶縁層上のコンタクトホールを通じてドレイン電極143bと電気的に接続されている画素電極147と、から成る構造である。
【００２０】
もし、ここで第２絶縁層140が形成されてない場合には、半導体層139は、開口を通じて露出されて、コンタクト物質から保護されない。それで、半導体層139との粘着性が良い酸化シリコンあるいは窒化シリコンで第２絶縁層140を形成するため、前記第２絶縁膜は、エッチストッパ及び半導体層139の保護膜の役割をする。
【００２１】
【発明の効果】
従って、本発明は第２金属層143、不純物半導体層139及び半導体層137を一つの工程で同時にパターニングするので、製造コストが低減され、製造の時間が短縮される。又、ソース電極及びドレイン電極を付加的なマスク工程を必要とすることなく、単一の工程で形成することができる。それ故、歩留まりが向上する。
【図面の簡単な説明】
【図１】液晶表示装置の回路図。
【図２】液晶表示装置の一部を示す拡大平面図。
【図３】従来の液晶表示装置の製造工程を示す断面図。
【図４】従来の液晶表示装置の製造工程を示す断面図。
【図５】従来の液晶表示装置の製造工程を示す断面図。
【図６】従来の液晶表示装置の製造工程を示す断面図。
【図７】従来の液晶表示装置の製造工程を示す断面図。
【図８】本発明の実施形態による液晶表示装置の製造工程を示す断面図。
【図９】本発明の実施形態による液晶表示装置の製造工程を示す断面図。
【図１０】本発明の実施形態による液晶表示装置の製造工程を示す断面図。
【図１１】本発明の実施形態による液晶表示装置の製造工程を示す断面図。
【図１２】本発明の実施形態による液晶表示装置の製造工程を示す断面図。
【図１３】本発明の実施形態による液晶表示装置の製造工程を示す断面図。
【図１４】本発明の実施形態による液晶表示装置の製造工程を示す断面図。
【図１５】本発明の実施形態による液晶表示装置の製造工程を示す断面図。
【図１６】本発明の実施形態による液晶表示装置の製造工程を示す断面図。
【符号の説明】
13 ゲートバス配線
14 ソース配線
31、131 透明ガラス基板
33、133 ゲート電極
35、135 第１絶縁層
37、137 半導体層
39、139 不純物半導体層
40、140 エッチストッパ
43、143 第２金属層
43a、143a ソース電極
43b、143b ドレイン電極
45、145 保護絶縁層
47、147 画素電極[0001]
BACKGROUND OF THE INVENTION
The present invention relates to the manufacture how the active matrix liquid crystal display device.
[0002]
[Prior art]
A general active matrix liquid crystal display device (hereinafter referred to as “AMLCD”) includes an active element such as a thin film transistor (hereinafter referred to as “TFT”) as a switching element for driving and controlling each pixel. Is used.
In a general liquid crystal display device having a TFT array as shown in FIG. 1, pixel electrodes 47 having a substantially rectangular shape are arranged close to each other in rows and columns on a transparent glass substrate. The gate bus lines (atres lines) 13 are formed close to each other along the row arrangement of the pixel electrodes 47, and the source bus lines (data lines) 14 are formed close to each other along the column arrangement of the pixel electrodes 47. Has been.
[0003]
FIG. 2 is an enlarged plan view of a part of the liquid crystal display element of FIG. 1 , and a gate bus wiring 13 having a gate electrode forming portion 33 (FIG. 3) is formed on a transparent glass substrate (not shown). . An insulating layer 35 (see FIG. 4) covers the gate bus wiring 13 and the gate electrode 33, and a number of parallel source bus wirings 14 intersecting the gate bus wiring 13 are formed on the insulating layer. A semiconductor layer 37 (see FIG. 4) is formed on the insulating layer covering the gate bus line and the gate electrode in the vicinity of the intersection of the gate bus line 13 and the source bus electrode 14. On the semiconductor layer, the source electrode 43a and the gate electrode 43b are formed so as to be opposed to each other so as to constitute a TFT as an active element.
[0004]
A conventional AMLCD manufacturing method will be described with reference to FIGS. 3 to 7 which are cut surfaces taken along line 2-2 in FIG.
[0005]
After the first metal layer is deposited on the transparent glass substrate 31, patterning is performed to form a gate electrode 33 which is an extended portion of the gate bus wiring 13 (FIG. 3).
A first insulating layer (gate insulating layer) 35 made of SiNx, a semiconductor layer 37 made of a-Si, and a second insulating layer made of SiNx are sequentially deposited on the entire surface of the substrate.
As shown in FIG. 4, the second insulating layer is patterned to form an etch stopper 40, and a semiconductor 39 layer doped with impurities composed of n + type a-Si is deposited on the entire surface of the substrate. The impurity semiconductor layer 39 and the semiconductor layer 37 are patterned simultaneously (FIG. 5).
[0006]
The second metal layer 43 is deposited on the entire surface of the front Stories substrate to the next, then, by patterning the second metal layer, a source electrode 43a branched from the source bus line and source bus line, and a drain electrode 43b formed To do. Next, as shown in FIG. 6, the exposed portion of the impurity semiconductor layer 39 is etched using the source and drain electrodes as a mask.
[0007]
A protective insulating layer 45 is formed by depositing a silicon nitride layer on the entire surface of the substrate on which the first insulating layer and the source electrode 43a and drain electrode 43b are formed. Next, the protective insulating layer is etched to form a contact hole. Subsequently, an ITO layer is deposited on the insulating protective layer on the entire surface of the substrate by sputtering, and the ITO layer is patterned to form a pixel electrode 47. The pixel electrode is in electrical contact with the drain electrode 43b through the contact hole (FIG. 7).
[0008]
[Problems to be solved by the invention]
Conventional TFT manufacturing methods are very complex. Also, in each pattern formation process of AMLCD, a lot of time is required in processes such as mask pattern formation, advanced mask alignment for accurate patterning, photoresist application and phenomenon, etc. There are problems such as yield reduction due to the occurrence of defects.
[0009]
[Means for Solving the Problems]
An object of the present invention is to perform simultaneous patterning of the second metal layer and the semiconductor layer in the manufacturing process of AMLCD and reduce the number of mask processes for pattern formation. In addition, the source electrode and the drain electrode are formed by simultaneously etching the second metal layer and the second semiconductor layer containing impurities using the protective insulating layer as a mask.
[0010]
In particular, in order to achieve the above-mentioned object, the present invention is manufactured by the following method. After depositing the first metal layer on the transparent glass substrate, patterning is performed to form gate bus lines and gate electrodes. A gate insulating layer, a first semiconductor layer, and an etching preventing (insulating) layer are sequentially deposited on the transparent glass substrate on which the gate bus wiring and the gate electrode are formed. The etch stop insulating layer is patterned to form an etch stopper, and an impurity-doped second semiconductor layer is deposited on the etch stopper and the first semiconductor layer. Said second metal layer deposited on the second semiconductor layer on the impurity doped, the second metal layer, patterning the second semiconductor layer and the first semiconductor layer of doped.
[0011]
A protective insulating layer is deposited on the patterned second metal layer and gate insulating layer. The protective insulating layer is patterned to form a contact hole, and a part of the second metal layer on the etch stopper is exposed. A transparent conductive film is formed on the exposed second metal layer and protective insulating layer. A pixel electrode is formed by patterning the transparent conductive film so as to be electrically connected to the second metal layer through the contact hole. Then, using the protective insulating layer as a mask, a part of the second metal layer and a part of the impurity- doped second semiconductor layer are etched to form a source electrode and a drain electrode.
[0012]
Accordingly, the AMLCD according to the present invention includes a transparent glass substrate, a gate bus wiring and a gate electrode formed on the transparent glass substrate, and a gate insulation formed on the substrate on which the gate bus wiring and the gate electrode are formed. a layer, a first semiconductor layer formed on the gate insulating layer, and the etch stopper formed on a portion of said first semiconductor layer, said separated into two regions on the etch stopper, not pure product dope A second semiconductor layer; a source electrode and a drain electrode formed on each portion of the impurity- doped second semiconductor layer formed separately; and a contact hole formed on the source electrode and the drain electrode. It has a structure comprising a protective insulating layer and a pixel electrode electrically connected to the drain electrode through the contact hole and formed on the protective insulating layer.
[0013]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, an embodiment of a method for producing an AMLCD of the present invention will be described with reference to the drawings.
First, a first metal layer made of Al or an Al-based alloy Al—Pd, Al—Si, Al—Si—Ti, Al—Si—Cu or the like is deposited on one surface of the transparent glass substrate 131 by a sputtering method. . The gate electrode 133 is formed by selectively etching the first metal layer by photolithography (FIG. 8).
If necessary, the gate electrode 133 may be anodized to form an anodized layer in order to improve chemical resistance, heat resistance, and particularly adhesion to the gate insulating layer to be subsequently formed. Good. The anodized layer functions as an insulating layer together with the silicon nitride of the gate insulating layer to be subsequently formed, and plays a role of improving electrical insulation between the gate electrode 133 and the adjacent signal line.
[0014]
A first insulating layer (gate insulating layer) 135, a non-doped a-Si semiconductor layer 137, and a second insulating layer 140 made of silicon nitride are sequentially deposited on the transparent glass substrate 131 on which the gate electrode is formed. (FIG. 9).
[0015]
As can be seen from FIG. 10, an etch stopper 140 is formed by etching the second insulating layer, and an N + semiconductor layer 139 is formed on the etch stopper 140 and the semiconductor layer 137 using a plasma CVD apparatus with hydrogen gas and phosphine gas. It adheres (FIG. 11).
[0016]
Subsequently, as shown in FIG. 12, a second metal layer 143 made of one of Pd, Al—Si, Al—Si—Ti, and Al—Si—Cu is deposited by a sputtering method. A photosensitive film (not shown) is applied on the second metal layer 143. Then, the selected portion of the photosensitive film is exposed to cause a phenomenon, and the selected portion of the second metal layer 143 is exposed. Next, the second metal layer 143, the N + semiconductor layer 139, and the semiconductor layer 137 are removed with the above-described phenomenon. As shown in FIG. 13, the second metal layer 143, the N + semiconductor layer 139, and the semiconductor layer 137 are patterned in a desired form.
[0017]
A protective insulating layer 145 made of a silicon nitride layer is deposited on the gate insulating layer 135 and the patterned second metal layer 143 using a plasma CVD apparatus using ammonia gas, silane gas, and hydrogen gas.
Then, the protective insulating layer 145 is patterned so as to form an opening on the etch stopper 140 and a contact hole in which a part of the second metal layer 143 is exposed (FIG. 14).
[0018]
As shown in FIG. 15, a pixel electrode 147 is formed. Then, an ITO layer is deposited in the contact hole and on the protective insulating layer 145 so as to be electrically connected to the second metal layer 143 through the contact hole by patterning.
Then, as shown in FIG. 16, using the protective insulating layer 145 as a mask, the exposed portion 143 of the second metal layer and the N + semiconductor layer 139 are etched to form the source electrode 143a and the drain electrode 143b. Form.
The reason why the contact hole is formed in the protective insulating layer 145 before the etching of the second metal layer 143 and the N + semiconductor layer 139 and then the pixel electrode 147 is formed is that This is to prevent the second metal layer 143 exposed through the etching from being etched. Therefore, the order of the manufacturing process is important. Therefore, the second metal layer 143 and the N + semiconductor layer 139 are etched in a single process. On the other hand, according to the conventional process, each layer formed on the etching stopper 140 is etched in a separate process.
[0019]
The AMCLD manufactured by the method described above has the structure described below. A gate bus wiring and gate electrode 133 formed on the transparent glass substrate 131, a gate insulating layer 135 formed on the substrate on which the gate bus wiring and gate electrode 133 are formed, and on the gate insulating layer 135 The formed semiconductor layer 137, the etch stopper 140 formed in accordance with the position of the gate electrode 133 on the semiconductor layer 137, and the impurity N + semiconductor layer separated in two regions covering each of the etch stopper 140 and the semiconductor layer 137 139, a source electrode 143a formed on one region of the impurity N + semiconductor layer 139, a drain electrode 143b formed on another region, and the gate insulating layer, the source electrode 143a and the drain electrode 143b. And a pixel electrode 147 electrically connected to the drain electrode 143b through a contact hole on the protective insulating layer.
[0020]
If the second insulating layer 140 is not formed here, the semiconductor layer 139 is exposed through the opening and is not protected from the contact material. Therefore, since the second insulating layer 140 is formed of silicon oxide or silicon nitride having good adhesion to the semiconductor layer 139, the second insulating film serves as an etch stopper and a protective film for the semiconductor layer 139.
[0021]
【The invention's effect】
Accordingly, since the second metal layer 143 , the impurity semiconductor layer 139, and the semiconductor layer 137 are simultaneously patterned in one process according to the present invention, the manufacturing cost is reduced and the manufacturing time is shortened. Further, the source electrode and the drain electrode can be formed in a single process without requiring an additional mask process. Therefore, the yield is improved.
[Brief description of the drawings]
FIG. 1 is a circuit diagram of a liquid crystal display device.
FIG. 2 is an enlarged plan view showing a part of a liquid crystal display device.
FIG. 3 is a cross-sectional view showing a manufacturing process of a conventional liquid crystal display device.
FIG. 4 is a cross-sectional view showing a manufacturing process of a conventional liquid crystal display device.
FIG. 5 is a cross-sectional view showing a manufacturing process of a conventional liquid crystal display device.
FIG. 6 is a cross-sectional view showing a manufacturing process of a conventional liquid crystal display device.
FIG. 7 is a cross-sectional view showing a manufacturing process of a conventional liquid crystal display device.
FIG. 8 is a cross-sectional view showing a manufacturing process of a liquid crystal display device according to an embodiment of the present invention.
FIG. 9 is a cross-sectional view showing a manufacturing process of a liquid crystal display device according to an embodiment of the present invention.
FIG. 10 is a cross-sectional view showing a manufacturing process of a liquid crystal display device according to an embodiment of the present invention.
FIG. 11 is a cross-sectional view showing a manufacturing process of a liquid crystal display device according to an embodiment of the present invention.
FIG. 12 is a cross-sectional view showing a manufacturing process of a liquid crystal display device according to an embodiment of the present invention.
FIG. 13 is a cross-sectional view showing a manufacturing process of a liquid crystal display device according to an embodiment of the present invention.
FIG. 14 is a cross-sectional view showing a manufacturing process of a liquid crystal display device according to an embodiment of the present invention.
FIG. 15 is a cross-sectional view showing a manufacturing process of a liquid crystal display device according to an embodiment of the present invention.
FIG. 16 is a cross-sectional view showing a manufacturing process of a liquid crystal display device according to an embodiment of the present invention.
[Explanation of symbols]
13 Gate bus wiring
14 Source wiring
31, 131 Transparent glass substrate
33, 133 Gate electrode
35, 135 First insulation layer
37, 137 Semiconductor layer
39, 139 Impurity semiconductor layer
40, 140 etch stopper
43, 143 Second metal layer
43a, 143a Source electrode
43b, 143b Drain electrode
45, 145 Protective insulation layer
47, 147 Pixel electrode

Claims (10)

半導体装置の製造方法であって、
基板上に第１金属層を被着する工程と、
ゲート電極を形成するために前記第１金属層をパターニングする工程と、
前記基板及び前記ゲート電極上にゲート絶縁層を被着する工程と、
前記ゲート絶縁層上に第１半導体層を被着する工程と、
前記第１半導体層上にエッチング防止層を被着する工程と、
前記エッチング防止層をパターニングしてエッチストッパを形成する工程と、
前記第１半導体層および前記エッチストッパ上に第２半導体層を被着する工程と、
前記第２半導体層上に第２金属層を被着する工程と、
前記第２金属層、前記第２半導体層及び前記第１半導体層を単一の工程でパターニングする工程と、
前記パターニングされた前記第２金属層及び前記ゲート絶縁層上に保護絶縁層を被着する工程と、
前記保護絶縁層をパターニングして、前記エッチストッパの上方に第１の開口を、パターニングされた前記第２金属層の一部分の上に第２の開口を形成する工程と、
前記保護絶縁層上に透明導電層を被着して、前記第２の開口を通じて前記透明導電層と前記第２金属層とを電気的に接触させるようにして、前記透明導電層をパターニングする工程と、
前記パターニングされた前記保護絶縁層をマスクとして用いて、前記第１の開口を通じて、前記第２金属層と第２半導体層との一部分をエッチングする工程と、
を含むことを特徴とする半導体装置の製造方法。A method for manufacturing a semiconductor device, comprising:
Depositing a first metal layer on a substrate;
Patterning the first metal layer to form a gate electrode;
Depositing a gate insulating layer on the substrate and the gate electrode;
Depositing a first semiconductor layer on the gate insulating layer ;
Depositing an anti-etching layer on the first semiconductor layer;
Patterning the etch stop layer to form an etch stopper;
Depositing a second semiconductor layer on the first semiconductor layer and the etch stopper ;
Depositing a second metal layer on the second semiconductor layer;
Patterning the second metal layer, the second semiconductor layer, and the first semiconductor layer in a single step;
Depositing a protective insulating layer on the patterned second metal layer and the gate insulating layer;
Patterning the protective insulating layer to form a first opening over the etch stopper and a second opening over a portion of the patterned second metal layer ;
Depositing a transparent conductive layer on the protective insulating layer, and patterning the transparent conductive layer so that the transparent conductive layer and the second metal layer are in electrical contact through the second opening. When,
Etching a part of the second metal layer and the second semiconductor layer through the first opening using the patterned protective insulating layer as a mask;
A method for manufacturing a semiconductor device, comprising: 前記第２半導体層は不純物がドープされていることを特徴とする、請求項１記載の半導体装置の製造方法。  The method of manufacturing a semiconductor device according to claim 1, wherein the second semiconductor layer is doped with an impurity. 前記透明導電層をパターニングして透明電極を形成することを特徴とする、請求項１記載の半導体装置の製造方法。  2. The method of manufacturing a semiconductor device according to claim 1, wherein the transparent conductive layer is patterned to form a transparent electrode. 前記透明電極は透明導電物質で構成されていることを特徴とする、請求項３記載の半導体装置の製造方法。4. The method of manufacturing a semiconductor device according to claim 3 , wherein the transparent electrode is made of a transparent conductive material. 前記透明電極は画素電極であることを特徴とする、請求項４記載の半導体装置の製造方法。5. The method of manufacturing a semiconductor device according to claim 4 , wherein the transparent electrode is a pixel electrode. 半導体装置の製造方法であって、
基板の表面上にゲート電極を形成する工程と、
前記基板及び前記ゲート電極上にゲート絶縁層を被着する工程と、
前記ゲート絶縁層上に第１半導体層を被着する工程と、
前記第１半導体層上にエッチング防止層を被着する工程と、
前記エッチング防止層をパターニングしてエッチストッパを形成する工程と、
前記第１半導体層および前記エッチストッパ上に第２半導体層を形成する工程と、
前記第２半導体層上に金属層を形成する工程と、
前記金属層上に保護絶縁層を形成する工程と、
前記保護絶縁層をパターニングして、前記エッチストッパの上方に第１の開口を、前記金属層の一部分の上に第２の開口を形成し、前記第１と第２の開口を通じて、前記金属層の第１と第２の部分が露出されるようにする工程と、
前記保護絶縁層上に、前記第２の開口を通じて前記金属層と接触するように透明導電層を形成する工程と、
前記パターニングされた保護絶縁層をマスクとして用いて、前記金属層の第１の部分と、前記金属層の前記第１の部分の下にある前記第２半導体層の一部分とをエッチングする工程と、
を含むことを特徴とする、半導体装置の製造方法。A method for manufacturing a semiconductor device, comprising:
Forming a gate electrode on the surface of the substrate ;
Depositing a gate insulating layer on the substrate and the gate electrode;
Depositing a first semiconductor layer on the gate insulating layer;
Depositing an anti-etching layer on the first semiconductor layer;
Patterning the etch stop layer to form an etch stopper;
Forming a second semiconductor layer on the first semiconductor layer and the etch stopper;
Forming a metal layer on the second semiconductor layer;
Forming a protective insulating layer on the metal layer;
The protective insulating layer is patterned to form a first opening above the etch stopper and a second opening over a portion of the metal layer, and the metal layer is formed through the first and second openings. a step first and you so that the second part is exposed,
Forming a transparent conductive layer on the protective insulating layer in contact with the metal layer through the second opening;
Using a protective insulating layer that is the patterning as a mask, a first portion of said metal layer, and etching the portion of the second semiconductor layer underlying said first portion of said metal layer,
A method for manufacturing a semiconductor device, comprising: 前記エッチングする工程が前記半導体装置のソース及びドレイン領域を形成することを特徴とする、請求項６記載の半導体装置の製造方法。7. The method of manufacturing a semiconductor device according to claim 6 , wherein the etching step forms source and drain regions of the semiconductor device. 前記透明導電層は透明電極を含むことを特徴とする、請求項６記載の半導体装置の製造方法。The method of manufacturing a semiconductor device according to claim 6 , wherein the transparent conductive layer includes a transparent electrode. 前記半導体装置は薄膜トランジスタであることを特徴とする、請求項６記載の半導体装置の製造方法。The method of manufacturing a semiconductor device according to claim 6 , wherein the semiconductor device is a thin film transistor. 基板上に第１金属層を被着する工程と、
前記第１金属層がゲート電極を形成するようにパターニングする工程と、
前記基板及び前記ゲート電極上にゲート絶縁層を被着する工程と、
前記ゲート絶縁層上に第１半導体層を被着する工程と、
前記第１半導体層上にエッチング防止層を被着する工程と、
前記エッチング防止層がエッチストッパを形成するようにパターニングする工程と、
前記エッチストッパ及び前記第１半導体層上に不純物を含む第２半導体層を被着する工程と、
前記不純物を含む第２半導体層上に第２金属層を被着する工程と、
前記第２金属層、前記不純物を含む第２半導体層及び前記第１半導体層を単一の工程でパターニングする工程と、
前記パターニングされた第２金属層及び前記ゲート絶縁層上に保護絶縁層を被着する工程と、
前記保護絶縁層を、前記エッチストッパ上に第１の開口と前記パターニングされた第２金属層の一部分上にコンタクトホールを形成するように第２の開口とを、パターニングする工程と、
前記パターニングされた保護絶縁層及び前記第１と第２の開口に透明導電層を被着する工程と、
前記透明導電層を第２金属層の一部分と第２の開口を通じて電気的に接触する画素電極を形成するようにパターニングする工程と、
前記パターニングされた保護絶縁層をマスクとして用いて、ソース及びドレイン電極を形成するように、前記第２金属層と前記不純物を含んでいる第２半導体層を前記第１の開口を通じてエッチングする工程から成る半導体装置の製造方法。Depositing a first metal layer on a substrate;
Patterning the first metal layer to form a gate electrode;
Depositing a gate insulating layer on the substrate and the gate electrode;
Depositing a first semiconductor layer on the gate insulating layer;
Depositing an anti-etching layer on the first semiconductor layer;
Patterning the etch stop layer to form an etch stopper;
Depositing a second semiconductor layer containing impurities on the etch stopper and the first semiconductor layer;
Depositing a second metal layer on the second semiconductor layer containing the impurities;
Patterning the second metal layer, the second semiconductor layer containing impurities, and the first semiconductor layer in a single step;
Depositing a protective insulating layer on the patterned second metal layer and the gate insulating layer;
Patterning the protective insulating layer with a first opening on the etch stopper and a second opening to form a contact hole on a portion of the patterned second metal layer;
Depositing a transparent conductive layer on the patterned protective insulating layer and the first and second openings;
Patterning the transparent conductive layer to form a pixel electrode in electrical contact with a portion of the second metal layer through a second opening;
Etching the second metal layer and the second semiconductor layer containing the impurity through the first opening to form source and drain electrodes using the patterned protective insulating layer as a mask. A method for manufacturing a semiconductor device.
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9252160B2 (en) 2013-12-16 2016-02-02 Samsung Display Co., Ltd. Thin film transistor array panel and method of manufacturing the same
US9397127B2 (en) 2013-12-16 2016-07-19 Samsung Display Co., Ltd. Thin film transistor array panel and method of manufacturing the same

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JPH1039331A (en) 1998-02-13
GB2312092B (en) 1998-06-03
JP4117369B2 (en) 2008-07-16
DE19714690C2 (en) 2003-12-11
GB2312092A (en) 1997-10-15
DE19714690A1 (en) 1997-10-30
KR100202236B1 (en) 1999-07-01
JP2007206712A (en) 2007-08-16
GB9706824D0 (en) 1997-05-21
KR970072497A (en) 1997-11-07
FR2747237A1 (en) 1997-10-10
FR2747237B1 (en) 1999-04-16

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