GB2312092A - Liquid crystal display and method of manufacture - Google Patents

Liquid crystal display and method of manufacture Download PDF

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Publication number
GB2312092A
GB2312092A GB9706824A GB9706824A GB2312092A GB 2312092 A GB2312092 A GB 2312092A GB 9706824 A GB9706824 A GB 9706824A GB 9706824 A GB9706824 A GB 9706824A GB 2312092 A GB2312092 A GB 2312092A
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layer
semiconductor
depositing
semiconductor layer
accordance
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GB9706824D0 (en
GB2312092B (en
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Ki-Hynn Lyn
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LG Electronics Inc
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LG Electronics Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66765—Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78663—Amorphous silicon transistors
    • H01L29/78669—Amorphous silicon transistors with inverted-type structure, e.g. with bottom gate
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Liquid Crystal (AREA)
  • Thin Film Transistor (AREA)

Description

2312092 LIQUID CRYSTAL DISPLAY AND METHOD OF MANUFACTURING THE SAME The
present invention relates to a method for manufacturing active matrix liquid crystal displays ("AMLCD"), and to the structure of AMI-CI)s manufactured by such a method.
AMLCI)s comprise active elements such as thin film transistors ('7FT") as switching devices for driving and controlling each pixel of the display.
As shown in FIG. 1A, in a conventional AMI-CI) including an array of Ms, substantially rectangular pixel electrodes 47 are closely arranged in rows and columns on a transparent glass substrate. Gate bus lines (address lines) 13 are respectively formed closely along the rows of the pixel electrodes 47 and source bus lines (data lines) 14 are respectively formed closely along the columns of the pixel electrodes.
Referring to FIG. 1B, a plan view showing an enlargement of a single pixel of the AMLCI) shown in FIG. 1A, gate bus lines 13 having gate electrode extensions 33 are formed on a transparent glass substrate 31 (FIG. 2A). An insulating layer 35 (FIG. 213) covers the gate bus lines 13 and the gate electrodes 33, and a plurality of parallel source bus lines 14 are provided on the insulating layer extending perpendicular to gate bus lines 13. Near each gate bus line 13 and source bus line 14 intersection, a semiconductor layer 37 (FIG. 2B) is formed on the insulating layer covering the gate bus lines and the gate electrodes. Spaced source and drain electrodes, 43a and 43b respectively (FIG, 2D), are formed opposite one another on the semiconductor layer. In this manner, Ms as active elements are formed.
A manufacturing process of a conventional AMLCD is described below with reference to FIGs. 2A to 2E, showing cross-sectional views taken along a line 2 - 2 of FIG. 1B.
2 A gate electrode 33 (extension of a gate bus line 13) is formed on a transparent glass substrate 31 by depositing and patterning a first metal layer (FIG. 2A). A first insulating layer (a gate insulating layer) 35 made of SiN,', a semiconductor layer 37 made of a-Si, and a second insulating layer made of SiN. are then successively deposited on the entire surface of the substrate.
As shown in FIG. 2B, an etch-stopper 40 is formed by patterning the second insulating layer, and an impurity doped semiconductor layer 39 including n' a-Si is then deposited over the entire substrate and patterned together with the semiconductor layer 37 (FIG. 2C).
A second metal layer 43 is next deposited on the entire surface of the substrate, which is then patterned to form a source bus line, a source electrode 43a branching out from the source bus line, and a drain electrode 43b. Next, an exposed portion of the impurity doped semiconductor layer 39 is etched using the source and drain electrodes as masks, as shown in FIG. 2D.
An insulating passivation layer 45 is then formed by depositing another Si-nitride layer over the first insulating layer and the source and drain electrodes. Then a contact hole is formed by etching the insulating passivation layer 45. An ITO layer is sputter deposited on the insulating passivation layer 45. The ITO layer is patterned to form a pixel electrode 47, which is electrically connected to the drain electrode 43b through the contact hole (FIG. 2E).
This conventional process of manufacturing the TFTs is very complicated. Moreover, it takes a great deal of time to pattern the various layers of the AMLC1) because masks must be aligned precisely, and photoresists must be coated and developed for each patterning step. Further, the manufacturing yield is low.
An objective of the present invention is to provide a method for manufacturing AMI-CDs, in which the number of mask steps is reduced by 3 patterning a second metal layer and a semiconductor layer at the same time. Moreover, source and drain electrodes are formed by etching a portion of the second metal layer together with a portion of an impurity doped semiconductor layer using an insulating passivation layer as a mask.
In particular, in one aspect the method according to the present invention comprises the following steps. A first metal layer is deposited on a transparent substrate, and gate bus lines and gate electrodes are formed by patterning the first metal layer. A first insulating layer, a semiconductor layer and a second insulating layer are sequentially deposited on the substrate on which the gate bus line and the gate electrode are formed. An etchstopper is formed by patterning the second insulating layer, and an impuritydoped semiconductor layer is deposited on the etch-stopper and the semiconductor layer. A second metal layer is deposited on the impuritydoped semiconductor layer, and the second metal layer, the impurity-doped semiconductor layer and the semiconductor layer are patterned. An insulating passivation layer is deposited on the patterned second metal layer and the first insulating layer. A contact hole is then formed and a part of the second metal layer on the etchstopper is exposed by patterning the insulating passivation layer. A transparent conductive layer is deposited on the insulating passivation layer and onto the exposed part of the second metal layer. A pixel electrode is formed by patterning the transparent conductive layer such that the pixel electrode is electrically connected with the second metal layer through the contact hole. Source and drain electrodes are formed by etching a part of the second metal layer and a part of the impurity-doped semiconductor layer, with the insulating passivation layer being used as a mask.
An AMLC1), according to one aspect of the present invention, comprises a transparent glass substrate, gate bus lines and gate electrodes formed on the transparent glass substrate, a gate insulating layer formed on 4 the transparent glass substrate on which the gate bus lines and the gate electrodes are formed, a semiconductor layer formed on the gate iiisulating layer, an etch-stopper formed on a portion of the semiconductor layer, an impurity-doped semiconductor layer formed on the semiconductor layer and separated into two parts on the etch-stopper, source and drain electrodes formed on each part of the separated impuritydoped semiconductor layer. respectively, an insulating passivation layer formed on the source and drain electrodes and having a contact hole, and a pixel electrode formed on a portion of the insulating passivation layer, the pixel electrode being electrically connected with the drain electrode through the contact hole.
For a better understanding of the invention an embodiment will now be described, with reference to the accompanying drawings, in which:
FIG. 1A is an overall plan view of a conventional LC1); FIG. 1B is an enlarged plan view of one liquid crystal display element of the conventional LC1) of FIG. 1; FIGs. 2A to 2E are cross-sectional views showing a conventional AMLCI) at various stages of a conventional manufacturing process; and FIGs. 3A to 31 illustrate cross-sectional views of an AMLCI) according to the present invention at various stages of a manufacturing process therefor, in accordance with the present invention.
A first metal layer of A] or AI alloy, such as AI-Pd, AI-Si, AI-Si-Ti. AISi-Cu, is preferably sputter deposited on a transparent glass substrate 131. A gate electrode 133 is then formed by selectively etching the first metal layer using a photo-lithography technique (FIG. 3A).
If necessary, an anodized layer may be formed on the gate electrode 133 by anodizing the gate electrode 133 in order to improve its chemicalresistance, heat-resistance and adhesiveness to a subsequently formed gate insulating layer. The anodized layer also functions as an insulating layer together with a Si-nitride gate insulating layer and therefore improves electrical isolation between the gate electrode 133 and an ajacent signal line.
As shown in FIG. 3B, a first insulating layer (a gate insulating layer) 135, an undoped a-Si semiconductor layer 137, and a second insulating layer 140 of Si-nitride are successively deposited on transparent glass substrate 131 As seen in FIG. 3C, an etch-stopper 140 is then formed by patterning the second insulating laver, followed by deposition of a doped n' semiconductor layer 139 on the etch-stopper 140 and the semiconductor layer 137 by plasma CV1) in an atmosphere of hydrogen and phosphine gases (FIG 3D).
Next, as shown in FIG. 3E, a second metal layer 143, comprising one of Pd, M-Si, Al- Si-Ti, and M-Si-Cu, is sputter deposited, followed by depositing of a photosensitive layer. The photosensitive layer (not shown) is then exposed and developed to reveal selected portions of second metal layer 143. These portions are then removed, along with corresponding portions of the n' semiconductor layer 139 and semiconductor layer 137.Second metal layer 143, n' semiconductor layer 139, and semiconductor layer 137 are then patterned into a desired shape, as shown in FIG. 3F.
An insulating passivation layer 145 of Si-nitride is then deposited on the patterned second metal layer 143 and the gate insulating layer 135 by plasma CVD in an atmosphere of ammonia, silane, and hydrogen gases. Next, as shown in FIG. 3G, the insulating passivation layer is patterned to form an opening over etch-stopper 140 and a contact hole exposing a portion of second metal layer 143.
An ITO layer is deposited into the contact hole and on the insulating passivation layer 145 which is then patterned to form a pixel electrode 147 electrically connected with the second metal layer 143 through the contact hole as seen in FIG. 3H. As seen in FIG. 31, source and drain electrodes, 143a and 143jb, are next formed by etching the exposed portion of the second 6 metal layer 143 and the n' semiconductor layer 139 using insulating passivation layer 145 as a mask. The reason of forming the pixel electrode 147 after etching the passivation layer 145 to form the opening and the contact hole, and before etching the second metal layer 143 and n+ semiconductor layer 139, is that the pixel electrode 147 protects the second metal layer 143 exposed through the contact hole. So, the sequence of manufacturing step is very important. Accordingly, second metal layer 143 and n+ semiconductor layer 139 are etched in a single processing step. In contrast, in the conventional method described above, these layers overlying etch stopper 140 are etched respectively in separate steps.
The AMLCI) manufactured by the above-described method has the structure described below. A gate bus line and a gate electrode 133 are formed on a transparent substrate 131. A gate insulating layer 135 covers the transparent glass substrate on which the gate bus line and the gate electrode 133 are formed. A semiconductor layer 137 is formed on the gate insulating layer 135, and an etch-stopper 140 is provided on the semiconductor layer 137 aligned with gate electrode 133. An impuritydoped n' semiconductor layer 139, includes two spaced portions, each of which overlaps etch-stopper 140 and semiconductor layer 137. Of the two spaced portions of n' semiconductor layer 139, one portion has a source electrode formed thereon and the other portion has a drain electrode 143b formed thereon. An insulating passivation layer 145 covers the gate insulating layer, the source electrode 143a and the drain electrode 143b, and a pixel electrode on the insulating passivation layer is electrically connected with the drain electrode 143b through a contact hole formed in the insulating passivation layer.
Even though, the second insulating layer 140 may be not needed, in this case, the semiconductor layer 139 is exposed through the opening. So, the semiconductor layer 139 is not protected from the contacting materials thereon. Because the second insulating layer 140 made of silicon-oxide or 7 silicon-nitride has a good adhesion with the semiconductor layer 139, it serves as etch stopper and passivation layer of semiconductor layer 139.
According to the embodiment, the manufacturing cost is lowered and processing time is reduced because second metal layer 143 and impuritydoped semiconductor layer 139 and semiconductor layer 137 are patterned in the same step. Further, as recited above, source and drain regions are formed in a single processing step, without any additional mask steps. Yield is thus improved.
It well be apparent to those skilled in the art that various modifications and variations can be made in the AMLCI) of the present invention and in construction of this AMLCI) without departing from the scope or spirit of the invention.
Other embodiments of the invention will be apparent to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the invention being indicated by the following claims..

Claims (27)

8 CLAIMS
1. A method for manufacturing a semiconductor device comprising the steps of: depositing a first semiconductor]aver on a substrate; depositing a second semiconductor layer on said first semiconductor layer; depositing a conductive layer on said second semiconductor layer; depositing a passivation layer on said conductive layer; patterning said passivation layer; and etching portions of said conductive layer and said second semiconductor layer using said patterned passivation layer as a mask.
2. A method in accordance with claim 1, further comprising the step of depositing an etch resistant layer on said first semiconductor layer prior to said step of depositing said second semiconductor layer.
3. A method in accordance with claim 2, wherein said etch resistant layer remains substantially after said step of etching said conductive layer and said second semiconductor layer.
4. A method in accordance with claims 1, 2 or 3, wherein said conductive layer is a second conductive layer, and prior to said step of depositing said first semiconductor layer, said method further comprising the step of: depositing a first conductive layer on said substrate; patterning said first conductive layer to form a gate electrode; and 9 depositing an insulating layer on said gate electrode.
5. A method in accordance with claims 1, 2, 3 or 4, wherein said second semiconductor layer is doped.
6. A method in accordance with claim 2, wherein said step of depositing said etch resistant layer includes the steps of:
depositing an insulating layer on said first semiconductor layer; and patterning said insulating layer to form said etch resistant layer.
7. A method in accordance with any one of claims 1 to 6, wherein said patterning step includes the steps of forming a first opening and a second opening in said passivation layer, said portions of said conductive layer and said second semiconductor layer being etched through said first opening, said method further comprising the step of:
depositing an electrode layer on said passivation layer into said second opening such that said electrode layer is electrically connected to said second conductive layer.
8. A method in accordance with claim 7, wherein said electrode comprises transparent conductive material.
9. A method in accordance with claim 8, wherein said electrode is a pixel electrode.
10. A method of fabricating a semiconductor device, comprising the steps of: forming a semiconductor layer on a surface of a substrate; forming a first conductive layer on said semiconductor layer; forming a passivation layer on said first conductive 1Aver; patterning said passivation layer to provide first and second openings in said passivation layer to expose first and second portions, respectively, of said first conductive]aver; forming a second conductive layer on said passivation layer and extending through said first opening to contact said first conductive layer; and etching said second portion of said first conductive layer and a portion of said semiconductor layer underlying said second portion of said conductive layer using said patterned passivation layer as a mask.
11. A method in accordance with claim 10, wherein said etching step forms source and drain regions of said semiconductor device.
12. A method in accordance with claim 10 or 11, wherein prior to forming said semiconductor layer, said method further comprising the steps of forming an insulating layer on said substrate; and patterning said insulating layer to form an etch stop layer.
13. A method in accordance with claim 12, wherein said step of patterning said passivation layer includes a step of providing said second opening substantially aligned with said etch stop layer.
14. A method in accordance with claim 10, 11, 12 or 13, wherein said second conductive layer includes a transparent conductive layer.
15. A method in accordance with claim 10, 11, 12, 13 or 14, wherein said semiconductor device is a thin film transistor.
11
16. A semiconductor device, comprising a substrate; a doped semiconductor layer having an edge portion provided on said substrate; a conductive layer provided on said doped semiconductor layer, an edge portion of said conductive layer being substantially aligned with said edge portion of said doped semiconductor layer; and a passivation layer having an opening, a sidewall of said opening being substantially aligned with said edge portion of said conductive layer.
17. A semiconductor device in accordance with claim 16, further comprising a substantially undoped semiconductor layer provided between said doped semiconductor layer and said substrate, said substantially undoped semiconductor layer having an edge portion substantially aligned with other edge portions of said conductive layer and said doped semiconductor la Pr.
18. A semiconductor device in accordance with claim 16, 17 or 18, further comprising: a gate electrode formed on said substrate; and an insulating layer formed on said gate electrode, said undoped semiconductor layer and said doped semiconductor layer being formed on said insulating layer.
19. A semiconductor device in accordance with claim 17, wherein said doped semiconductor layer includes first and second spaced portions, said semiconductor device further comprising: an etch stop layer provided on said substantially undoped semiconductor layer between said first and second portions of said doped semiconductor layer.
12
20. A semiconductor device in accordance with claim 19, wherein said opening of said passivation layer is substantially aligned with said etch stop layer.
21. A semiconductor device in accordance with claim 16, wherein said conductive layer includes first and second spaced portions, said semiconductor device further comprising; an electrode layer provided on a selected portion of said patterned passivation layer, said patterned passivation layer including a contact hole exposing a part of said first portion of conductive layer, said electrode layer electrically contacting said first portion of said conductive layer through said contact hole.
22. A semiconductor device in accordance with'claim 21, wherein said electrode layer includes transparent conductive material.
23. A method of manufacturing an active matrix liquid crystal display, comprising the steps of: depositing a first metal layer on a substrate; patterning said first metal layer to form a gate electrode; depositing a gate insulating layer on said substrate and said gate electrode; depositing a first, semiconductor layer on said gate insulating layer; depositing an etch resistant layer on said first semiconductor layer; patterning said etch resistant layer to form an etch stop portion; depositing a second, impurity containing, semiconductor layer on said etch stop portion and said first semiconductor layer; depositing a second metal layer on said impurity containing layer; patterning said second metal layer, said second impurity containing 13 semiconductor layer and said first semiconductor layer in a single step; depositing a passivation layer on said patterned second metal layer and said gate insulating layer; patterning said passivation layer to form an opening over said etch stop portion and a contact hole over part of said patterned second metal layer; depositing a transparent conductive layer on said patterned passivation layer and in said contact hole; patterning said transparent conductive layer to form a pixel electrode electrically connected to said part of said patterned second metal layer; and etching said second metal layer and said second impurity containing semiconductor layer using said patterned passivation layer as a mask to thereby form source and drain electrodes.
24. A method of manufacturing a thin film transistor, wherein a hole in a conductive layer which forms the soruce and drain electrodes of the transistor is not formed until after the step of forming a passivation layer over said conductive layer.
25. A method of manufacturing a semiconductor device substantially as hereinbefore described with reference to and/or as illustated in any one of or any combination of FIGS 3A to 31.
26. A method of manufacturing a thin film transistor substantially as hereinbefore described with reference to and/or as illustated in any one of or any combination of FIGS 3A to 31.
27. A semiconductor device substantially as hereinbefore described with reference to and/or as illustated in any one of or any combination of FIGS 3A to 31.
GB9706824A 1996-04-09 1997-04-04 Liquid crystal display and method of manufacturing the same Expired - Lifetime GB2312092B (en)

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KR1019960010637A KR100202236B1 (en) 1996-04-09 1996-04-09 Active matrix panel and its making method

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GB9706824D0 GB9706824D0 (en) 1997-05-21
GB2312092A true GB2312092A (en) 1997-10-15
GB2312092B GB2312092B (en) 1998-06-03

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KR (1) KR100202236B1 (en)
DE (1) DE19714690C2 (en)
FR (1) FR2747237B1 (en)
GB (1) GB2312092B (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
SG132505A1 (en) * 2000-12-11 2007-06-28 Semiconductor Energy Lab Semiconductor device, and manufacturing method thereof
US8735909B2 (en) 2000-12-21 2014-05-27 Semiconductor Energy Laboratory Co., Ltd. Light emitting device and method of manufacturing the same

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100538293B1 (en) * 1998-04-03 2006-03-17 삼성전자주식회사 Method of manufacturing flat drive liquid crystal display
KR100980015B1 (en) * 2003-08-19 2010-09-03 삼성전자주식회사 Thin film transistor array panel and manufacturing method thereof
KR102183920B1 (en) 2013-12-16 2020-11-30 삼성디스플레이 주식회사 Thin film transistor array panel and method of manufacturing the same
CN104022126B (en) * 2014-05-28 2017-04-12 京东方科技集团股份有限公司 Array substrate and manufacturing method thereof, and display apparatus

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0195560A (en) * 1987-10-08 1989-04-13 Casio Comput Co Ltd Manufacture of thin-film transistor
US5294811A (en) * 1990-11-30 1994-03-15 Hitachi, Ltd. Thin film semiconductor device having inverted stagger structure, and device having such semiconductor device
US5349205A (en) * 1991-12-02 1994-09-20 Matsushita Electric Industrial Co., Ltd. Thin-film transistor array with anodic oxide for use in a liquid crystal display
US5539219A (en) * 1995-05-19 1996-07-23 Ois Optical Imaging Systems, Inc. Thin film transistor with reduced channel length for liquid crystal displays

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5173753A (en) * 1989-08-10 1992-12-22 Industrial Technology Research Institute Inverted coplanar amorphous silicon thin film transistor which provides small contact capacitance and resistance
US5130263A (en) * 1990-04-17 1992-07-14 General Electric Company Method for photolithographically forming a selfaligned mask using back-side exposure and a non-specular reflecting layer
EP0476701B1 (en) * 1990-09-21 1995-12-13 Casio Computer Company Limited A thin-film transistor and a thin film transistor panel using thin-film transistors of this type
EP0504390B1 (en) * 1990-10-05 1996-01-10 General Electric Company Thin film transistor stucture with improved source/drain contacts
EP0566838A3 (en) * 1992-02-21 1996-07-31 Matsushita Electric Ind Co Ltd Manufacturing method of thin film transistor

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0195560A (en) * 1987-10-08 1989-04-13 Casio Comput Co Ltd Manufacture of thin-film transistor
US5294811A (en) * 1990-11-30 1994-03-15 Hitachi, Ltd. Thin film semiconductor device having inverted stagger structure, and device having such semiconductor device
US5349205A (en) * 1991-12-02 1994-09-20 Matsushita Electric Industrial Co., Ltd. Thin-film transistor array with anodic oxide for use in a liquid crystal display
US5539219A (en) * 1995-05-19 1996-07-23 Ois Optical Imaging Systems, Inc. Thin film transistor with reduced channel length for liquid crystal displays

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
Patent Abstracts of Japan, Section E, Section No 794, Vol 13, No 333, Pg 16, 26/7/89 & JP01-095560A *

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
SG132505A1 (en) * 2000-12-11 2007-06-28 Semiconductor Energy Lab Semiconductor device, and manufacturing method thereof
US9059216B2 (en) 2000-12-11 2015-06-16 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device, and manufacturing method thereof
US9666601B2 (en) 2000-12-11 2017-05-30 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device, and manufacturing method thereof
US10665610B2 (en) 2000-12-11 2020-05-26 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device, and manufacturing method thereof
US8735909B2 (en) 2000-12-21 2014-05-27 Semiconductor Energy Laboratory Co., Ltd. Light emitting device and method of manufacturing the same
US9793335B2 (en) 2000-12-21 2017-10-17 Semiconductor Energy Laboratory Co., Ltd. Light emitting device and method of manufacturing the same

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GB9706824D0 (en) 1997-05-21
DE19714690A1 (en) 1997-10-30
JP4117369B2 (en) 2008-07-16
JP4034376B2 (en) 2008-01-16
GB2312092B (en) 1998-06-03
FR2747237A1 (en) 1997-10-10
FR2747237B1 (en) 1999-04-16
KR100202236B1 (en) 1999-07-01
JPH1039331A (en) 1998-02-13
JP2007206712A (en) 2007-08-16
DE19714690C2 (en) 2003-12-11
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