JPH04357832A - Etching method and manufacture of thin film transistor - Google Patents

Abstract

PURPOSE:To pattern a titanium layer and an aluminum layer in the same lithography step by forming a protective film by using an etchant containing mixture gas of sulfur hexafluoride and oxygen at an initial stage of etching the titanium layer laminated with the aluminum layer with a resist layer as a mask. CONSTITUTION:An insulating layer 21 made of a silicon nitride layer, a titanium layer 22 and an aluminum layer 23 are sequentially deposited on a substrate 20. After a resist layer 24 is formed with a predetermined region of its upper surface as a mask, the exposed layer 23 is selectively etched. Then, at the initial time of etching the titanium layer by anisotropically etching with the layer 24 as a mask, sulfur hexafluoride added with a trace amount of oxygen is used as an etchant, and a protective film 25 made of organic material is formed on the side face of the layer 23. Thereafter, with the layer 24 as a mask the layer 22 is etched by using an etchant containing mixture gas of chlorine gas and boron trichloride.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention relates to a liquid crystal display device (LCD).
) and electroluminescent (EL) display devices, etc., and in particular relates to a method for etching stacked titanium layers and aluminum layers that constitute the source electrode, drain electrode, and drain bus of the TFT.

0002

2. Description of the Related Art An example of the structure of an LCD having a TFT is shown in FIG. Figure (a) is a cross-sectional view, Figure (b)
is a top view of the transparent substrate 1 side. More precisely,
Figure (a) represents the xx section of Figure (b). The display principle of this LCD is that a transparent electrode 1A is formed for each display cell on a transparent substrate 1, and a transparent substrate 2
By changing the transmittance of the liquid crystal layer 3 due to the voltage applied between it and the transparent electrode 2A formed above, display dots with different contrast or color tone from the surroundings are generated.

[0003] The above applied voltage is applied to the gate electrode 4 formed on the transparent substrate 1 and the amorphous silicon (a-Si).
Switching is performed by a TFT consisting of an active layer consisting of layer 5. In the figure, reference numeral 6 indicates a gate insulating layer, 7 a source electrode, 8 a drain electrode, 9 a gate bus, and 10 a drain bus. That is, the gate bus 9 is connected, for example, to the gate electrodes 4 of TFTs arranged in the X direction, and the drain bus 10 is connected to the gate electrodes 4 of TFTs arranged in the
It is connected to the drain electrodes 8 of the TFTs arranged in the direction. Therefore, gate bus 9 and drain bus 10
By selecting and switching the TFT at the intersection, a desired display dot can be generated. The structure shown in the figure is called an inverted stagger type. On the other hand, an active layer is formed on the substrate side,
The operating principle is the same for the staggered structure in which the gate electrode, source, and drain electrodes are stacked on top of this.

0004

[Problem to be solved by the invention] Usually, the source electrode 7
and the drain electrode 8 are made of a layer of a high melting point metal such as titanium or its silicide, and the drain bus 1
0, an aluminum layer is used. The former is
A titanium layer or the like is selected because it does not react with the a-Si active layer 5 during the heat treatment process, and the latter is because there is no material that can replace aluminum for the thin drain bus 10 with low resistivity.

In the conventional manufacturing method, the source electrode 7, the drain electrode 8, and the drain bus 10 are manufactured separately. That is, a titanium layer is deposited on the transparent substrate 1 on which the a-Si layer 5 is formed, and this is etched to form the source electrode 7 and the drain electrode 8. Then, an aluminum layer is deposited, and this is etched to form the source electrode 7 and the drain electrode 8. A two-step lithographic process was used to etch the shape.

Even if the source electrode 7, the drain electrode 8, and the drain bus 10 have a two-layer structure of a titanium layer and an aluminum layer, there is no problem in terms of function and characteristics. That is, such two layers may be patterned by the same lithographic process. However, since an etchant consisting of chlorine gas or chlorine compound gas is usually used for etching the titanium layer, chlorine molecules and the like tend to remain on the surface of the aluminum layer after patterning. It is difficult to easily remove such residual chlorine molecules through cleaning treatment. As a result, the aluminum layer is corroded by the residual chlorine molecules, resulting in increased resistance and disconnection of the thin drain bus 10 made of the aluminum layer.

For the above reasons, it was necessary to first etch the titanium layer constituting the source electrode 7 and drain electrode 8, and then pattern the drain bus 10 made of an aluminum layer. For this reason,
The efficiency of the lithography process cannot be improved, and there are constraints on miniaturization, that is, high resolution, due to the margin of alignment of mask patterns in each lithography process.

Furthermore, another problem with the conventional manufacturing method is that in the etching process for forming the gate electrode 4 and the gate bus 9, as shown in the cross-sectional view of FIG. If the taper angle of the edge of the gate bus 9 is large and over-etching is performed in consideration of the layer thickness distribution of the titanium layer within the plane of the transparent substrate 1, the SiO2 layer 1B on the surface of the transparent substrate 1 will be etched. This can be mentioned. The large taper angle of the gate electrode 4 means that
Short circuits are more likely to occur due to poor coverage of the insulating layer. Furthermore, when the SiO2 layer 1B becomes thinner, pinholes are generated, which tends to cause poor insulation between the storage capacitor electrode formed on the transparent substrate and the gate and gate bus.

An object of the present invention is to enable patterning of the titanium layer and the aluminum layer in the same lithographic process, thereby improving productivity and easing restrictions on higher resolution. Another object of the present invention is to prevent the above problems associated with the taper angle by making it possible to form the gate electrode 4 with a small taper angle.

0010

[Means for Solving the Problems] The first object is to sequentially deposit a layer of a high melting point metal or its silicide and an aluminum layer on one surface of a substrate covered with an insulator, and to deposit a layer of a high melting point metal or its silicide and an aluminum layer in a predetermined area. forming a resist layer that selectively covers the area, selectively etching the aluminum layer using the resist layer as a mask to expose the high melting point metal layer or silicide layer, and applying chlorine to the side surface of the etched aluminum layer. After forming a protective film that is resistant to an etchant made of gas or chlorine compound gas, the high melting point metal layer or silicide layer exposed from the resist layer is dry etched using the etchant made of chlorine gas or chlorine compound gas. The etching method according to the present invention is characterized in that it includes various steps, or on one surface of a substrate in which a plurality of element formation regions are defined
A plurality of gate electrodes made of titanium extend in a first direction in each of the element formation regions, and a plurality of gate electrodes extend in a second direction intersecting the first direction and arranged in the second direction. a first insulating layer made of silicon nitride and a first amorphous silicon layer on the surface of the transparent substrate on which the gate electrode and the gate bus are formed; Second
a resist layer corresponding to the gate electrode is formed on the second insulating layer, and the second insulating layer exposed from the resist layer is selectively etched to remove the second insulating layer. A first amorphous silicon layer is exposed, and a doped amorphous silicon layer, a titanium layer, and an aluminum layer are sequentially deposited so as to cover at least the exposed first amorphous silicon layer, and a doped amorphous silicon layer, a titanium layer, and an aluminum layer are sequentially deposited on both sides of each gate electrode. After selectively removing the aluminum layer, leaving portions corresponding to the source and drain regions defined in and a portion extending in the second direction from the portion corresponding to the drain region, Dry etching a portion of the titanium layer exposed from the aluminum layer in the layer thickness direction using an etchant consisting of a mixed gas of sulfur hexafluoride and oxygen, and removing the remainder of the titanium layer exposed from the aluminum layer. and the doped amorphous silicon layer are sequentially and selectively removed using an etchant consisting of chlorine gas or chlorine compound gas to expose the first amorphous silicon layer, and the exposed first amorphous silicon layer is exposed. It is characterized by comprising the steps of forming a display cell electrode separated for each element formation region, connected to the aluminum layer remaining in a portion corresponding to the source region, and separated for each element formation region. This is achieved by the method for manufacturing a thin film transistor according to the present invention.

A second object of the present invention is to pattern a conductive layer made of titanium, tantalum, molybdenum, or their silicides by dry etching using an etchant made of a mixed gas of sulfur hexafluoride and helium. This is achieved by the etching method according to the present invention, which is characterized by:

0012

[Operation] When etching a titanium layer laminated with an aluminum layer using a resist layer as a mask, an etchant consisting of a mixed gas of sulfur hexafluoride (SF6) and oxygen (O2) can be used, for example, in the initial stage of etching. As a result, a protective film made of organic matter is formed on the side surfaces of the upper aluminum layer. As a result, the aluminum layer was removed during the process of etching the titanium layer using an etchant consisting of chlorine gas or chlorine compound gas.
No side etching.

[0013] Furthermore, in etching for patterning a layer made of a high melting point metal such as titanium or its silicide, an etchant made of a mixed gas of SF6 and He can be used to reduce the taper of the edge of the etched titanium layer. The angle can be reduced, and etching of the underlying SiO2 layer can be suppressed.

[0014]

[Example] Figure 1 is a cross-sectional view of a process for explaining the principle of the etching method of the present invention.
As shown in , an insulating layer 2 made of silicon nitride (Si3N4) is placed on a substrate 20 made of glass, for example.
1, titanium (Ti) layer 22, and aluminum (Al) layer 2
3 are sequentially deposited. After forming a resist layer 24 that masks a predetermined region on the upper surface of the Al layer 23, the resist layer 24 is
The Al layer 23 exposed from the surface is selectively etched. This etching is performed by wet etching using a phosphoric acid aqueous solution containing nitric acid and acetic acid as the etchant. The broken line in the figure indicates the boundary between the portion removed in the above etching and the remaining portion.

Next, using the resist layer 24 as a mask, the Ti layer 22 is etched by anisotropic etching such as reactive ion etching (RIE). At the beginning of this etching, SF6 to which a small amount of O2 has been added is etched. is used as an etchant. the result,
As shown in FIG. 1(b), a protective film 25 made of an organic substance is formed on the side surface of the Al layer 23 that has been patterned previously. The formation mechanism of the protective film 25 is that the resist layer 24 is sputtered during RIE, and the decomposition products generated at this time are deposited on surfaces that are relatively difficult to receive ion irradiation, such as the side surfaces of the Al layer 23, to form a film. It is considered a thing. A small amount of O2 added to SF6 is
Promote the formation of decomposition products such as those mentioned above. Since the surface of the Ti layer 22 exposed from the resist layer 24 is ion irradiated during RIE, the protective film 25 is not formed. It is also effective to promote the formation of the protective film 25 on the side surfaces of the Al layer 23 by causing side etching in the Al layer 23 during the etching, so that the side surfaces thereof are set back from the edges of the resist layer 24. be.

After forming the protective film 25 as described above, for example, chlorine gas (Cl2) and boron trichloride (BC
Using a well-known etchant consisting of a mixed gas of l3),
As shown in FIG. 1(c), the Ti layer 22 is etched using the resist layer 24 as a mask. Thereafter, the resist layer 24 is removed using dry asher as in the normal process. In this step, the protective film 25 is also removed. Therefore, the patterned Al layer 23
No chlorine molecules remain on the surface, and the corrosion described above does not occur.

The formation of the above-mentioned protective film is shown in FIG. 2(a).
) As shown in A, the resist layer 24 is used as a mask.
The l layer 23 is etched. After that, the resist layer 24 is melted by heater heating or plasma irradiation, etc.
As shown in figure (b), part of it is the Al layer 23.
This can also be done using another method of flowing the water down to cover the sides. In etching the Al layer 23,
It is preferable to perform side etching so that the side surfaces of the Al layer 23 are set back from the edges of the resist layer 24.

FIGS. 3 and 4 are sectional views of essential parts for explaining the manufacturing process of the TFT according to the present invention. Figure 3 (a
), on the surface of the transparent substrate 30 made of glass or the like, a plurality of element formation areas and a display area (all not shown) corresponding to each element formation area are defined. In the figure, gate electrodes 31 are formed in each of two element formation regions in the X direction, and a gate bus 32 is formed extending in the X direction and connected to these gate electrodes 31. Each gate electrode 31 extends in the Y direction.

The gate bus 32 is formed on the transparent substrate 3 in advance.
Core portion 32 made of an aluminum layer formed on the surface of
A and a cladding part 32 consisting of a titanium layer covering it.
It consists of B. The core portion 32A is provided for low resistance. The gate electrode 31 is formed by patterning the same titanium layer as the cladding part 32B. In addition, core part 3
The height of the cladding part 2A is about 50 nm, and the height of the cladding part 32B including this is about 80 nm.

A layer with a thickness of about 300 nm is formed on the surface of the transparent substrate 30 on which the gate electrode 31 and gate bus 32 as described above are formed.
A layer 33 of Si3N4 is deposited. In order to increase the adhesive strength with the transparent substrate 1, a part of the Si3N4 layer 33 near the boundary with the transparent substrate 1 may be replaced with a SiO2 layer 33B with a thickness of approximately 100 nm, as shown in FIG. 3(b). good. Figure 3(b) is a cross-sectional view perpendicular to the X direction defined in Figure 3(a), and shows the gate bus 3.
A cross section of 2 is shown.

Next, on the Si3N4 layer 33, an a-Si layer 34 with a thickness of about 15 nm and an S layer 34 with a thickness of about 150 nm are formed.
An iO2 layer 35 and an a-Si layer 36 with a thickness of about 5 nm are sequentially deposited. Si3N4 layer 33 and a-Si layer 34
constitute the gate insulating layer and active layer of the TFT, respectively, as described below. The SiO2 layer 35 is a
-Si This is an insulating layer that masks the channel region of the active layer 34, and the a-Si layer 36 is provided for the purpose of increasing the adhesive strength of the resist layer shown in the next figure. Formation of each of these layers may be performed using well-known CVD technology.

A resist layer 37 is formed on the uppermost a-Si layer 36 of the multilayer structure formed as described above, as shown in FIG. 3(c), using ordinary lithography technology. a- exposed from the resist layer 37
The Si layer 36 and the SiO2 layer 35 are sequentially selectively etched. These can be performed with sufficient selectivity using the well-known RIE method. In this way,
The a-Si layer 34 on both sides of the channel region is exposed. Note that Fig. 3(c) is based on Y defined in Fig. 3(a).
3 is a cross-sectional view perpendicular to the direction, and shows a cross section of the gate electrode 31.

The above steps are the same as the conventional process for manufacturing an inverted staggered TFT. After the above, the surface of the transparent substrate 30 is doped with n-type impurities to a thickness of approximately 50 nm.
A silicon (n+-Si) layer of about 100 nm, a Ti layer about 100 nm thick, and an Al layer about 300 nm thick are sequentially deposited. Then, on this Al layer, for example, as shown in the cross-sectional view of Fig. 4(a) and the corresponding top view (b),
A resist layer 40 is formed to mask the source region 4S and drain region 4D. The resist layer 40 connects to the drain region 4D and connects to a drain bus 41, which will be described later, and which extends in a direction (Y direction) intersecting the gate bus 32.
It has a portion that masks the area where the .

Then, using the resist layer 40 as a mask, the Al layer, the Ti layer, and the n+-Si layer are sequentially selectively etched, and the exposed a-Si layer 34 is subsequently etched. In FIG. 4(a), reference numeral 42 refers to the n+-Si layer, and 43 refers to the Ti layer.
Layer 44 indicates the Al layer. The above etching is
The Al layer 44 is etched by wet etching using a phosphoric acid aqueous solution containing nitric acid and acetic acid, and the Ti layer 43 is
As explained with reference to Figure 1, the etching process is as follows:
For example, in the initial stage, an etchant consisting of a mixed gas of SF6 and O2 is used to form a protective film (not shown) on the side surface of the Al layer 44. After that,
For example, the Ti layer 43, the n+-Si layer 42, and the a-Si layer 34 are sequentially etched by RIE using a well-known etchant consisting of a mixed gas of Cl2 and BCl3. a-Si layer 3 in the channel region on the gate electrode 31
4 is not etched because it is protected by the SiO2 layer 35.

As described above, the n + -Si layer 42, the Ti layer 43, and the Al layer 44 are in ohmic contact with the a-Si layer 34 of the source region 4S and drain region 4D.
A source electrode, a drain electrode, and a drain bus 41 having a laminated structure are formed by the same lithography process. Therefore, the process becomes more efficient, and
This eliminates the need for alignment margins between the source and drain electrodes and the drain bus 41, making it possible to miniaturize them.

After the above, a target made of, for example, indium (In) doped with tin (Sn) is subjected to reactive sputtering to form a material as shown in the cross-sectional view of FIG. 4(c) and the corresponding plan view (d). In, transparent substrate 30
A transparent conductive film made of indium oxide (ITO) is deposited on the surface and patterned into transparent electrodes 46 separated for each display area. The transparent electrode 46 is connected to the Al layer 44 on the source region 4S.

[0027] As described above, the TFT according to the present invention
An LCD equipped with this is completed. Note that the reference numeral 41 in FIG. 4 is a well-known redundant circuit provided in parallel with the drain bus 41. FIG. 5 is an explanatory diagram of an etching method according to the present invention for patterning the front gate bus 32. As shown in FIG. Referring to figure (a), as before,
A core portion 32A made of aluminum and having a thickness of approximately 50 nm is formed on one surface of a transparent substrate 30 made of glass or the like on which a SiO2 layer 50 having a thickness of approximately 200 nm is formed. Next, it was made to cover the core part 32A to a thickness of about 80n.
Deposit a Ti layer 320 of m.

In order to pattern the Ti layer 320 into the shape of the cladding part, etching is performed using the resist layer 51, and in the present invention, a mixed gas of SF6 and He is used as the etchant at this time. When the etchant is only SF6, as explained with reference to FIG. 7, the taper angle of the edge of the cladding part 32B is large, and when the over-etching condition is met, the SiO2 layer 50 is etched. Put it away.

On the other hand, when He is added to SF6, as shown in FIG. 5(b), the Ti layer 32
The taper angle of the edge of the cladding portion 32B made of zero becomes smaller. That is, the side surface of the cladding portion 32B becomes a gently sloped surface. Further, even if the etching of the Ti layer 320 is set to an overetching condition of about 10%, the SiO2 layer 50 is not etched. In other words, the uniformity of etching is improved by adding He, and as a result, regions where local overetching occurs no longer occur, making it possible to suppress the thinning of the SiO2 layer to a small level. In addition, instead of He, Ne
When a rare gas with a larger mass such as Ar or Ar was added, the etching rate of the Ti layer 320 decreased, and the above-mentioned effects such as those of the addition of He were not observed.

[0030]

[Effects of the Invention] According to the present invention, a source electrode, a drain electrode, and a drain bus having a laminated structure of a Ti layer and an Al layer can be patterned all at once in the same lithography process, which improves the efficiency of the TFT manufacturing process. And high resolution becomes possible. In addition, the shape of the side surface of the core part of the gate bus made of the Ti layer can be made into a gently sloped surface, which solves the problem of short circuits caused by insufficient coverage of the conventional insulating layer, and also reduces the etching problem of the Ti layer. The improved uniformity suppresses the thinning of the underlying SiO2 layer and has the effect of solving the problem of short circuits between the storage capacitor electrode, gate, and gate bus.

[Brief explanation of the drawing]

[Figure 1] Diagram explaining the principle of the present invention

[Figure 2] An explanatory diagram of another method for forming a protective film in the present invention

[Figure 3] TFT manufacturing process explanatory diagram according to the present invention (Part 1)

[Fig. 4] TFT manufacturing process explanatory diagram according to the present invention (Part 2)

[Fig. 5] An explanatory diagram of the etching method according to the present invention for forming a gate bus

[Figure 6] Diagram explaining problems in conventional TFT manufacturing method

[
Figure 7: Diagram explaining the problems of the conventional gate bus formation method

[Explanation of symbols]

20, 30 board
32B Clad part 21 Insulating layer
33 Si3N4 layer 22,
43, 320 Ti layer
33B, 35, 50 SiO2
Layer 23, 44 Al layer
34, 36 a-Si layer 24, 37, 40, 51 resist layer
41 Drain bath 25 Protective film
42 n+ -Si layer 31 Gate electrode
46 Transparent electrode 32 Gate bus 4
S source area 32A core part
4D drain region

Claims (5)

[Claims] 1. A step of sequentially depositing a layer made of a high melting point metal or its silicide and an aluminum layer on one surface of a substrate covered with an insulator, and a resist layer selectively covering a predetermined region of the aluminum layer. The process of forming;
A step of selectively etching the aluminum layer using the resist layer as a mask to expose the high melting point metal layer or silicide layer, and applying an etchant consisting of chlorine gas or chlorine compound gas to the side surface of the etched aluminum layer. After forming a resistant protective film, the method includes the step of dry etching the high melting point metal layer or silicide layer exposed from the resist layer using the etchant made of the chlorine gas or chlorine compound gas. Etching method. 2. The protective film is formed by using an etchant made of a mixed gas of sulfur hexafluoride and oxygen at least initially in the step of dry etching the high melting point metal layer or the silicide layer. The etching method according to claim 1. 3. After etching the aluminum layer using the resist layer as a mask, the resist layer is heated or exposed to plasma to melt it, thereby forming the protective film made of the molten resist layer on the side surface of the etched aluminum layer. Claim 1 characterized in that it forms
Etching method described. 4. A gate electrode made of titanium extending in a first direction in each of the device formation regions is provided on one surface of the substrate in which a plurality of device formation regions are defined, and a gate electrode made of titanium is provided in each of the device formation regions in the first direction. forming a gate bus made of at least titanium and connected to the plurality of gate electrodes extending in an intersecting second direction and arranged in the second direction; and forming the gate electrode and the gate bus. sequentially depositing a first insulating layer made of silicon nitride, a first amorphous silicon layer, and a second insulating layer on the surface of the transparent substrate;
forming a resist layer corresponding to the gate electrode on the second insulating layer; and selectively etching the second insulating layer exposed from the resist layer to form the first amorphous silicon layer. a step of sequentially depositing a doped amorphous silicon layer, a titanium layer, and an aluminum layer so as to cover at least the exposed first amorphous silicon layer; After selectively removing the aluminum layer, leaving portions corresponding to the source and drain regions and a portion extending in the second direction from the portion corresponding to the drain region, the aluminum layer is removed. A step of dry etching a part of the titanium layer exposed from the aluminum layer in the layer thickness direction using an etchant consisting of a mixed gas of sulfur hexafluoride and oxygen, and the remaining part of the titanium layer exposed from the aluminum layer. and the doped amorphous silicon layer to expose the first amorphous silicon layer by sequentially selectively removing the doped amorphous silicon layer using an etchant consisting of chlorine gas or chlorine compound gas; a step of separating the silicon layer into each element formation region; and a step of forming a display cell electrode connected to the aluminum layer remaining in the portion corresponding to the source region and separated for each element formation region. A method of manufacturing a thin film transistor, comprising: [Claim 5] Titanium, tantalum or molybdenum,
Alternatively, an etching method characterized in that a conductive layer made of these silicides is patterned by dry etching using an etchant made of a mixed gas of sulfur hexafluoride and helium.