KR100709707B1 - Thin film transistor substrate including the contact structure and method manufacturing the same - Google Patents

Abstract

First, an aluminum-based conductive film and a conductive film including aluminum and silicon are sequentially stacked and patterned to form a horizontal gate wiring including a gate line, a gate electrode, and a gate pad on the substrate, and a first low resistance layer thereon. do. Next, a gate insulating film is formed, and a semiconductor layer and an ohmic contact layer are sequentially formed thereon. Subsequently, a conductive film including aluminum and silicon, an aluminum-based conductive film, and a conductive film including aluminum and silicon are sequentially stacked and patterned to intersect the second low resistance layer and the gate line with data lines, source electrodes, drain electrodes, and data. The data line including the pad and the third low resistance layer are sequentially formed. Subsequently, the protective layer is stacked and patterned to form contact holes that expose the first and third low resistance layers on the drain electrode, the gate pad, and the data pad, respectively. Subsequently, the IZO is stacked and patterned to form pixel electrodes, auxiliary gate pads, and auxiliary data pads connected to the drain electrodes, the gate pads, and the data pads via the first and third low resistance layers, respectively.

Aluminum, IZO, Silicon, Contact Characteristics

Description

Thin film transistor substrate and its manufacturing method {THIN FILM TRANSISTOR SUBSTRATE INCLUDING THE CONTACT STRUCTURE AND METHOD MANUFACTURING THE SAME}

1 is a thin film transistor substrate for a liquid crystal display device according to a first embodiment of the present invention;

FIG. 2 is a cross-sectional view of the thin film transistor substrate illustrated in FIG. 1 taken along the line II-II.

3A, 4A, 5A, 6A, and 7A are layout views of a thin film transistor substrate in an intermediate process of manufacturing a thin film transistor substrate for a liquid crystal display device according to a first embodiment of the present invention;

3B is a cross-sectional view taken along the line IIIb-IIIb ′ in FIG. 3A;

4B is a cross-sectional view taken along the line IVb-IVb ′ in FIG. 4A and is a cross-sectional view showing the next step in FIG. 3B;

FIG. 5B is a cross-sectional view taken along the line Vb-Vb ′ in FIG. 5A and is a cross-sectional view showing the next step in FIG. 4B;

FIG. 6B is a cross-sectional view taken along the line VIb-VIb ′ in FIG. 6A and is a cross-sectional view showing the next step in FIG. 5B;

7 is a layout view of a thin film transistor substrate for a liquid crystal display according to a second exemplary embodiment of the present invention.

8 and 9 are cross-sectional views of the thin film transistor substrate shown in FIG. 7 taken along lines VIII-VIII 'and IX-IX',

10A is a layout view of a thin film transistor substrate in a first step of manufacturing according to the second embodiment of the present invention;

10B and 10C are cross-sectional views taken along the lines Xb-Xb 'and Xc-Xc' in FIG. 10A, respectively.

11A and 11B are cross-sectional views taken along the lines Xb-Xb 'and Xc-Xc' of FIG. 10A, respectively, and are cross-sectional views of the next steps of FIGS. 10B and 10C.

12A is a layout view of a thin film transistor substrate in FIGS. 11A and 11B next steps;

12B and 12C are cross-sectional views taken along the lines XIIb-XIIb 'and XIIc-XIIc' in FIG. 12A, respectively.

13A, 14A, 15A and 13B, 14B, and 15B are cross-sectional views taken along the lines XIIb-XIIb 'and XIIc-XIIc' in FIG. 12A, respectively, illustrating the following steps in the order of the process. ,

FIG. 16A is a layout view of a thin film transistor substrate in the next steps of FIGS. 15A and 15B;

16B and 16C are cross-sectional views taken along lines XVIb-XVIb 'and XVIc-XVIc', respectively, in FIG. 16A.

The present invention relates to a contact structure of a wiring, a method of manufacturing the same, a thin film transistor substrate including the same, and a method of manufacturing the same.

In general, the wiring in the semiconductor device is used as a means for transmitting a signal, it is required to minimize the signal delay.

In this case, in order to prevent signal delay, the wiring is generally made of a metal material having a low resistance, particularly an aluminum-based metal material such as aluminum (Al) or aluminum alloy (Al alloy). However, since the aluminum-based wiring has weak physical or chemical properties, corrosion occurs when connected to other conductive materials at the contact portion, thereby increasing contact resistance and deteriorating characteristics of the semiconductor device. In order to improve such contact characteristics, wiring may be interposed with other metals when forming an aluminum series. However, in order to form a multilayer wiring, not only different etching solutions are required but also multiple etching processes are required, which makes the manufacturing process complicated. .

On the other hand, the liquid crystal display device is one of the most widely used flat panel display devices, and consists of two substrates on which electrodes are formed and a liquid crystal layer inserted therebetween. The display device controls the amount of light transmitted by rearranging.                         

Among the liquid crystal display devices, a liquid crystal display device having a thin film transistor for forming an electrode on each of two substrates and switching a voltage applied to the electrode is generally used. The thin film transistor is generally formed on one of two substrates.

In such a liquid crystal display device, in order to prevent signal delay, the wiring generally uses a low resistance material such as aluminum (Al) or aluminum alloy (Al alloy) having a low resistance. However, in the case of forming a pixel electrode or securing pad part reliability using indium tin oxide (ITO) or indium zinc oxide (IZO), which is a transparent conductive material, as in a liquid crystal display device, an aluminum-based metal and ITO or IZO The contact properties are poor, but intervenes with other metals such as molybdenum series or chromium, but aluminum or aluminum alloys need to be removed from the contact portion, which causes a complicated manufacturing process.

On the other hand, in the manufacturing method of the liquid crystal display device, the substrate on which the thin film transistor is formed is generally manufactured through a photolithography process using a mask. At this time, it is preferable to reduce the number of masks in order to reduce the production cost.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a contact structure of a wiring made of a low resistance material and having a low resistance contact characteristic, and a method of manufacturing the same.

Another object of the present invention is to provide a thin film transistor substrate including a contact structure of a wiring having excellent contact characteristics and a method of manufacturing the same.                         

In addition, another object of the present invention is to simplify the manufacturing method of the thin film transistor substrate.

In order to solve this problem, in the present invention, a low resistance layer including at least aluminum and silicon is formed on the upper or lower portion of the wiring made of aluminum-based metal.

In the method for manufacturing a thin film transistor substrate according to the present invention, first, a gate wiring and a data wiring insulated from the gate wiring are formed. Next, a low resistance layer including aluminum and silicon is formed on at least one of the gate wiring and the data wiring, and a conductive layer electrically connected to the gate wiring or the data wiring is formed via the low resistance layer.

In this case, the gate wiring or the data wiring is preferably formed of an aluminum-based conductive material and the conductive layer is formed of IZO, which is a transparent conductive material.

Here, the low resistance layer may be formed by sputtering using a target including aluminum and silicon of 1 to 10 at% or less, and the low resistance layer may be formed only on the upper portion of the gate wiring and only on the upper portion of the data wiring. have.

In addition, a conductive film may be formed by sputtering using a buffer film containing chromium, molybdenum, or molybdenum alloy or a target including aluminum and 1 to 30 at% or less of silicon below the data line.

The gate wiring includes a gate line extending in the horizontal direction, a gate electrode connected to the gate line, and a gate pad receiving a scan signal from the outside and transferring the scan signal to the gate line. The data wiring includes a data line and data extending in the vertical direction. A source electrode connected to the line, a source electrode separated from the source electrode, a drain electrode facing the source electrode, and a data pad configured to transfer an image signal from the outside to a data line.

Next, a thin film transistor substrate for a liquid crystal display device and a method of manufacturing the same according to embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. do.

As a semiconductor device, particularly a wiring for transmitting a signal, an aluminum-based metal material having a low resistivity of 15 μΩcm or less is suitable to minimize signal delay. In this case, the wiring should be connected to another conductive layer in order to receive a signal from the outside or to transmit a signal to the outside, and should not be easily corroded when contacted with other materials in the manufacturing process. To this end, in the method for manufacturing a contact structure of a wiring according to an embodiment of the present invention, first, a wiring made of a metal having a low resistance on a substrate and a low resistance layer containing a conductive material and silicon are formed on the substrate, and then The insulating insulating film is laminated and patterned to form a contact hole that exposes the low resistance layer on the upper portion of the wiring, and a conductive layer electrically connected to the wiring via the low resistance layer through the contact hole on the insulating layer.

Here, the conductive layer may be formed of a transparent conductive material, preferably indium tin oxide (ITO) or indium zinc oxide (IZO), and the wiring may be formed of an aluminum-based metal having low resistance.

In this case, the low resistance layer is preferably formed by a sputtering method using a target containing 1-10 at% (atomic percent) or less of silicon and an aluminum-based conductive material in consideration of resistance.

Here, the low resistance layer has a function of lowering the contact resistance between the aluminum based wiring and the conductive layer of ITO or IZO or preventing corrosion of the aluminum based wiring at the contact portion.

The wiring may be used as a gate wiring or a data wiring of a thin film transistor for a liquid crystal display device.

First, a structure of a thin film transistor substrate for a liquid crystal display according to a first embodiment of the present invention will be described in detail with reference to FIGS. 1 and 2.

1 is a thin film transistor substrate for a liquid crystal display according to a first embodiment of the present invention, and FIG. 2 is a cross-sectional view of the thin film transistor substrate shown in FIG. 1 taken along the line II-II '.

A gate wiring made of an aluminum-based metal material having low resistance is formed on the insulating substrate 10. The gate wire is connected to the gate line 22 and the gate line 22 extending in the horizontal direction, and are connected to the gate pad 24 and the gate line 22 which receive a gate signal from the outside and transmit the gate signal to the gate line. A gate electrode 26 of the thin film transistor.

A first low resistance layer 320 including an aluminum-based conductive material and silicon is formed on the gate wires 22, 24, and 26.

On the substrate 10, a gate insulating film 30 made of silicon nitride (SiN _x ) covers the gate wirings 22, 24, and 26 and the low resistance layer 320, and the gate insulating film 30 is a protective film formed thereafter. Along with 70, a contact hole 74 exposing the low resistance layer 320 over the gate pad 24 is provided.

A semiconductor layer 40 made of a semiconductor such as amorphous silicon is formed on the gate insulating film 30 of the gate electrode 24 in an island shape, and silicide or n-type impurities are doped with high concentration on the semiconductor layer 40. Resistive contact layers 54 and 56 made of a material such as n + hydrogenated amorphous silicon are formed, respectively.

On the resistive contact layers 54 and 56 and the gate insulating layer 30, aluminum (Al) or aluminum alloy (Al alloy), molybdenum (Mo) or molybdenum-tungsten (MoW) alloy, chromium (Cr), tantalum (Ta), etc. The data wirings 62, 64, 66, 68 made of metal or conductors are formed. The data line is formed in the vertical direction and crosses the gate line 22 to define a pixel, the data line 62 and the branch of the data line 62 and the source electrode 64 extending to the upper portion of the ohmic contact layer 54. ), Which is connected to one end of the data line 62 and is separated from the data pad 68 and the source electrode 64 to which an image signal from the outside is applied, and is opposite to the source electrode 64 with respect to the gate electrode 26. And a drain electrode 66 formed on the ohmic contact layer 56.

The data wires 62, 64, 66, and 68 are preferably formed of a single film of aluminum series as in the embodiment of the present invention, but may be formed of two or more layers. In the case of forming more than two layers, it is preferable that one layer is made of a material having a low resistance and the other layer is made of a material having good contact properties with other materials. Examples thereof include Cr / Al (or Al alloy) or Al / Mo.

Further, second and lower portions of the data lines 62, 65, 66, and 68 are formed in the same shape as the data lines 62, 65, 66, and 68, and include aluminum-based conductive materials and silicon. Third low resistance layers 760 and 650 are formed.

The passivation layer 70 is formed on the data lines 62, 64, 66, and 68 and the semiconductor layer 40 not covered by the data lines 62. In the passivation layer 90, contact holes 76 and 78 respectively exposing the drain electrode 66 and the upper low resistance layer 760 on the data pad 68 are formed, respectively, and the gate pad 30 is formed together with the gate insulating layer 30. (24) The contact hole 74 which exposes the low resistance layer 320 in the upper part is formed.

Here, the first and third low resistance layers 320 and 760 may be formed of pixel wires 82, 86, and 88 of indium zinc oxide (IZO) or indium tin oxide (ITO) formed thereafter, and an aluminum-based metal. As a layer for improving the contact characteristics between the gate pad 24 and the drain electrode 66 and the data pad 68, the contact resistance of the contact is lowered or impurities are prevented from flowing into the wirings 24, 66, and 68 from the contact. It has a function to prevent the progress of corrosion. In addition, the second low resistance layer 650 has a function of lowering the contact resistance between the source and drain electrodes 65 and 66 and the semiconductor layer 40, and the aluminum metal of the source and drain electrodes 65 and 66 is a semiconductor layer. It has a function of preventing the diffusion to 40. In this case, a buffer film including chromium, molybdenum, molybdenum alloy, or the like may be formed in place of the second low resistance layer 650.

On the passivation layer 70, the pixel electrode 82, which is electrically connected to the drain electrode 66 and positioned in the pixel, is in contact with the third low resistance layer 760 on the drain electrode 66 through the contact hole 76. The contact holes 74 and 78 are electrically connected to the pads 24 and 68 via the first and third low resistance layers 320 and 760 on the gate pad 24 and the data pad 68, respectively. A subsidiary gate pad 86 and an auxiliary data pad 88, and pixel wirings formed of IZO or ITO are formed.

1 and 2, the pixel electrode 82 overlaps with the gate line 22 to form a storage capacitor. When the storage capacitor is insufficient, the pixel electrode 82 is disposed on the same layer as the gate wirings 22, 24, and 26. It is also possible to add a storage capacitor wiring.

In the structure according to the embodiment of the present invention, the low resistance includes the gate wirings 22, 24, and 26 and the data wirings 62, 64, 66, and 68 made of aluminum-based metal, so that the liquid crystal display having a high resolution is large. Applicable to the device. At the same time, the gate pad 24, the data pad 68, and the drain electrode 66 and the auxiliary gate pad 86, the auxiliary data pad 88, and the pixel electrode 82 of IZO or ITO, respectively, have their contact characteristics. Since the first and third low resistance layers 320 and 760 are electrically connected to each other through the first and third low resistance layers, corrosion does not occur in the pad part. Therefore, the pad part can be secured.

Next, a method of manufacturing a thin film transistor substrate for a liquid crystal display device having a structure according to a first embodiment of the present invention will be described in detail with reference to FIGS. 1 and 2 and FIGS. 3A to 6B.

First, as shown in FIGS. 3A and 3B, an aluminum-based conductive film having a low resistance and a conductive film including aluminum and silicon are laminated and patterned on the substrate 10 to a thickness of about 2,500 kPa and 1,000 kPa or less, respectively. A gate line in the horizontal direction including the gate line 22, the gate electrode 26, and the gate pad 24 is formed, and the first low resistance layer 320 thereon is formed.

In this case, a target for forming the low resistance layer 320 is formed by a sputtering method using a target including silicon and aluminum of 1 to 10 at% (atomic percent) or less, and the first low resistance layer 320. ) Is preferably formed by dry etching. More specifically, the target for forming the low resistance layer 320 is produced by vacuum dissolution method or spray-forming method by placing silicon of 1 ~ 10 at% (atomic percent) or less in molten aluminum. The target thus manufactured is mounted on a DC magnetron sputter to form a thin film by sputtering. The direct current magnetron uses direct current as a power source, and a magnet is mounted on the rear of the target to increase plasma density and deposition rate. Typically, the gas uses Ar as an inert gas. At this time, the pressure is about 1 ~ 10mT, the temperature proceeds at about 200 ℃ at room temperature.

Next, as shown in FIGS. 4A and 4B, a three-layer film of the gate insulating film 30, the semiconductor layer 40 made of amorphous silicon, and the doped amorphous silicon layer 50 is successively stacked, and a patterning process using a mask is performed. The semiconductor layer 40 and the doped amorphous silicon layer 50 are patterned to form an island-shaped semiconductor layer 40 and an ohmic contact layer 50 on the gate insulating layer 30 facing the gate electrode 24. do.

Next, as shown in FIGS. 5A to 5B, a conductive film made of aluminum and silicon, a conductive film made of an aluminum-based metal having low resistance, and a conductive film made of aluminum and silicon are respectively 1,000 kPa or less and 2,500 kPa. After stacking each one at a precision and a thickness of 1,000 Å or less, patterning is performed by a photolithography process using a mask. The data line 62 and the data line 62 intersect the gate line 22 and are connected to the upper portion of the gate electrode 26. The source electrode 65 and the data line 62 extending to each other are separated from the data pad 68 and the source electrode 65 connected to one end, and the source electrode 66 and the gate electrode 26. Second and third low resistance layers 650 and 760 are formed on the data line including opposite drain electrodes 66 and under and over the data lines.

In this case, the target for forming the third low resistance layer 320 is preferably formed by a sputtering method using a target containing 1 to 10 at% (atomic percent) of silicon and aluminum. 2 The target for forming the low resistance layer 650 is preferably formed by a sputtering method using a target containing 1 to 30 at% (atomic percent) of silicon and aluminum. Of course, even in this case, the second and third low resistance layers 650 and 760 are preferably patterned by dry etching.

Subsequently, the doped amorphous silicon layer pattern 50, which is not covered by the data lines 62, 65, 66, and 68, is etched and separated on both sides of the gate electrode 26, while both doped amorphous silicon layers ( The semiconductor layer pattern 40 between 55 and 56 is exposed. Subsequently, in order to stabilize the surface of the exposed semiconductor layer 40, it is preferable to perform oxygen plasma.

6A and 6B, a protective film 70 made of silicon nitride or an organic insulating film is laminated, and then patterned by dry etching together with the gate insulating film 30 in a photolithography process using a mask, thereby forming a gate. Contact holes 74, 76, and 78 are formed to expose the pad 24, the drain electrode 66, and the first and third low resistance layers 320 and 760 on the data pad 68.

Next, as shown in FIGS. 1 and 2, IZO or ITO is stacked and patterned using a mask to form a third low resistance layer 760 on the drain electrode 66 through the contact hole 76. Auxiliary gate pads connected to the first and third low resistance layers 320 and 760 on the gate pad 24 and the data pad 68 through the pixel electrodes 82 and the contact holes 74 and 78, respectively. 86 and auxiliary data pads 88 are formed, respectively.

In the manufacturing method according to the exemplary embodiment of the present invention, the low resistance layers 320 and 760 are formed in order to improve contact characteristics between IZO or ITO and an aluminum-based metal.

In the first embodiment, as described above, the present invention can be applied to a manufacturing method using five masks, but the same can be applied to the manufacturing method of a thin film transistor substrate for liquid crystal display devices using four masks. This will be described in detail with reference to the drawings.

First, a unit pixel structure of a thin film transistor substrate for a liquid crystal display device completed using four masks according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 7 to 9.

FIG. 7 is a layout view of a thin film transistor substrate for a liquid crystal display according to a second exemplary embodiment of the present invention, and FIGS. 8 and 9 are lines VII-VII 'and IX-IX', respectively, of the thin film transistor substrate shown in FIG. 7. A cross-sectional view taken along the line.

First, a gate wiring including a gate line 22, a gate pad 24, and a gate electrode 26 made of an aluminum-based metal on the insulating substrate 10 and the first low layer thereon is formed as in the first embodiment. The resistance layer 320 is formed. The gate wiring includes a storage electrode 28 that is parallel to the gate line 22 on the substrate 10 and receives a voltage such as a common electrode voltage input to the common electrode of the upper plate from the outside. The first low resistance layer 320 is also formed on the top of the back panel). The storage electrode 28 overlaps with the conductive capacitor conductor 68 for the storage capacitor connected to the pixel electrode 82, which will be described later, to form a storage capacitor which improves the charge retention capability of the pixel. The pixel electrode 82 and the gate line, which will be described later, If the holding capacity generated by the overlap of (22) is sufficient, it may not be formed.

A gate insulating film 30 made of silicon nitride (SiN _x ) is formed on the gate wirings 22, 24, 26, and 28 to cover the low resistance layer 320 on the gate wirings 22, 24, 26, and 28. .

Semiconductor patterns 42 and 48 made of semiconductors such as hydrogenated amorphous silicon are formed on the gate insulating layer 30, and high concentrations of n-type impurities such as phosphorus (P) are formed on the semiconductor patterns 42 and 48. An ohmic contact layer pattern or an intermediate layer pattern 55, 56, 58 made of amorphous silicon doped with is formed.

On the ohmic contact layer patterns 55, 56, and 58, a data line made of an aluminum-based conductive material having low resistance is formed. The data line is a thin film transistor which is a branch of the data line 62 formed in the vertical direction, the data pad 68 connected to one end of the data line 62 to receive an image signal from the outside, and the data line 62. And a data line portion of the source electrode 65 of the source electrode 65. The data line portion is separated from the data line portions 62, 68, and 65, and the source electrode 65 is separated from the gate electrode 26 or the channel portion C of the thin film transistor. It also includes a conductive capacitor conductor 64 for the storage capacitor located on the drain electrode 66 and the storage electrode 28 of the thin film transistor located on the opposite side. When the sustain electrode 28 is not formed, the conductor pattern 64 for the storage capacitor is also not formed. Here, second and third low resistance layers 650 and 760 are formed on the upper and lower portions of the data lines 62, 64, 65, 66 and 68 as in the first embodiment.

The data lines 62, 64, 65, 66, and 68 may also be formed of a single layer of aluminum, similar to the gate lines 22, 24, 26, and 28, but may be formed of a double layer containing chromium or molybdenum or molybdenum alloys. It may be formed.                     

The contact layer patterns 55, 56, and 58 serve to lower the contact resistance between the semiconductor patterns 42 and 48 below and the data lines 62, 64, 65, 66, and 68 above them. It has exactly the same form as (62, 64, 65, 66, 68). That is, the data line part intermediate layer pattern 55 is the same as the data line parts 62, 68, and 65, the drain electrode intermediate layer pattern 56 is the same as the drain electrode 66, and the storage capacitor intermediate layer pattern 58 is It is the same as the conductor pattern 64 for holding capacitors.

The semiconductor patterns 42 and 48 have the same shape as the data lines 62, 64, 65, 66, and 68 and the ohmic contact layer patterns 55, 56, and 58 except for the channel portion C of the thin film transistor. Doing. Specifically, the semiconductor capacitor 48 for the storage capacitor, the conductor pattern 68 for the storage capacitor, and the contact layer pattern 58 for the storage capacitor have the same shape, but the semiconductor pattern 42 for the thin film transistor has data wiring and contact. Slightly different from the rest of the layer pattern. That is, in the channel portion C of the thin film transistor, the data line portions 62, 66, 65, and 68, in particular, the source electrode 65 and the drain electrode 66 are separated, and the data line portion intermediate layer 55 contacts the drain electrode. Although the layer pattern 56 is also separated, the semiconductor pattern 42 for thin film transistors is connected here without disconnection to generate a channel of the thin film transistor.

The passivation layer 70 is formed on the data wires 62, 64, 65, 66, and 68, and the passivation layer 70 is formed on the drain electrode 66, the data pad 68, and the conductive pattern 64 for the storage capacitor. Contact holes 71, 73, and 74 that expose the third low resistance layer 760, and contact the first low resistance layer 320 above the gate pad 24 together with the gate insulating layer 30. It has a hole 72. The passivation layer 70 may be made of an organic insulating material such as silicon nitride or acrylic.

On the passivation layer 70, a pixel electrode 82 that receives an image signal from a thin film transistor and generates an electric field together with the electrode of the upper plate is formed. The pixel electrode 82 is made of a transparent conductive material such as indium tin oxide (IZO) or indium tin oxide (ITO), and the drain electrode 66 via the third low resistance layer 760 through the contact hole 71. ) Is electrically connected to and receives an image signal. The pixel electrode 82 also overlaps with the neighboring gate line 22 and the data line 62 to increase the aperture ratio, but may not overlap. The pixel electrode 82 is also connected to the conductor pattern 64 through the contact hole 74 via the third low resistance layer 760 on the conductive pattern 64 for the storage capacitor to transmit an image signal. . On the other hand, the auxiliary gate pad 84 and the auxiliary data pad 86 connected to the gate pad 24 and the low resistance layers 320 and 760 on the data pad 68 through the contact holes 72 and 73, respectively. Are formed, and these are not essential to serve to protect the pad and to protect the adhesion between the pads 24 and 68 and the external circuit device, and their application is optional.

Here, although transparent IZO or ITO is mentioned as an example of the material of the pixel electrode 82, in the case of a reflective liquid crystal display, an opaque conductive material may be used.

Next, a method of manufacturing a thin film transistor substrate for a liquid crystal display device having the structure of FIGS. 7 to 9 using four masks will be described in detail with reference to FIGS. 7 to 9 and 10A to 16C. .

First, as shown in FIGS. 10A to 10C, similarly to the first embodiment, the aluminum-based conductive film and the conductive film including aluminum and silicon are sequentially stacked, and the substrate 10 is subjected to a photolithography process using a first mask. A gate line including a gate line 22, a gate pad 24, a gate electrode 26, and a storage electrode 28 is formed thereon, and a first low resistance layer 320 is formed thereon.

Next, as shown in FIGS. 11A and 11B, the gate insulating film 30, the semiconductor layer 40, and the intermediate layer 50 are respectively 1,500 kV to 5,000 kV, 500 kV to 2,000 kV, and 300 kV using chemical vapor deposition. And continuously deposited to a thickness of 600 kPa, and then sputtering the conductive layer 650 including aluminum and silicon, the aluminum-based conductor layer 60 having low resistance, and the conductive layer 760 including aluminum and silicon. By a method of 1,000 Å or less, 1,500 to 3,000 Å, and 1,000 Å or less in thickness, respectively, and then the photosensitive film 110 is applied thereon in a thickness of 1 μm to 2 μm.

Thereafter, the photosensitive film 110 is irradiated with light through a second mask and then developed to form photosensitive film patterns 112 and 114 as shown in FIGS. 12B and 12C. In this case, among the photoresist patterns 112 and 114, the channel portion C of the thin film transistor, that is, the first portion 114 positioned between the source electrode 65 and the drain electrode 66, is the data wiring portion A, that is, the data. The thickness of the wirings 62, 64, 65, 66, and 68 is smaller than that of the second portion 112 positioned at the portion where the wirings 62, 64, 65, 66, and 68 are to be formed. At this time, the ratio of the thickness of the photoresist film 114 remaining in the channel portion C to the thickness of the photoresist film 112 remaining in the data wiring portion A should be different depending on the process conditions in the etching process described later. It is preferable that the thickness of the first portion 114 is 1/2 or less of the thickness of the second portion 112, for example, 4,000 kPa or less.

As such, there may be various methods of varying the thickness of the photoresist layer according to the position. In order to control the light transmittance in the A region, a slit or lattice-shaped pattern is mainly formed or a translucent film is used.

In this case, the line width of the pattern located between the slits, or the interval between the patterns, that is, the width of the slits, is preferably smaller than the resolution of the exposure apparatus used for exposure. A thin film having a thickness or a thin film may be used.

When the light is irradiated to the photosensitive film through such a mask, the polymers are completely decomposed at the part directly exposed to the light, and the polymers are not completely decomposed because the amount of light is small at the part where the slit pattern or the translucent film is formed. In the area covered by, the polymer is hardly decomposed. Subsequently, when the photoresist film is developed, only a portion where the polymer molecules are not decomposed is left, and a thin photoresist film may be left at a portion where the light is not irradiated at a portion less irradiated with light. In this case, if the exposure time is extended, all molecules are decomposed, so it should not be so.

The thin film 114 is formed by using a photoresist film made of a reflowable material, and is exposed to a conventional mask that is divided into a part that can completely transmit light and a part that cannot fully transmit light, and then develops and ripples. It may be formed by lowering a portion of the photosensitive film to a portion where the photosensitive film does not remain.

Subsequently, etching is performed on the photoresist pattern 114 and the underlying layers, that is, the conductor layers 60, the conductive layers 650 and 760, the intermediate layer 50, and the semiconductor layer 40. In this case, the data line and the layers under the data line remain in the data wiring portion A, and only the semiconductor layer should remain in the channel portion C, and the five layers 760, 60, All of the 650, 50, and 40 should be removed to expose the gate insulating film 30.

First, as shown in FIGS. 13A and 13B, the exposed conductor layer 60 of the other portion B and the conductive layers 760 and 650 of the upper and lower portions of the conductor layer 60 are removed to remove the intermediate layer thereunder. Expose (50). In this process, both a dry etching method and a wet etching method may be used. In this case, the conductor layer 60 and the conductive layers 650 and 760 may be etched and the photoresist patterns 112 and 114 may be hardly etched. However, in the case of dry etching, since only the conductor layer 60 and the conductive layers 760 and 650 are etched and the photoresist patterns 112 and 114 are difficult to find, the photoresist patterns 112 and 114 are also etched. It can be performed under conditions. In this case, the thickness of the first portion 114 is thicker than that of the wet etching so that the first portion 114 is removed in this process so that the lower conductive layer 650 is not exposed.

When the conductor layer 60 is any one of Mo or MoW alloy, Al or Al alloy, and Ta, either dry etching or wet etching can be used. However, since Cr is not easily removed by the dry etching method, it is preferable to use only wet etching if the conductor layer 60 is Cr. In the case of wet etching in which the conductor layer 60 is Cr, CeNHO ₃ may be used as an etchant. In the case of dry etching in which the conductor layer 60 is Mo or MoW, the mixed gas or CF of CF ₄ and HCl may be used as the etching gas. A mixed gas of ₄ and O ₂ can be used, and in the latter case, the etching ratio to the photoresist film is almost the same.

In this way, as shown in FIGS. 13A and 13B, the conductor layers of the channel portion C and the data wiring portion B, that is, the conductor pattern 67 for the source / drain and the conductor pattern 64 for the storage capacitor, Only the lower and upper conductive layers 650 and 760 remain, and the conductor layer 60 and the conductive layers 650 and 760 in the other portion B are all removed to reveal the lower intermediate layer 50. The remaining conductor patterns 67 and 64 have the same shape as the data lines 62, 64, 65, 66 and 68 except that the source and drain electrodes 65 and 66 are connected without being separated. In addition, when dry etching is used, the photoresist patterns 112 and 114 are also etched to a certain thickness.

Subsequently, as shown in FIGS. 14A and 14B, the exposed intermediate layer 50 of the other portion B and the semiconductor layer 40 thereunder are simultaneously removed by the dry etching method together with the first portion 114 of the photosensitive film. do. At this time, etching is performed under the condition that the photoresist patterns 112 and 114, the intermediate layer 50, and the semiconductor layer 40 (the semiconductor layer and the intermediate layer have almost no etching selectivity) are simultaneously etched, and the gate insulating layer 30 is not etched. In particular, it is preferable to etch under conditions where the etching ratios of the photoresist patterns 112 and 114 and the semiconductor layer 40 are almost the same. For example, by using a mixed gas of SF ₆ and HCl or a mixed gas of SF ₆ and O ₂ , the two films can be etched to almost the same thickness. When the etching ratios of the photoresist patterns 112 and 114 and the semiconductor layer 40 are the same, the thickness of the first portion 114 should be equal to or smaller than the sum of the thicknesses of the semiconductor layer 40 and the intermediate layer 50.

In this case, as shown in FIGS. 14A and 14B, the first portion 114 of the channel portion C is removed to expose the conductive layer 760 on the source / drain conductor pattern 67 and the other portion ( The intermediate layer 50 and the semiconductor layer 40 of B) are removed to reveal the gate insulating film 30 thereunder. On the other hand, since the second portion 112 of the data wiring portion A is also etched, the thickness becomes thin. In this step, the semiconductor patterns 42 and 48 are completed. Reference numerals 57 and 58 denote intermediate layer patterns under the source / drain conductor patterns 67 and intermediate layer patterns under the storage capacitor conductor patterns 64, respectively.

Subsequently, ashing removes photoresist residue remaining on the surface of the source / drain conductor pattern 67 of the channel portion C.

Next, as shown in FIGS. 15A and 15B, the conductive layer 760 of the channel portion C, the conductor pattern 67 for the source / drain, the conductive layer 650 and the intermediate layer pattern for the source / drain below 57) to be removed by etching. In this case, the etching may be performed only by dry etching on the conductive layers 760 and 650 and the source / drain conductor patterns 67 and the intermediate layer pattern 57, and the conductive layers 760 and 650 may be dry etching. For the source / drain conductor pattern 67, the wet pattern may be wet etching, and the intermediate layer pattern 57 may be dry etching. In the former case, it is preferable to perform etching under the condition that the etching selectivity of the conductive layers 650 and 760 and the source / drain conductor pattern 67 and the intermediate layer pattern 57 is large, which is the etching end point when the etching selectivity is not large. This is because it is difficult to find the thickness of the semiconductor pattern 42 remaining in the channel portion C because it is difficult to find. For example, those of etching the SF ₆ and O ₂ by using the mixed gas of the source / drain conductive pattern 67. In the latter case of alternating between wet etching and dry etching, the side surface of the conductive pattern 67 for wet etching of the source / drain is etched, but the intermediate layer pattern 57 which is dry etched is hardly etched, and thus is formed in a step shape. Examples of the etching gas used to etch the intermediate layer pattern 57 and the semiconductor pattern 42 include the aforementioned mixed gas of CF ₄ and HCl or mixed gas of CF ₄ and O ₂ , and CF ₄ and O _{Using 2} can leave the semiconductor pattern 42 in a uniform thickness. In this case, as shown in FIG. 15B, a portion of the semiconductor pattern 42 may be removed to reduce the thickness, and the second portion 112 of the photoresist pattern may also be etched to a certain thickness at this time. At this time, the etching should be performed under the condition that the gate insulating film 30 is not etched, and the photoresist film is not exposed so that the second portion 112 is etched so that the data lines 62, 64, 65, 66, and 68 underneath are not exposed. It is a matter of course that the pattern is thick.

In this way, the source electrode 65 and the drain electrode 66 are separated, thereby completing the data lines 62, 64, 65, 66, and 68 and the contact layer patterns 55, 56, and 58 under the data lines. At this time, the third and second low resistance layers 760 and 650 on the upper and lower portions of the data lines 62, 64, 65, 66 and 68 are also completed. As described in the first embodiment, the third and second The low resistance layers 760 and 650 are preferably patterned by dry etching.

Finally, the photosensitive film second portion 112 remaining in the data wiring portion A is removed. However, the removal of the second portion 112 may be made after removing the conductor pattern 67 for the channel portion C source / drain and before removing the intermediate layer pattern 57 thereunder.

As mentioned earlier, wet and dry etching can be alternately used or only dry etching can be used. In the latter case, since only one type of etching is used, the process is relatively easy, but it is difficult to find a suitable etching condition. On the other hand, in the former case, the etching conditions are relatively easy to find, but the process is more cumbersome than the latter.

After the data wirings 62, 64, 65, 66, and 68 are formed in this manner, as shown in FIGS. 16A to 16C, silicon nitride is deposited by CVD or spin-coated an organic insulating material to have a thickness of 3,000 3,000 or more. The protective film 70 is formed. Subsequently, the passivation layer 70 is etched together with the gate insulating layer 30 by using a third mask, and the upper portion of the drain electrode 66, the gate pad 24, the data pad 64, and the conductive pattern 68 for the storage capacitor is formed. Contact holes 71, 72, 73, and 74 are formed to expose the first and third low resistance layers 320 and 760, respectively.

Finally, as shown in FIGS. 11 to 13, the IZO layer having a thickness of 400 kHz to 500 kHz is deposited and etched using a fourth mask to drain the electrode 66 via the third low resistance layer 760. And the auxiliary gate pad 84 and the third low resistance layer 93 connected to the gate pad 24 via the pixel electrode 82 and the first low resistance layer 320 connected to the conductive pattern 64 for the storage capacitor. Auxiliary data pad 88 connected to the data pad 68 is formed through the.

In the second embodiment of the present invention, in addition to the effects according to the first embodiment, the data wirings 62, 64, 65, 66, 68 and the contact layer patterns 55, 56, 58 and semiconductor patterns (below) 42 and 48 may be formed using one mask, and the source electrode 65 and the drain electrode 66 may be separated in this process to simplify the manufacturing process.

In the embodiment of the present invention, in order to improve the contact characteristics between the aluminum-based metal and the IZO film, a low resistance layer including a low resistance layer including aluminum and silicon was formed therebetween. It is also possible to form a low-resistance layer containing another metal and silicon by forming a wiring with another metal such as chromium or molybdenum or molybdenum alloy. It is also possible to use other materials instead of silicon.

As described above, according to the present invention, a low resistance layer including metal and silicon is formed on the contact portion to secure the pad part reliability, and at the same time, the wiring is formed of aluminum or aluminum alloy of low resistance, thereby improving the characteristics of the product having a high resolution. You can. In addition, the manufacturing process may be simplified to manufacture a thin film transistor substrate for a liquid crystal display, thereby simplifying the manufacturing process and reducing the manufacturing cost.

Claims (14)

Forming a gate wiring, Forming a first low resistance layer including aluminum and silicon on the gate wiring; Forming a data line insulated from the gate line; Forming a second low resistance layer comprising aluminum and silicon on the data line; Forming a conductive layer electrically connected to the gate wiring or the data wiring via the first or second low resistance layer; Method of manufacturing a thin film transistor substrate comprising a. In claim 1, The gate wiring or the data wiring is formed of an aluminum-based conductive material manufacturing method of a thin film transistor substrate. In claim 1, And the conductive layer is formed of IZO, which is a transparent conductive material. In claim 1, The low resistance layer is formed by sputtering using a target containing aluminum and 1 to 10 at% or less silicon. delete delete In claim 1, Fabrication of a thin film transistor substrate further comprising forming a conductive film by sputtering using a buffer film containing chromium, molybdenum or molybdenum alloy or a target including aluminum and 1 to 30 at% or less of silicon below the data line. Way. A gate wiring formed on an insulating substrate, A first low resistance layer formed on the gate wiring and including aluminum and silicon; A gate insulating film covering the gate wiring, A semiconductor layer formed on the gate insulating film, A data line formed over the gate insulating film, A second low resistance layer formed on the data line and including aluminum and silicon; A protective film covering the data wiring, A transparent conductive film pattern electrically connected to the gate wiring or the data wiring via the first or second low resistance layer Thin film transistor substrate comprising a. In claim 8, The gate wiring and the data wiring include a thin film transistor substrate including an aluminum-based metal. In claim 9, The transparent conductive film pattern is a thin film transistor substrate made of IZO. In claim 10, The thin film transistor substrate further comprising an insulating layer formed between the first and second low resistance layers and the transparent conductive layer pattern, the insulating layer having contact holes exposing the first and second low resistance layers. In claim 11, The insulating film includes a gate insulating film formed on the gate wiring and a passivation film formed on the data wiring. In claim 12, The gate line includes a gate line extending in a horizontal direction, a gate electrode connected to the gate line, and a gate pad receiving a scan signal from the outside and transferring the scan signal to the gate line, The data line may include a data line extending in a vertical direction, a source electrode connected to the data line, a drain electrode separated from the source electrode and facing the source electrode around the gate electrode, and receiving image signals from the outside. A thin film transistor substrate comprising a data pad to transfer to the data line. In claim 10, And a third low resistance layer formed between the gate insulating film and the data line and formed of aluminum and silicon.

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