KR100375497B1 - A contact portion of a wirings and method manufacturing the same, and thin film transistor panel including the contact portion and method manufacturing the same - Google Patents

Abstract

First, a conductive material of aluminum or an aluminum alloy is stacked and patterned to form a horizontal gate wiring including a gate line, a gate electrode, and a gate pad on a substrate. Next, a gate insulating film is formed, and a semiconductor layer and an ohmic contact layer are sequentially formed thereon. Subsequently, a conductive layer including a lower layer of chromium and an upper layer of aluminum or an aluminum alloy is stacked and patterned to form a data line including a data line, a source electrode, a drain electrode, and a data pad crossing the gate line. Subsequently, a protective film is laminated and a heat treatment step is performed by annealing. At this time, the aluminum oxide film having high resistance and remaining on the gate wiring and the data wiring during the manufacturing process is removed. The protective film is then patterned to form contact holes that expose the drain electrode, gate pad and data pad. Next, the IZO is stacked and patterned to form a pixel electrode, an auxiliary gate pad, and an auxiliary data pad electrically connected to the drain electrode, the gate pad, and the data pad, respectively. By performing annealing to remove the aluminum oxide film having high resistance, the contact resistance including the aluminum and the IZO at the contact portion of the contact hole can be minimized even if they are in direct contact.

Description

A contact portion of a wiring, a method of manufacturing the same, and a thin film transistor substrate including the same and a method for manufacturing the same.

The present invention relates to a contact portion of a wiring, a method of manufacturing the same, a thin film transistor substrate including the same, and a method of manufacturing the same.

In general, the wiring in the semiconductor device is used as a means for transmitting a signal, it is required to minimize the signal delay.

In this case, in order to prevent signal delay, the wiring is generally made of a metal material having a low resistance, particularly an aluminum-based metal material such as aluminum (Al) or aluminum alloy (Al alloy). However, since aluminum-based wiring is weak in physical or chemical properties, corrosion occurs when connected to other conductive materials at the contact portion, thereby degrading the characteristics of the semiconductor device. In order to improve such contact characteristics, wiring may be interposed with other metals when forming an aluminum series. However, in order to form a multilayer wiring, not only different etching solutions are required but also multiple etching processes are required, which makes the manufacturing process complicated. .

On the other hand, the liquid crystal display device is one of the most widely used flat panel display devices, and consists of two substrates on which electrodes are formed and a liquid crystal layer inserted therebetween. The display device controls the amount of light transmitted by rearranging.

Among the liquid crystal display devices, a liquid crystal display device having a thin film transistor for forming an electrode on each of two substrates and switching a voltage applied to the electrode is generally used. The thin film transistor is generally formed on one of two substrates.

In such a liquid crystal display device, in order to prevent signal delay, the wiring generally uses a low resistance material such as aluminum (Al) or aluminum alloy (Al alloy) having a low resistance. However, in the case of forming a pixel electrode using ITO (indium tin oxide), which is a transparent conductive material as in a liquid crystal display device, or when securing the pad part reliability, an aluminum-based metal and ITO do not have good contact characteristics. Intervening with other metals, such as aluminum, or aluminum alloy in the contact portion has to be removed, so the manufacturing process is complicated.

On the other hand, in the manufacturing method of the liquid crystal display device, the substrate on which the thin film transistor is formed is generally manufactured through a photolithography process using a mask. At this time, it is preferable to reduce the number of masks in order to reduce the production cost.

It is an object of the present invention to provide a contact portion of a wiring having a low resistance contact characteristic and a method of manufacturing the same.

Another object of the present invention is to provide a thin film transistor substrate including a contact portion of a wiring having excellent contact characteristics and a method of manufacturing the same.

In addition, another object of the present invention is to simplify the manufacturing method of the thin film transistor substrate.

1 is a thin film transistor substrate for a liquid crystal display device according to a first embodiment of the present invention;

FIG. 2 is a cross-sectional view of the thin film transistor substrate illustrated in FIG. 1 taken along the line II-II.

3A, 4A, 5A, and 7A are layout views of a thin film transistor substrate illustrating an intermediate process of manufacturing a thin film transistor substrate for a liquid crystal display device according to a first embodiment of the present invention according to a process sequence thereof.

3B is a cross-sectional view taken along the line IIIb-IIIb ′ in FIG. 3A;

4B is a cross-sectional view taken along the line IVb-IVb ′ in FIG. 4A and is a cross-sectional view showing the next step in FIG. 3B;

FIG. 5B is a cross-sectional view taken along the line Vb-Vb ′ in FIG. 5A and is a cross-sectional view showing the next step in FIG. 4B;

FIG. 6 is a cross-sectional view taken along line Vb-Vb 'at 5a, and is a cross-sectional view showing the next step of FIG. 5b;

FIG. 7B is a cross-sectional view taken along the line VIIb-VIIb ′ of FIG. 7A and illustrating the next step of FIG. 6;

8 is a layout view of a thin film transistor substrate for a liquid crystal display according to a second exemplary embodiment of the present invention.

9 and 10 are cross-sectional views of the thin film transistor substrate illustrated in FIG. 8 taken along lines IX-IX 'and X-X',

11A is a layout view of a thin film transistor substrate at a first stage of manufacture in accordance with a second embodiment of the present invention,

11B and 11C are cross-sectional views taken along the lines XIb-XIb 'and XIc-XIc' of FIG. 12A, respectively.

12A and 12B are cross-sectional views taken along the lines XIb-XIb 'and XIc-XIc' of FIG. 11A, respectively, and are cross-sectional views of the next steps of FIGS. 11B and 11C;

FIG. 13A is a layout view of a thin film transistor substrate at a next step of FIGS. 12A and 12B;

13B and 13C are cross-sectional views taken along the lines XIIIb-XIIIb 'and XIIIc-XIIIc' of FIG. 13A, respectively.

14A, 15A, 16A and 14B, 15B, 16B are cross-sectional views taken along the lines XIIIb-XIIIb 'and XIIIc-XIIIc' in FIG. 13A, respectively, illustrating the following steps in the order of the process. ,

17A and 17B are cross-sectional views of a thin film transistor substrate in the next steps of FIGS. 16A and 16B,

18A is a layout view of a thin film transistor substrate at a next step of FIGS. 17A and 17B,

18B and 18C are cross-sectional views taken along the lines XVIIIb-XVIIIb 'and XVIIIc-XVIIIc' in FIG. 18A, respectively;

19 and 20 are photographs showing a wiring structure of an Al-Nd metal film according to whether annealing is performed in a manufacturing method according to an embodiment of the present invention through a transmission electron microscope (TEM),

21A to 21C are photographs illustrating a surface of an Al-Nd metal film through a transmission electron microscope (TEM) in a method of manufacturing a thin film transistor substrate according to an exemplary embodiment of the present invention.

In order to solve this problem, in the present invention, after performing a heat treatment process by annealing, a conductive layer of IZO connected to a wiring including aluminum is laminated.

In the manufacturing method of the contact part of the wiring which concerns on this invention, metal wiring is formed first on a board | substrate, and the inorganic insulating film which covers wiring is laminated | stacked. Subsequently, after performing a heat treatment process, the inorganic insulating layer is patterned to form contact holes for exposing the wiring, and a conductive layer electrically connected to the wiring is formed.

At this time, the heat treatment process is carried out by annealing (annealing), the annealing is preferably carried out in the temperature range of 250 ~ 400 ℃.

Here, the wiring is preferably formed of an aluminum-based conductive material, and the inorganic insulating film is preferably formed of silicon nitride. At this time, the inorganic insulating film is preferably laminated in a temperature range of 250 ~ 400 ℃.

The conductive layer may be a transparent conductive material, may be formed of IZO, and may be formed in a range of 250 ° C. or less.

The contact portion of the wiring and the method of forming the same can be applied to the thin film transistor substrate and the manufacturing method thereof.

First, gate wirings, data wirings, and semiconductor layers are formed, and an insulating film covering them is formed. Next, a heat treatment process is performed and the insulating film is patterned to form contact holes that expose the gate wiring or the data wiring. Next, a transparent conductive layer electrically connected to the gate wiring or the data wiring is formed through the contact hole.

In this case, the gate wiring and the data wiring are preferably formed by including a conductive material of aluminum or aluminum alloy, and the insulating film is preferably formed of silicon nitride.

It is preferable to form an insulating film in the 250-400 degreeC temperature range, and heat processing process is preferable to perform annealing in the 250-400 degreeC temperature range.

The transparent conductive layer may be formed of IZO, and in this case, the IZO may be laminated in a range of 250 ° C. or less.

In more detail, a first conductive material is stacked and patterned on an insulating substrate to form a gate wiring including a gate line and a gate electrode connected to the gate line, and a gate insulating layer is stacked. Subsequently, a semiconductor layer is formed on the gate insulating layer, and a second conductive material is stacked and patterned on the gate insulating layer, and the source electrode is connected to the data line crossing the gate line, the source electrode connected to the data line, and adjacent to the gate electrode. A data line is formed that includes the drain electrode positioned opposite to the side of the substrate. Next, a protective film is laminated and a heat treatment step is performed. Subsequently, the passivation layer is patterned to form a first contact hole exposing the drain electrode, and a pixel electrode electrically connected to the drain electrode is formed on the passivation layer.

Here, the heat treatment step is preferably carried out by annealing at a temperature range of 250 ~ 400 ℃, it is preferable that the first and second conductive material comprises a metal of aluminum or aluminum alloy.

In addition, the gate insulating film and the protective film stacking step is preferably formed in the range of 250 ~ 400 ℃, the gate insulating film and the protective film is preferably formed of silicon nitride.

The pixel electrode may be formed of a transparent conductive material, and the pixel electrode may be formed of IZO.

The gate wiring further includes a gate pad connected to the gate line, the data wiring further includes a data pad connected to the data line, and the passivation layer together with the data pad and the gate insulating layer exposes the second and third gate pads. The auxiliary gate pad and the auxiliary data pad may be further formed on the same layer as the pixel electrode and electrically connected to the gate pad and the data pad through the second and third contact holes.

The data line and the semiconductor layer may be formed together by a photolithography process using a photoresist pattern having a different thickness, and the photoresist pattern may include a first part having a first thickness, a second part thicker than the first thickness, and a first thickness. It is preferred to include a third portion which is thin and excludes the first and second portions.

In the photolithography process, the photoresist pattern may be formed using an optical mask including a first region, a second region having a lower transmittance than the first region, and a third region having a higher transmittance than the first region. In the etching process, the first portion is preferably formed between the source electrode and the drain electrode, and the second portion is positioned above the data line.

In order to control the transmittance of the first to third regions differently, a slit pattern smaller than the resolution of the translucent film or the exposure machine may be formed in the photomask, and the thickness of the first portion is 1/2 or less with respect to the thickness of the second portion. It is preferable to form.

The method may further include forming an ohmic contact layer between the semiconductor layer and the data line, and the data line, the contact layer, and the semiconductor layer may be formed using one mask.

Here, the contact hole may be formed in a shape or circle having an angle, and the area of the first contact hole does not exceed 10 μm × 10 μm, and preferably 4 μm × 4 μm or more.

In this case, the conductive film including the aluminum film and the IZO are in direct contact with the contact hole, and the conductive film including the aluminum film may have a flat surface.

Then, a person having ordinary knowledge in the technical field to which the present invention pertains to a contact portion of a wiring according to an embodiment of the present invention, a manufacturing method thereof, a thin film transistor substrate including the same, and a manufacturing method thereof will be described with reference to the accompanying drawings. It will be described in detail so that you can carry out.

As a semiconductor device, particularly a wiring for transmitting a signal, an aluminum-based metal material having a low resistivity of 15 μΩcm or less is suitable to minimize signal delay. In this case, the wiring should be connected to another conductive layer in order to receive a signal from the outside or to transmit a signal to the outside, and should not be easily corroded when contacted with other conductive materials in the manufacturing process. To this end, in the method for manufacturing a contact structure of a wiring according to an embodiment of the present invention, first, a wiring made of a metal layer made of aluminum or an aluminum alloy having low resistance is formed on a substrate, and an inorganic insulating film covering the wiring is laminated. Subsequently, the heat treatment process is performed by annealing. Through the heat treatment process, the aluminum oxide layer having high resistance and remaining on the aluminum-based metal layer may be removed. Subsequently, the inorganic insulating film is patterned to form a contact hole in the upper portion of the wiring, and to form a conductive layer directly connected to the wiring through the contact hole.

In addition, the annealing process is preferably carried out for 30 minutes to 2 hours in the 250 ~ 400 ℃ temperature range, the insulating film is preferably laminated in a temperature range of about 250 ~ 400 ℃.

In addition, the inorganic insulating film is preferably silicon nitride, the conductive layer may be formed of a transparent conductive material, it is preferable that the indium zinc oxide (IZO).

In this annealing process, a high resistance residual layer such as aluminum oxide film (Al ₂ O ₃ ) formed in the manufacturing process on the wiring of aluminum or aluminum alloy is removed, so that the contact portion is in direct contact with the IZO and the aluminum film. Therefore, by performing annealing and using the conductive layer as the IZO, the contact resistance between the wiring including aluminum and the IZO can be minimized, and corrosion can be prevented from occurring at the contact portion.

The contact portion of the wiring may be used as a gate wiring or a data wiring of a thin film transistor for a liquid crystal display device.

Next, a thin film transistor substrate and a manufacturing method for a liquid crystal display including the contact portion of the wiring according to the present invention will be described in detail with reference to the drawings.

First, a structure of a thin film transistor substrate for a liquid crystal display according to a first embodiment of the present invention will be described in detail with reference to FIGS. 1 and 2.

1 is a thin film transistor substrate for a liquid crystal display device according to a first embodiment of the present invention, and FIG. 2 is a cross-sectional view of the thin film transistor substrate shown in FIG. 1 taken along the line II-II.

A gate wiring made of a metal material of aluminum or aluminum alloy having low resistance is formed on the insulating substrate 10. The gate wire is connected to the gate line 22 and the gate line 22 extending in the horizontal direction, and are connected to the gate pad 24 and the gate line 22 which receive a gate signal from the outside and transmit the gate signal to the gate line. A gate electrode 26 of the thin film transistor.

On the substrate 10, a gate insulating film 30 made of silicon nitride (SiN _x ) covers the gate wirings 22, 24, and 26.

A semiconductor layer 40 made of a semiconductor such as amorphous silicon is formed on the gate insulating film 30 of the gate electrode 24 in an island shape, and silicide or n-type impurities are doped with high concentration on the semiconductor layer 40. Resistive contact layers 55 and 56 made of a material such as n + hydrogenated amorphous silicon are formed, respectively.

On the resistive contact layers 55 and 56 and the gate insulating layer 30, aluminum (Al) or aluminum alloy (Al alloy), molybdenum (Mo) or molybdenum-tungsten (MoW) alloy, chromium (Cr), tantalum (Ta), A data wiring made of a metal such as titanium (Ti) or a conductor is formed. The data line is formed in the vertical direction and crosses the gate line 22 to define a pixel, and the data line 62 is a branch of the data line 62 and the source electrode 65 extending to the upper portion of the ohmic contact layer 55. ), Which is connected to one end of the data line 62 and is separated from the data pad 68 and the source electrode 65 to which an image signal from the outside is applied, and is opposite to the source electrode 65 with respect to the gate electrode 26. And a drain electrode 66 formed on the ohmic contact layer 56.

The data lines 62, 65, 66, and 68 are preferably formed of a single film of aluminum series, but may be formed of two or more layers. In the case of forming more than two layers, it is preferable that one layer is made of a material having a low resistance and the other layer is made of a material having good contact properties with other materials. Examples thereof include Cr / Al (or Al alloy) or Al / Mo. In the exemplary embodiment of the present invention, the data lines 62, 65, 66, and 68 may be formed of the lower layer 601 of Cr and the aluminum alloy. The upper film 602 is formed.

The passivation layer 70 made of silicon nitride is formed on the data lines 62, 65, 66, and 68 and the semiconductor layer 40 which is not covered.

In the passivation layer 70, contact holes 76 and 78 are formed to expose the drain electrode 66 and the data pad 68, respectively. The contact hole 74 exposing the gate pad 24 together with the gate insulating layer 30 is formed. Is formed. At this time, the contact holes 74, 76, 78 may be formed in a variety of angles or circular shape, the contact hole 76, which exposes the area of the contact hole, in particular the drain electrode 66 is 10㎛ 10㎛ It is preferable not to exceed 4 mu m x 4 mu m or more, and the other contact holes 74 and 78 are preferably formed larger than the contact hole 76.

On the passivation layer 70, a pixel electrode 82 electrically connected to the drain electrode 66 and positioned in the pixel is formed through the contact hole 76. In addition, the auxiliary gate pad 86 and the auxiliary data pad 88, which are connected to the gate pad 24 and the data pad 68, respectively, are formed on the passivation layer 70 through the contact holes 74 and 78. Here, the pixel electrode 82, the auxiliary gates, and the data pads 86 and 88 are made of indium zinc oxide (IZO). At this time, in the structure of the present invention, the metal films 24, 66, 68 containing aluminum and the IZO films 82, 86, 88 are in direct contact with the contact portions of the contact holes 74, 76, 78. In such a contact structure, corrosion does not occur between the metal films 24, 66 and 68 including aluminum and the IZO films 82, 86 and 88, and impurities are removed from the contacts because the impurities have high resistance therebetween. This decreases.

1 and 2, the pixel electrode 82 overlaps with the gate line 22 to form a storage capacitor. When the storage capacitor is insufficient, the pixel electrode 82 is disposed on the same layer as the gate wirings 22, 24, and 26. It is also possible to add a storage capacitor wiring.

In the structure according to the exemplary embodiment of the present invention, the gate wirings 22, 24, 26 and the data wirings 62, 64, 66, and 68 include aluminum or an aluminum alloy having low resistance, so that a liquid crystal display having a high screen resolution is possible. Applicable to the device.

In addition, the aluminum-based metal of the gate pad 24, the data pad 68, and the drain electrode 66 is directly in contact with the IZO of the auxiliary gate pad 86, the auxiliary data pad 88, and the pixel electrode 82. The contact resistance at the contact portion can be minimized, and the aluminum-based metal can be prevented from being corroded, thereby ensuring the reliability of the contact portion including the pad portion.

Next, a method of manufacturing the thin film transistor substrate for a liquid crystal display according to the first embodiment of the present invention will be described in detail with reference to FIGS. 1 and 2 and FIGS. 3A to 7B.

First, as shown in FIGS. 3A and 3B, a thickness of about 2,500 mW is used by using a target including Al-Nd containing 2 at% of Nd among aluminum or an aluminum alloy having low resistance on the substrate 10. And sputtering at about 150 ° C. and patterned to form a gate wiring including the gate line 22, the gate electrode 26, and the gate pad 24.

Next, as shown in FIGS. 4A and 4B, a three-layer film of a gate insulating film 30 made of silicon nitride, a semiconductor layer 40 made of amorphous silicon, and a doped amorphous silicon layer 50 is successively laminated, and a mask is formed. The semiconductor layer 40 and the ohmic contact layer 50 are formed on the gate insulating layer 30 facing the gate electrode 24 by patterning the semiconductor layer 40 and the doped amorphous silicon layer 50 by the patterning process. do. Here, the gate insulating film 30 is preferably formed by laminating silicon nitride to a thickness of about 2,000 to 5,000 Pa, in a temperature range of 250 to 400 ° C. In the embodiment of the present invention, the gate insulating film 30 is laminated to a thickness of about 4,500 kPa at a temperature of about 300 ℃.

Next, as shown in FIGS. 5A to 5B, a lower film 601 made of molybdenum, molybdenum alloy, chromium, or the like is about 500 GPa thick, and Nd of 2 at% of aluminum or aluminum alloy having low resistance is obtained. The upper layer 602 was sequentially stacked by sputtering to a thickness of about 2,500 에서 at a temperature of about 150 ° C. by using a target of Al-Nd, and then patterned by a photo process using a mask to form a gate line 22. A data line 62 intersecting with the data line 62, a source electrode 65 connected to the data line 62 and extending to an upper portion of the gate electrode 26, a data pad 68 connected to one end thereof; A data line separated from the source electrode 64 and including the drain electrode 66 facing the source electrode 65 is formed around the gate electrode 26. Here, both the upper layer 602 and the lower layer 601 may be etched by wet etching, the upper layer 602 may be etched by wet etching, and the lower layer 601 may be etched by dry etching.

Subsequently, the doped amorphous silicon layer pattern 50, which is not covered by the data lines 62, 65, 66, and 68, is etched and separated on both sides of the gate electrode 26, while both doped amorphous silicon layers ( The semiconductor layer pattern 40 between 55 and 56 is exposed. Subsequently, in order to stabilize the surface of the exposed semiconductor layer 40, it is preferable to perform oxygen plasma.

Next, as shown in FIG. 6, an inorganic insulating film such as silicon nitride is laminated in the range of 250 to 400 ° C. to form a protective film 70, and annealing is performed in the range of 250 to 400 ° C. for 30 minutes to 2 hours. do. In the embodiment of the present invention, the protective film 70 is preferably laminated at a thickness of about 2,000 to 3,000 Pa at about 300 ° C., and then annealed at about 300 ° C., and the annealing is performed for about 30 minutes to 1 hour. In the annealing process, the residual layer of high resistance formed on the upper surface of the aluminum metal of the wirings 22, 24, 26, 62, 65, 66, and 68 at the manufacturing process can be removed in the process of annealing. For example, on the surface of the aluminum-based metal, oxygen in the air and aluminum in the metal film react with each other to form a residual film including Al ₂ O ₃ , which is removed by annealing. This will be described in detail with reference to FIGS. 19 and 20. In addition, in the embodiment of the present invention, alkaline or electrolyte cleaning is performed to remove organic materials or residual materials such as Al ₂ O ₃ or the like on top of the data lines 62, 65, 66, and 68 before stacking the protective layer 70. It is preferable to carry out, and may be performed using an aluminum etchant for etching the material containing aluminum.

7A and 7B, the passivation layer 70 is patterned by dry etching together with the gate insulating layer 30 by a photolithography process using a mask to form the gate pad 24, the drain electrode 66, and the like. Contact holes 74, 76, and 78 are formed to expose the data pads 68, respectively. Here, when forming the contact holes 74, 76, and 78, the etching condition may preferably be a condition in which an aluminum-based metal film is not etched. An F-based gas may be used as the etching gas. At this time, the contact holes 74, 76 and 78 may be formed in an angled shape or a circular shape, and the contact hole 76 exposing the area of the contact hole, particularly the drain electrode 66, may be 10 μm × 10 μm. It is preferable not to exceed 4 mu m x 4 mu m or more, which will be described later. Of course, the contact holes 74 and 78 exposing the gate pad 24 and the data pad 68 may be formed larger than the contact holes 76.

Next, as shown in FIGS. 1 and 2, the IZO film is laminated by sputtering and patterned using a mask to contact the pixel electrode 82 and the contact hole connected to the drain electrode 66 through the contact hole 76. An auxiliary gate pad 86 and an auxiliary data pad 88 connected to the gate pad 24 and the data pad 68, respectively, are formed through 74 and 78. In this case, in the manufacturing method of the present invention, annealing is performed before the protective film 70 is patterned to remove the high-resistance residual film on the aluminum-based metal film 24, 66, 68, thereby contacting the holes 74, 76, and 78. At the contact portion of the metal film (24, 66, 68) containing aluminum and the IZO film (82, 86, 88) is in direct contact. In such a contact structure, corrosion does not occur between the metal films 24, 66 and 68 including aluminum and the IZO films 82, 86 and 88, and impurities are removed from the contacts because the impurities have high resistance therebetween. This decreases. In the exemplary embodiment of the present invention, a target for forming the IZO films 82, 86, and 88 is a product called indium x-metal oxide (IDIXO) manufactured by Imitsu, and the target is In ₂ O ₃ and ZnO is included, and the content of Zn is preferably in the range of 15-20 at%. In addition, in order to minimize contact resistance, the IZO film is preferably laminated in the range of 250 ° C or lower.

In the manufacturing method according to the exemplary embodiment of the present invention, before the lamination of the IZO film, a heat treatment process is performed to improve the contact property between the IZO and the aluminum-based metal, thereby minimizing the contact resistance of the contact part including the pad part to secure reliability of the contact part. can do.

As described above, the method can be applied to a manufacturing method using five masks, but the same method can be applied to a manufacturing method of a thin film transistor substrate for a liquid crystal display device using four masks. This will be described in detail with reference to the drawings.

First, a unit pixel structure of a thin film transistor substrate for a liquid crystal display device completed using four masks according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 8 to 10.

8 is a layout view of a thin film transistor substrate for a liquid crystal display according to a second exemplary embodiment of the present invention, and FIGS. 9 and 10 are along the IX-IX 'and XX' lines of the thin film transistor substrate shown in FIG. It is sectional drawing cut out.

First, a gate line including a gate line 22, a gate pad 24, and a gate electrode 26 made of an aluminum-based metal is formed on the insulating substrate 10 as in the first embodiment. The gate wiring includes a sustain electrode 28 that is parallel to the gate line 22 on the substrate 10 and receives a voltage such as a common electrode voltage input to the common electrode of the upper plate from the outside. The storage electrode 28 overlaps with the conductive pattern 64 for the storage capacitor connected to the pixel electrode 82 to be described later to form a storage capacitor which improves the charge retention capability of the pixel. The pixel electrode 82 and the gate line to be described later will be described. If the holding capacity generated by the overlap of (22) is sufficient, it may not be formed.

A gate insulating film 30 made of silicon nitride (SiN _x ) is formed on the gate wirings 22, 24, 26, and 28 to cover the gate wirings 22, 24, 26, and 28.

Semiconductor patterns 42 and 48 made of semiconductors such as hydrogenated amorphous silicon are formed on the gate insulating layer 30, and high concentrations of n-type impurities such as phosphorus (P) are formed on the semiconductor patterns 42 and 48. An ohmic contact layer pattern or an intermediate layer pattern 55, 56, 58 made of amorphous silicon doped with is formed.

On the ohmic contact layer patterns 55, 56, and 58, a data line made of a conductive material of aluminum or an aluminum alloy having low resistance is formed. The data line is a thin film transistor which is a branch of the data line 62 formed in the vertical direction, the data pad 68 connected to one end of the data line 62 to receive an image signal from the outside, and the data line 62. And a data line portion of the source electrode 65 of the source electrode 65. The data line portion is separated from the data line portions 62, 68, and 65, and the source electrode 65 is separated from the gate electrode 26 or the channel portion C of the thin film transistor. It also includes a conductive capacitor conductor 64 for the storage capacitor located on the drain electrode 66 and the storage electrode 28 of the thin film transistor located on the opposite side. When the sustain electrode 28 is not formed, the conductor pattern 64 for the storage capacitor is also not formed.

The data lines 62, 64, 65, 66, 68 may also be formed of a single layer made of a metal of aluminum or an aluminum alloy like the gate lines 22, 24, 26, 28, but the same as in the first embodiment. It may be formed from a double film including a lower film made of chromium or molybdenum or molybdenum alloy or tantalum or titanium and an upper film made of metal of aluminum or aluminum alloy.

The contact layer patterns 55, 56, and 58 lower the contact resistance between the semiconductor patterns 42 and 48 below and the data lines 62, 64, 65, 66, and 68 above the data layer. It has exactly the same form as (62, 64, 65, 66, 68). That is, the data line part intermediate layer pattern 55 is the same as the data line parts 62, 68, and 65, the drain electrode intermediate layer pattern 56 is the same as the drain electrode 66, and the storage capacitor intermediate layer pattern 58 is It is the same as the conductor pattern 64 for holding capacitors.

The semiconductor patterns 42 and 48 have the same shape as the data lines 62, 64, 65, 66, and 68 and the ohmic contact layer patterns 55, 56, and 58 except for the channel portion C of the thin film transistor. Doing. Specifically, the semiconductor capacitor 48 for the storage capacitor, the conductor pattern 64 for the storage capacitor, and the contact layer pattern 58 for the storage capacitor have the same shape, but the semiconductor pattern 42 for the thin film transistor has data wiring and contact. Slightly different from the rest of the layer pattern. That is, in the channel portion C of the thin film transistor, the data line portions 62, 68, and 65, in particular, the source electrode 65 and the drain electrode 66 are separated, and the contact layer pattern for the data line intermediate layer 55 and the drain electrode. Although 56 is also separated, the semiconductor pattern 42 for thin film transistors is not disconnected here and is connected to generate a channel of the thin film transistor.

A protective film 70 made of silicon nitride is formed on the data lines 62, 64, 65, 66, and 68.

The protective film 70 has contact holes 76, 78, and 72 that expose the drain electrode 66, the data pad 68, and the conductive pattern 64 for the storage capacitor, and also the gate along with the gate insulating film 30. It has a contact hole 74 which exposes the pad 24.

On the passivation layer 70, a pixel electrode 82 that receives an image signal from a thin film transistor and generates an electric field together with the electrode of the upper plate is formed. The pixel electrode 82 is made of a transparent conductive material such as indium tin oxide (IZO), and is physically and electrically connected to the drain electrode 66 through the contact hole 76 to receive an image signal. The pixel electrode 82 also overlaps with the neighboring gate line 22 and the data line 62 to increase the aperture ratio, but may not overlap. In addition, the pixel electrode 82 is also connected to the storage capacitor conductor pattern 64 through the contact hole 72 to transmit an image signal to the conductor pattern 64. On the other hand, an auxiliary gate pad 86 and an auxiliary data pad 88 connected to the gate pad 24 and the data pad 68 through the contact holes 74 and 78, respectively, are formed. 68) and to protect the pads and the adhesion of the external circuit device, and is not essential, their application is optional.

Although the transparent IZO is mentioned as an example of the material of the pixel electrode 82, it may be formed of a transparent conductive polymer or the like. In the case of a reflective liquid crystal display, an opaque conductive material may be used.

Next, a method of manufacturing a thin film transistor substrate for a liquid crystal display device having the structure of FIGS. 8 to 10 using four masks will be described in detail with reference to FIGS. 8 to 10 and FIGS. 11A to 18C. .

First, as shown in FIGS. 11A to 11C, the gate line 22, the gate pad 24, and the gate electrode 26 are formed on the substrate 10 by a photolithography process using a first mask as in the first embodiment. And a sustain electrode 28 to form a gate wiring made of an aluminum-based metal having low resistance.

Next, as shown in FIGS. 12A and 12B, the gate insulating film 30, the semiconductor layer 40, and the intermediate layer 50 made of silicon nitride are respectively 1,500 kV to 5,000 kPa and 500 kPa to 2,000 using chemical vapor deposition. 증착, 300 600 to 600 연속 continuously deposited, and then a conductor layer 60 including an upper layer and a lower layer made of chromium with an aluminum-based metal having a low resistance, may be spun from 1,500 1 to 3,000 Å After the deposition to a thickness of the photosensitive film 110 is applied thereon to a thickness of 1 μm to 2 μm. At this time, the gate insulating film 30 is preferably laminated in the range of 250 ~ 400 ℃, in the embodiment of the present invention was formed to a thickness of about 4,500 kPa at a temperature of about 300 ℃.

Thereafter, the photoresist film 110 is irradiated with light through a second mask and then developed to form photoresist patterns 112 and 114 as illustrated in FIGS. 13B and 13C. In this case, among the photoresist patterns 112 and 114, the channel portion C of the thin film transistor, that is, the first portion 114 positioned between the source electrode 65 and the drain electrode 66, is the data wiring portion A, that is, the data. The thickness of the wirings 62, 64, 65, 66, and 68 is smaller than that of the second portion 112 positioned at the portion where the wirings 62, 64, 65, 66, and 68 are to be formed, and all the photoresist of the other portion B is removed. At this time, the ratio of the thickness of the photoresist film 114 remaining in the channel portion C to the thickness of the photoresist film 112 remaining in the data wiring portion A should be different depending on the process conditions in the etching process described later. It is preferable to make the thickness of the 1st part 114 into 1/2 or less of the thickness of the 2nd part 112, for example, it is good that it is 4,000 Pa or less.

As such, there may be various methods of varying the thickness of the photoresist layer according to the position. In order to control the light transmittance in the A region, a slit or lattice-shaped pattern is mainly formed or a translucent film is used.

In this case, the line width of the pattern located between the slits, or the interval between the patterns, that is, the width of the slits, is preferably smaller than the resolution of the exposure apparatus used for exposure. A thin film having a thickness or a thin film may be used.

When the light is irradiated to the photosensitive film through such a mask, the polymers are completely decomposed at the part directly exposed to the light, and the polymers are not completely decomposed because the amount of light is small at the part where the slit pattern or the translucent film is formed. In the area covered by, the polymer is hardly decomposed. Subsequently, when the photoresist film is developed, only a portion where the polymer molecules are not decomposed is left, and a thin photoresist film may be left at a portion where the light is not irradiated at a portion less irradiated with light. In this case, if the exposure time is extended, all molecules are decomposed, so it should not be so.

The thin film 114 is formed by using a photoresist film made of a reflowable material, and is exposed to a conventional mask that is divided into a part that can completely transmit light and a part that cannot fully transmit light, and then develops and ripples. It can also be formed by letting a part of the photosensitive film flow to the part which does not remain by making it low.

Subsequently, etching is performed on the photoresist pattern 114 and the underlying layers, that is, the conductor layer 60, the intermediate layer 50, and the semiconductor layer 40. In this case, the data line and the lower layer of the data line remain in the data wiring portion A, and only the semiconductor layer should remain in the channel portion C, and the upper three layers 60, 50, 40 must be removed to expose the gate insulating film 30.

First, as shown in FIGS. 14A and 14B, the exposed conductor layer 60 of the other portion B is removed to expose the lower intermediate layer 50. In this process, both a dry etching method and a wet etching method may be used. In this case, the conductor layer 60 may be etched and the photoresist patterns 112 and 114 may be hardly etched. However, in the case of dry etching, it is difficult to find a condition in which only the conductor layer 60 is etched and the photoresist patterns 112 and 114 are not etched, so that the photoresist patterns 112 and 114 may also be etched together. In this case, the thickness of the first portion 114 is thicker than that of the wet etching so that the first portion 114 is removed in this process so that the lower conductive layer 60 is not exposed.

When the conductor layer 60 is any one of Mo or MoW alloy, Al or Al alloy, and Ta, either dry etching or wet etching can be used. However, since Cr is not easily removed by the dry etching method, it is preferable to use only wet etching if the conductor layer 60 is Cr. In the case of wet etching in which the conductor layer 60 is Cr, CeNHO ₃ may be used as an etchant. In the case of dry etching in which the conductor layer 60 is Mo or MoW, the mixed gas or CF of CF ₄ and HCl may be used as the etching gas. A mixed gas of ₄ and O ₂ can be used, and the latter has almost the same etching ratio to the photoresist film.

In this way, as shown in Figs. 14A and 14B, only the conductor layer of the channel portion C and the data wiring portion B, that is, the conductor pattern 67 for the source / drain and the conductor pattern 64 for the storage capacitor All of the conductor layer 60 of the remaining portion B is removed, revealing the underlying intermediate layer 50. The remaining conductor patterns 67 and 64 have the same shape as the data lines 62, 64, 65, 66 and 68 except that the source and drain electrodes 65 and 66 are connected without being separated. In addition, when dry etching is used, the photoresist patterns 112 and 114 are also etched to a certain thickness.

Subsequently, as shown in FIGS. 15A and 15B, the exposed intermediate layer 50 of the other portion B and the semiconductor layer 40 below it are simultaneously removed together with the first portion 114 of the photosensitive film by a dry etching method. do. At this time, etching is performed under the condition that the photoresist patterns 112 and 114, the intermediate layer 50, and the semiconductor layer 40 (the semiconductor layer and the intermediate layer have almost no etching selectivity) are simultaneously etched, and the gate insulating layer 30 is not etched. In particular, it is preferable to etch under conditions in which the etch ratios of the photoresist patterns 112 and 114 and the semiconductor layer 40 are almost the same. For example, by using a mixed gas of SF ₆ and HCl or a mixed gas of SF ₆ and O ₂ , the two films can be etched to almost the same thickness. When the etching ratios of the photoresist patterns 112 and 114 and the semiconductor layer 40 are the same, the thickness of the first portion 114 should be equal to or smaller than the sum of the thicknesses of the semiconductor layer 40 and the intermediate layer 50.

This removes the first portion 114 of the channel portion C, revealing the source / drain conductor pattern 67, as shown in FIGS. 15A and 15B, and the intermediate layer 50 of the other portion B. And the semiconductor layer 40 is removed to expose the gate insulating layer 30 thereunder. On the other hand, since the second portion 112 of the data wiring portion A is also etched, the thickness becomes thin. In this step, the semiconductor patterns 42 and 48 are completed. Reference numerals 57 and 58 denote intermediate layer patterns under the source / drain conductor patterns 67 and intermediate layer patterns under the storage capacitor conductor patterns 64, respectively.

Subsequently, ashing removes photoresist residue remaining on the surface of the source / drain conductor pattern 67 of the channel portion C.

Next, as shown in FIGS. 16A and 16B, the source / drain conductor pattern 67 of the channel part C and the source / drain interlayer pattern 57 below are etched and removed. In this case, the etching may be performed only by dry etching with respect to both the source / drain conductor pattern 67 and the intermediate layer pattern 57. The etching may be performed by wet etching on the source / drain conductor pattern 67. 57 may be performed by dry etching. In the former case, it is preferable to perform etching under a condition in which the etching selectivity of the source / drain conductor pattern 67 and the interlayer pattern 57 is large, which is difficult to find the etching end point when the etching selectivity is not large. This is because it is not easy to adjust the thickness of the semiconductor pattern 42 remaining in the " For example, those of etching the SF ₆ and O ₂ by using the mixed gas of the source / drain conductive pattern 67. In the latter case of alternating between wet etching and dry etching, the side surface of the conductive pattern 67 for wet etching of the source / drain is etched, but the intermediate layer pattern 57 which is dry etched is hardly etched, and thus is formed in a step shape. Examples of the etching gas used to etch the intermediate layer pattern 57 and the semiconductor pattern 42 include the aforementioned mixed gas of CF ₄ and HCl or mixed gas of CF ₄ and O ₂ , and CF ₄ and O _{Using 2} can leave the semiconductor pattern 42 in a uniform thickness. In this case, as shown in FIG. 15B, a portion of the semiconductor pattern 42 may be removed to reduce the thickness, and the second portion 112 of the photoresist pattern may also be etched to a certain thickness at this time. At this time, the etching must be performed under the condition that the gate insulating film 30 is not etched, and the photoresist film is not exposed so that the second portion 112 is etched so that the data lines 62, 64, 65, 66, and 68 underneath are not exposed. It is a matter of course that the pattern is thick.

In this way, the source electrode 65 and the drain electrode 66 are separated, thereby completing the data lines 62, 64, 65, 66, and 68 and the contact layer patterns 55, 56, and 58 under the data lines.

Finally, the second photoresist layer 112 remaining in the data wiring portion A is removed. However, the removal of the second portion 112 may be made after removing the conductor pattern 67 for the channel portion C source / drain and before removing the intermediate layer pattern 57 thereunder.

As mentioned earlier, wet and dry etching can be alternately used or only dry etching can be used. In the latter case, since only one type of etching is used, the process is relatively easy, but it is difficult to find a suitable etching condition. On the other hand, in the former case, the etching conditions are relatively easy to find, but the process is more cumbersome than the latter.

After the data wirings 62, 64, 65, 66, and 68 were formed in this manner, as shown in FIGS. 17A and 17B, silicon nitride was deposited in the range of 250 to 400 DEG C by the CVD method as shown in the first embodiment. The protective film 70 is formed. Subsequently, as in the first embodiment, a heat treatment process is performed through annealing in the range of 250 ° C. to 400 ° C., so that the gate wirings 22, 24, 26, and 28 and the data wirings 62, 64, 65, 66, and 68 are disposed on the upper portion. Remove the remaining residual film. Also in this case, it is preferable to add a cleaning process to remove the organic material or the residual material before the protective film 70 is laminated.

18A to 18C, the protective film 70 is etched together with the gate insulating film 30 using the third mask, and the drain electrode 66 and the gate pad 24, as in the first embodiment, are etched. Contact holes 76, 74, 78, 72 exposing the data pads 68 and the conductor pattern 64 for the storage capacitor, respectively.

Finally, as shown in FIGS. 8 to 10, in the same manner as in the first embodiment, an IZO layer having a thickness of 400 mW to 500 mW is deposited by a sputtering method and etched using a fourth mask to drain the drain electrode 66. And a pixel electrode 82 connected to the conductive capacitor 64 for the storage capacitor, an auxiliary gate pad 86 connected to the gate pad 24, and an auxiliary data pad 88 connected to the data pad 68. In this case, the pixel electrode 82, the auxiliary gate pad 86, and the auxiliary data pad 88 may be formed of ITO, but an etchant for patterning the ITO may corrode aluminum metal. However, the etchant for patterning IZO uses a chromium etchant that is used to etch a metal film of chromium (Cr), which does not corrode aluminum and thus prevents the data or gate wiring from corroding. ₃ / (NH ₄ ) ₂ Ce (NO ₃ ) ₆ / H ₂ O), and the like.

In the second embodiment of the present invention, the data wirings 62, 64, 65, 66, and 68 and the contact layer patterns 55, 56, 58 and the semiconductor pattern 42 below the data wirings 62, 64, 65, 66, and 68, as well as the effects of the first embodiment. , 48) may be formed using one mask, and the source electrode 65 and the drain electrode 66 may be separated in this process to simplify the manufacturing process.

As described above, it will be described in detail with reference to the drawings that the residual film formed during the manufacturing process is removed from the upper part of the metal film including aluminum through annealing.

19 and 20 are photographs showing a wiring structure of an Al-Nd metal film according to whether annealing is performed in a manufacturing method according to an embodiment of the present invention through a transmission electron microscope (TEM). 19 is a case where annealing process is not performed, and FIG. 20 is sectional drawing which performed the annealing process.

19 and 20 are stacked at 150 ° C by sputtering method using a target Al-Nd containing 2 at% of Nd in accordance with a manufacturing method according to an embodiment of the present invention to laminate a metal film 600, the metal The protective film 700 covering the film 600 shows a case where silicon nitride is laminated at about 300 ° C. On the other hand, Figure 20 shows the case of annealing for 30 minutes at about 300 ℃.

As shown in FIG. 19, when the annealing is not performed, it can be seen that a residual film 800 including Al ₂ O ₃ or the like is formed on the upper portion of the metal film 600. When the heat treatment was performed through annealing, the residual film was removed. As described above, by performing annealing as in the present invention, the aluminum-based metal film and the IZO film are directly in contact with each other in the contact structure, and the residual film is removed to minimize contact resistance of the contact portion.

On the other hand, in the manufacturing method according to an embodiment of the present invention look at the surface of the aluminum-based metal film in detail as follows.

21A to 21C are photographs showing the surface of an Al—Nd metal film through a transmission electron microscope (TEM) in the method of manufacturing a thin film transistor substrate according to an exemplary embodiment of the present invention. FIG. 21A shows a surface of a state laminated at 150 ° C by sputtering using Al-Nd containing 2at% of Nd as a target, and FIG. 21B shows a protective film of silicon nitride at about 300 ° C under the same conditions as in FIG. 21A. After stacking at, the surface of the Al-Nd metal film is shown in the state of removing the protective film, and FIG. 21C shows the surface of the Al-Nd metal film having the protective film laminated thereon under the same condition as that of FIG. 21B, annealing at about 300 ° C., and then removing the protective film. Will appear.

As shown in FIGS. 21A to 21C, it can be seen that the grain size of Al-Nd gradually increases when the protective film is laminated and annealed.

In the manufacturing method according to the first and second embodiments of the present invention, in order to measure the contact resistance of the contact portion including the contact holes 72, 74, 76, and 78, the gate wiring is performed in the same order as the manufacturing method of the present invention. In the same layer as the pixel electrode 82 and the contact hole of the protective film 70 exposing the metal film and the metal film of the same layer as the (22, 24, 26, 28) or the data wirings 62, 64, 65, 66, 68 A plurality of measurement patterns were formed in series including an IZO film electrically connecting a plurality of metal films through contact holes. At this time, 200 contact holes were formed and the contact resistances of the contact holes directly contacting the metal film and the IZO film were measured. At this time, the contact resistance of the contact hole is formed to be E ⁷ Ω or less as a whole. When annealing is performed as in the embodiment of the present invention, even when the contact hole is reduced to an area of 4 μm × 4 μm, the contact hole is E ⁷ Ω. This resistance could be obtained. At this time, in particular, the contact hole 76 exposing the drain electrode 66 (see the first and second embodiments) preferably does not exceed 10 μm × 10 μm in consideration of the aperture ratio of the pixel.

In addition, in the method of manufacturing the thin film transistor substrate for the liquid crystal display device according to the first and second embodiments of the present invention, after forming the passivation layer 70 and then performing a heat treatment process, the characteristics of the thin film transistor after completing the thin film transistor substrate The step of heat-treating the thin film transistor substrate for a liquid crystal display device performed to stabilize the temperature can be omitted.

As described above, according to the present invention, by performing a heat treatment process to remove the residual material on the upper part of the metal film, the contact resistance of the contact part made of aluminum-based metal and IZO can be minimized, and the contact part including the pad part can be secured. . In addition, by forming the wiring with low-resistance aluminum or aluminum alloy, it is possible to improve the characteristics of a large screen high definition product. In addition, the manufacturing process may be simplified to manufacture a thin film transistor substrate for a liquid crystal display, thereby simplifying the manufacturing process and reducing the manufacturing cost.

Claims (46)

(Correction) forming a wiring made of a conductive material on the substrate, Stacking an inorganic insulating film covering the wiring; Performing a heat treatment process, Patterning the inorganic insulating film to form a contact hole exposing the wiring; and Forming a conductive layer electrically connected to the wirings Method for forming a contact portion of the wiring comprising a. (Correction) In paragraph 1, And the conductive material is formed of aluminum or an aluminum alloy. (Correction) In paragraph 1, And the inorganic insulating film is formed of silicon nitride. (Correction) In paragraph 1, The inorganic insulating film is a wiring contact forming method of laminating in the 250 ~ 400 ℃ temperature range. (Correction) In paragraph 1, And the conductive layer is formed of a transparent conductive material. (Correction) In Clause 5, And the conductive layer is formed of IZO. (Correction) In Clause 6, The said IZO is the contact part formation method of the wiring formed in 250 degrees C or less range. (Correction) In paragraph 1, And the heat treatment step is performed through annealing. (Correction) In Clause 8, The annealing is a contact portion forming method of the wiring to be carried out in the range of 250 ~ 400 ℃. (Correction) a wiring formed of a conductive material containing aluminum or an aluminum alloy on the substrate, An inorganic insulating film covering the wiring and having a contact hole for exposing a part of the wiring; A conductive layer formed of IZO on the inorganic insulating film and directly in contact with the wiring through the contact hole. Contact portion of the wiring comprising a. (Correction) In paragraph 10, The contact hole has an angle or is formed in a circle shape, the contact portion of the wiring having a length or diameter of one side of 4㎛ × 4㎛ or more. (Correction) In paragraph 10, And the inorganic insulating film is silicon nitride. (Correction) In paragraph 10, And wherein the wiring has a flat surface. Forming a gate wiring, Forming a data wiring, Forming a semiconductor layer, Forming an insulating layer covering the gate line, the data line, or the semiconductor layer; Performing a heat treatment process, Patterning the insulating film to form a contact hole exposing the gate wiring or the data wiring; Forming a conductive layer connected to the gate wiring or the data wiring through the contact hole; Method of manufacturing a thin film transistor substrate comprising a. (Correction) In clause 14, And the gate wiring and the data wiring include a conductive material of aluminum or an aluminum alloy. The method of claim 14, And the insulating film is formed of silicon nitride. In 14th, The insulating film is a method of manufacturing a thin film transistor substrate to be formed in the range of 250 ~ 400 ℃. The method of claim 14, And the conductive layer is formed of IZO. The method of claim 18, The IZO is a method for manufacturing a thin film transistor substrate laminated in the range of 250 ℃ or less. The method of claim 14, The thin film transistor substrate manufacturing method which consists of annealing by the said heat processing process. The method of claim 20, The annealing is a manufacturing method of a thin film transistor substrate to be carried out at a temperature range of 250 ~ 400 ℃. Stacking and patterning a first conductive material on the (correction) insulating substrate to form a gate line including a gate line and a gate electrode connected to the gate line, Stacking a gate insulating film, Forming a semiconductor layer, A data line stacked on and intersecting the gate line by stacking and patterning a second conductive material, a source electrode connected to the data line and adjacent to the gate electrode, and a drain electrode opposite to the source electrode with respect to the gate electrode; Forming a data wiring, Laminating a protective film, Performing a heat treatment process, Patterning the passivation layer to form a first contact hole exposing the drain electrode; Forming a pixel electrode on the passivation layer, the pixel electrode being electrically connected to the drain electrode Method of manufacturing a thin film transistor substrate for a liquid crystal display device comprising a. (Correction) In clause 22, The first and second conductive materials are formed of aluminum or an aluminum alloy. The method of claim 22, The gate insulating film and the protective film stacking step is a method of manufacturing a thin film transistor substrate for a liquid crystal display device performed in the range of 250 ~ 400 ℃. The method of claim 22, And the gate insulating film and the protective film are formed of silicon nitride. The method of claim 22, The pixel electrode is formed of a transparent conductive material. The method of claim 26, And the pixel electrode is formed of IZO. The method of claim 27, The said IZO is a manufacturing method of the thin film transistor substrate for liquid crystal display devices formed in 250 degrees C or less range. The method of claim 22, And said heat treatment step is performed through annealing. The method of claim 29, The annealing is a manufacturing method of a thin film transistor substrate for a liquid crystal display device performed in a temperature range of 250 ~ 400 ℃ or more. The method of claim 22, The gate line further includes a gate pad receiving a scan signal from the outside and transferring the scan signal to the gate line, The data line further includes a data pad which transfers an image signal from an external source to the data line. The passivation layer has second and third contact holes exposing the gate pad together with the data pad and the gate insulating layer. And forming an auxiliary gate pad and an auxiliary data pad electrically connected to the gate pad and the data pad through the second and third contact holes on the same layer as the pixel electrode. . The method of claim 22, And the data line and the semiconductor layer are formed together in a photolithography process using a photoresist pattern having a partially different thickness. 33. The method of claim 32, The photoresist pattern may include a first part having a first thickness, a second part thicker than the first thickness, and a third part having no thickness and excluding the first and second parts. Manufacturing method. The method of claim 33, In the photolithography process, the photoresist pattern is formed using a photomask including a first region, a second region having a lower transmittance than the first region, and a third region having a higher transmittance than the first region. Method for manufacturing a thin film transistor substrate for a device. The method of claim 34, And forming the first portion between the source electrode and the drain electrode and the second portion over the data line in the photolithography process. The method of claim 35, A method of manufacturing a thin film transistor substrate for a liquid crystal display device, in which a slit pattern smaller than the resolution of a translucent film or an exposure machine is formed in the photomask in order to differently control the transmittance of the first to third regions. The method of claim 36, And a thickness of the first portion is 1/2 or less with respect to a thickness of the second portion. The method of claim 22, And forming an ohmic contact layer between the semiconductor layer and the data line. The method of claim 38 wherein A method of manufacturing a thin film transistor substrate for a liquid crystal display device, wherein the data line, the contact layer, and the semiconductor layer are formed using one mask. (Correction) a gate wiring comprising a first conductive film of aluminum or an aluminum alloy on an insulating substrate, A gate insulating film covering the gate wiring and an inorganic insulating material, A semiconductor layer formed on the gate insulating film, A data line including a conductive film made of aluminum or an aluminum alloy and formed on the gate insulating film; A protective film of an inorganic insulating material covering the data wiring, A transparent conductive film pattern made of IZO, which is directly connected to the first or second conductive film of the gate wiring or the data wiring through a first contact hole formed in the gate insulating film or the protective film. Thin film transistor substrate comprising a. (delete) (Correction) In paragraph 41, The thin film transistor substrate of claim 1, wherein the first and second conductive layers contacting the transparent conductive layer pattern have a flat surface. 41. The method of claim 40 wherein The thin film transistor substrate of which the gate insulating film and the protective film are made of silicon nitride. (delete) 41. The method of claim 40 wherein The gate line includes a gate line extending in a horizontal direction, a gate electrode connected to the gate line, and a gate pad receiving a scan signal from the outside and transferring the scan signal to the gate line, The data line may include a data line extending in a vertical direction, a source electrode connected to the data line, a drain electrode separated from the source electrode and facing the source electrode around the gate electrode, and receiving image signals from the outside. A thin film transistor substrate comprising a data pad to transfer to the data line. The method of claim 45, The passivation layer has second and third contact holes exposing the gate pad together with the data pad and the gate insulating layer. The thin film transistor substrate of claim 1, wherein the first to third contact holes have an angle or are formed in a circle shape, and the contact holes have a size of 4 μm × 4 μm or more.