KR100729776B1 - Thin film transistor substrate for liquid crystal display and manufacturing method thereof - Google Patents

Abstract

First, an aluminum-based lower layer and a refractory metal upper layer are sequentially stacked and patterned to form a horizontal gate line including a gate line, a gate electrode, and a gate pad on the substrate. At this time, the upper layer of the gate pad is removed using a photoresist pattern having a different thickness as an etching mask. Next, a gate insulating film is formed, and a semiconductor layer and an ohmic contact layer are sequentially formed thereon. Subsequently, the conductive material is stacked and patterned to form a data line including a data line, a source electrode, a drain electrode, and a data pad crossing the gate line. Subsequently, the protective film is stacked and patterned to form contact holes that expose the drain electrode, the gate pad, and the data pad, respectively. In this case, the contact hole in the upper portion of the gate pad is formed so that only the lower layer is exposed, and the gate insulating layer or the protective layer is formed so as to completely cover the upper layer. Subsequently, ITO is stacked and patterned to form a pixel electrode, a gate pad, and an auxiliary data pad connected to the drain electrode, the auxiliary gate pad, and the data pad, respectively. Therefore, in such a manufacturing method, corrosion or erosion of the gate wiring can be prevented, and reliability of the pad portion can be ensured.

Aluminum, transmittance, photoresist, ITO

Description

Thin film transistor substrate for liquid crystal display device and manufacturing method therefor {THIN FILM TRANSISTOR SUBSTRATE FOR LIQUID CRYSTAL DISPLAY AND MANUFACTURING METHOD THEREOF}

1 is a thin film transistor substrate for a liquid crystal display device according to a first embodiment of the present invention;

FIG. 2 is a cross-sectional view of the thin film transistor substrate illustrated in FIG. 1 taken along the line II-II.

3A, 6A, 7A and 8A are layout views of a thin film transistor substrate in an intermediate process of manufacturing according to an embodiment of the present invention,

3B, 4 and 5 are cross-sectional views taken along the line IIIb-IIIb 'in FIG. 3A,

FIG. 6B is a cross-sectional view taken along the line VIb-VIb ′ in FIG. 6A, and is a cross-sectional view showing the next step in FIG. 3B;

FIG. 7B is a cross-sectional view taken along the line VIIb-VIIb ′ in FIG. 7A and illustrating the next step in FIG. 6B;

FIG. 8B is a cross-sectional view taken along the line VIIIb-VIIIb ′ in FIG. 8A and is a cross-sectional view showing the next step in FIG. 7B;

9 is a layout view of a thin film transistor substrate for a liquid crystal display according to a second exemplary embodiment of the present invention.

10 and 11 are cross-sectional views of the thin film transistor substrate illustrated in FIG. 9 taken along lines X-X 'and XI-XI',

12A is a layout view of a thin film transistor substrate in a first step of manufacturing according to the second embodiment of the present invention;

12B and 12C are cross-sectional views taken along the lines XIIb-XIIb 'and XIIc-XIIc' in FIG. 12A, respectively.

13A and 13B are cross-sectional views taken along the lines XIIb-XIIb 'and XIIc-XIIc' in FIG. 12A, respectively, and are cross-sectional views in the next steps of FIGS. 12B and 12C;

FIG. 14A is a layout view of a thin film transistor substrate at a next step of FIGS. 13A and 13B;

14B and 14C are cross-sectional views taken along the lines XIVb-XIVb ′ and XIVVIc-XIVc ′ in FIG. 14A, respectively.

15A, 16A, 17A and 15B, 16B, 17B are cross-sectional views taken along lines XIVb-XIVb 'and XIVc-XIVc' in FIG. 14A, respectively, illustrating the following steps in the order of the process. ,

18A is a layout view of a thin film transistor substrate in the next steps of FIGS. 17A and 17B,

18B and 18C are cross-sectional views taken along the lines XVIIIb-XVIIIb 'and XVIIIc-XVIIIc' in FIG. 18A, respectively.

The present invention relates to a thin film transistor substrate for a liquid crystal display device and a manufacturing method thereof.

The liquid crystal display is one of the most widely used flat panel display devices. The liquid crystal display includes two substrates on which electrodes are formed and a liquid crystal layer interposed therebetween, and rearranges the liquid crystal molecules of the liquid crystal layer by applying a voltage to the electrode. By controlling the amount of light transmitted.

Among the liquid crystal display devices, a liquid crystal display device having a thin film transistor for forming an electrode on each of two substrates and switching a voltage applied to the electrode is generally used. The thin film transistor is generally formed on one of two substrates.

The substrate on which the thin film transistor is formed is generally manufactured through a photolithography process using a mask. At this time, it is preferable to reduce the number of masks in order to reduce the production cost.

On the other hand, in order to prevent signal delay, the wiring is generally made of a material such as aluminum (Al) or aluminum alloy (Al alloy) having a low resistance. However, in the case of using indium tin oxide (ITO) in the pad portion to secure the pad portion, as in a liquid crystal display device, aluminum or aluminum alloy and ITO have poor contact characteristics, so that other metals are interposed and aluminum or aluminum alloy is removed. Should be.

However, since wet etching is used to remove aluminum or an aluminum alloy, undercut occurs, causing a problem that the ITO film formed on the pad portion is broken. This causes corrosion in the pad part.

An object of the present invention is to provide a method of manufacturing a thin film transistor substrate for a liquid crystal display device capable of preventing corrosion or erosion of a signal line.

In addition, another object of the present invention is to ensure the reliability of the pad portion and to simplify the manufacturing method of the thin film transistor substrate for a liquid crystal display device.

In order to solve this problem, a photoresist pattern having a different thickness is used as an etching mask to remove only the aluminum-based conductive film from the plurality of conductive films and to cover the aluminum-based conductive film completely with a gate insulating film or a protective film. .

According to the present invention, a plurality of conductive layers are stacked on at least two insulating substrates, and one of the lower layers is partially removed to selectively expose the plurality of conductive layers, thereby selectively patterning the plurality of conductive layers to form a gate electrode, a gate electrode connected to the gate line, and a gate. The gate line is connected to a line to form a gate line including a gate pad configured to receive a scan signal from the outside. Subsequently, a gate insulating film is formed, a semiconductor layer is formed on the gate insulating film facing the gate electrode, a data line crossing the gate line, a source electrode connected to the data line and adjacent to the gate electrode, and a source electrode for the gate electrode. A data line is formed that includes the drain electrode positioned opposite to the side of the substrate. Subsequently, a protective film is stacked and a pixel electrode connected to the drain electrode is formed.

Here, in order to selectively pattern the plurality of conductive films when forming the gate wiring, it is preferable to form a photolithography process using a photoresist pattern having a different thickness, and the photoresist pattern may include a first portion and a first thickness having a first thickness. A second portion thicker than one thickness, the third portion having no thickness and excluding the first and second portions.

In order to form such a photoresist pattern in a photolithography process, an optical mask including a first region, a second region having a higher transmittance than the first region, and a third region having a higher transmittance than the second region is used.

In this case, the first portion is formed to be located on the gate pad, the second portion is located above the gate line and the gate electrode, and the thickness of the first portion is preferably formed to be 1/2 or less of the thickness of the second portion.

Here, in order to adjust the transmittance of the first to third regions differently, a slit pattern smaller than the resolution of the translucent film or the exposure apparatus may be used.

The multiple conductive films are preferably formed of a double film including a lower film made of chromium, molybdenum, molybdenum alloy or titanium having excellent contact properties with ITO, and an upper film having a low resistance, including a top film made of an aluminum-based conductive film.

In this case, in the gate wiring forming step, the gate pad may be formed only as a lower layer, and the gate insulating layer and the passivation layer may have a first contact hole exposing the gate pad. Here, the protective film and the gate insulating film are preferably formed so as to completely cover the upper film.

The data line further includes a data pad receiving a data signal from the outside, and an auxiliary gate pad connected to the gate pad through a first contact hole and an auxiliary pad connected to the data pad through a second contact hole in the same layer as the pixel electrode. Form a data pad.

Here, the pixel electrode is preferably formed of ITO.

The semiconductor device may further include an ohmic contact layer between the semiconductor layer and the data line, and the data line, the contact layer, and the semiconductor layer may be formed using one mask.

Then, the liquid crystal display according to an exemplary embodiment of the present invention and a manufacturing method thereof will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily implement the present invention.

First, a structure of a thin film transistor substrate for a liquid crystal display according to a first embodiment of the present invention will be described in detail with reference to FIGS. 1 and 2.

1 is a thin film transistor substrate for a liquid crystal display device according to a first embodiment of the present invention, and FIG. 2 is a cross-sectional view of the thin film transistor substrate shown in FIG. 1 taken along the line II-II.

A gate wiring including a lower film 201 made of a metal having excellent contact properties with ITO, such as chromium, molybdenum, or molybdenum alloy, on the insulating substrate 10 and an upper film 202 made of an aluminum or aluminum-based alloy having low resistance. Is formed. The gate wiring is connected to the gate line 22 and the end of the gate line 22 extending in the horizontal direction, and the branch of the gate pad 24 and the gate line 22 which receive a gate signal from the outside and transfer the gate signal to the gate line. A gate electrode 26 of the phosphor thin film transistor. In this case, the gate pad 24 is formed only of the lower layer 201.

On the substrate 10, a gate insulating film 30 made of silicon nitride (SiN _x ) covers the gate wirings 22, 24, and 26, and the gate insulating film 30 is provided with a gate pad along with a protective film 70 formed thereafter. It has a contact hole 74 which exposes 24 and completely covers the upper film 202 of the gate wirings 22 and 26.

A semiconductor layer 40 made of a semiconductor such as amorphous silicon is formed on the gate insulating film 30 of the gate electrode 24 in an island shape, and silicide or n-type impurities are doped with high concentration on the semiconductor layer 40. Resistive contact layers 54 and 56 made of a material such as n + hydrogenated amorphous silicon are formed, respectively.

On the ohmic contacts 54 and 56 and the gate insulating film 30, data lines 62, 64, 66 and 68 made of chromium (Cr) or molybdenum-tungsten alloy are formed. The data line is formed in the vertical direction and crosses the gate line 22 to define a pixel, the data line 62 and the branch of the data line 62 and the source electrode 64 extending to the upper portion of the ohmic contact layer 54. ), Which is connected to one end of the data line 62 and is separated from the data pad 68 and the source electrode 64 to which an image signal from the outside is applied, and is opposite to the source electrode 64 with respect to the gate electrode 24. The drain electrode 68 is formed on the ohmic contact layer 56.

The passivation layer 70 is formed on the data lines 62, 64, 66, and 68 and the semiconductor layer 40 not covered by the data lines 62. In the passivation layer 90, contact holes 76 and 78 respectively exposing the drain electrode 66 and the data pad 68 are formed, and the lower layer 201 of the gate pad 24 together with the gate insulating layer 30 is formed. The contact hole 74 which exposes a bay is formed.

The pixel electrode 82 connected to the drain electrode 66 is formed on the passivation layer 70 of the pixel through the contact hole 76, and the lower layer of the gate pad 24 is formed through the contact holes 74 and 78, respectively. An auxiliary gate pad 86 and an auxiliary data pad 88 connected to the 201 and the data pad 68 are formed.

1 and 2, the pixel electrode 82 overlaps with the gate line 22 to form a storage capacitor. When the storage capacitor is insufficient, the pixel electrode 82 is disposed on the same layer as the gate wirings 22, 24, and 26. It is also possible to add a storage capacitor wiring.

Next, a method of manufacturing a thin film transistor substrate for a liquid crystal display device having a structure according to this embodiment will be described in detail with reference to FIGS. 1 to 2 and FIGS. 3A to 8B.

3A, 6A, 7A, and 8A are layout views of a thin film transistor substrate during an intermediate process of manufacturing according to an embodiment of the present invention, and are shown in sequence according to the manufacturing sequence. 3B, 4 and 5 are cross-sectional views taken along the line IIIb-IIIb 'in FIG. 3A, and FIG. 6B is a view taken along the line VIb-VIb' in FIG. 6A and shows the next step in FIG. 3B. FIG. 7B is a cross-sectional view taken along the line VIIb-VIIb 'in FIG. 7A and is a cross-sectional view illustrating the next step of FIG. 6B, and FIG. 8B is a cutaway view taken along the line VIIIb-VIIIb' in FIG. 8A. Fig. 7b is a sectional view showing the next step.

First, as shown in FIGS. 3A to 3B, a lower film 201 formed of a conductive film made of a refractory metal having excellent contact properties with ITO, such as chromium, molybdenum or molybdenum alloy, titanium (Ti), etc., on the substrate 10; An upper layer 202 made of aluminum or an aluminum-based conductive layer having low resistance is sequentially stacked and patterned to have a thickness of about 500 GPa and 2,500 GPa, thereby forming a gate line 22 including the lower layer 201 and the upper layer 202. ) And a gate wiring in a horizontal direction including a gate pad 24 composed of only the gate electrode 26 and the lower layer 201.

In this case, all portions of the conductive layers 201 and 202 except for the gate lines 22, 24, and 26 should be removed, and only the upper layer 202 should be removed from the gate pad 24. To this end, a photoresist pattern having at least three parts having different thicknesses should be used as an etching mask, and in order to form such a photoresist pattern, an optical mask having at least three regions having different transmittances should be used. This will be described in detail with reference to FIGS. 4 and 5.

First, as shown in FIG. 4, the lower layer 201 and the upper layer 202 are sequentially stacked on the substrate 10, the photosensitive layer is coated on the upper layer 202, and has three different transmittances. The photoresist film is exposed and developed using the photomask 100 including the regions A, B, and C to form photoresist patterns 112 and 114 having different thicknesses. As the photosensitive film used herein, both positive and negative photosensitive films may be used, and it is preferable to form 1.9 μm or more, and the thick part 112 is preferably formed to be twice or more than the thin part 114.

As such, there may be various methods of varying the thickness of the photoresist layer according to the position. In order to control the light transmittance in the A region, a slit or lattice-shaped pattern is mainly formed or a translucent film is used.

In this case, the line width of the pattern located between the slits, or the interval between the patterns, that is, the width of the slits, is preferably smaller than the resolution of the exposure apparatus used for exposure. A thin film having a thickness or a thin film may be used.

When the light is irradiated to the photosensitive film through such a mask, the polymers are completely decomposed at the part directly exposed to the light, and the polymers are not completely decomposed because the amount of light is small at the part where the slit pattern or the translucent film is formed. In the area covered by, the polymer is hardly decomposed. Subsequently, when the photoresist film is developed, only a portion where the polymer molecules are not decomposed is left, and a thin photoresist film may be left at a portion where the light is not irradiated at a portion less irradiated with light. In this case, prolonging the exposure time decomposes all the molecules, so it should not be so.

The thin film 114 is formed by using a photoresist film made of a reflowable material, and is exposed to a conventional mask that is divided into a part that can completely transmit light and a part that cannot fully transmit light, and then develops and ripples. It can also be formed by letting a part of the photosensitive film flow to the part which does not remain by making it low.

Subsequently, as shown in FIG. 5, the lower layer 201 and the upper layer 202 are sequentially etched using the photoresist patterns 112 and 114 as a mask. Here, when the lower layer 201 and the upper layer 202 are each made of an aluminum-based conductive layer and chromium, it is preferable to use wet etching.

Subsequently, an ashing process is performed to remove the photoresist pattern 114 of FIG. 5, and the upper photoresist 202 is removed using the remaining photoresist pattern 112 as an etch mask, and the gate pad 24 is formed as shown in FIG. 3B. Formed only with 201 and remaining photoresist film is removed. Here, after finishing the ashing process, the thickness of the photosensitive film pattern 112 is preferably left at about 2,000 kPa. At this time, the edge of the upper film 202 is formed in a tapered structure having a gentle inclination angle.

In this way, when a photoresist pattern having a partly different thickness is used as an etching mask, when the wiring is formed of at least two or more multilayer films, one of the lower layers may be selected to form a wiring so that a part thereof is exposed.

Next, as shown in FIGS. 6A and 6B, the gate insulating film 30, the semiconductor layer 40 made of amorphous silicon, and the three layer films of the doped amorphous silicon layer 50 are successively laminated and patterned using a mask. An island-like semiconductor layer 40 and an ohmic contact layer 50 are formed on the gate insulating layer 30 facing the gate electrode 26.

Next, as shown in FIGS. 7A to 7B, molybdenum, molybdenum alloy, or chromium is laminated, and then patterned by a photo process using a mask to intersect the data line 62 and the data line 62 with the gate line 22. ) Is connected to the source electrode 64 and the data line 62 extending to the upper portion of the gate electrode 24 is separated from the data pad 68 and the source electrode 64 connected to one end, the gate electrode 26 ) And a data line including a drain electrode 66 facing the source electrode 66.

Subsequently, the doped amorphous silicon layer pattern 50, which is not covered by the data lines 62, 64, 66, and 68, is etched and separated on both sides of the gate electrode 26, while both doped amorphous silicon layers ( The semiconductor layer pattern 40 between 54 and 56 is exposed.

Next, as shown in FIGS. 8A to 8B, after the protective film 70 made of the organic insulating film is stacked, the gate pad 26 is patterned by dry etching together with the gate insulating film 30 by a photolithography process using a mask. ), Contact holes 74, 76, 78 exposing the drain electrode 66 and the data pad 68 are formed. At this time, the contact hole 74 on the gate pad 24 is formed on the upper portion of the lower layer 201 so that the aluminum-based conductive layer, which is the upper layer 202 of the gate lines 22 and 26, is completely covered with the gate insulating layer 30. Only form it.

Next, as shown in FIGS. 1 and 2, the ITO film is laminated and patterned using a mask to contact the drain electrodes 66 and the pixel electrodes 82 and the contact holes 74 and 78 through the contact holes 76. The auxiliary gate pads 86 and the auxiliary data pads 88 connected to the gate pads 24 and the data pads 68 are respectively formed through the?

In the manufacturing method according to the embodiment of the present invention, an undercut is generated by omitting a process of removing the upper layer 202 of the gate wiring to prevent the ITO and aluminum-based metals from contacting each other before laminating the ITO film. ITO membrane does not break. Therefore, moisture may flow into the gate wiring to prevent corrosion of the wiring, and the upper layer 202 made of aluminum-based metal may be completely covered with the protective film 70 and the gate insulating film 30 to corrode the wiring. Can be prevented. In addition, since only the chromium and ITO contact each other in the pad part, it is possible to secure reliability of the pad part.

In addition, in the embodiment of the present invention, a protective film 70 made of an organic insulating film having a lower dielectric constant than an insulating film made of silicon nitride or silicon oxide is formed, so that the signal is formed so as to overlap the pixel electrode 82 and the data line 62. Interference can be minimized to improve the aperture ratio of the pixel.

As described above, the method can be applied to a manufacturing method using a five-sheet mask, but the same method can be applied to a manufacturing method of a thin film transistor substrate for a liquid crystal display device using a four-mask. This will be described in detail with reference to the drawings.

First, a unit pixel structure of a thin film transistor substrate for a liquid crystal display according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 9 to 11.

9 is a layout view of a thin film transistor substrate for a liquid crystal display according to a second exemplary embodiment of the present invention, and FIGS. 10 and 11 are along the XX 'line and the XI-XI' line of the thin film transistor substrate shown in FIG. 9, respectively. It is sectional drawing cut out.

First, the gate line 22 including the lower layer 201 and the upper layer 202 and the gate pad including only the gate electrode 26 and the lower layer 201 are formed on the insulating substrate 10 as in the first embodiment. A gate wiring including 24 is formed. The gate wiring includes a sustain electrode 28 that is parallel to the gate line 22 on the substrate 10 and receives a voltage such as a common electrode voltage input to the common electrode of the upper plate from the outside. The storage electrode 28 overlaps with the conductive capacitor conductor 68 for the storage capacitor connected to the pixel electrode 82, which will be described later, to form a storage capacitor which improves the charge retention capability of the pixel. The pixel electrode 82 and the gate line, which will be described later, If the holding capacity generated by the overlap of (22) is sufficient, it may not be formed.

A gate insulating film 30 made of silicon nitride (SiN _x ) is formed on the gate wirings 22, 24, 26, and 28 to cover the gate wirings 22, 24, 26, and 28.

Semiconductor patterns 42 and 48 made of semiconductors such as hydrogenated amorphous silicon are formed on the gate insulating layer 30, and high concentrations of n-type impurities such as phosphorus (P) are formed on the semiconductor patterns 42 and 48. An ohmic contact layer pattern or an intermediate layer pattern 55, 56, 58 made of amorphous silicon doped with is formed.

On the ohmic contact layer patterns 55, 56, and 58, a data line made of a conductive material such as Mo or MoW alloy, Cr, Al or Al alloy, and Ta is formed. The data line is a thin film transistor which is a branch of the data line 62 formed in the vertical direction, the data pad 64 connected to one end of the data line 62 to receive an image signal from the outside, and the data line 62. And a data line portion of the source electrode 65 of the source electrode 65, separated from the data line portions 62, 64, and 65, of the source electrode 65 with respect to the gate electrode 26 or the channel portion C of the thin film transistor. It also includes a conductive capacitor conductor 68 for the storage capacitor located on the drain electrode 66 and the storage electrode 28 of the thin film transistor located on the opposite side. When the sustain electrode 28 is not formed, the conductor pattern 68 for the storage capacitor is also not formed.

The data lines 62, 64, 65, 66, 68 may also be formed in a single layer like the gate lines 22, 24, 26, 28, but may be formed in a double layer or a triple layer. Of course, when forming more than two layers, it is preferable that one layer is made of a material having a low resistance and the other layer is made of a material having good contact properties with other materials.

The contact layer patterns 55, 56, and 58 serve to lower the contact resistance between the semiconductor patterns 42 and 48 below and the data lines 62, 64, 65, 66, and 68 above them. It has exactly the same form as (62, 64, 65, 66, 68). That is, the data line part intermediate layer pattern 55 is the same as the data line parts 62, 64 and 65, the drain electrode intermediate layer pattern 56 is the same as the drain electrode 66, and the storage capacitor intermediate layer pattern 58 is It is the same as the conductor pattern 68 for holding capacitors.

The semiconductor patterns 42 and 48 have the same shapes as the data lines 62, 64, 65, 66, and 68 and the ohmic contact layer patterns 55, 56, and 57 except for the channel portion C of the thin film transistor. Doing. Specifically, the semiconductor capacitor 48 for the storage capacitor, the conductor pattern 68 for the storage capacitor, and the contact layer pattern 58 for the storage capacitor have the same shape, but the semiconductor pattern 42 for the thin film transistor has data wiring and contact. Slightly different from the rest of the layer pattern. That is, the data line parts 62, 64, 65, in particular, the source electrode 65 and the drain electrode 66 are separated from the channel portion C of the thin film transistor, and the contact layer pattern for the data line intermediate layer 55 and the drain electrode is separated. Although 56 is also separated, the semiconductor pattern 42 for thin film transistors is not disconnected here and is connected to generate a channel of the thin film transistor.

The passivation layer 70 is formed on the data wires 62, 64, 65, 66, and 68, and the passivation layer 70 forms the drain electrode 66, the data pad 64, and the conductive pattern 68 for the storage capacitor. The contact holes 71, 73, and 74 are exposed, and the contact holes 72 are exposed to expose the gate pad 24 together with the gate insulating film 30. As shown in FIG. The passivation layer 70 may be made of an organic insulating material such as silicon nitride or acrylic.

On the passivation layer 70, a pixel electrode 82 that receives an image signal from a thin film transistor and generates an electric field together with the electrode of the upper plate is formed. The pixel electrode 82 is made of a transparent conductive material such as indium tin oxide (ITO), and is physically and electrically connected to the drain electrode 66 through the contact hole 71 to receive an image signal. The pixel electrode 82 also overlaps with the neighboring gate line 22 and the data line 62 to increase the aperture ratio, but may not overlap. In addition, the pixel electrode 82 is also connected to the storage capacitor conductor pattern 68 through the contact hole 74 to transmit an image signal to the conductor pattern 68. On the other hand, an auxiliary gate pad 84 and an auxiliary data pad 86 connected to the gate pad 24 and the data pad 64 through the contact holes 72 and 73, respectively, are formed. , 64) and to protect the pads and the adhesion of the external circuit device, it is not essential, and their application is optional.

Although transparent ITO has been used as an example of the material of the pixel electrode 82, an opaque conductive material may be used for the reflective liquid crystal display device.

Next, a method of manufacturing a thin film transistor substrate for a liquid crystal display device having the structure of FIGS. 9 to 11 using four masks will be described in detail with reference to FIGS. 9 to 11 and 12A to 18C. .

 First, as shown in FIGS. 12A to 12C, the gate line 22, the gate pad 24, and the gate electrode 26 are formed on the substrate 10 by a photolithography process using a first mask as in the first embodiment. And a gate wiring including the sustain electrode 28.

Here, the gate wiring is formed of a double layer, but may be formed of a plurality of conductive layers including the double layer, and in the case of including an aluminum-based metal as in the first embodiment, a photosensitive layer pattern having a partly different thickness is formed. By using the gate pad 24 to remove the aluminum-based metal.

13A and 13B, the gate insulating film 30, the semiconductor layer 40, and the intermediate layer 50 are respectively 1,500 kV to 5,000 kV, 500 kV to 2,000 kV, 300 kV using chemical vapor deposition. Continuously deposited to a thickness of 600 to 600 kPa, and then depositing a conductor layer 60 such as a metal to a thickness of 1,500 kPa to 3,000 kPa by sputtering or the like, and then depositing a photoresist film 110 thereon at a thickness of 1 μm to 2 μm. Apply with

Thereafter, the photoresist film 110 is irradiated with light through a second mask and then developed to form photoresist patterns 112 and 114 as shown in FIGS. 14B and 14C. In this case, among the photoresist patterns 112 and 114, the channel portion C of the thin film transistor, that is, the first portion 114 positioned between the source electrode 65 and the drain electrode 66, is the data wiring portion A, that is, the data. The thickness of the wirings 62, 64, 65, 66, and 68 is smaller than that of the second portion 112 positioned at the portion where the wirings 62, 64, 65, 66, and 68 are to be formed. At this time, the ratio of the thickness of the photoresist film 114 remaining in the channel portion C to the thickness of the photoresist film 112 remaining in the data wiring portion A should be different depending on the process conditions in the etching process described later. It is preferable to make the thickness of the 1st part 114 into 1/2 or less of the thickness of the 2nd part 112, for example, it is good that it is 4,000 Pa or less.

Subsequently, etching is performed on the photoresist pattern 114 and the underlying layers, that is, the conductor layer 60, the intermediate layer 50, and the semiconductor layer 40. In this case, the data line and the lower layer of the data line remain in the data wiring portion A, and only the semiconductor layer should remain in the channel portion C, and the upper three layers 60, 50, 40 must be removed to expose the gate insulating film 30.

First, as shown in FIGS. 15A and 15B, the exposed conductor layer 60 of the other portion B is removed to expose the lower intermediate layer 50. In this process, both a dry etching method and a wet etching method may be used. In this case, the conductor layer 60 may be etched and the photoresist patterns 112 and 114 may be hardly etched. However, in the case of dry etching, it is difficult to find a condition in which only the conductor layer 60 is etched and the photoresist patterns 112 and 114 are not etched, so that the photoresist patterns 112 and 114 may also be etched together. In this case, the thickness of the first portion 114 is thicker than that of the wet etching so that the first portion 114 is removed in this process so that the lower conductive layer 60 is not exposed.

When the conductor layer 60 is any one of Mo or MoW alloy, Al or Al alloy, and Ta, either dry etching or wet etching can be used. However, since Cr is not easily removed by the dry etching method, it is preferable to use only wet etching if the conductor layer 60 is Cr. In the case of wet etching in which the conductor layer 60 is Cr, CeNHO ₃ may be used as an etchant. In the case of dry etching in which the conductor layer 60 is Mo or MoW, the mixed gas or CF of CF ₄ and HCl may be used as the etching gas. A mixed gas of ₄ and O ₂ can be used, and in the latter case, the etching ratio to the photoresist film is almost the same.

In this way, as shown in Figs. 15A and 15B, only the conductor layers of the channel portion C and the data wiring portion B, that is, the conductor pattern 67 for the source / drain and the conductor pattern 68 for the storage capacitor, are shown. All of the conductor layer 60 of the remaining portion B is removed, revealing the underlying intermediate layer 50. The remaining conductor patterns 67 and 68 have the same shape as the data lines 62, 64, 65, 66, and 68 except that the source and drain electrodes 65 and 66 are connected without being separated. In addition, when dry etching is used, the photoresist patterns 112 and 114 are also etched to a certain thickness.

Subsequently, as shown in FIGS. 16A and 16B, the exposed intermediate layer 50 of the other portion B and the semiconductor layer 40 below it are simultaneously removed together with the first portion 114 of the photosensitive film by a dry etching method. do. At this time, etching is performed under the condition that the photoresist patterns 112 and 114, the intermediate layer 50, and the semiconductor layer 40 (the semiconductor layer and the intermediate layer have almost no etching selectivity) are simultaneously etched, and the gate insulating layer 30 is not etched. In particular, it is preferable to etch under conditions where the etching ratios of the photoresist patterns 112 and 114 and the semiconductor layer 40 are almost the same. For example, by using a mixed gas of SF ₆ and HCl or a mixed gas of SF ₆ and O ₂ , the two films can be etched to almost the same thickness. When the etching ratios of the photoresist patterns 112 and 114 and the semiconductor layer 40 are the same, the thickness of the first portion 114 should be equal to or smaller than the sum of the thicknesses of the semiconductor layer 40 and the intermediate layer 50.

This removes the first portion 114 of the channel portion C, revealing the source / drain conductor pattern 67, as shown in FIGS. 16A and 16B, and the intermediate layer 50 of the other portion B. And the semiconductor layer 40 is removed to expose the gate insulating layer 30 thereunder. On the other hand, since the second portion 112 of the data wiring portion A is also etched, the thickness becomes thin. In this step, the semiconductor patterns 42 and 48 are completed. Reference numerals 57 and 58 indicate the intermediate layer pattern under the source / drain conductor pattern 67 and the intermediate layer pattern under the storage capacitor conductor pattern 68, respectively.

Subsequently, ashing removes photoresist residue remaining on the surface of the source / drain conductor pattern 67 of the channel portion C.

Next, as illustrated in FIGS. 17A and 17B, the source / drain conductor pattern 67 of the channel portion C and the source / drain interlayer pattern 57 below are etched and removed. In this case, the etching may be performed only by dry etching with respect to both the source / drain conductor pattern 67 and the intermediate layer pattern 57. The etching may be performed by wet etching on the source / drain conductor pattern 67. 57 may be performed by dry etching. In the former case, it is preferable to perform etching under a condition in which the etching selectivity of the source / drain conductor pattern 67 and the interlayer pattern 57 is large, which is difficult to find the etching end point when the etching selectivity is not large. This is because it is not easy to adjust the thickness of the semiconductor pattern 42 remaining in Fig. 2). For example, those of etching the SF ₆ and O ₂ by using the mixed gas of the source / drain conductive pattern 67. In the latter case of alternating between wet etching and dry etching, the side surface of the conductive pattern 67 for wet etching of the source / drain is etched, but the intermediate layer pattern 57 which is dry etched is hardly etched, and thus is formed in a step shape. Examples of the etching gas used to etch the intermediate layer pattern 57 and the semiconductor pattern 42 include the aforementioned mixed gas of CF ₄ and HCl or mixed gas of CF ₄ and O ₂ , and CF ₄ and O _{Using 2} can leave the semiconductor pattern 42 in a uniform thickness. In this case, as shown in FIG. 10B, a portion of the semiconductor pattern 42 may be removed to reduce the thickness, and the second portion 112 of the photoresist pattern may also be etched to a certain thickness at this time. At this time, the etching should be performed under the condition that the gate insulating film 30 is not etched, and the photoresist film is not exposed so that the second portion 112 is etched so that the data lines 62, 64, 65, 66, and 68 underneath are not exposed. It is a matter of course that the pattern is thick.

In this way, the source electrode 65 and the drain electrode 66 are separated, thereby completing the data lines 62, 64, 65, 66, and 68 and the contact layer patterns 55, 56, and 58 under the data lines.

Finally, the second photoresist layer 112 remaining in the data wiring portion A is removed. However, the removal of the second portion 112 may be made after removing the conductor pattern 67 for the channel portion C source / drain and before removing the intermediate layer pattern 57 thereunder.

As mentioned earlier, wet and dry etching can be alternately used or only dry etching can be used. In the latter case, since only one type of etching is used, the process is relatively easy, but it is difficult to find a suitable etching condition. On the other hand, in the former case, the etching conditions are relatively easy to find, but the process is more cumbersome than the latter.

After the data wirings 62, 64, 65, 66, and 68 are formed in this manner, as shown in FIGS. 18A to 18C, silicon nitride is deposited by CVD or spin-coated an organic insulating material to have a thickness of 3,000 Å or more. The protective film 70 is formed. Subsequently, the passivation layer 70 is etched together with the gate insulating layer 30 by using a third mask to form the drain electrode 66, the gate pad 24, the data pad 64, and the conductive pattern 68 for the storage capacitor, respectively. The exposed contact holes 71, 72, 73, 74 are formed.

Finally, as shown in FIGS. 10 through 11, an ITO layer having a thickness of 400 μs to 500 μs is deposited and etched using a fourth mask to form the pixel electrode 82, the auxiliary gate pad 84, and the auxiliary data pad. Form 86.

In the second embodiment of the present invention, the data wirings 62, 64, 65, 66, and 68 and the contact layer patterns 55, 56, 58 and the semiconductor pattern 42 below the data wirings 62, 64, 65, 66, and 68, as well as the effects of the first embodiment. , 48) may be formed using one mask, and the source electrode 65 and the drain electrode 66 may be separated in this process to simplify the manufacturing process.

In the embodiment of the present invention, a photosensitive film pattern having a different thickness is used in order to avoid contact between the aluminum-based metal and the ITO film, but this method is optional in the case of forming a wiring with multiple conductive films. It can also be used in the method of manufacturing a semiconductor device to expose the underlayer.

As described above, according to the present invention, the gate pad is formed of a conductive material having good contact characteristics with ITO, thereby ensuring reliability of the pad portion, and simultaneously forming a low resistance aluminum or aluminum alloy so that the wiring is completely covered with the gate insulating film or the protective film. Corrosion or erosion can be prevented. In addition, by manufacturing the thin film transistor substrate for a liquid crystal display device by simplifying the manufacturing process, the manufacturing cost may be reduced, and the aperture ratio of the pixel may be improved.

Claims (17)

Stacking and patterning a multilayer conductive film on an insulating substrate, the gate line, a gate electrode connected to the gate line, and a portion of one of the lower layers of the conductive film of the multilayer are exposed, and are connected to the gate line to scan signals from the outside. Forming an applied gate pad, Forming a gate insulating film to cover the upper film of the multilayer conductive film, Forming a semiconductor layer on the gate insulating layer facing the gate electrode; Forming a data line including a data line crossing the gate line, a source electrode connected to the data line and a drain electrode adjacent to the gate electrode, and a drain electrode opposite to the source electrode; Forming a protective film having a portion in which one of the lower films of the conductive film of the gate pad is exposed and a contact hole exposing the drain electrode; Forming an auxiliary gate pad connected to a pixel electrode connected to the drain electrode through the contact hole and a portion of one of the lower layers of the conductive film of the multilayer of the gate pad through the contact hole; Method of manufacturing a thin film transistor substrate for a liquid crystal display device comprising a. In claim 1, The gate line, the gate electrode and the gate pad are formed by a photolithography process using a photoresist pattern having a partially different thickness. In claim 2, The photoresist pattern may include a first part having a first thickness, a second part thicker than the first thickness, and a third part having no thickness and excluding the first and second parts. Manufacturing method. In claim 3, In the photolithography process, the photoresist pattern is formed using a photomask including a first region, a second region having a higher transmittance than the first region, and a third region having a higher transmittance than the second region. Method for manufacturing a thin film transistor substrate for a device. In claim 4, And forming the first portion on the gate pad and the second portion on the gate line and the gate electrode in the photolithography process. In claim 5, A method of manufacturing a thin film transistor substrate for a liquid crystal display device, wherein a slit pattern smaller than the resolution of a translucent film or an exposure machine is formed in the photomask to differently control the transmittance of the first to third regions. In claim 3, And a thickness of the first portion is 1/2 or less with respect to a thickness of the second portion. In claim 1, A portion for removing one of the plurality of conductive films so that the film is exposed is the gate pad. In claim 1, The multiple conductive film is a double film consisting of an upper film and a lower film. In claim 9, And the lower layer is formed of chromium, molybdenum, molybdenum alloy, or titanium, and the upper layer is formed of an aluminum-based conductive layer. In claim 10, And the gate pad is formed only of a lower layer. In claim 11, And the gate insulating film and the passivation film have a first contact hole exposing the gate pad. In claim 12, And the passivation layer and the gate insulating layer are formed to completely cover the upper layer. In claim 13, The data line further includes a data pad receiving a data signal from an external device. Forming an auxiliary gate pad connected to the gate pad through the first contact hole and an auxiliary data pad connected to the data pad through the second contact hole in the pixel electrode forming step. Manufacturing method. In claim 1, And the pixel electrode is formed of ITO. In claim 1, And a resistive contact layer between the semiconductor layer and the data line. The method of claim 16, And forming the data line, the contact layer, and the semiconductor layer using a single mask.

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