KR100695347B1 - A thin film transistor array panel and method for manufacturing the same - Google Patents

Abstract

First, an aluminum-based conductive material is stacked and patterned to form a horizontal gate line including a gate line, a gate electrode, and a gate pad on a substrate. At this time, in order to uniformly transfer the gate signal through the gate wiring, the thickness increases so as to move away from the gate pad. Next, a gate insulating film is formed by laminating silicon nitride, and a semiconductor layer and an ohmic contact layer are sequentially formed thereon. In this case, the upper portion of the gate insulating layer may have a curved surface to thickly stack the conductive material for data wiring formed later. Subsequently, a metal line such as chromium is stacked and patterned to form a data line including a data line, a source electrode, a drain electrode, and a data pad crossing the gate line. Subsequently, an organic material or silicon nitride is stacked to form a protective film and patterned by dry etching to form contact holes that expose the drain electrode, the gate pad, and the data pad, respectively. Subsequently, the transparent conductive material is stacked and patterned to form a pixel electrode, an auxiliary gate pad, and an auxiliary data pad electrically connected to the drain electrode, the gate pad, and the data pad, respectively.

Delay, contact resistance, dry etching

Description

A thin film transistor substrate and a method of manufacturing the same {A THIN FILM TRANSISTOR ARRAY PANEL AND METHOD FOR MANUFACTURING THE SAME}

1A and 2B are cross-sectional views illustrating a method of forming a thin film using a photosensitive film pattern having a different thickness according to a position, in order;

3 is a thin film transistor substrate for a liquid crystal display device according to a first embodiment of the present invention;

4 is a cross-sectional view of the thin film transistor substrate illustrated in FIG. 1 taken along a line II-II;

5A, 6A, 7A, and 8A are layout views of a thin film transistor substrate, illustrating an intermediate process of manufacturing a thin film transistor substrate for a liquid crystal display device according to a first embodiment of the present invention, according to a process sequence thereof;

5B is a cross-sectional view taken along the line Vb-Vb ′ in FIG. 5A;

FIG. 6B is a cross-sectional view taken along the line VIb-VIb ′ in FIG. 6A and is a cross-sectional view showing the next step in FIG. 5B;

FIG. 7B is a cross-sectional view taken along the line VIIb-VIIb ′ in FIG. 7A and illustrating the next step in FIG. 6B;

FIG. 8B is a cross-sectional view taken along the line VIIIb-VIIIb ′ in FIG. 8A, and is a cross-sectional view showing the next step of FIG. 7A;

9 is a layout view of a thin film transistor substrate for a liquid crystal display according to a second exemplary embodiment of the present invention.

10 and 11 are cross-sectional views of the thin film transistor substrate illustrated in FIG. 9 taken along lines X-X 'and XI-XI',

12A is a layout view of a thin film transistor substrate in a first step of manufacturing according to the second embodiment of the present invention;

12B and 12C are cross-sectional views taken along the lines XIIb-XIIb 'and XIIc-XIIc' in FIG. 12A, respectively.

13A and 13B are cross-sectional views taken along the lines XIIb-XIIb 'and XIIc-XIIc' in FIG. 12A, respectively, and are cross-sectional views in the next steps of FIGS. 12B and 12C;

FIG. 14A is a layout view of a thin film transistor substrate at a next step of FIGS. 13A and 13B;

14B and 14C are cross-sectional views taken along the lines XIVb-XIVb ′ and XIVc-XIVc ′ in FIG. 14A, respectively.

15A, 16A, 17A and 15B, 16B, 17B are cross-sectional views taken along lines XIVb-XIVb 'and XIVc-XIVc' in FIG. 14A, respectively, illustrating the following steps in the order of the process. ,

18A is a layout view of a thin film transistor substrate at a next step of FIGS. 17A and 17B,                 

18B and 18C are cross-sectional views taken along the lines XVIIIb-XVIIIb 'and XVIIIc-XVIIIc', respectively, in FIG. 18A.

The present invention relates to a thin film transistor substrate and a method of manufacturing the same.

The liquid crystal display is one of the most widely used flat panel display devices. The liquid crystal display includes two substrates on which electrodes are formed and a liquid crystal layer interposed therebetween, and rearranges the liquid crystal molecules of the liquid crystal layer by applying a voltage to the electrode. Device to display an image by adjusting the amount of transmitted light.

Here, one of the two substrates is provided with a wiring for transmitting an image signal or a scanning signal and defining pixels of a matrix array, and each pixel is electrically connected to the wiring and is for removing the transmission of the image signal. A thin film transistor and a pixel electrode to which an image signal is transmitted are formed, which is called a thin film transistor substrate.

In this case, since the wiring is used as a means for transmitting the signal, it is required to uniformly transmit the signal. However, as the distance from the signal is applied, the signal is unevenly transmitted due to an increase in delay. The problem is that the characteristics are poor.

In addition, in order to transfer a desired signal through the wiring, it is desirable to minimize delay for the signal. For this purpose, a low resistance conductive material may be used, and there is a method of increasing the thickness of the wiring. However, in the case of thickly stacking a conductive material in order to increase the thickness of the wiring, stress may be severely generated at the interface between the conductive material and the substrate, thereby breaking the substrate.

On the other hand, in order to manufacture a thin film transistor through a photolithography process using a plurality of masks, it is preferable to reduce the number of masks in order to reduce the production cost.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a thin film transistor substrate including a wiring having a uniformly low resistance and a uniform signal transmission.

In order to solve this problem, in the present invention, the thickness of the wiring is gradually increased or decreased through a photolithography process using a photosensitive film pattern having a different thickness, or the lower layer on which the conductive material of the wiring is laminated has a curved surface. To form.

More specifically, a gate wiring including a gate line and a gate electrode connected thereto is formed on an insulating substrate, and a gate insulating film, a semiconductor layer, and an ohmic contact layer covering the gate wiring are sequentially formed. Subsequently, a data line is formed on the contact layer, which is separated from each other and includes a source electrode and a drain electrode made of the same layer, and a data line connected to the source electrode. In this case, the gate wiring or the data wiring is formed by dry etching through a photolithography process using a photosensitive film pattern whose thickness increases or decreases in the longitudinal direction of the gate wiring or the data wiring.

Here, a pixel electrode connected to the drain electrode may be further formed.

At this time, the photosensitive film pattern is formed by a photo process using a mask having a different transmittance depending on the position, and in order to control the transmittance, the mask preferably includes a pattern having a size smaller than the resolution of the light source used in the translucent film or the photo process.

The data line, the ohmic contact layer, and the semiconductor layer can be formed using one mask.

In addition, it is preferable to form the upper portion of the gate insulating film to have a curved surface.

Next, a thin film transistor array substrate and a method of manufacturing the same according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily implement the present invention.

Since the wiring is used as a means of transmitting a signal, it is required to minimize the uniform transmission of the signal. For this purpose, in order to uniformly transmit the signal transmitted to the wiring, the wiring is further separated from the point where the signal is applied. The thickness is gradually thickened. This prevents the delay of the signal from increasing as it moves away from the point where the signal is applied, thereby delivering the signal uniformly. At this time, in order to gradually increase the thickness of the wiring, the thickness of the photosensitive film pattern used as a mask in the photolithography process of patterning the wiring must be formed differently according to the position. This will be described in detail with reference to the drawings. Here, the case where a positive photosensitive film is used is demonstrated.

1A to 1B and 2A to 2B are cross-sectional views illustrating a method of forming a thin film using a photosensitive film pattern having a different thickness according to a position, in order.

The method of forming the thickness of the photoresist pattern differently according to the position is to form a pattern smaller than the resolution, for example, a slit or lattice pattern in the mask to control the irradiation amount of light.

First, as shown in FIG. 1A, a photosensitive film 200 is coated on a wiring thin film 300 deposited on a substrate 10. In this case, the thickness of the photoresist film 200 may be formed to be about 1.6 to 2 μm thicker than the conventional thickness, which is to make it possible to control the film remaining after development. Next, light is irradiated using the photomask 400 on which the slit 410 is formed. At this time, in order to prevent the photoresist film from being completely removed or completely removed by the slit 410 and the pattern 420, the line width of the pattern 420 located between the slits 410 or the interval between the patterns 420. The width of the slit 410 should be smaller than the resolution of the exposure machine, and in order to gradually increase the amount of light transmitted, it is preferable to form the pattern 420 by increasing the width of the slit 410 as shown in FIG. 1A.

When the light is irradiated to the photosensitive film 200 through such a mask, the polymers of the photosensitive film 200 exposed to light are decomposed by light, and as the amount of light is increased, more and more polymers are decomposed. In this case, if the exposure time is extended, all the molecules are decomposed, so it should be avoided. Subsequently, when the exposed photoresist film 200 is developed, the photoresist film may be left at a different thickness depending on the degree of decomposition of the polymers, so that the thickness of the photoresist film may be reduced or increased. In FIG. 1A, reference numeral 220 denotes a portion to be removed in the development process, and 210 denotes a portion that is left to pattern the lower wiring thin film 300 and used as an etching mask.

Subsequently, as shown in FIG. 1B, when the dry etching process is performed using the photoresist pattern 210 as an etching mask, a thin film for wiring 310 gradually increasing or decreasing in one direction may be formed.

In addition, in order to transfer a desired signal through the wiring, it is desirable to increase the thickness of the wiring to minimize the delay for the signal. To this end, in the present invention, it is necessary to increase the thickness of the wiring to disperse the stress generated as the thickness of the wiring increases. The thin film located at the bottom is formed to have a curved surface. At this time, in order to form a thin film to have a curved surface, as shown in Figure 2a, by using a mask 400 that increases or decreases the light transmittance, the photosensitive film 300 is exposed, developed, and using the remaining photosensitive film pattern as an etching mask When the lower thin film 30 is patterned, a thin film 310 having a curved surface 311 may be formed as shown in FIG. 2B. In FIG. 2A, reference numeral 210 denotes a portion where the photosensitive film remains after development, and reference numeral 220 denotes a portion where the photosensitive film is removed after development.

In this way, in order to minimize the delay of the signal applied to the wiring and to uniformly transmit the signal, the thickness of the wiring is gradually increased or decreased, or the lower thin film of the wiring is formed to have a curved surface. It is also applicable to a manufacturing method.

Next, a thin film transistor substrate and a manufacturing method for a liquid crystal display according to the present invention will be described in detail with reference to the accompanying drawings.

First, a structure of a thin film transistor substrate for a liquid crystal display according to a first embodiment of the present invention will be described in detail with reference to FIGS. 3 and 4.

3 is a thin film transistor substrate for a liquid crystal display according to a first exemplary embodiment of the present invention, and FIG. 4 is a cross-sectional view of the thin film transistor substrate shown in FIG. 3 taken along line IV-IV.

On the insulating substrate 10, a gate wiring made of an aluminum-based single film having a low resistance or a multilayer film including the same is formed. The gate wire is connected to the gate line 22 and the gate line 22 extending in the horizontal direction, and are connected to the gate pad 24 and the gate line 22 which receive a gate signal from the outside and transmit the gate signal to the gate line. A gate electrode 26 of the thin film transistor. At this time, as the gate wirings 22, 24, and 26 are moved away from the gate pad 24, which is a point where a signal is transmitted from the outside, as shown in FIG. 3, the length of the wiring between the gate electrode 26 and the gate line 22 is increased. It is formed to be gradually thicker in the direction, and as described above to prevent the delay of the gate signal transmitted to the gate wirings 22, 24, and 26 to increase so that the gate signal is uniformly transmitted.                     

On the substrate 10, a gate insulating film 30 made of silicon nitride (SiN _x ) or the like covers the gate wirings 22, 24, and 26.

A semiconductor layer 40 made of a semiconductor such as amorphous silicon is formed on the gate insulating film 30 of the gate electrode 24, and n + having a high concentration of silicide or n-type impurity is formed on the semiconductor layer 40. Resistive contact layers 55 and 56 made of a material such as hydrogenated amorphous silicon are formed, respectively.

At this time, the upper portion of the gate insulating film 30 which is not covered with the semiconductor layer 40 is formed to have a curved surface 301, which is to disperse the stress generated when the thin film is formed later. .

On the ohmic contact layers 55 and 56 and the gate insulating layer 30, data lines 62, 65, 66, and 68 formed of a single film made of a conductive material such as aluminum or a multilayer film including the same are formed. The data line is formed in a vertical direction and is connected to the data line 62 and the data line 62 defining the pixel by crossing the gate line 22 and extending to an upper portion of the ohmic contact layer 55. 65, a data pad 68 connected to one end of the data line 62 and separated from the source electrode 65 to which an image signal from the outside is applied, and the source electrode 65 with respect to the gate electrode 26. And a drain electrode 66 formed over the opposite ohmic contact layer 56. In addition, the data line may include a conductor pattern 64 for an organic capacitor that overlaps the gate line 22 to improve the storage capacitance. In this case, the gate insulating layer 30 may have a curved surface to disperse the stress generated when the conductive material is thickly formed in the manufacturing process. Therefore, a low resistance wiring can be realized by forming a thick conductive material for the data wirings 62, 64, 65, 66, and 68, thereby minimizing a delay with respect to a signal transmitted to the wiring.

In the case where the data lines 62, 64, 65, 66, and 68 are formed in two or more layers, one layer is formed of an aluminum-based conductive material having a low resistance, and the other layer is formed of a material having good contact properties with other materials. It is desirable to make. Examples thereof include Cr / Al (or Al alloy) or Al / Mo.

A passivation layer 70 made of an organic material or silicon nitride having high transmittance and excellent planarization characteristics is formed on the data lines 62, 64, 65, 66, and 68 and the semiconductor layer 40 that is not covered.

In the passivation layer 70, contact holes 76, 72, and 78 are formed to expose the drain electrode 66, the conductor pattern 64 for the organic capacitor, and the data pad 68, respectively, and together with the gate insulating layer 30. The contact hole 74 which exposes the gate pad 24 is formed.

On the passivation layer 70, a pixel electrode 82 positioned in the pixel and electrically connected to the conductive pattern conductor 64 for the storage capacitor and the drain electrode 66 is formed through the contact holes 72 and 76. In addition, the auxiliary gate pad 86 and the auxiliary data pad 88, which are connected to the gate pad 24 and the data pad 68, respectively, are formed on the passivation layer 70 through the contact holes 74 and 78. Here, the pixel electrode 82, the auxiliary gates, and the data pads 86 and 88 are made of indium tin oxide (ITO) or indium zinc oxide (IZO), which are transparent conductive materials.

Here, in the case of the passivation layer 70 of the planarized organic insulating material, as illustrated in FIGS. 1 and 2, the pixel electrode 82 overlaps the gate line 22 and the data line 62 to obtain the maximum aperture ratio. A passivation layer 70 having a low dielectric constant is formed between them to minimize delay or interference with respect to signals transmitted through the wirings 22 and 62. Here, the conductive capacitor pattern 64 for the storage capacitor connected to the pixel electrode 82 overlaps the gate line 22 to form a storage capacitor, and when the storage capacitor is insufficient, the same layer as the gate wirings 22, 24, and 26. It is also possible to add a storage capacitor wiring.

Next, a method of manufacturing the thin film transistor substrate for a liquid crystal display according to the first exemplary embodiment of the present invention will be described in detail with reference to FIGS. 3 and 4 and FIGS. 5A to 9B.

First, as illustrated in FIGS. 5A and 5B, a gate wiring conductive film made of an aluminum series metal having low resistance is laminated on the substrate 10 to a thickness of about several thousand micrometers. Subsequently, as shown in FIGS. 1A and 1B, a photo process using a mask having a gradually increasing or decreasing transmittance forms a photoresist pattern having a thickness gradually increasing or decreasing in the longitudinal direction of the wiring, and using the etching mask. Thus, the gate wiring conductive film is patterned to form a gate wiring in a horizontal direction including the gate line 22, the gate electrode 26, and the gate pad 24, and have a gradually thick thickness from the gate pad 24.

Next, as shown in FIGS. 6A and 6B, a three-layer film of a gate insulating film 30 made of silicon nitride, a semiconductor layer 40 made of amorphous silicon, and a doped amorphous silicon layer 50 is sequentially stacked and masked. The semiconductor layer 40 and the ohmic contact layer 50 are patterned on the gate insulating layer 30 facing the gate electrode 24 by patterning the semiconductor layer 40 and the doped amorphous silicon layer 50 by using a patterning process using a patterning process. Form. At this time, the curved surface 301 of the gate insulating film 30, which is not covered by the semiconductor layer 40, to form a thick conductive material for the data wiring formed later to implement the low resistance wiring, as shown in FIGS. 2A and 2B. To have). In addition, in the portion where the data line 62 and the gate line 22 intersect thereafter, a step is severely generated. As a result, the gate line 22 and the data line are prevented to prevent the data line 62 from being disconnected. It is preferable to form the thickness of the gate insulating film 30 in the portion where the 62 crosses thinner than other portions, where the gate insulating film 30 is preferably laminated for at least 5 minutes in a temperature range of 300 ° C or higher. .

Next, as shown in FIGS. 7A to 7B, a metal film made of chromium, molybdenum, molybdenum alloy, titanium, tantalum, or the like is laminated, and patterned by a photolithography process using a mask to intersect with the gate line 22. A source electrode 65 connected to the data line 62 and extending to an upper portion of the gate electrode 26, and a data pad 68 and a source electrode 65 connected to one end thereof. And a data line including a drain electrode 66 facing the source electrode 65 and a conductor pattern 64 for a storage capacitor, which are separated from the gate electrode 26 and overlap the gate line 22. do. In this case, since the gate insulating layer 30 has the curved surface 301, even if the data lines 62, 64, 65, and 66 are formed thick, the stress generated at this time may be dispersed to prevent the substrate 10 from being damaged. can do.

Subsequently, the doped amorphous silicon layer pattern 50, which is not covered by the data lines 62, 64, 65, 66, and 68, is etched to separate the gate electrode 26 from both sides, while the doped amorphous silicon on both sides is etched. The semiconductor layer pattern 40 between the layers 55 and 56 is exposed. Subsequently, in order to stabilize the surface of the exposed semiconductor layer 40, it is preferable to perform oxygen plasma.

Next, as shown in FIGS. 8A and 8B, a protective film 70 is formed by stacking an organic material or silicon nitride having a low dielectric constant and excellent planarization characteristics. In this case, similarly to the formation of the gate insulating film 30, the protective film 70 is preferably laminated for a time period of 5 minutes or more in a temperature range of 300 ° C. or higher. Subsequently, the photolithography pattern is patterned together with the gate insulating layer 30 in a photolithography process using a photoresist pattern to expose the gate pad 24, the drain electrode 66, the conductive capacitor pattern 64 for the storage capacitor, and the data pad 68. Holes 74, 76, 72 and 78 are formed. Here, when forming the contact holes 74, 76, 72, 78, the gate insulating film 30 is formed on the gate pad 24, the contact holes 76, 72, 78 are completed first. At this time, the drain electrode 66, the conductive capacitor pattern 64 and the data pad 68 through the contact holes 76, 72, and 78 are exposed to the etching conditions for a long time or over-etched. This may occur, which may increase the contact resistance of the contact portion. In order to prevent this, as shown in FIGS. 1A and 2B, a portion of the photoresist layer may be left on the gate pad 24 using a mask having a transmittance that varies depending on the position. Here, when there is no etching selectivity between the protective film 70 and the photoresist pattern, it is preferable that the thickness of the photoresist pattern is sufficient to prevent the data lines 62, 64, 65, 66, and 68 from being exposed.

Next, as shown in FIGS. 3 and 4, the ITO or IZO film is laminated and patterned using a mask to conduct the drain electrode 66 and the conductor pattern 64 for the storage capacitor through the contact holes 76 and 72. ) And an auxiliary gate pad 86 and an auxiliary data pad 88 connected to the gate pad 24 and the data pad 68, respectively, through the pixel electrode 82 and the contact holes 74 and 78 connected to each other. do. In an embodiment of the present invention, in order to minimize the contact resistance of the contact portion, it is preferable to stack IZO in a range of 200 ° C. or less at room temperature, and targets used to form the IZO thin film are In ₂ O ₃ and ZnO. It is preferable to include, and it is preferable to use the target whose content of Zn is 15-20 at%. Here, before the deposition of the IZO, it is preferable to perform a cleaning process using an aluminum etchant to remove a film having a high resistance such as AlO _X on the upper portions of the contact portions 24, 66, 68.

As described above, the method can be applied to a manufacturing method using five masks, but the same method can be applied to a manufacturing method of a thin film transistor substrate for a liquid crystal display device using four masks. This will be described in detail with reference to the drawings.

First, the unit pixel structure of the thin film transistor substrate for a liquid crystal display device completed using the four masks according to the second embodiment of the present invention will be described in detail with reference to FIGS. 9 to 11.

9 is a layout view of a thin film transistor substrate for a liquid crystal display according to a second exemplary embodiment of the present invention, and FIGS. 10 and 11 are along the XX 'line and the XI-XI' line of the thin film transistor substrate shown in FIG. 9, respectively. It is sectional drawing cut out.

First, the gate line 22, the gate pad 24, and the gate electrode 26 made of an aluminum-based metal, as in the first embodiment, are disposed on the insulating substrate 10 and moved away from the gate pad 24. The gate wiring with increasing thickness is formed. The gate wiring includes a sustain electrode 28 that is parallel to the gate line 22 on the substrate 10 and receives a voltage such as a common electrode voltage input to the common electrode of the upper plate from the outside. The storage electrode 28 overlaps with the conductive capacitor conductor 68 for the storage capacitor connected to the pixel electrode 82, which will be described later, to form a storage capacitor which improves the charge retention capability of the pixel. The pixel electrode 82 and the gate line, which will be described later, If the holding capacity generated by the overlap of (22) is sufficient, it may not be formed.

A gate insulating film 30 made of silicon nitride (SiN _x ) is formed on the gate wirings 22, 24, 26, and 28 to cover the gate wirings 22, 24, 26, and 28.

Semiconductor patterns 42 and 48 made of semiconductors such as hydrogenated amorphous silicon are formed on the gate insulating layer 30, and high concentrations of n-type impurities such as phosphorus (P) are formed on the semiconductor patterns 42 and 48. An ohmic contact layer pattern or an intermediate layer pattern 55, 56, 58 made of amorphous silicon doped with is formed.

On the ohmic contact layer patterns 55, 56 and 58, data wirings made of chromium or molybdenum or molybdenum alloy or metal such as tantalum or titanium are formed. The data line is a thin film transistor which is a branch of the data line 62 formed in the vertical direction, the data pad 68 connected to one end of the data line 62 to receive an image signal from the outside, and the data line 62. And a data line portion of the source electrode 65 of the source electrode 65. The data line portion is separated from the data line portions 62, 68, and 65, and the source electrode 65 is separated from the gate electrode 26 or the channel portion C of the thin film transistor. It also includes a conductive capacitor conductor 64 for the storage capacitor located on the drain electrode 66 and the storage electrode 28 of the thin film transistor located on the opposite side. When the sustain electrode 28 is not formed, the conductor pattern 64 for the storage capacitor is also not formed.

The data lines 62, 64, 65, 66, and 68 may be formed of a double layer including a conductive film made of chromium or molybdenum or molybdenum alloy or tantalum or titanium and a conductive film made of an aluminum-based metal.

The contact layer patterns 55, 56, and 58 serve to lower the contact resistance between the semiconductor patterns 42 and 48 below and the data lines 62, 64, 65, 66, and 68 above them. It has exactly the same form as (62, 64, 65, 66, 68). That is, the data line part intermediate layer pattern 55 is the same as the data line parts 62, 68, and 65, the drain electrode intermediate layer pattern 56 is the same as the drain electrode 66, and the storage capacitor intermediate layer pattern 58 is It is the same as the conductor pattern 64 for holding capacitors.

The semiconductor patterns 42 and 48 have the same shape as the data lines 62, 64, 65, 66, and 68 and the ohmic contact layer patterns 55, 56, and 58 except for the channel portion C of the thin film transistor. Doing. Specifically, the semiconductor capacitor 48 for the storage capacitor, the conductor pattern 64 for the storage capacitor, and the contact layer pattern 58 for the storage capacitor have the same shape, but the semiconductor pattern 42 for the thin film transistor has data wiring and contact. Slightly different from the rest of the layer pattern. That is, in the channel portion C of the thin film transistor, the data line portions 62, 68, and 65, in particular, the source electrode 65 and the drain electrode 66 are separated, and the contact layer pattern for the data line intermediate layer 55 and the drain electrode. Although 56 is also separated, the semiconductor pattern 42 for thin film transistors is not disconnected here and is connected to generate a channel of the thin film transistor.

On the data lines 62, 64, 65, 66, and 68, a protective film 70 made of an organic material or silicon nitride having a low dielectric constant and excellent planarization characteristics is formed.

The protective film 70 has contact holes 76, 78, and 72 that expose the drain electrode 66, the data pad 64, and the conductive pattern 68 for the storage capacitor, and also the gate along with the gate insulating film 30. It has a contact hole 74 which exposes the pad 24.

On the passivation layer 70, a pixel electrode 82 that receives an image signal from a thin film transistor and generates an electric field together with the electrode of the upper plate is formed. The pixel electrode 82 is made of a transparent conductive material such as ITO or IZO, and is physically and electrically connected to the drain electrode 66 through the contact hole 76 to receive an image signal. The pixel electrode 82 also overlaps with the neighboring gate line 22 and the data line 62 to increase the aperture ratio, but may not overlap. In addition, the pixel electrode 82 is also connected to the storage capacitor conductor pattern 64 through the contact hole 72 to transmit an image signal to the conductor pattern 64. On the other hand, an auxiliary gate pad 86 and an auxiliary data pad 88 connected to the gate pad 24 and the data pad 68 through the contact holes 74 and 78, respectively, are formed. 68) and to protect the pads and the adhesion of the external circuit device, and is not essential, their application is optional.

Next, a method of manufacturing a thin film transistor substrate for a liquid crystal display device having the structure of FIGS. 9 to 11 using four masks will be described in detail with reference to FIGS. 9 to 11 and 12A to 19C. .

 First, as shown in FIGS. 12A to 12C, the gate lines 22 and the gate pads are stacked on the substrate 10 by a photolithography process using a mask by laminating an aluminum-based metal in a single layer as in the first embodiment. The gate wiring including the gate electrode 26 and the sustain electrode 28 is formed to increase in thickness as it moves away from the gate pad 24.

Next, as shown in FIGS. 13A and 13B, the gate insulating film 30, the semiconductor layer 40, and the intermediate layer 50 made of silicon nitride are respectively 1,500 kV to 5,000 kPa and 500 kPa to 2,000 using chemical vapor deposition. 증착, 300 600 to 600 연속 of continuous deposition, and then a conductor layer 60 including a metal film made of chromium is deposited to a thickness of 1,500 Å to 3,000 Å by sputtering or the like, and then on the photoresist film 110 thereon. Is applied in a thickness of 1 μm to 2 μm. In this case, the gate insulating film 30 is preferably laminated for at least 5 minutes in a temperature range of 300 ° C. or higher. Here, in order to prevent AlO _{X from} being formed on the aluminum-based metal films 22, 24, and 26 before depositing the gate insulating layer 30, a cleaning process may be performed with a plasma containing hydrogen, helium, or argon. in-situ).

Thereafter, the photosensitive film 110 is irradiated with light through a mask and then developed to form photosensitive film patterns 112 and 114 as shown in FIGS. 14B and 14C. In this case, among the photoresist patterns 112 and 114, the channel portion C of the thin film transistor, that is, the first portion 114 positioned between the source electrode 65 and the drain electrode 66, is the data wiring portion A, that is, the data. The thickness of the wirings 62, 64, 65, 66, and 68 is smaller than that of the second portion 112 positioned at the portion where the wirings 62, 64, 65, 66, and 68 are to be formed. At this time, the ratio of the thickness of the photoresist film 114 remaining in the channel portion C to the thickness of the photoresist film 112 remaining in the data wiring portion A should be different depending on the process conditions in the etching process described later. It is preferable to make the thickness of the 1st part 114 into 1/2 or less of the thickness of the 2nd part 112, for example, it is good that it is 4,000 Pa or less.

As such, there may be various methods of varying the thickness of the photoresist layer according to the position. In order to control the light transmittance in the A region, a slit or lattice-shaped pattern is mainly formed or a translucent film is used.

At this time, the line width of the pattern located between the slits or the interval between the patterns, that is, the width of the slits is preferably smaller than the resolution of the exposure machine used during exposure, in the case of using a translucent film in order to control the transmittance when manufacturing a mask Thin films having different transmittances or thin films having different thicknesses may be used.

Subsequently, etching is performed on the photoresist pattern 114 and the underlying layers, that is, the conductor layer 60, the intermediate layer 50, and the semiconductor layer 40. In this case, the data line and the lower layer of the data line remain in the data wiring portion A, and only the semiconductor layer should remain in the channel portion C, and the upper three layers 60, 50, 40 must be removed to expose the gate insulating film 30.

First, as shown in FIGS. 15A and 15B, the exposed conductor layer 60 of the other portion B is removed to expose the lower intermediate layer 50. In this process, both a dry etching method and a wet etching method may be used. In this case, the conductor layer 60 may be etched and the photoresist patterns 112 and 114 may be hardly etched. However, in the case of dry etching, it is difficult to find a condition in which only the conductor layer 60 is etched and the photoresist patterns 112 and 114 are not etched, so that the photoresist patterns 112 and 114 may also be etched together. In this case, the thickness of the first portion 114 is thicker than that of the wet etching so that the first portion 114 is removed in this process so that the lower conductive layer 60 is not exposed.

When the conductor layer 60 is any one of Mo or MoW alloy, Al or Al alloy, and Ta, either dry etching or wet etching can be used. However, since Cr is not easily removed by the dry etching method, it is preferable to use only wet etching if the conductor layer 60 is Cr. In the case of wet etching in which the conductor layer 60 is Cr, CeNHO ₃ may be used as an etchant. In the case of dry etching in which the conductor layer 60 is Mo or MoW, the mixed gas or CF of CF ₄ and HCl may be used as the etching gas. A mixed gas of ₄ and O ₂ can be used, and in the latter case, the etching ratio to the photoresist film is almost the same.

In this way, as shown in Figs. 15A and 15B, only the conductor layers of the channel portion C and the data wiring portion B, that is, the conductor pattern 67 for the source / drain and the conductor pattern 64 for the storage capacitor, are shown. All of the conductor layer 60 of the remaining portion B is removed, revealing the underlying intermediate layer 50. The remaining conductor patterns 67 and 64 have the same shape as the data lines 62, 64, 65, 66 and 68 except that the source and drain electrodes 65 and 66 are connected without being separated. In addition, when dry etching is used, the photoresist patterns 112 and 114 are also etched to a certain thickness.

Subsequently, as shown in FIGS. 16A and 16B, the exposed intermediate layer 50 of the other portion B and the semiconductor layer 40 below it are simultaneously removed together with the first portion 114 of the photosensitive film by a dry etching method. do. At this time, etching is performed under the condition that the photoresist patterns 112 and 114, the intermediate layer 50, and the semiconductor layer 40 (the semiconductor layer and the intermediate layer have almost no etching selectivity) are simultaneously etched, and the gate insulating layer 30 is not etched. In particular, it is preferable to etch under conditions where the etching ratios of the photoresist patterns 112 and 114 and the semiconductor layer 40 are almost the same. For example, by using a mixed gas of SF ₆ and HCl or a mixed gas of SF ₆ and O ₂ , the two films can be etched to almost the same thickness. When the etch ratios of the photoresist patterns 112 and 114 and the semiconductor layer 40 are the same, the thickness of the first portion 114 should be equal to or smaller than the sum of the thicknesses of the semiconductor layer 40 and the intermediate layer 50.

This removes the first portion 114 of the channel portion C, revealing the source / drain conductor pattern 67, as shown in FIGS. 16A and 16B, and the intermediate layer 50 of the other portion B. And the semiconductor layer 40 is removed to expose the gate insulating layer 30 thereunder. On the other hand, since the second portion 112 of the data wiring portion A is also etched, the thickness becomes thin. In this step, the semiconductor patterns 42 and 48 are completed. Reference numerals 57 and 58 denote intermediate layer patterns under the source / drain conductor patterns 67 and intermediate layer patterns under the storage capacitor conductor patterns 64, respectively.

Subsequently, ashing removes photoresist residue remaining on the surface of the source / drain conductor pattern 67 of the channel portion C.

Next, as illustrated in FIGS. 17A and 17B, the source / drain conductor pattern 67 of the channel portion C and the source / drain interlayer pattern 57 below are etched and removed. In this case, the etching may be performed only by dry etching with respect to both the source / drain conductor pattern 67 and the intermediate layer pattern 57. The etching may be performed by wet etching on the source / drain conductor pattern 67. 57 may be performed by dry etching. In the former case, it is preferable to perform etching under a condition in which the etching selectivity of the source / drain conductor pattern 67 and the interlayer pattern 57 is large, which is difficult to find the etching end point when the etching selectivity is not large. This is because it is not easy to adjust the thickness of the semiconductor pattern 42 remaining in Fig. 2). For example, those of etching the SF ₆ and O ₂ by using the mixed gas of the source / drain conductive pattern 67. In the latter case of alternating between wet etching and dry etching, the side surface of the conductive pattern 67 for wet etching of the source / drain is etched, but the intermediate layer pattern 57 which is dry etched is hardly etched, and thus is formed in a step shape. Examples of the etching gas used to etch the intermediate layer pattern 57 and the semiconductor pattern 42 include the aforementioned mixed gas of CF ₄ and HCl or mixed gas of CF ₄ and O ₂ , and CF ₄ and O _{Using 2} can leave the semiconductor pattern 42 in a uniform thickness. In this case, as shown in FIG. 15B, a portion of the semiconductor pattern 42 may be removed to reduce the thickness, and the second portion 112 of the photoresist pattern may also be etched to a certain thickness at this time. At this time, the etching should be performed under the condition that the gate insulating film 30 is not etched, and the photoresist film is not exposed so that the second portion 112 is etched so that the data lines 62, 64, 65, 66, and 68 underneath are not exposed. It is a matter of course that the pattern is thick.

In this way, the source electrode 65 and the drain electrode 66 are separated, thereby completing the data lines 62, 64, 65, 66, and 68 and the contact layer patterns 55, 56, and 58 under the data lines.

Finally, the second photoresist layer 112 remaining in the data wiring portion A is removed. However, the removal of the second portion 112 may be made after removing the conductor pattern 67 for the channel portion C source / drain and before removing the intermediate layer pattern 57 thereunder.

As mentioned earlier, wet and dry etching can be alternately used or only dry etching can be used. In the latter case, since only one type of etching is used, the process is relatively easy, but it is difficult to find a suitable etching condition. On the other hand, in the former case, the etching conditions are relatively easy to find, but the process is more cumbersome than the latter.

After forming the data wirings 62, 64, 65, 66, and 68 in this manner, as shown in FIGS. 18A to 18C, an organic insulating material or silicon nitride is deposited to form the protective film 70, and a mask is used. The protective film 70 is etched together with the gate insulating film 30 to expose the drain electrode 66, the gate pad 24, the data pad 68, and the conductive pattern 64 for the storage capacitor, respectively. 74, 78, 72).

Finally, as shown in Figs. 9 to 11, the IZO layer or the ITO layer having a thickness of 400 kHz to 500 kHz is deposited and etched using a mask to form the drain electrode 66 and the conductor pattern 64 for the storage capacitor. A pixel electrode 82 connected to the second electrode, an auxiliary gate pad 86 connected to the gate pad 24, and an auxiliary data pad 88 connected to the data pad 68 are formed. In this case, the etching solution for patterning the IZO of the pixel electrode 82, the auxiliary gate pad 86, and the auxiliary data pad 88 uses a chromium etchant that is used to etch a metal film of chromium (Cr). It does not corrode the metal to prevent the corrosion of the aluminum-based metal exposed in the contact structure, and (HNO ₃ / (NH ₄ ) ₂ Ce (NO ₃ ) ₆ / H ₂ O) and the like as an etchant. Here, the gas used in the pre-heating process before laminating the IZO is the metal oxide film remaining on the upper portions of the metal films 24, 64, 66, and 68 where the contact holes 72, 74, 76, and 78 are exposed. It is preferable to perform the cleaning process using an aluminum etchant, and the aluminum etchant preferably contains HNO ₃ , H ₃ PO ₄ , CH ₃ COOH and deionized water.

In the second embodiment of the present invention, the data wirings 62, 64, 65, 66, and 68 and the contact layer patterns 55, 56, 58 and the semiconductor pattern 42 below the data wirings 62, 64, 65, 66, and 68, as well as the effects of the first embodiment. , 48) may be formed using one mask, and the source electrode 65 and the drain electrode 66 may be separated in this process to simplify the manufacturing process.

As described above, in the photolithography process using a photosensitive film pattern having a different thickness according to the position of the present invention, the wiring is gradually formed to increase in thickness from a point where an external signal is applied, thereby uniformly transmitting a signal applied to the wiring. have. In addition, the lower layer of the wiring is formed to have a curved surface to disperse the stress generated when the wiring is thickly stacked to form a thick wiring with low resistance, thereby minimizing a delay for a signal applied to the wiring. .

Claims (18)

A gate wiring on the insulating substrate, the gate wiring including a gate electrode connected to the gate line A gate insulating film covering the gate wiring, A semiconductor layer formed on the gate insulating film, A data line formed on the gate insulating layer, the data line including a data line, a source electrode connected to the data line and adjacent to the gate electrode, and a drain electrode positioned opposite to the source electrode with respect to the gate electrode; Including; The thin film transistor substrate of which the gate line or the data line is formed to increase or decrease in thickness. In claim 1, The gate line further includes a gate pad connected to an end of the gate line, The data line further includes a data pad connected to an end of the data line. The gate line is formed thicker away from the gate pad, And the data line is formed thicker away from the data pad. In claim 1, The thin film transistor substrate further comprising a pixel electrode connected to the drain electrode. In claim 1, The thin film transistor substrate of claim 1, wherein an upper portion of the gate insulating layer on which the data line is formed has a curved surface. Forming a gate wiring including a gate line and a gate electrode connected to the insulating substrate, Forming a gate insulating film covering the gate wiring; Forming a semiconductor layer on the gate insulating film, Forming an ohmic contact layer over the semiconductor layer; Forming a data line formed on the contact layer and separated from each other and including a source electrode and a drain electrode formed of the same layer, and a data line connected to the source electrode; Including; And forming the gate line or the data line by dry etching through a photolithography process using a photoresist pattern having a thickness increasing or decreasing in a length direction of the gate line or the data line. In claim 5, And forming a pixel electrode connected to the drain electrode. In claim 5, The photoresist pattern is formed by a photo process using a mask having a different transmittance according to a position, and the mask includes a slit pattern or a lattice pattern to control the transmittance, and the interval between the slit patterns or the lattice pattern is a semitransparent film or A method of manufacturing a thin film transistor substrate comprising a pattern having a size smaller than a resolution of a light source used in the photolithography process. In claim 5, And the data line, the ohmic contact layer, and the semiconductor layer are formed using a single mask. In claim 5, A method of manufacturing a thin film transistor substrate, the upper portion of the gate insulating film is formed to have a curved surface. A gate wiring on the insulating substrate, the gate wiring including a gate electrode connected to the gate line; A gate insulating film covering the gate wiring, and an upper portion formed of a curved surface; A semiconductor layer formed on the gate insulating film, Data formed on the curved surface of the gate insulating layer, the data line including a data line, a source electrode connected to the data line, and a drain electrode adjacent to the gate electrode and positioned opposite to the source electrode with respect to the gate electrode; A thin film transistor substrate comprising wiring. In claim 10, The thin film transistor substrate of which the gate wiring or the data wiring is formed to increase or decrease in thickness. In claim 11, The gate line further includes a gate pad connected to an end of the gate line, The data line further includes a data pad connected to an end of the data line. The gate line is formed thicker away from the gate pad, And the data line is formed thicker away from the data pad. In claim 10, The thin film transistor substrate further comprising a pixel electrode connected to the drain electrode. Forming a gate wiring including a gate line and a gate electrode connected to the insulating substrate, Forming a gate insulating film covering the gate wiring; Forming a semiconductor layer on the gate insulating film, Forming an ohmic contact layer over the semiconductor layer; Forming a data line formed on the contact layer and separated from each other and including a source electrode and a drain electrode formed of the same layer, and a data line connected to the source electrode; Including; And forming a gate surface of the gate insulating layer to be a curved surface through a photolithography process using a photoresist pattern having a different thickness. The method of claim 14, And forming a pixel electrode connected to the drain electrode. The method of claim 14, The photoresist pattern is formed by a photo process using a mask having a different transmittance according to a position, and the mask includes a slit pattern or a lattice pattern to control the transmittance, and the interval between the slit patterns or the lattice pattern is a semitransparent film or A method of manufacturing a thin film transistor substrate comprising a pattern having a size smaller than a resolution of a light source used in the photolithography process. The method of claim 14, And the data line, the ohmic contact layer, and the semiconductor layer are formed using a single mask. In claim 5, The gate wiring or the data wiring may be patterned by dry etching through a photolithography process using a photoresist pattern having a different thickness, thereby increasing or decreasing the thickness in the longitudinal direction of the gate wiring or the data wiring. Manufacturing method.

Images