KR20010017529A - Thin film transistor substrate for liquid crystal display and manufacturing method thereof - Google Patents

Abstract

PURPOSE: A TFT-LCD substrate and a method of fabricating the same are provided to prevent the corrosion or erosion of a gate line by using the upper film of doped silicon, secure the reliability and simplify a TFT-LCD substrate fabricating method. CONSTITUTION: A conductive film(202) of doped silicon is formed on the upper of an aluminium system metalic film(201). Each gate wiring(22,24) including a gate line(22) and a gate electrode is formed by patterning the conductive film(202) and the metalic film(201). A semiconductor layer, each data wiring(62,64,68) and an ohmic contact layer(56) are formed by using one mask. The conductive film(202) of doped silicon intervenes between a gate pad(201) of aluminium system metal and an auxiliary gate pad(86) of ITO(indium tin oxide). Thereby, the corrosion of the pad and the wiring are prevented. The conductive film(202) protects a low resistance aluminium alloy. Thereby, the short or the corrosion of the wiring are prevented.

Description

Thin film transistor substrate for liquid crystal display device and manufacturing method therefor {THIN FILM TRANSISTOR SUBSTRATE FOR LIQUID CRYSTAL DISPLAY AND MANUFACTURING METHOD THEREOF}

The present invention relates to a thin film transistor substrate for a liquid crystal display device and a manufacturing method thereof.

The liquid crystal display is one of the most widely used flat panel display devices. The liquid crystal display includes two substrates on which electrodes are formed and a liquid crystal layer interposed therebetween, and rearranges the liquid crystal molecules of the liquid crystal layer by applying a voltage to the electrode. By controlling the amount of light transmitted.

Among the liquid crystal display devices, a liquid crystal display device having a thin film transistor for forming an electrode on each of two substrates and switching a voltage applied to the electrode is generally used. The thin film transistor is generally formed on one of two substrates.

The substrate on which the thin film transistor is formed is generally manufactured through a photolithography process using a mask. At this time, it is preferable to reduce the number of masks in order to reduce the production cost.

On the other hand, in order to prevent signal delay, the wiring is generally made of a material such as aluminum (Al) or aluminum alloy (Al alloy) having a low resistance. However, in the case of using indium tin oxide (ITO) in the pad part to secure the pad part as in a liquid crystal display device, aluminum or aluminum alloy and ITO have poor contact characteristics, and thus intervene with other metals such as molybdenum series or chromium. The aluminum or aluminum alloy of the pad part must be removed.

However, when chromium is used, wet etching is used to remove aluminum or an aluminum alloy from the pad part, so undercut occurs, and the ITO film formed on the pad part is broken, thereby weakening the structure of the pad part. Corrosion will occur. In addition, since the molybdenum-based metal has relatively poor corrosion resistance and has a property of being eroded by the ITO etchant, it is difficult to completely solve the corrosion of the pad part.

An object of the present invention is to provide a method of manufacturing a thin film transistor substrate for a liquid crystal display device capable of preventing corrosion or erosion of a signal line.

In addition, another object of the present invention is to ensure the reliability of the pad portion and to simplify the manufacturing method of the thin film transistor substrate for a liquid crystal display device.

1 is a thin film transistor substrate for a liquid crystal display device according to a first embodiment of the present invention;

FIG. 2 is a cross-sectional view of the thin film transistor substrate illustrated in FIG. 1 taken along the line II-II.

3A, 4A, 5A, and 6A are layout views of a thin film transistor substrate in an intermediate process of manufacturing according to an embodiment of the present invention,

3B is a cross-sectional view taken along the line IIIb-IIIb ′ in FIG. 3A;

4B is a cross-sectional view taken along the line IVb-IVb ′ in FIG. 4A and is a cross-sectional view showing the next step in FIG. 3B;

FIG. 5B is a cross-sectional view taken along the line Vb-Vb ′ in FIG. 5A and is a cross-sectional view showing the next step in FIG. 4B;

FIG. 6B is a cross-sectional view taken along the line VIb-VIb ′ in FIG. 6A and is a cross-sectional view showing the next step in FIG. 5B;

7 is a layout view of a thin film transistor substrate for a liquid crystal display according to a second exemplary embodiment of the present invention.

8 and 9 are cross-sectional views of the thin film transistor substrate shown in FIG. 7 taken along lines VIII-VIII 'and IX-IX',

10A is a layout view of a thin film transistor substrate in a first step of manufacturing according to the second embodiment of the present invention;

10B and 10C are cross-sectional views taken along the lines Xb-Xb 'and Xc-Xc' in FIG. 10A, respectively.

11A and 11B are cross-sectional views taken along the lines Xb-Xb 'and Xc-Xc' of FIG. 10A, respectively, and are cross-sectional views of the next steps of FIGS. 10B and 10C.

12A is a layout view of a thin film transistor substrate in FIGS. 11A and 11B next steps;

12B and 12C are cross-sectional views taken along the lines XIIb-XIIb 'and XIIc-XIIc' in FIG. 12A, respectively.

13A, 14A, 15A and 13B, 14B, and 15B are cross-sectional views taken along the lines XIIb-XIIb 'and XIIc-XIIc' in FIG. 12A, respectively, illustrating the following steps in the order of the process. ,

FIG. 16A is a layout view of a thin film transistor substrate in the next steps of FIGS. 15A and 15B;

16B and 16C are cross-sectional views taken along lines XVIb-XVIb 'and XVIc-XVIc', respectively, in FIG. 16A.

In order to solve this problem, a conductive film made of doped silicon is formed on the aluminum-based metal film to form wiring.

According to the present invention, a gate line including a gate line and a gate electrode connected to the gate line is formed by sequentially stacking and patterning a conductive film made of a metal film having a low resistance and a doped silicon on an insulating substrate. Subsequently, a gate insulating film is formed, a semiconductor layer is formed on the gate insulating film, and a data line intersecting the gate line and a source electrode connected to the data line and positioned adjacent to the source electrode are adjacent to the gate electrode and the gate electrode. A data line including a drain electrode is formed. Next, a passivation layer is stacked and a pixel electrode connected to the drain electrode is formed on the passivation layer.

Here, the metal film is preferably formed of an aluminum-based metal, and the conductive film may be formed of amorphous silicon or polycrystalline silicon.

In addition, the manufacturing method of the thin film transistor substrate for a liquid crystal display device according to the present invention may be formed using five masks, but may be formed using four masks to simplify the manufacturing cost and process.

In the case of using four masks, a photoresist pattern having a partly different thickness is used as an etching mask, and the photoresist pattern may be formed using a mask having a partly different transmittance.

In this case, the gate wiring and the data wiring further include gate pads and data pads that receive scan signals and image signals from the outside and transfer the scan signals and the image signals to the gate lines and the data lines, respectively, and contact holes of a protective film or a gate insulating film in the same layer as the pixel electrode. An auxiliary gate pad and an auxiliary data pad connected to the gate pad and the data pad may be further formed through the gate pad and the data pad.

Here, the pixel electrode is preferably formed of ITO.

The semiconductor device may further include an ohmic contact layer between the semiconductor layer and the data line, and the data line, the contact layer, and the semiconductor layer may be formed using one mask.

Then, the liquid crystal display according to an exemplary embodiment of the present invention and a manufacturing method thereof will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily implement the present invention.

First, a structure of a thin film transistor substrate for a liquid crystal display according to a first embodiment of the present invention will be described in detail with reference to FIGS. 1 and 2.

1 is a thin film transistor substrate for a liquid crystal display device according to a first embodiment of the present invention, and FIG. 2 is a cross-sectional view of the thin film transistor substrate shown in FIG. 1 taken along the line II-II.

A gate wiring including a lower layer 201 made of aluminum-based or molybdenum-based or the like and a top layer 202 made of doped silicon is formed on the insulating substrate 10. The gate wiring is connected to the gate line 22 and the end of the gate line 22 extending in the horizontal direction, and the branch of the gate pad 24 and the gate line 22 which receive a gate signal from the outside and transfer the gate signal to the gate line. A gate electrode 26 of the phosphor thin film transistor. In this case, the gate pad 24 is formed only of the lower layer 201.

On the substrate 10, a gate insulating film 30 made of silicon nitride (SiN _x ) covers the gate wirings 22, 24, and 26, and the gate insulating film 30 is provided with a gate pad along with a protective film 70 formed thereafter. It has a contact hole 74 that exposes 24.

A semiconductor layer 40 made of a semiconductor such as amorphous silicon is formed on the gate insulating film 30 of the gate electrode 24 in an island shape, and silicide or n-type impurities are doped with high concentration on the semiconductor layer 40. Resistive contact layers 54 and 56 made of a material such as n + hydrogenated amorphous silicon are formed, respectively.

On the ohmic contacts 54 and 56 and the gate insulating film 30, data lines 62, 64, 66 and 68 made of chromium (Cr) or molybdenum-tungsten alloy are formed. The data line is formed in the vertical direction and crosses the gate line 22 to define a pixel, the data line 62 and the branch of the data line 62 and the source electrode 64 extending to the upper portion of the ohmic contact layer 54. ), Which is connected to one end of the data line 62 and is separated from the data pad 68 and the source electrode 64 to which an image signal from the outside is applied, and is opposite to the source electrode 64 with respect to the gate electrode 26. The drain electrode 68 is formed on the ohmic contact layer 56.

The passivation layer 70 is formed on the data lines 62, 64, 66, and 68 and the semiconductor layer 40 not covered by the data lines 62. In the passivation layer 90, contact holes 76 and 78 respectively exposing the drain electrode 66 and the data pad 68 are formed, and the upper layer 202 of the gate pad 24 together with the gate insulating layer 30 is formed. The contact hole 74 which exposes the opening is formed.

The pixel electrode 82 connected to the drain electrode 66 is formed on the passivation layer 70 of the pixel through the contact hole 76. The gate pad 24 and the data pad are respectively formed through the contact holes 74 and 78, respectively. An auxiliary gate pad 86 and an auxiliary data pad 88 which are connected to the 68 are formed.

1 and 2, the pixel electrode 82 overlaps with the gate line 22 to form a storage capacitor. When the storage capacitor is insufficient, the pixel electrode 82 is disposed on the same layer as the gate wirings 22, 24, and 26. It is also possible to add a storage capacitor wiring.

In the structure according to the embodiment of the present invention, the pad portion is formed by contacting the gate pad 201 made of aluminum-based metal and the auxiliary gate pad 86 made of ITO with an upper layer 202 made of doped silicon. Not only can the corrosion be prevented from being negatively formed, but also the upper film 202 of the gate wirings 22, 24, and 26 can be formed of silicon to prevent corrosion of the wiring.

Next, a method of manufacturing a thin film transistor substrate for a liquid crystal display device having a structure according to this embodiment will be described in detail with reference to FIGS. 1 to 2 and FIGS. 3A to 8B.

3A, 4A, 5A, and 6A are layout views of a thin film transistor substrate during an intermediate process of manufacturing according to an embodiment of the present invention, and are shown in sequence according to the manufacturing sequence. FIG. 3B is a cross-sectional view taken along the line IIIb-IIIb 'in FIG. 3A, and FIG. 4B is a cross-sectional view taken along the line IVb-IVb' in FIG. 4A, and is a cross-sectional view showing the next step of FIG. 3B. FIG. 5A is a cross-sectional view taken along the line Vb-Vb 'of FIG. 4B, and FIG. 6B is a cross-sectional view taken along the line VIb-VIb' of FIG. 6A. It is sectional drawing.

First, as shown in FIGS. 3A and 3B, a lower film 201 made of an aluminum-based or molybdenum-based conductive film having a low resistance on the substrate 10 and an upper film 202 made of a conductive film of silicon doped. Are sequentially stacked and patterned to form a horizontal gate line including a gate line 22, a gate electrode 26, and a gate pad 24 including the lower layer 201 and the upper layer 202.

In this case, the upper layer 202 of the doped silicon is sputtered using a silicon target (Si Target) containing impurities such as phosphorus or boron, and Si gas such as SiH ₄ and SiH ₂ Cl ₂ . Gases containing impurities such as PH ₃ , B ₂ H ₆ and the like are properly mixed and deposited by chemical vapor deposition, or pure Si is deposited by chemical vapor deposition or sputtering, and then impurities of phosphorus or boron through ion implantation It can be formed by a method such as doping.

In the case of using the sputtering method, the upper layer 202 may be continuously formed by an in-situ process together with the aluminum-based lower layer 201, thereby simplifying the process.

In addition, the upper film 202 may be formed of amorphous silicon as in the embodiment of the present invention, but may also be formed of polycrystalline silicon.

Next, as shown in FIGS. 4A and 4B, a three-layer film of the gate insulating film 30, the semiconductor layer 40 made of amorphous silicon, and the doped amorphous silicon layer 50 is successively laminated and patterned using a mask. The semiconductor layer 40 and the doped amorphous silicon layer 50 are patterned to form an island-like semiconductor layer 40 and an ohmic contact layer 50 on the gate insulating layer 30 facing the gate electrode 24. .

Next, as shown in FIGS. 5A to 5B, molybdenum or molybdenum alloy or chromium is laminated, and then patterned by a photo process using a mask to intersect the data line 62 and the data line 62 with the gate line 22. ), The source electrode 64 and the data line 62 connected to the gate electrode 26 and the upper portion of the gate electrode 26 are separated from the data pad 68 and the source electrode 64 connected to one end thereof. ) And a data line including a drain electrode 66 facing the source electrode 66.

Subsequently, the doped amorphous silicon layer pattern 50, which is not covered by the data lines 62, 64, 66, and 68, is etched and separated on both sides of the gate electrode 26, while both doped amorphous silicon layers ( The semiconductor layer pattern 40 between 54 and 56 is exposed.

6A and 6B, a protective film 70 made of silicon nitride or an organic insulating film is laminated, and then patterned by dry etching together with the gate insulating film 30 in a photolithography process using a mask, thereby forming a gate. Contact holes 74, 76, and 78 are formed to expose the pad 24, the drain electrode 66, and the data pad 68.

Next, as shown in FIGS. 1 and 2, the ITO film is laminated and patterned using a mask to contact the pixel electrodes 82 and the contact holes 74 and 78 connected to the drain electrode 66 through the contact holes 76. The auxiliary gate pads 86 and the auxiliary data pads 88 connected to the gate pads 24 and the data pads 68 are respectively formed through the?

In the manufacturing method according to the exemplary embodiment of the present invention, the upper layer 202 of the gate wiring is formed of doped silicon to prevent the ITO and aluminum-based metals from contacting each other before the ITO layer is laminated. Therefore, the pad part can be prevented from being corroded, thereby ensuring the reliability of the pad part, and the gate wirings 22, 24, and 26 can be prevented from being disconnected or eroded.

As described above, the method can be applied to a manufacturing method using a five-sheet mask, but the same method can be applied to a manufacturing method of a thin film transistor substrate for a liquid crystal display device using a four-mask. This will be described in detail with reference to the drawings.

First, a unit pixel structure of a thin film transistor substrate for a liquid crystal display device completed using four masks according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 7 to 9.

FIG. 7 is a layout view of a thin film transistor substrate for a liquid crystal display device according to a second exemplary embodiment of the present invention, and FIGS. 8 and 9 are lines VIII-VIII 'and IX-IX', respectively, of the thin film transistor substrate shown in FIG. A cross-sectional view taken along the line.

First, a gate line including a gate line 22, a gate pad 24, and a gate electrode 26 formed of a lower layer 201 and an upper layer 202 on the insulating substrate 10, as in the first embodiment. Is formed. The gate wiring includes a sustain electrode 28 that is parallel to the gate line 22 on the substrate 10 and receives a voltage such as a common electrode voltage input to the common electrode of the upper plate from the outside. The storage electrode 28 overlaps with the conductive capacitor conductor 68 for the storage capacitor connected to the pixel electrode 82, which will be described later, to form a storage capacitor which improves the charge retention capability of the pixel. The pixel electrode 82 and the gate line, which will be described later, If the holding capacity generated by the overlap of (22) is sufficient, it may not be formed.

A gate insulating film 30 made of silicon nitride (SiN _x ) is formed on the gate wirings 22, 24, 26, and 28 to cover the gate wirings 22, 24, 26, and 28.

Semiconductor patterns 42 and 48 made of semiconductors such as hydrogenated amorphous silicon are formed on the gate insulating layer 30, and high concentrations of n-type impurities such as phosphorus (P) are formed on the semiconductor patterns 42 and 48. An ohmic contact layer pattern or an intermediate layer pattern 55, 56, 58 made of amorphous silicon doped with is formed.

On the ohmic contact layer patterns 55, 56, and 58, a data line made of a conductive material such as Mo or MoW alloy, Cr, Al or Al alloy, and Ta is formed. The data line is a thin film transistor which is a branch of the data line 62 formed in the vertical direction, the data pad 64 connected to one end of the data line 62 to receive an image signal from the outside, and the data line 62. And a data line portion of the source electrode 65 of the source electrode 65, separated from the data line portions 62, 64, and 65, of the source electrode 65 with respect to the gate electrode 26 or the channel portion C of the thin film transistor. It also includes a conductive capacitor conductor 68 for the storage capacitor located on the drain electrode 66 and the storage electrode 28 of the thin film transistor located on the opposite side. When the sustain electrode 28 is not formed, the conductor pattern 68 for the storage capacitor is also not formed.

The data lines 62, 64, 65, 66, 68 may also be formed in a single layer like the gate lines 22, 24, 26, 28, but may be formed in a double layer or a triple layer. Of course, when forming more than two layers, it is preferable that one layer is made of a material having a low resistance and the other layer is made of a material having good contact properties with other materials.

The contact layer patterns 55, 56, and 58 serve to lower the contact resistance between the semiconductor patterns 42 and 48 below and the data lines 62, 64, 65, 66, and 68 above them. It has exactly the same form as (62, 64, 65, 66, 68). That is, the data line part intermediate layer pattern 55 is the same as the data line parts 62, 64 and 65, the drain electrode intermediate layer pattern 56 is the same as the drain electrode 66, and the storage capacitor intermediate layer pattern 58 is It is the same as the conductor pattern 68 for holding capacitors.

The semiconductor patterns 42 and 48 have the same shapes as the data lines 62, 64, 65, 66, and 68 and the ohmic contact layer patterns 55, 56, and 57 except for the channel portion C of the thin film transistor. Doing. Specifically, the semiconductor capacitor 48 for the storage capacitor, the conductor pattern 68 for the storage capacitor, and the contact layer pattern 58 for the storage capacitor have the same shape, but the semiconductor pattern 42 for the thin film transistor has data wiring and contact. Slightly different from the rest of the layer pattern. That is, the data line parts 62, 64, 65, in particular, the source electrode 65 and the drain electrode 66 are separated from the channel portion C of the thin film transistor, and the contact layer pattern for the data line intermediate layer 55 and the drain electrode is separated. Although 56 is also separated, the semiconductor pattern 42 for thin film transistors is not disconnected here and is connected to generate a channel of the thin film transistor.

The passivation layer 70 is formed on the data wires 62, 64, 65, 66, and 68, and the passivation layer 70 forms the drain electrode 66, the data pad 64, and the conductive pattern 68 for the storage capacitor. The contact holes 71, 73, and 74 are exposed, and the contact holes 72 are exposed to expose the gate pad 24 together with the gate insulating film 30. As shown in FIG. The passivation layer 70 may be made of an organic insulating material such as silicon nitride or acrylic.

On the passivation layer 70, a pixel electrode 82 that receives an image signal from a thin film transistor and generates an electric field together with the electrode of the upper plate is formed. The pixel electrode 82 is made of a transparent conductive material such as indium tin oxide (ITO), and is physically and electrically connected to the drain electrode 66 through the contact hole 71 to receive an image signal. The pixel electrode 82 also overlaps with the neighboring gate line 22 and the data line 62 to increase the aperture ratio, but may not overlap. In addition, the pixel electrode 82 is also connected to the storage capacitor conductor pattern 68 through the contact hole 74 to transmit an image signal to the conductor pattern 68. On the other hand, an auxiliary gate pad 84 and an auxiliary data pad 86 connected to the gate pad 24 and the data pad 64 through the contact holes 72 and 73, respectively, are formed. , 64) and to protect the pads and the adhesion of the external circuit device, it is not essential, and their application is optional.

Although transparent ITO has been used as an example of the material of the pixel electrode 82, an opaque conductive material may be used for the reflective liquid crystal display device.

Next, a method of manufacturing a thin film transistor substrate for a liquid crystal display device having the structure of FIGS. 7 to 9 using four masks will be described in detail with reference to FIGS. 7 to 19 and 10A to 16C. .

First, as shown in FIGS. 10A to 10C, the gate line 22, the gate pad 24, and the gate electrode 26 are formed on the substrate 10 by a photolithography process using a first mask as in the first embodiment. And a storage electrode 28, and forming a gate wiring including an aluminum-based lower layer 201 and a doped silicon upper layer 202.

Next, as shown in FIGS. 11A and 11B, the gate insulating film 30, the semiconductor layer 40, and the intermediate layer 50 are respectively 1,500 kV to 5,000 kV, 500 kV to 2,000 kV, and 300 kV using chemical vapor deposition. Continuously deposited to a thickness of 600 to 600 kPa, and then depositing a conductor layer 60 such as a metal to a thickness of 1,500 kPa to 3,000 kPa by sputtering or the like, and then depositing a photoresist film 110 thereon at a thickness of 1 μm to 2 μm. Apply with

Thereafter, the photosensitive film 110 is irradiated with light through a second mask and then developed to form photosensitive film patterns 112 and 114 as shown in FIGS. 12B and 12C. In this case, among the photoresist patterns 112 and 114, the channel portion C of the thin film transistor, that is, the first portion 114 positioned between the source electrode 65 and the drain electrode 66, is the data wiring portion A, that is, the data. The thickness of the wirings 62, 64, 65, 66, and 68 is smaller than that of the second portion 112 positioned at the portion where the wirings 62, 64, 65, 66, and 68 are to be formed. At this time, the ratio of the thickness of the photoresist film 114 remaining in the channel portion C to the thickness of the photoresist film 112 remaining in the data wiring portion A should be different depending on the process conditions in the etching process described later. It is preferable to make the thickness of the 1st part 114 into 1/2 or less of the thickness of the 2nd part 112, for example, it is good that it is 4,000 Pa or less.

As such, there may be various methods of varying the thickness of the photoresist layer according to the position. In order to control the light transmittance in the A region, a slit or lattice-shaped pattern is mainly formed or a translucent film is used.

In this case, the line width of the pattern located between the slits, or the interval between the patterns, that is, the width of the slits, is preferably smaller than the resolution of the exposure apparatus used for exposure. A thin film having a thickness or a thin film may be used.

When the light is irradiated to the photosensitive film through such a mask, the polymers are completely decomposed at the part directly exposed to the light, and the polymers are not completely decomposed because the amount of light is small at the part where the slit pattern or the translucent film is formed. In the area covered by, the polymer is hardly decomposed. Subsequently, when the photoresist film is developed, only a portion where the polymer molecules are not decomposed is left, and a thin photoresist film may be left at a portion where the light is not irradiated at a portion less irradiated with light. In this case, if the exposure time is extended, all molecules are decomposed, so it should not be so.

The thin film 114 is formed by using a photoresist film made of a reflowable material, and is exposed to a conventional mask that is divided into a part that can completely transmit light and a part that cannot fully transmit light, and then develops and ripples. It can also be formed by letting a part of the photosensitive film flow to the part which does not remain by making it low.

Subsequently, etching is performed on the photoresist pattern 114 and the underlying layers, that is, the conductor layer 60, the intermediate layer 50, and the semiconductor layer 40. In this case, the data line and the lower layer of the data line remain in the data wiring portion A, and only the semiconductor layer should remain in the channel portion C, and the upper three layers 60, 50, 40 must be removed to expose the gate insulating film 30.

First, as shown in FIGS. 13A and 13B, the exposed conductor layer 60 of the other portion B is removed to expose the lower intermediate layer 50. In this process, both a dry etching method and a wet etching method may be used. In this case, the conductor layer 60 may be etched and the photoresist patterns 112 and 114 may be hardly etched. However, in the case of dry etching, it is difficult to find a condition in which only the conductor layer 60 is etched and the photoresist patterns 112 and 114 are not etched, so that the photoresist patterns 112 and 114 may also be etched together. In this case, the thickness of the first portion 114 is thicker than that of the wet etching so that the first portion 114 is removed in this process so that the lower conductive layer 60 is not exposed.

When the conductor layer 60 is any one of Mo or MoW alloy, Al or Al alloy, and Ta, either dry etching or wet etching can be used. However, since Cr is not easily removed by the dry etching method, it is preferable to use only wet etching if the conductor layer 60 is Cr. In the case of wet etching in which the conductor layer 60 is Cr, CeNHO ₃ may be used as an etchant. In the case of dry etching in which the conductor layer 60 is Mo or MoW, the mixed gas or CF of CF ₄ and HCl may be used as the etching gas. A mixed gas of ₄ and O ₂ can be used, and in the latter case, the etching ratio to the photoresist film is almost the same.

In this way, as shown in FIGS. 13A and 13B, only the conductor layers of the channel portion C and the data wiring portion B, that is, the conductor pattern 67 for the source / drain and the conductor pattern 68 for the storage capacitor, are provided. All of the conductor layer 60 of the remaining portion B is removed, revealing the underlying intermediate layer 50. The remaining conductor patterns 67 and 68 have the same shape as the data lines 62, 64, 65, 66, and 68 except that the source and drain electrodes 65 and 66 are connected without being separated. In addition, when dry etching is used, the photoresist patterns 112 and 114 are also etched to a certain thickness.

Subsequently, as shown in FIGS. 14A and 14B, the exposed intermediate layer 50 of the other portion B and the semiconductor layer 40 thereunder are simultaneously removed by the dry etching method together with the first portion 114 of the photosensitive film. do. At this time, etching is performed under the condition that the photoresist patterns 112 and 114, the intermediate layer 50, and the semiconductor layer 40 (the semiconductor layer and the intermediate layer have almost no etching selectivity) are simultaneously etched, and the gate insulating layer 30 is not etched. In particular, it is preferable to etch under conditions in which the etch ratios of the photoresist patterns 112 and 114 and the semiconductor layer 40 are almost the same. For example, by using a mixed gas of SF ₆ and HCl or a mixed gas of SF ₆ and O ₂ , the two films can be etched to almost the same thickness. When the etching ratios of the photoresist patterns 112 and 114 and the semiconductor layer 40 are the same, the thickness of the first portion 114 should be equal to or smaller than the sum of the thicknesses of the semiconductor layer 40 and the intermediate layer 50.

This removes the first portion 114 of the channel portion C, revealing the source / drain conductor pattern 67, as shown in FIGS. 14A and 14B, and the intermediate layer 50 of the other portion B. And the semiconductor layer 40 is removed to expose the gate insulating layer 30 thereunder. On the other hand, since the second portion 112 of the data wiring portion A is also etched, the thickness becomes thin. In this step, the semiconductor patterns 42 and 48 are completed. Reference numerals 57 and 58 indicate the intermediate layer pattern under the source / drain conductor pattern 67 and the intermediate layer pattern under the storage capacitor conductor pattern 68, respectively.

Subsequently, ashing removes photoresist residue remaining on the surface of the source / drain conductor pattern 67 of the channel portion C.

Next, as illustrated in FIGS. 15A and 15B, the source / drain conductor pattern 67 of the channel portion C and the source / drain interlayer pattern 57 below are etched and removed. In this case, the etching may be performed only by dry etching with respect to both the source / drain conductor pattern 67 and the intermediate layer pattern 57. The etching may be performed by wet etching on the source / drain conductor pattern 67. 57 may be performed by dry etching. In the former case, it is preferable to perform etching under the condition that the etching selectivity of the source / drain conductor pattern 67 and the interlayer pattern 57 is large. This is because it is not easy to adjust the thickness of the semiconductor pattern 42 remaining in Fig. 2). For example, those of etching the SF ₆ and O ₂ by using the mixed gas of the source / drain conductive pattern 67. In the latter case of alternating between wet etching and dry etching, the side surface of the conductive pattern 67 for wet etching of the source / drain is etched, but the intermediate layer pattern 57 which is dry etched is hardly etched, and thus is formed in a step shape. Examples of the etching gas used to etch the intermediate layer pattern 57 and the semiconductor pattern 42 include the aforementioned mixed gas of CF ₄ and HCl or mixed gas of CF ₄ and O ₂ , and CF ₄ and O _{Using 2} can leave the semiconductor pattern 42 in a uniform thickness. In this case, as shown in FIG. 15B, a part of the semiconductor pattern 42 may be removed to reduce the thickness, and the second part 112 of the photoresist pattern may also be etched to a certain thickness at this time. At this time, the etching must be performed under the condition that the gate insulating film 30 is not etched, and the photoresist film is not exposed so that the second portion 112 is etched so that the data lines 62, 64, 65, 66, and 68 underneath are not exposed. It is a matter of course that the pattern is thick.

In this way, the source electrode 65 and the drain electrode 66 are separated, thereby completing the data lines 62, 64, 65, 66, and 68 and the contact layer patterns 55, 56, and 58 under the data lines.

Finally, the second photoresist layer 112 remaining in the data wiring portion A is removed. However, the removal of the second portion 112 may be made after removing the conductor pattern 67 for the channel portion C source / drain and before removing the intermediate layer pattern 57 thereunder.

As mentioned earlier, wet and dry etching can be alternately used or only dry etching can be used. In the latter case, since only one type of etching is used, the process is relatively easy, but it is difficult to find a suitable etching condition. On the other hand, in the former case, the etching conditions are relatively easy to find, but the process is more cumbersome than the latter.

After the data wirings 62, 64, 65, 66, and 68 are formed in this manner, as shown in FIGS. 16A to 16C, silicon nitride is deposited by CVD or spin-coated an organic insulating material to have a thickness of 3,000 3,000 or more. The protective film 70 is formed. Subsequently, the passivation layer 70 is etched together with the gate insulating layer 30 by using a third mask to form the drain electrode 66, the gate pad 24, the data pad 64, and the conductive pattern 68 for the storage capacitor, respectively. The exposed contact holes 71, 72, 73, 74 are formed.

Finally, as shown in FIGS. 10 through 11, an ITO layer having a thickness of 400 μs to 500 μs is deposited and etched using a fourth mask to form the pixel electrode 82, the auxiliary gate pad 84, and the auxiliary data pad. Form 86.

In the second embodiment of the present invention, the data wirings 62, 64, 65, 66, and 68 and the contact layer patterns 55, 56, 58 and the semiconductor pattern 42 below the data wirings 62, 64, 65, 66, and 68, as well as the effects of the first embodiment. , 48) may be formed using one mask, and the source electrode 65 and the drain electrode 66 may be separated in this process to simplify the manufacturing process.

In this embodiment of the present invention, a doped silicon layer is formed on the upper portion of the wiring to avoid contact between the aluminum-based metal and the ITO film.

As described above, according to the present invention, a conductive film made of doped silicon is formed between the aluminum-based metal film and the ITO film to ensure the reliability of the pad portion and to protect the wiring of the low-resistance aluminum or aluminum alloy with the conductive film. It is possible to prevent disconnection or erosion. In addition, the manufacturing cost may be reduced by manufacturing the thin film transistor substrate for the liquid crystal display by simplifying the manufacturing process.

Claims (6)

Stacking and patterning a metal film and a conductive film of doped silicon on an insulating substrate to form a gate line including a gate line and a gate electrode connected to the gate line; Forming a gate insulating film, Forming a semiconductor layer on the gate insulating layer; Forming a data line including a data line crossing the gate line, a source electrode connected to the data line and a drain electrode adjacent to the gate electrode, and a drain electrode opposite to the source electrode; Laminating a protective film, Forming a pixel electrode connected to the drain electrode Method of manufacturing a thin film transistor substrate for a liquid crystal display device comprising a. In claim 1, And the conductive film is formed of amorphous silicon or polycrystalline silicon, and the metal film is formed of an aluminum-based metal. In claim 1, The gate line further includes a gate pad receiving a scan signal from the outside and transferring the scan signal to the gate line, The data line further includes a data pad which transfers an image signal from an external source to the data line. The passivation layer has first and second contact holes exposing the gate pad together with the data pad and the gate insulating layer. And forming an auxiliary gate pad and an auxiliary data pad respectively connected to the gate pad and the data pad through the first and second contact holes in the same layer as the pixel electrode. In claim 1, And the pixel electrode is formed of ITO. Insulation board, A first conductive film formed of an aluminum-based metal on the insulating substrate and a second conductive film formed on the first conductive film and formed of doped amorphous silicon or doped polycrystalline silicon, and connected to a gate line and the gate line. A gate wiring including a gate electrode, A gate insulating film covering the gate wiring, A semiconductor layer formed on the gate insulating film, A data line intersecting the gate line, a data line connected to the data line and including a source electrode adjacent to the gate electrode and a drain electrode opposite to the source electrode with respect to the gate electrode; A protective film formed on the substrate and having a first contact hole exposing the drain electrode; A pixel electrode connected to the drain electrode through the first contact hole and formed of ITO Thin film transistor substrate for a liquid crystal display device comprising a. In claim 5, The gate line further includes a gate pad receiving a scan signal from the outside and transferring the scan signal to the gate line, The data line further includes a data pad which transfers an image signal from an external source to the data line. The passivation layer has second and third contact holes exposing the gate pad together with the data pad and the gate insulating layer. And an auxiliary gate pad and an auxiliary data pad respectively connected to the gate pad and the data pad through the second and third contact holes on the same layer as the pixel electrode.