KR100656913B1 - A thin film transistor array panel and method for manufacturing the same - Google Patents

Abstract

First, an aluminum-based conductive material is stacked and patterned to form a horizontal gate line including a gate line, a gate electrode, and a gate pad on a substrate. Next, a gate insulating film is formed by laminating silicon nitride, and a semiconductor layer and an ohmic contact layer are sequentially formed thereon. Subsequently, a metal line such as chromium is stacked and patterned to form a data line including a data line, a source electrode, a drain electrode, and a data pad crossing the gate line. Subsequently, a thermosetting organic material is laminated to form a protective film and patterned by dry etching to form contact holes that expose the drain electrode, the gate pad, and the data pad, respectively. Next, the IZO is stacked and patterned to form a pixel electrode, an auxiliary gate pad, and an auxiliary data pad electrically connected to the drain electrode, the gate pad, and the data pad, respectively.

Thermosetting, organic materials, contact resistance, dry etching

Description

A thin film transistor substrate and a method of manufacturing the same {A THIN FILM TRANSISTOR ARRAY PANEL AND METHOD FOR MANUFACTURING THE SAME}

1 is a thin film transistor substrate for a liquid crystal display device according to a first embodiment of the present invention;

FIG. 2 is a cross-sectional view of the thin film transistor substrate illustrated in FIG. 1 taken along the line II-II.

3A, 4A, 5A, and 6A are layout views of a thin film transistor substrate, illustrating an intermediate process of manufacturing a thin film transistor substrate for a liquid crystal display device according to a first embodiment of the present invention, according to a process sequence thereof;

3B is a cross-sectional view taken along the line IIIb-IIIb ′ in FIG. 3A;

4B is a cross-sectional view taken along the line IVb-IVb ′ in FIG. 4A and is a cross-sectional view showing the next step in FIG. 3B;

FIG. 5B is a cross-sectional view taken along the line Vb-Vb ′ in FIG. 5A and is a cross-sectional view showing the next step in FIG. 4B;

FIG. 6B is a cross-sectional view taken along the line VIb-VIb ′ in FIG. 6A and is a cross-sectional view showing the next step in FIG. 6.

7 is a layout view of a thin film transistor substrate for a liquid crystal display according to a second exemplary embodiment of the present invention.

8 and 9 are cross-sectional views of the thin film transistor substrate shown in FIG. 7 taken along the lines VII-VII 'and IX-IX',

10A is a layout view of a thin film transistor substrate in a first step of manufacturing according to the second embodiment of the present invention;

10B and 10C are cross-sectional views taken along the lines Xb-Xb 'and Xc-Xc' in FIG. 10A, respectively.

11A and 11B are cross-sectional views taken along the lines Xb-Xb 'and Xc-Xc' of FIG. 10A, respectively, and are cross-sectional views of the next steps of FIGS. 10B and 10C.

12A is a layout view of a thin film transistor substrate in FIGS. 11A and 11B next steps;

12B and 12C are cross-sectional views taken along the lines XIIb-XIIb 'and XIIc-XIIc' in FIG. 12A, respectively.

13A, 14A, 15A and 13B, 14B, and 15B are cross-sectional views taken along the lines XIIb-XIIb 'and XIIc-XIIc' in FIG. 12A, respectively, illustrating the following steps in the order of the process. ,

16A and 16B are cross-sectional views of the thin film transistor substrate in the next steps of FIGS. 15A and 15B;

17A is a layout view of a thin film transistor substrate at a next step of FIGS. 16A and 16B,                 

17B and 17C are cross-sectional views taken along the lines XVIIb-XVIIb 'and XVIIc-XVIIc', respectively, in FIG. 17A.

The present invention relates to a thin film transistor substrate and a method of manufacturing the same.

The liquid crystal display is one of the most widely used flat panel display devices. The liquid crystal display includes two substrates on which electrodes are formed and a liquid crystal layer interposed therebetween, and rearranges the liquid crystal molecules of the liquid crystal layer by applying a voltage to the electrode. Device to display an image by adjusting the amount of transmitted light.

Here, one of the two substrates is provided with a wiring for transmitting an image signal or a scanning signal and defining pixels of a matrix array, and each pixel is electrically connected to the wiring and is for removing the transmission of the image signal. A thin film transistor and a pixel electrode to which an image signal is transmitted are formed, which is called a thin film transistor substrate.

In this case, in order to maximize the pixel, the wiring and the pixel electrode are formed to overlap each other with an insulating film therebetween, and a photosensitive organic film having a favorable patterning process is used as the insulating film. However, the photosensitive organic film has a problem in that the light transmittance in the short wavelength is deteriorated and the screen looks yellow.

On the other hand, in order to manufacture a thin film transistor through a photolithography process using a plurality of masks, it is preferable to reduce the number of masks in order to reduce the production cost.

An object of the present invention is to provide a thin film transistor substrate having a transmittance and a method of manufacturing the same.

In order to solve this problem, in the present invention, a thermosetting organic film is used, and the insulating film is patterned by dry etching to form a contact hole exposing the contact portion of the wiring.

More specifically, first, a gate line including a gate line and a gate electrode connected to the gate line is formed on an insulating substrate, a gate insulating film and a semiconductor layer are formed, and then connected to the data line and the data line and adjacent to the gate electrode. A data line including a drain electrode located opposite the source electrode is formed with respect to the source electrode and the gate electrode. Subsequently, a thermosetting organic material is laminated to form a protective film, and patterned by dry etching to form a first contact hole exposing the drain electrode. Subsequently, the transparent conductive material is stacked and patterned to form a pixel electrode connected to the drain electrode through the first contact hole.

Here, the dry etching gas used in the dry etching patterning step may include SF ₆ , and may form a buffer film made of silicon nitride on the semiconductor layer, and may pattern the protective film and the buffer film together.

In addition, it is preferable to remove the film remaining on the upper portion of the contact portion by washing with an aluminum etchant before forming the pixel electrode.

The gate wiring further includes a gate pad connected to the gate line, and the data wiring further includes a data pad connected to the data line, and the second and third portions exposing the gate pad and the data pad in the first contact hole forming step. Further contact holes may be further formed, and an auxiliary gate and an auxiliary data pad connected to the gate pad and the data pad may be further formed through the second and third contact holes in the pixel electrode forming step.

Here, the ohmic contact layer may be formed between the semiconductor layer and the data line, and the data line, the contact layer, and the semiconductor layer may be formed using one mask.

Next, a thin film transistor array substrate and a method of manufacturing the same according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily implement the present invention.

Next, a thin film transistor substrate and a manufacturing method for a liquid crystal display according to the present invention will be described in detail with reference to the accompanying drawings.

First, a structure of a thin film transistor substrate for a liquid crystal display according to a first embodiment of the present invention will be described in detail with reference to FIGS. 1 and 2.

1 is a thin film transistor substrate for a liquid crystal display device according to a first embodiment of the present invention, and FIG. 2 is a cross-sectional view of the thin film transistor substrate shown in FIG. 1 taken along the line II-II.                     

On the insulating substrate 10, a gate wiring made of an aluminum-based single film having a low resistance or a multilayer film including the same is formed. The gate wire is connected to the gate line 22 and the gate line 22 extending in the horizontal direction, and are connected to the gate pad 24 and the gate line 22 which receive a gate signal from the outside and transmit the gate signal to the gate line. A gate electrode 26 of the thin film transistor.

On the substrate 10, a gate insulating film 30 made of silicon nitride (SiN _x ) covers the gate wirings 22, 24, and 26.

A semiconductor layer 40 made of a semiconductor such as amorphous silicon is formed on the gate insulating film 30 of the gate electrode 24, and n + having a high concentration of silicide or n-type impurity is formed on the semiconductor layer 40. Resistive contact layers 55 and 56 made of a material such as hydrogenated amorphous silicon are formed, respectively.

On the ohmic contact layers 55 and 56 and the gate insulating layer 30, data lines 62, 65, 66, and 68 formed of a single film made of a conductive material such as aluminum or a multilayer film including the same are formed. The data line is formed in the vertical direction and crosses the gate line 22 to define a pixel, and the data line 62 is a branch of the data line 62 and the source electrode 65 extending to the upper portion of the ohmic contact layer 55. ), Which is connected to one end of the data line 62 and is separated from the data pad 68 and the source electrode 65 to which an image signal from the outside is applied, and is opposite to the source electrode 65 with respect to the gate electrode 26. And a drain electrode 66 formed on the ohmic contact layer 56. In addition, the data line may include a conductive pattern 64 for an organic capacitor that overlaps the gate line 22 to improve the storage capacitance.

In the case where the data lines 62, 64, 65, 66, and 68 are formed in two or more layers, one layer is formed of an aluminum-based conductive material having a low resistance, and the other layer is formed of a material having good contact properties with other materials. It is desirable to make. Examples thereof include Cr / Al (or Al alloy) or Al / Mo.

A passivation layer 70 made of a thermosetting organic material having high transmittance and excellent planarization property is formed on the data lines 62, 64, 65, 66, and 68 and the semiconductor layer 40 which is not covered by these.

In the passivation layer 70, contact holes 76, 72, and 78 are formed to expose the drain electrode 66, the conductor pattern 64 for the organic capacitor, and the data pad 68, respectively, and together with the gate insulating layer 30. The contact hole 74 which exposes the gate pad 24 is formed.

A pixel electrode 82 positioned in the pixel is electrically formed on the planarized passivation layer 70 and is electrically connected to the conductive pattern for the storage capacitor and the drain electrode 66 through the contact holes 72 and 76. In addition, the auxiliary gate pad 86 and the auxiliary data pad 88, which are connected to the gate pad 24 and the data pad 68, respectively, are formed on the passivation layer 70 through the contact holes 74 and 78. Here, the pixel electrode 82, the auxiliary gates, and the data pads 86 and 88 are made of indium tin oxide (ITO) or indium zinc oxide (IZO), which are transparent conductive materials.

1 and 2, the pixel electrode 82 overlaps the gate line 22 and the data line 62 to secure the maximum aperture ratio, and a protective film having a low dielectric constant therebetween. 70 is formed to minimize delay or interference with respect to the signal transmitted through the wires 22 and 62. In addition, the protective film 70 may be made of a thermosetting organic material having excellent transmittance, thereby ensuring maximum transmittance. Here, the conductive capacitor pattern 64 for the storage capacitor connected to the pixel electrode 82 overlaps the gate line 22 to form a storage capacitor, and when the storage capacitor is insufficient, the same layer as the gate wirings 22, 24, and 26. It is also possible to add a storage capacitor wiring.

In addition, a buffer film made of silicon nitride may be further formed between the semiconductor layer 40 and the passivation layer 70 to secure the characteristics of the thin film transistor.

Next, a method of manufacturing the thin film transistor substrate for a liquid crystal display according to the first embodiment of the present invention will be described in detail with reference to FIGS. 1 and 2 and FIGS. 3A to 7B.

First, as shown in FIGS. 3A and 3B, a single film made of an aluminum-based metal having a low resistance on the substrate 10 is stacked and patterned to a thickness of about 2,500 GHz to form a gate line 22 and a gate electrode 26. And a gate wiring in a horizontal direction including the gate pad 24.

Next, as shown in FIGS. 4A and 4B, a three-layer film of a gate insulating film 30 made of silicon nitride, a semiconductor layer 40 made of amorphous silicon, and a doped amorphous silicon layer 50 is successively laminated, and a mask is formed. The semiconductor layer 40 and the ohmic contact layer 50 are formed on the gate insulating layer 30 facing the gate electrode 24 by patterning the semiconductor layer 40 and the doped amorphous silicon layer 50 by the patterning process. do. Here, the gate insulating film 30 is preferably laminated for at least 5 minutes in the temperature range of 300 ℃ or more. In addition, in order to prevent AlO _{X from} being formed on the aluminum-based metal films 22, 24, and 26 before depositing the gate insulating layer 30, a cleaning process may be performed with a plasma containing hydrogen, helium, or argon. in-situ).

Next, as shown in FIGS. 5A to 5B, a metal film made of chromium, molybdenum, molybdenum alloy, titanium, tantalum, or the like is stacked, and patterned by a photo process using a mask to cross the gate line 22. A source electrode 65 connected to the data line 62 and extending to an upper portion of the gate electrode 26, and a data pad 68 and a source electrode 65 connected to one end thereof. And a data line including a drain electrode 66 facing the source electrode 65 and a conductor pattern 64 for a storage capacitor, which are separated from the gate electrode 26 and overlap the gate line 22. do.

Subsequently, the doped amorphous silicon layer pattern 50, which is not covered by the data lines 62, 64, 65, 66, and 68, is etched to separate the gate electrode 26 from both sides, while the doped amorphous silicon on both sides is etched. The semiconductor layer pattern 40 between the layers 55 and 56 is exposed. Subsequently, in order to stabilize the surface of the exposed semiconductor layer 40, it is preferable to perform oxygen plasma.

Next, as shown in FIGS. 6A and 6B, a protective film 70 is formed by stacking a thermosetting organic material having a low dielectric constant and a high transmittance among organic materials having excellent planarization characteristics. In this case, similarly to the formation of the gate insulating film 30, the protective film 70 is preferably laminated for a time period of 5 minutes or more in a temperature range of 300 ° C. or higher. Subsequently, the photoresist pattern is patterned by dry etching together with the gate insulating layer 30 in the photolithography process to form the gate pad 24, the drain electrode 66, the conductor pattern 64 for the storage capacitor, and the data pad 68. To form contact holes 74, 76, 72, and 78, which reveal. Here, when there is no etching selectivity between the protective film 70 and the photoresist pattern, it is preferable that the thickness of the photoresist pattern is sufficient so that the data lines 62, 64, 65, 66, and 68 are not exposed. It is preferable to increase the etching rate by adding ₆ .

In this case, as described above, in order to form a buffer layer made of silicon nitride covering the semiconductor layer 40 before stacking the passivation layer 70 to secure the characteristics of the thin film transistor, a photolithography process using a mask may be added. However, when SF ₆ is used as the dry etching gas, the protective film 70 of the organic material and the buffer film of silicon nitride can be etched together so that an additional process is not required.

Next, as shown in FIGS. 1 and 2, the ITO or IZO film is laminated and patterned using a mask to conduct the drain electrode 66 and the conductor pattern 64 for the storage capacitor through the contact holes 76 and 72. ) And an auxiliary gate pad 86 and an auxiliary data pad 88 connected to the gate pad 24 and the data pad 68, respectively, through the pixel electrode 82 and the contact holes 74 and 78 connected to each other. do. In the embodiment of the present invention, in order to minimize the contact resistance of the contact it is preferable to laminate in the range of not more than 200 ℃ the IZO at room temperature, and the target (target) used to form the IZO thin film was In ₂ O ₃ and It is preferable to include ZnO, and it is preferable to use the target whose content of Zn is 15-20 at%. Here, before the deposition of the IZO, it is preferable to perform a cleaning process using an aluminum etchant to remove a film having a high resistance such as AlO _X on the upper portions of the contact portions 24, 66, 68.

As described above, the method can be applied to a manufacturing method using five masks, but the same method can be applied to a manufacturing method of a thin film transistor substrate for a liquid crystal display device using four masks. This will be described in detail with reference to the drawings.

First, a unit pixel structure of a thin film transistor substrate for a liquid crystal display device completed using four masks according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 7 to 9.

FIG. 7 is a layout view of a thin film transistor substrate for a liquid crystal display device according to a second exemplary embodiment of the present invention, and FIGS. 8 and 9 are lines VIII-VIII 'and IX-IX', respectively, of the thin film transistor substrate shown in FIG. A cross-sectional view taken along the line.

First, a gate line including a gate line 22, a gate pad 24, and a gate electrode 26 made of an aluminum-based metal is formed on the insulating substrate 10 as in the first embodiment. The gate wiring includes a sustain electrode 28 that is parallel to the gate line 22 on the substrate 10 and receives a voltage such as a common electrode voltage input to the common electrode of the upper plate from the outside. The storage electrode 28 overlaps with the conductive capacitor conductor 68 for the storage capacitor connected to the pixel electrode 82, which will be described later, to form a storage capacitor which improves the charge retention capability of the pixel. The pixel electrode 82 and the gate line, which will be described later, If the holding capacity generated by the overlap of (22) is sufficient, it may not be formed.

A gate insulating film 30 made of silicon nitride (SiN _x ) is formed on the gate wirings 22, 24, 26, and 28 to cover the gate wirings 22, 24, 26, and 28.

Semiconductor patterns 42 and 48 made of semiconductors such as hydrogenated amorphous silicon are formed on the gate insulating layer 30, and high concentrations of n-type impurities such as phosphorus (P) are formed on the semiconductor patterns 42 and 48. An ohmic contact layer pattern or an intermediate layer pattern 55, 56, 58 made of amorphous silicon doped with is formed.

On the ohmic contact layer patterns 55, 56 and 58, data wirings made of chromium or molybdenum or molybdenum alloy or metal such as tantalum or titanium are formed. The data line is a thin film transistor which is a branch of the data line 62 formed in the vertical direction, the data pad 68 connected to one end of the data line 62 to receive an image signal from the outside, and the data line 62. And a data line portion of the source electrode 65 of the source electrode 65. The data line portion is separated from the data line portions 62, 68, and 65, and the source electrode 65 is separated from the gate electrode 26 or the channel portion C of the thin film transistor. It also includes a conductive capacitor pattern 64 for the storage capacitor located on the drain electrode 66 and the storage electrode 28 of the thin film transistor located on the opposite side. When the sustain electrode 28 is not formed, the conductor pattern 64 for the storage capacitor is also not formed.

The data lines 62, 64, 65, 66, and 68 may be formed of a double layer including a conductive film made of chromium or molybdenum or molybdenum alloy or tantalum or titanium and a conductive film made of an aluminum-based metal.

The contact layer patterns 55, 56, and 58 serve to lower the contact resistance between the semiconductor patterns 42 and 48 below and the data lines 62, 64, 65, 66, and 68 above them. It has exactly the same form as (62, 64, 65, 66, 68). That is, the data line part intermediate layer pattern 55 is the same as the data line parts 62, 68, and 65, the drain electrode intermediate layer pattern 56 is the same as the drain electrode 66, and the storage capacitor intermediate layer pattern 58 is It is the same as the conductor pattern 64 for holding capacitors.

The semiconductor patterns 42 and 48 have the same shape as the data lines 62, 64, 65, 66, and 68 and the ohmic contact layer patterns 55, 56, and 58 except for the channel portion C of the thin film transistor. Doing. Specifically, the semiconductor capacitor 48 for the storage capacitor, the conductor pattern 64 for the storage capacitor, and the contact layer pattern 58 for the storage capacitor have the same shape, but the semiconductor pattern 42 for the thin film transistor has data wiring and contact. Slightly different from the rest of the layer pattern. That is, in the channel portion C of the thin film transistor, the data line portions 62, 68, and 65, in particular, the source electrode 65 and the drain electrode 66 are separated, and the contact layer pattern for the data line intermediate layer 55 and the drain electrode. Although 56 is also separated, the semiconductor pattern 42 for thin film transistors is connected here without disconnection to generate a channel of the thin film transistor.

On the data lines 62, 64, 65, 66, and 68, a protective film 70 made of a thermosetting organic material having low dielectric constant and excellent transmittance among organic materials having excellent planarization characteristics is formed.

The protective film 70 has contact holes 76, 78, and 72 that expose the drain electrode 66, the data pad 64, and the conductive pattern 68 for the storage capacitor, and also the gate along with the gate insulating film 30. It has a contact hole 74 which exposes the pad 24.

On the passivation layer 70, a pixel electrode 82 that receives an image signal from a thin film transistor and generates an electric field together with the electrode of the upper plate is formed. The pixel electrode 82 is made of a transparent conductive material such as ITO or IZO, and is physically and electrically connected to the drain electrode 66 through the contact hole 76 to receive an image signal. The pixel electrode 82 also overlaps with the neighboring gate line 22 and the data line 62 to increase the aperture ratio, but may not overlap. In addition, the pixel electrode 82 is also connected to the storage capacitor conductor pattern 64 through the contact hole 72 to transmit an image signal to the conductor pattern 64. On the other hand, an auxiliary gate pad 86 and an auxiliary data pad 88 connected to the gate pad 24 and the data pad 68 through the contact holes 74 and 78, respectively, are formed. 68) and to protect the pads and the adhesion of the external circuit device, and is not essential, their application is optional.

Next, a method of manufacturing a thin film transistor substrate for a liquid crystal display device having the structure of FIGS. 7 to 9 using four masks will be described in detail with reference to FIGS. 8 to 10 and 10A to 17C. .

 First, as shown in FIGS. 10A to 10C, the gate lines 22 and the gate pads are stacked on the substrate 10 by a photolithography process using a mask by laminating an aluminum-based metal in a single layer as in the first embodiment. 24, a gate wiring including the gate electrode 26 and the sustain electrode 28 is formed.

Next, as shown in FIGS. 11A and 11B, the gate insulating film 30, the semiconductor layer 40, and the intermediate layer 50 made of silicon nitride are respectively 1,500 kV to 5,000 kPa and 500 kPa to 2,000 using chemical vapor deposition. 증착, 300 600 to 600 연속 of continuous deposition, and then a conductor layer 60 including a metal film made of chromium is deposited to a thickness of 1,500 Å to 3,000 Å by sputtering or the like, and then on the photoresist film 110 thereon. Is applied in a thickness of 1 μm to 2 μm. In this case, the gate insulating film 30 is preferably laminated for at least 5 minutes in a temperature range of 300 ° C. or higher. Here, in order to prevent AlO _{X from} being formed on the aluminum-based metal films 22, 24, and 26 before depositing the gate insulating layer 30, a cleaning process may be performed with a plasma containing hydrogen, helium, or argon. in-situ).

Thereafter, the photosensitive film 110 is irradiated with light through a mask and then developed to form photosensitive film patterns 112 and 114 as shown in FIGS. 12B and 12C. In this case, among the photoresist patterns 112 and 114, the channel portion C of the thin film transistor, that is, the first portion 114 positioned between the source electrode 65 and the drain electrode 66, is the data wiring portion A, that is, the data. The thickness of the wirings 62, 64, 65, 66, and 68 is smaller than that of the second portion 112 positioned at the portion where the wirings 62, 64, 65, 66, and 68 are to be formed. At this time, the ratio of the thickness of the photoresist film 114 remaining in the channel portion C to the thickness of the photoresist film 112 remaining in the data wiring portion A should be different depending on the process conditions in the etching process described later. It is preferable to make the thickness of the 1st part 114 into 1/2 or less of the thickness of the 2nd part 112, for example, it is good that it is 4,000 Pa or less.

As such, there may be various methods of varying the thickness of the photoresist layer according to the position. In order to control the light transmittance in the A region, a slit or lattice-shaped pattern is mainly formed or a translucent film is used.

In this case, the line width of the pattern located between the slits, or the interval between the patterns, that is, the width of the slits, is preferably smaller than the resolution of the exposure apparatus used for exposure. A thin film having a thickness or a thin film may be used.

When the light is irradiated to the photosensitive film through such a mask, the polymers are completely decomposed at the part directly exposed to the light, and the polymers are not completely decomposed because the amount of light is small at the part where the slit pattern or the translucent film is formed. In the area covered by, the polymer is hardly decomposed. Subsequently, when the photoresist film is developed, only a portion where the polymer molecules are not decomposed is left, and a thin photoresist film may be left at a portion where the light is not irradiated at a portion less irradiated with light. In this case, if the exposure time is extended, all molecules are decomposed, so it should not be so.

The thin film 114 is formed by using a photoresist film made of a reflowable material, and is exposed to a conventional mask that is divided into a part that can completely transmit light and a part that cannot fully transmit light, and then develops and ripples. It can also be formed by letting a part of the photosensitive film flow to the part which does not remain by making it low.

Subsequently, etching is performed on the photoresist pattern 114 and the underlying layers, that is, the conductor layer 60, the intermediate layer 50, and the semiconductor layer 40. In this case, the data line and the lower layer of the data line remain in the data wiring portion A, and only the semiconductor layer should remain in the channel portion C, and the upper three layers 60, 50, 40 must be removed to expose the gate insulating film 30.

First, as shown in FIGS. 13A and 13B, the exposed conductor layer 60 of the other portion B is removed to expose the lower intermediate layer 50. In this process, both a dry etching method and a wet etching method may be used. In this case, the conductor layer 60 may be etched and the photoresist patterns 112 and 114 may be hardly etched. However, in the case of dry etching, it is difficult to find a condition in which only the conductor layer 60 is etched and the photoresist patterns 112 and 114 are not etched, so that the photoresist patterns 112 and 114 may also be etched together. In this case, the thickness of the first portion 114 is thicker than that of the wet etching so that the first portion 114 is removed in this process so that the lower conductive layer 60 is not exposed.                     

When the conductor layer 60 is any one of Mo or MoW alloy, Al or Al alloy, and Ta, either dry etching or wet etching can be used. However, since Cr is not easily removed by the dry etching method, it is preferable to use only wet etching if the conductor layer 60 is Cr. In the case of wet etching in which the conductor layer 60 is Cr, CeNHO ₃ may be used as an etchant. In the case of dry etching in which the conductor layer 60 is Mo or MoW, the mixed gas or CF of CF ₄ and HCl may be used as the etching gas. A mixed gas of ₄ and O ₂ can be used, and in the latter case, the etching ratio to the photoresist film is almost the same.

In this way, as shown in Figs. 13A and 13B, only the conductor layers of the channel portion C and the data wiring portion B, that is, the conductor pattern 67 for the source / drain and the conductor pattern 64 for the storage capacitor, are shown. All of the conductor layer 60 of the remaining portion B is removed, revealing the underlying intermediate layer 50. The remaining conductor patterns 67 and 64 have the same shape as the data lines 62, 64, 65, 66 and 68 except that the source and drain electrodes 65 and 66 are connected without being separated. In addition, when dry etching is used, the photoresist patterns 112 and 114 are also etched to a certain thickness.

Subsequently, as shown in FIGS. 14A and 14B, the exposed intermediate layer 50 of the other portion B and the semiconductor layer 40 thereunder are simultaneously removed by the dry etching method together with the first portion 114 of the photosensitive film. do. At this time, etching is performed under the condition that the photoresist patterns 112 and 114, the intermediate layer 50, and the semiconductor layer 40 (the semiconductor layer and the intermediate layer have almost no etching selectivity) are simultaneously etched, and the gate insulating layer 30 is not etched. In particular, the etching ratio of the photoresist patterns 112 and 114 and the semiconductor layer 40 is preferably equal. For example, by using a mixed gas of SF ₆ and HCl or a mixed gas of SF ₆ and O ₂ , the two films can be etched to almost the same thickness. When the etching ratios of the photoresist patterns 112 and 114 and the semiconductor layer 40 are the same, the thickness of the first portion 114 should be equal to or smaller than the sum of the thicknesses of the semiconductor layer 40 and the intermediate layer 50.

This removes the first portion 114 of the channel portion C, revealing the source / drain conductor pattern 67, as shown in FIGS. 14A and 14B, and the intermediate layer 50 of the other portion B. And the semiconductor layer 40 is removed to expose the gate insulating layer 30 thereunder. On the other hand, since the second portion 112 of the data wiring portion A is also etched, the thickness becomes thin. In this step, the semiconductor patterns 42 and 48 are completed. Reference numerals 57 and 58 denote intermediate layer patterns under the source / drain conductor patterns 67 and intermediate layer patterns under the storage capacitor conductor patterns 64, respectively.

Subsequently, ashing removes photoresist residue remaining on the surface of the source / drain conductor pattern 67 of the channel portion C.

Next, as illustrated in FIGS. 15A and 15B, the source / drain conductor pattern 67 of the channel part C and the source / drain interlayer pattern 57 below are etched and removed. In this case, the etching may be performed only by dry etching with respect to both the source / drain conductor pattern 67 and the intermediate layer pattern 57. The etching may be performed by wet etching on the source / drain conductor pattern 67. 57 may be performed by dry etching. In the former case, it is preferable to perform etching under a condition in which the etching selectivity of the source / drain conductor pattern 67 and the interlayer pattern 57 is large, which is difficult to find the etching end point when the etching selectivity is not large. This is because it is not easy to adjust the thickness of the semiconductor pattern 42 remaining in C). For example, those of etching the SF ₆ and O ₂ by using the mixed gas of the source / drain conductive pattern 67. In the latter case of alternating between wet etching and dry etching, the side surface of the conductive pattern 67 for wet etching of the source / drain is etched, but the intermediate layer pattern 57 which is dry etched is hardly etched, and thus is formed in a step shape. Examples of the etching gas used to etch the intermediate layer pattern 57 and the semiconductor pattern 42 include the aforementioned mixed gas of CF ₄ and HCl or mixed gas of CF ₄ and O ₂ , and CF ₄ and O _{Using 2} can leave the semiconductor pattern 42 in a uniform thickness. In this case, as shown in FIG. 15B, a portion of the semiconductor pattern 42 may be removed to reduce the thickness, and the second portion 112 of the photoresist pattern may also be etched to a certain thickness at this time. At this time, the etching must be performed under the condition that the gate insulating film 30 is not etched, and the photoresist film is not exposed so that the second portion 112 is etched so that the data lines 62, 64, 65, 66, and 68 underneath are not exposed. It is a matter of course that the pattern is thick.

In this way, the source electrode 65 and the drain electrode 66 are separated, thereby completing the data lines 62, 64, 65, 66, and 68 and the contact layer patterns 55, 56, and 58 under the data lines.

Finally, the second photoresist layer 112 remaining in the data wiring portion A is removed. However, the removal of the second portion 112 may be made after removing the conductor pattern 67 for the channel portion C source / drain and before removing the intermediate layer pattern 57 thereunder.

As mentioned earlier, wet and dry etching can be alternately used or only dry etching can be used. In the latter case, since only one type of etching is used, the process is relatively easy, but it is difficult to find a suitable etching condition. On the other hand, in the former case, the etching conditions are relatively easy to find, but the process is more cumbersome than the latter.

After forming the data lines 62, 64, 65, 66, and 68 in this manner, as shown in FIGS. 16A and 16B, a thermosetting organic insulating material is deposited to form the protective film 70. 17A to 17C, the protective layer 70 is etched together with the gate insulating layer 30 by using a mask to drain the electrode 66, the gate pad 24, the data pad 68, and the holder. Contact holes 76, 74, 78, and 72 are formed to expose the conductor pattern 64 for the capacitor, respectively.

Finally, as shown in Figs. 8 to 10, a pixel of 400 Å to 500 Å thickness of IZO is deposited and etched using a mask to connect the drain electrode 66 and the conductive pattern 64 for the storage capacitor. An electrode 82, an auxiliary gate pad 86 connected to the gate pad 24, and an auxiliary data pad 88 connected to the data pad 68 are formed. In this case, the etching solution for patterning the IZO of the pixel electrode 82, the auxiliary gate pad 86, and the auxiliary data pad 88 uses a chromium etchant that is used to etch a metal film of chromium (Cr). It does not corrode the metal to prevent the corrosion of the aluminum-based metal exposed in the contact structure, and (HNO ₃ / (NH ₄ ) ₂ Ce (NO ₃ ) ₆ / H ₂ O) and the like as an etchant. Here, the gas used in the pre-heating process before laminating the IZO is the metal oxide film remaining on the upper portions of the metal films 24, 64, 66, and 68 where the contact holes 72, 74, 76, and 78 are exposed. It is preferable to perform the cleaning process using an aluminum etchant, and the aluminum etchant preferably contains HNO ₃ , H ₃ PO ₄ , CH ₃ COOH and deionized water.

In the second embodiment of the present invention, the data wirings 62, 64, 65, 66, and 68 and the contact layer patterns 55, 56, 58 and the semiconductor pattern 42 below the data wirings 62, 64, 65, 66, and 68, as well as the effects of the first embodiment. , 48) may be formed using one mask, and the source electrode 65 and the drain electrode 66 may be separated in this process to simplify the manufacturing process.

In this manner, as in the present invention, the thermal transmittance can be improved while the aperture ratio is secured by using the thermosetting organic material as the protective film. In addition, by etching the protective film by dry etching using SF ₆ , the etching speed can be increased, and even if a silicon nitride buffer film is added to secure the characteristics of the thin film transistor, the protective film can be patterned together with the protective film to simplify the manufacturing process. . In addition, the contact resistance of the contact portion may be minimized by removing the high resistance film such as the metal oxide layer from the contact portion using the aluminum etchant.

Claims (11)

Forming a gate line on the insulating substrate, the gate line including a gate line and a gate electrode connected to the gate line; Stacking a gate insulating film, Forming a semiconductor layer, Forming a data line including a data line, a source electrode connected to the data line and adjacent to the gate electrode, and a drain electrode positioned opposite to the source electrode with respect to the gate electrode; Stacking a thermosetting organic material to form a protective film, Patterning the passivation layer by dry etching to form a first contact hole exposing the drain electrode; Stacking and patterning a transparent conductive material to form a pixel electrode connected to the drain electrode through the first contact hole Method of manufacturing a thin film transistor substrate comprising a. In claim 1, The dry etching gas used in the patterning of the dry etching comprises SF ₆ . In claim 1, And forming a buffer film of silicon nitride on the semiconductor layer. The method of claim 1 or 2, The patterning method of manufacturing a thin film transistor substrate further comprises patterning the protective film and the buffer film together. In claim 1, A method of manufacturing a thin film transistor substrate further comprising performing cleaning using an aluminum etchant before the pixel electrode forming step. In claim 1, The gate line further includes a gate pad connected to the gate line, and the data line further includes a data pad connected to the data line. And forming second and third contact holes exposing the gate pad and the data pad in the first contact hole forming step, and through the second and third contact holes in the pixel electrode forming step. A method of manufacturing a thin film transistor substrate further comprising an auxiliary gate and an auxiliary data pad connected to the data pad. In claim 1, And forming an ohmic contact layer between the semiconductor layer and the data line. In claim 7, And forming the data line, the contact layer, and the semiconductor layer using a single mask. A gate wiring on the insulating substrate, the gate wiring including a gate electrode connected to the gate line; A gate insulating film covering the gate wiring, A semiconductor layer formed on the gate insulating film, A data line formed on the gate insulating layer, the data line including a data line, a source electrode connected to the data line and adjacent to the gate electrode, and a drain electrode positioned opposite to the source electrode with respect to the gate electrode; A protective film covering the data line and made of a thermosetting organic material, A pixel electrode electrically connected to the drain electrode Thin film transistor substrate comprising a. In claim 9, A thin film transistor substrate covering the semiconductor layer and further comprising a buffer film made of silicon nitride. In claim 9, And the pixel electrode is formed on the passivation layer.

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