KR100750914B1 - A thin film transistor array panel for liquid crystal panel and method manufacturing the same - Google Patents

Abstract

First, an aluminum-based conductive material is stacked and patterned to form a horizontal gate line including a gate line, a gate electrode, and a gate pad on a substrate. Next, a gate insulating film, a semiconductor layer, and an ohmic contact layer are sequentially formed. Subsequently, a metal including an aluminum-based conductive material is stacked and patterned to form a data line including a data line, a source electrode, a drain electrode, and a data pad crossing the gate line. Subsequently, the protective film is stacked and patterned to form contact holes that expose the reaction layers on the drain electrode, the gate pad, and the data pad surface, respectively. Subsequently, the amorphous ITO and IZO are stacked and patterned to form a pixel electrode, an auxiliary gate pad, and an auxiliary data pad electrically connected to the drain electrode, the gate pad, and the data pad, respectively.

Amorphous ITO, IZO, chromium etchant, aluminum etchant

Description

A transparent conductive film for pixel electrodes and a thin film transistor substrate for a liquid crystal display including the same, and a method of manufacturing the same {A THIN FILM TRANSISTOR ARRAY PANEL FOR LIQUID CRYSTAL PANEL AND METHOD MANUFACTURING THE SAME}

1 is a graph showing transmittance characteristics of ITO and IZO used as a transparent conductive film in a liquid crystal display device;

2 and 3 are graphs showing the etching ratio of the amorphous ITO film to the chromium etchant and the aluminum etchant according to the oxygen (O ₂ ) supply amount,

4 and 5 are graphs showing the specific resistance and transmittance of the amorphous ITO membrane according to an embodiment of the present invention,

6 is a thin film transistor substrate for a liquid crystal display according to a first embodiment of the present invention;

FIG. 7 is a cross-sectional view of the thin film transistor substrate illustrated in FIG. 6 taken along the line VII-VII ′.

8A, 9A, 10A, and 11A are layout views of a thin film transistor substrate illustrating an intermediate process of manufacturing a thin film transistor substrate for a liquid crystal display device according to a first embodiment of the present invention, according to a process sequence thereof.                 

FIG. 8B is a cross-sectional view taken along the line VIIIb-VIIIb ′ in FIG. 8A;

FIG. 9B is a cross-sectional view taken along the line IXb-IXb 'of FIG. 9A and illustrates the next step of FIG. 8B;

FIG. 10B is a cross-sectional view taken along the line Xb-Xb 'of FIG. 10A and illustrates the next step of FIG. 9B;

FIG. 11B is a cross-sectional view taken along the line XIb-XIb ′ of FIG. 11A, and is a cross-sectional view showing the next step of FIG. 10B;

12 is a layout view of a thin film transistor substrate for a liquid crystal display according to a second exemplary embodiment of the present invention.

13 and 14 are cross-sectional views of the thin film transistor substrate illustrated in FIG. 12 taken along lines XIII-XIII 'and XIV-XIV',

15A is a layout view of a thin film transistor substrate at a first stage of manufacture in accordance with a second embodiment of the present invention;

15B and 15C are cross-sectional views taken along the XVb-XVb 'line and the XVc-XVc' line in FIG. 15, respectively.

16A and 16B are cross-sectional views taken along the XVb-XVb 'line and the XVc-XVc' line in FIG. 15A, respectively, and are cross-sectional views in the next steps of FIGS. 15B and 15C;

17A is a layout view of a thin film transistor substrate in the next steps of FIGS. 16A and 16B,

17B and 17C are cross-sectional views taken along lines XVIIb-XVIIb 'and XVIIc-XVIIc', respectively, in FIG. 17A;

18A, 19A, 20A and 18B, 19B, and 20B are cross-sectional views taken along the lines XVIIb-XVIIb 'and XVIIc-XVIIc' in FIG. 17A, respectively, illustrating the following steps in the order of the process. ,

FIG. 21A is a layout view of a thin film transistor substrate at a next step of FIGS. 20A and 20B;

21B and 21C are cross-sectional views taken along the lines XXIb-XXIb 'and XXIc-XXIc', respectively, in FIG. 21A.

The present invention relates to a transparent conductive film for pixel electrodes, a thin film transistor substrate for a liquid crystal display device including the same, and a method of manufacturing the same.

In general, the wiring in the semiconductor device is used as a means for transmitting a signal, it is required to minimize the signal delay.

In this case, in order to prevent signal delay, the wiring is generally made of a metal material having a low resistance, particularly an aluminum-based metal material such as aluminum (Al) or aluminum alloy (Al alloy). However, since aluminum-based wiring has weak physical or chemical properties, corrosion occurs to deteriorate the characteristics of the semiconductor device. In particular, when a pixel electrode is formed of indium tin oxide (ITO) as a transparent conductive material in a display device such as a liquid crystal display device, a problem arises in that an aluminum-based wiring is easily corroded with respect to an ITO etchant for patterning ITO. .

In addition, ITO or IZO, which is used as a transparent conductive material in a liquid crystal display, exhibits different transmittances depending on the wavelength change in the wavelength range of visible light, and thus it is difficult to obtain uniform optical characteristics.

On the other hand, in the manufacturing method of the liquid crystal display device, the substrate on which the thin film transistor is formed is generally manufactured through a photolithography process using a mask. At this time, it is preferable to reduce the number of masks in order to reduce the production cost.

An object of the present invention is to provide a transparent conductive film for pixel electrodes that can secure a uniform transmittance.

Another object of the present invention is to provide a thin film transistor substrate capable of preventing corrosion of wiring having low resistance and a method of manufacturing the same.

In addition, another technical problem to be achieved by the present invention is to simplify the manufacturing method of the thin film transistor substrate.

In order to solve this problem, in the present invention, a transparent conductive film for forming a pixel electrode is formed by using an amorphous indium tin oxide (ITO) and indium zinc oxide (IZO) together.

In this case, the amorphous ITO and IZO are preferably patterned together by wet etching using a chromium etchant or an aluminum etchant, and may anneal the transparent conductive film. In addition, it is preferable that the amorphous ITO and IZO are laminated to a thickness in the range of 300-600 kPa and 800-1,200 kPa, respectively.

Such a transparent conductive film may be used as a pixel electrode in a thin film transistor substrate for a liquid crystal display device and a method of manufacturing the same.

Specifically, a gate wiring including a gate line and a gate electrode connected to the gate line is formed on an insulating substrate, and a gate insulating film and a semiconductor layer are formed. Next, a data line intersecting the gate line, a data line connected to the data line and including a source electrode adjacent to the gate electrode and a drain electrode positioned opposite to the source electrode is formed to form a protective film. Subsequently, the amorphous ITO and IZO are stacked and patterned to form a pixel electrode of a transparent conductive film connected to the drain electrode.

Here, the data line and the semiconductor layer may be formed together by a photolithography process using a photoresist pattern having a different thickness, and the photoresist pattern may include a first part having a first thickness, a second part thicker than the first thickness, and a thickness. It is preferred to have a third portion, which does not have, and excludes the first and second portions. In order to form the photoresist pattern, a photomask is formed using a photomask including a first region, a second region having a lower transmittance than the first region, and a third region having a higher transmittance than the first region. In the etching process, the first portion is formed between the source electrode and the drain electrode, and the second portion is preferably formed above the data line.

The gate wiring further includes a gate pad connected to the gate line, the data wiring further includes a data pad connected to the data line, the auxiliary wiring pad formed on the same layer as the pixel electrode and connected to the gate pad; The apparatus may further include an auxiliary data pad connected to the data pad.

Next, a thin film transistor substrate for a liquid crystal display device and a method of manufacturing the same according to embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. do.

In a liquid crystal display device using a light source to display an image, a transparent conductive material ITO or IZO is used as the pixel electrode. However, ITO or IZO is very difficult to ensure uniform optical properties because the transmittance is varied in the visible light wavelength range. Next, the transmittance characteristics of ITO and IZO used as pixel electrodes in the liquid crystal display will be described in detail with reference to the accompanying drawings.

1 is a graph showing transmittance characteristics of ITO and IZO used as a transparent conductive film in a liquid crystal display. In FIG. 1, A is a transmittance of an ITO film formed on a thin film transistor substrate of about 400 GPa in a liquid crystal display device, and B is a transmittance of an ITO film formed on a color filter substrate of a liquid crystal display in a thickness of about 1200 GPa, and C Each of F to F represents the transmittance of the IZO film which is supplied with oxygen at 0.6, 0.6, 0.6, and 2.2 sccm, and the IZO film is formed to a thickness of about 600, 800, 1,200, 1,200 Hz under the power conditions of 445, 510, 800, and 800 W. will be.

As shown in FIG. 1, it can be seen that the light transmittance has various transmittances in the wavelength band of visible light. At this time, looking at the transmittance curve of A based on the wavelength band of about 550 nm, it can be seen that ITO has a low transmittance at a short wavelength and a high transmittance at a long wavelength. On the contrary, it can be seen from the transmittance curve of E that IZO has a high transmittance at a short wavelength and a low transmittance at a long wavelength. Therefore, when ITO and IZO are used together to form a transparent conductive film, it is possible to secure a constant transmittance in most wavelength bands. However, the transparent conductive film made of ITO and IZO should be patternable under one etching condition. When ITO etching solution is used, as has been pointed out in the problems of the prior art, it has a problem of corroding aluminum-based wirings. In the case of patterning the IZO by using the etching process, the etching proceeds so fast that the degree of etching cannot be controlled. Therefore, in the present invention, when forming a transparent conductive film for a display device, ITO and IZO are formed by laminating, but ITO uses amorphous ITO rather than crystalline ITO. Amorphous ITO and IZO are both chromium etchant for etching the chromium metal film and aluminum etchant for etching the aluminum-based metal film. Next, the etch ratio of the amorphous ITO film to the chromium etchant and the aluminum etchant will be described in detail with reference to the accompanying drawings.

2 and 3 are graphs showing the etching ratio of the amorphous ITO film to the chromium etchant and the aluminum etchant according to the oxygen (O ₂ ) supply amount. 2 and 3 are all deposited at a thickness of about 1,000 kPa at room temperature (about 25-30 ℃), Figure 2 is a case of supplying H ₂ O and Ar, Figure 3 is a case of supplying only Ar. At this time, the chromium etchant was used (NH ₄ ) ₂ Ce (NO ₃ ) ₆ + HNO ₃ , the aluminum etchant was used H ₃ PO ₄ + CH ₃ COOH + H ₂ O + HNO ₃ .

As shown in FIGS. 2 and 3, the etching ratio of the amorphous ITO membrane was measured, and the etching ratio of the amorphous ITO membrane was measured to be about 200 mW / min and decreased with increasing oxygen flow rate. In this case, IZO has an etching ratio of about ~ 600 μs / min and 1,800 μs / min with respect to chromium etchant and aluminum etchant. It can be patterned, and it is preferable to form amorphous ITO in the range of about 300 to 600 kPa and about IZO in the range of 800 to 1,400 kPa.

Here, in order to use the amorphous ITO film as a pixel electrode, specific resistance and transmittance characteristics will be described in detail.

,

,

는 산소 공급량이 0, 0.6 및 1.5 sccm인 경우 어닐링을 실시한 다음의 투과율을 측정한 그래프이며,

,

,

는 산소 공급량이 0, 0.6 및 1.5 sccm인 경우 어닐링을 실시하기 전의 투과율을 측정한 그래프이다.4 and 5 are graphs showing the specific resistance and transmittance of the amorphous ITO membrane according to an embodiment of the present invention. 4 and 5 illustrate that an amorphous ITO film was formed to a thickness of about 1,000 kPa while H ₂ O was added, and annealing was performed at about 230 ° C. for 1 hour. The specific resistance and transmittance were measured according to the amount supplied. In Figure 5

,

,

Is a graph measuring the transmittance after annealing when the oxygen supply amount is 0, 0.6 and 1.5 sccm,

,

,

Is a graph measuring the transmittance before annealing when the oxygen supply amount is 0, 0.6 and 1.5 sccm.

As shown in FIG. 4, before the annealing, the specific resistance of the amorphous ITO film was decreased as the supply amount of oxygen increased, and after the annealing, the specific resistance increased as the supply amount of oxygen increased.

As shown in FIG. 5, it can be seen that the transmittance varies with the wavelength band depending on the change in the oxygen supply amount and whether or not annealing is performed. Through these experiments, it can be seen that annealing is preferable to secure a high transmittance when forming a pixel electrode using an amorphous ITO film.

Next, as described above, a thin film transistor substrate for a liquid crystal display device having a transparent conductive film made of amorphous ITO and IZO as a pixel electrode, and a method of manufacturing the same will be described in detail.

First, the structure of the thin film transistor substrate for a liquid crystal display according to the first embodiment of the present invention will be described in detail with reference to FIGS. 6 and 7.

6 is a thin film transistor substrate for a liquid crystal display according to a first exemplary embodiment of the present invention, and FIG. 7 is a cross-sectional view of the thin film transistor substrate shown in FIG. 6 taken along the line VII-VII ′.

A gate wiring made of an aluminum-based metal material having low resistance is formed on the insulating substrate 10. The gate wire is connected to the gate line 22 and the gate line 22 extending in the horizontal direction, and are connected to the gate pad 24 and the gate line 22 which receive a gate signal from the outside and transmit the gate signal to the gate line. A gate electrode 26 of the thin film transistor.

On the substrate 10, a gate insulating film 30 made of silicon nitride (SiN _x ) covers the gate wirings 22, 24, and 26.

A semiconductor layer 40 made of a semiconductor such as amorphous silicon is formed on the gate insulating film 30 of the gate electrode 24 in an island shape, and silicide or n-type impurities are doped with high concentration on the semiconductor layer 40. Resistive contact layers 55 and 56 made of a material such as n + hydrogenated amorphous silicon are formed, respectively.

On the resistive contact layers 55 and 56 and the gate insulating layer 30, a data line made of metal such as molybdenum (Mo) or molybdenum-tungsten (MoW) alloy, chromium (Cr), tantalum (Ta), titanium (Ti), or the like ( 62, 65, 66, 68 are formed. The data line is formed in the vertical direction and crosses the gate line 22 to define a pixel, and the data line 62 is a branch of the data line 62 and the source electrode 65 extending to the upper portion of the ohmic contact layer 55. ), Which is connected to one end of the data line 62 and is separated from the data pad 68 and the source electrode 65 to which an image signal from the outside is applied, and is opposite to the source electrode 65 with respect to the gate electrode 26. And a drain electrode 66 formed on the ohmic contact layer 56.

In this case, when the data lines 62, 65, 66, and 68 are formed in two or more layers, one layer is formed of an aluminum-based conductive material having a low resistance, and the other layer is formed of a material having good contact properties with other materials. desirable. Examples thereof include Cr / Al (or Al alloy) or Al / Mo.

The passivation layer 70 made of silicon nitride is formed on the data lines 62, 65, 66, and 68 and the semiconductor layer 40 which is not covered.

In the passivation layer 70, contact holes 76 and 78 are formed to expose the drain electrode 66 and the data pad 68, respectively. The contact hole 74 exposing the gate pad 24 together with the gate insulating layer 30 is formed. Is formed.

On the passivation layer 70, a pixel electrode 82, which is electrically connected to the drain electrode 66 and positioned in the pixel, is formed through the contact hole 76. In addition, the auxiliary gate pad 86 and the auxiliary data pad 88, which are connected to the gate pad 24 and the data pad 68, respectively, are formed on the passivation layer 70 through the contact holes 74 and 78. Here, the pixel electrode 82, the auxiliary gate pads, and the auxiliary data pads 86 and 88 are formed of amorphous indium tin oxide (ITO) and indium zinc oxide (IZO).

In the thin film transistor array (array) substrate according to the first embodiment of the present invention, the pixel electrode 82 is made of amorphous ITO and IZO to ensure uniform transmittance in various wavelength bands.

1 and 2, the pixel electrode 82 overlaps with the gate line 22 to form a storage capacitor. When the storage capacitor is insufficient, the pixel electrode 82 is disposed on the same layer as the gate wirings 22, 24, and 26. It is also possible to add a storage capacitor wiring. In addition, the IZO patterns 82, 86, and 88 may be formed before the passivation layer 70, or may be formed before the data lines 62, 65, 66, and 68.

In the structure according to the exemplary embodiment of the present invention, the gate wirings 22, 24, and 26 are made of aluminum series having low resistance, and thus may be applied to a large screen high-definition liquid crystal display device.

Next, a method of manufacturing the TFT array substrate for a liquid crystal display according to the first exemplary embodiment of the present invention will be described in detail with reference to FIGS. 6 and 7 and FIGS. 8A to 11B.

First, as shown in FIGS. 8A and 8B, a single film made of an aluminum-based metal having a low resistance is stacked and patterned on the substrate 10 to a thickness of about 2,500 GHz to form a gate line 22 and a gate electrode 26. And a gate wiring in a horizontal direction including the gate pad 24.

Next, as shown in FIGS. 9A and 9B, a three-layer film of a gate insulating film 30 made of silicon nitride, a semiconductor layer 40 made of amorphous silicon, and a doped amorphous silicon layer 50 is successively stacked, and a mask is formed. An island-shaped semiconductor layer 40 and an ohmic contact layer 50 are formed on the gate insulating layer 30 facing the gate electrode 24 by patterning the semiconductor layer 40 and the doped amorphous silicon layer 50 by the patterning process. ). Here, the gate insulating film 30 is preferably laminated for at least 5 minutes in the temperature range of 300 ℃ or more.                     

Next, as illustrated in FIGS. 10A to 10B, a metal film made of chromium, molybdenum, molybdenum alloy, titanium, tantalum, or the like is laminated, and patterned by a photo process using a mask to cross the data line with the gate line 22. A source electrode 65 connected to the data line 62 and extending to an upper portion of the gate electrode 26, and a data pad 68 and a source electrode 64 connected to one end thereof. And a data line including a drain electrode 66 facing the source electrode 65 and separated from the gate electrode 26.

Subsequently, the doped amorphous silicon layer pattern 50, which is not covered by the data lines 62, 65, 66, and 68, is etched and separated on both sides of the gate electrode 26, while both doped amorphous silicon layers ( The semiconductor layer pattern 40 between 55 and 56 is exposed. Subsequently, in order to stabilize the surface of the exposed semiconductor layer 40, it is preferable to perform oxygen plasma.

Next, as shown in FIGS. 11A and 11B, an inorganic insulating film such as silicon nitride is laminated to form a protective film 70. In this case, similarly to the formation of the gate insulating film 30, the protective film 70 is preferably laminated for a time period of 5 minutes or more in a temperature range of 300 ° C. or higher. Subsequently, the passivation layer 70 is patterned to form contact holes 74, 76, and 78 that expose the gate pad 24, the drain electrode 66, and the data pad 68, respectively.

Next, as shown in FIGS. 1 and 2, amorphous ITO and IZO films are laminated to a thickness of about 300-600 mm 3 and about 800-1,400 mm, preferably 400 mm and 1,200 mm thick, and patterned using a mask. And an auxiliary gate pad connected to the pixel electrode 82 connected to the drain electrode 66 through the contact hole 76 and the gate pad 24 and the data pad 68 through the contact holes 74 and 78, respectively. 86 and auxiliary data pads 88 are formed, respectively. Here, the transparent conductive film patterns 82, 86, and 88 of amorphous ITO and IZO may be patterned by wet etching or dry etching at once, and when wet etching is used, aluminum etching solution or chromium etching solution is used. In this manufacturing method, it is not necessary to use aqua regia-based etchant for etching the crystal ITO, so that the wiring can be prevented from being eroded. The gas used in the pre-heating process before laminating amorphous ITO and IZO prevents the formation of a metal oxide film on top of the metal films 24, 66 and 68 exposing the contact holes 74, 76 and 78. It is preferable to use nitrogen for that purpose.

As described above, the method can be applied to a manufacturing method using five masks, but the same method can be applied to a manufacturing method of a thin film transistor substrate for a liquid crystal display device using four masks. This will be described in detail with reference to the drawings.

First, a unit pixel structure of a thin film transistor substrate for a liquid crystal display device completed using four masks according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 12 to 14.

12 is a layout view of a thin film transistor substrate for a liquid crystal display according to a second exemplary embodiment of the present invention, and FIGS. 13 and 14 are lines XIII-XIII 'and XIV-XIV', respectively, of the thin film transistor substrate shown in FIG. 12. A cross-sectional view taken along the line.                     

First, a gate line including a gate line 22, a gate pad 24, and a gate electrode 26 made of an aluminum-based metal is formed on the insulating substrate 10 as in the first embodiment. The gate wiring includes a sustain electrode 28 that is parallel to the gate line 22 on the substrate 10 and receives a voltage such as a common electrode voltage input to the common electrode of the upper plate from the outside. The storage electrode 28 overlaps with the conductive pattern 64 for the storage capacitor connected to the pixel electrode 82 to be described later to form a storage capacitor which improves the charge retention capability of the pixel. The pixel electrode 82 and the gate line to be described later will be described. If the holding capacity generated by the overlap of (22) is sufficient, it may not be formed.

A gate insulating film 30 made of silicon nitride (SiN _x ) is formed on the gate wirings 22, 24, 26, and 28 to cover the gate wirings 22, 24, 26, and 28.

Semiconductor patterns 42 and 48 made of semiconductors such as hydrogenated amorphous silicon are formed on the gate insulating layer 30, and high concentrations of n-type impurities such as phosphorus (P) are formed on the semiconductor patterns 42 and 48. An ohmic contact layer pattern or an intermediate layer pattern 55, 56, 58 made of amorphous silicon doped with is formed.

On the ohmic contact layer patterns 55, 56 and 58, data wirings made of chromium or molybdenum or molybdenum alloy or metal such as tantalum or titanium are formed. The data line is a thin film transistor which is a branch of the data line 62 formed in the vertical direction, the data pad 68 connected to one end of the data line 62 to receive an image signal from the outside, and the data line 62. And a data line portion of the source electrode 65 of the source electrode 65. The data line portion is separated from the data line portions 62, 68, and 65, and the source electrode 65 is separated from the gate electrode 26 or the channel portion C of the thin film transistor. It also includes a conductive capacitor conductor 64 for the storage capacitor located on the drain electrode 66 and the storage electrode 28 of the thin film transistor located on the opposite side. When the sustain electrode 28 is not formed, the conductor pattern 64 for the storage capacitor is also not formed.

The data lines 62, 64, 65, 66, and 68 may be formed of a double layer including a conductive film made of chromium or molybdenum or molybdenum alloy or tantalum or titanium and a conductive film made of an aluminum-based metal.

The contact layer patterns 55, 56, and 58 serve to lower the contact resistance between the semiconductor patterns 42 and 48 below and the data lines 62, 64, 65, 66, and 68 above them. It has exactly the same form as (62, 64, 65, 66, 68). That is, the data line part intermediate layer pattern 55 is the same as the data line parts 62, 68, and 65, the drain electrode intermediate layer pattern 56 is the same as the drain electrode 66, and the storage capacitor intermediate layer pattern 58 is It is the same as the conductor pattern 64 for holding capacitors.

The semiconductor patterns 42 and 48 have the same shape as the data lines 62, 64, 65, 66, and 68 and the ohmic contact layer patterns 55, 56, and 58 except for the channel portion C of the thin film transistor. Doing. Specifically, the semiconductor capacitor 48 for the storage capacitor, the conductor pattern 64 for the storage capacitor, and the contact layer pattern 58 for the storage capacitor have the same shape, but the semiconductor pattern 42 for the thin film transistor has data wiring and contact. Slightly different from the rest of the layer pattern. That is, in the channel portion C of the thin film transistor, the data line portions 62, 68, and 65, in particular, the source electrode 65 and the drain electrode 66 are separated, and the contact layer pattern for the data line intermediate layer 55 and the drain electrode. Although 56 is also separated, the semiconductor pattern 42 for thin film transistors is not disconnected here and is connected to generate a channel of the thin film transistor.

A protective film 70 made of silicon nitride is formed on the data lines 62, 64, 65, 66, and 68.

The protective film 70 has contact holes 76, 78, and 72 that expose the drain electrode 66, the data pad 64, and the conductive pattern 68 for the storage capacitor, and also the gate along with the gate insulating film 30. It has a contact hole 74 which exposes the pad 24.

On the passivation layer 70, a pixel electrode 82 that receives an image signal from a thin film transistor and generates an electric field together with the electrode of the upper plate is formed. The pixel electrode 82 is made of a transparent conductive material of amorphous ITO and IZO, and is physically and electrically connected to the drain electrode 66 through a contact hole 76 to receive an image signal. The pixel electrode 82 also overlaps with the neighboring gate line 22 and the data line 62 to increase the aperture ratio, but may not overlap. In addition, the pixel electrode 82 is also connected to the conductive capacitor conductor 64 for the storage capacitor through the contact hole 72 to transmit an image signal. On the other hand, an auxiliary gate pad 86 and an auxiliary data pad 88 connected to the gate pad 24 and the data pad 68 through the contact holes 74 and 78, respectively, are formed. 68) and to protect the pads and the adhesion of the external circuit device, and is not essential, their application is optional.                     

Next, a method of manufacturing a thin film transistor substrate for a liquid crystal display device having the structure of FIGS. 12 to 14 using four masks will be described in detail with reference to FIGS. 12 to 14 and FIGS. 15A to 22C. .

 First, as shown in FIGS. 15A to 15C, the gate line 22 and the gate pads are formed on the substrate 10 by a photolithography process using a mask by laminating an aluminum-based metal in a single layer as in the first embodiment. 24, a gate wiring including the gate electrode 26 and the sustain electrode 28 is formed.

Next, as shown in FIGS. 16A and 16B, the gate insulating film 30, the semiconductor layer 40, and the intermediate layer 50 made of silicon nitride are respectively 1,500 kV to 5,000 kPa and 500 kPa to 2,000 using chemical vapor deposition. 증착, 300 600 to 600 연속 of continuous deposition, and then a conductor layer 60 including a metal film made of chromium is deposited to a thickness of 1,500 Å to 3,000 Å by sputtering or the like, and then on the photoresist film 110 thereon. Is applied in a thickness of 1 μm to 2 μm. In this case, the gate insulating film 30 is preferably laminated for at least 5 minutes in a temperature range of 300 ° C. or higher.

Thereafter, the photosensitive film 110 is irradiated with light through a mask and then developed to form photosensitive film patterns 112 and 114 as shown in FIGS. 17B and 17C. In this case, among the photoresist patterns 112 and 114, the channel portion C of the thin film transistor, that is, the first portion 114 positioned between the source electrode 65 and the drain electrode 66, is the data wiring portion A, that is, the data. The thickness of the wirings 62, 64, 65, 66, and 68 is smaller than that of the second portion 112 positioned at the portion where the wirings 62, 64, 65, 66, and 68 are to be formed. At this time, the ratio of the thickness of the photoresist film 114 remaining in the channel portion C to the thickness of the photoresist film 112 remaining in the data wiring portion A should be different depending on the process conditions in the etching process described later. However, it is preferable that the thickness of the first portion 114 is 1/2 or less of the thickness of the second portion 112, for example, 4,000 kPa or less.

As such, there may be various methods of varying the thickness of the photoresist layer according to the position. In order to control the light transmittance in the A region, a slit or lattice-shaped pattern is mainly formed or a translucent film is used.

In this case, the line width of the pattern located between the slits or the interval between the patterns, that is, the width of the slits, is preferably smaller than the resolution of the exposure machine used for exposure, and in the case of using a translucent film, the transmittance is different in order to control the transmittance when fabricating a mask. A thin film having a thickness or a thin film may be used.

When the light is irradiated to the photosensitive film through such a mask, the polymers are completely decomposed at the part directly exposed to the light, and the polymers are not completely decomposed because the amount of light is small at the part where the slit pattern or the translucent film is formed. In the area covered by, the polymer is hardly decomposed. Subsequently, when the photoresist film is developed, only a portion where the polymer molecules are not decomposed is left, and a thin photoresist film may be left at a portion where the light is not irradiated at a portion less irradiated with light. In this case, if the exposure time is extended, all molecules are decomposed, so it should not be so.

The thin film 114 is formed by using a photoresist film made of a reflowable material, and is exposed to a conventional mask that is divided into a portion that can completely transmit light and a portion that cannot completely transmit light, and then develops and ripples. It can also be formed by letting a part of the photosensitive film flow to the part which does not remain by making it low.

Subsequently, etching is performed on the photoresist pattern 114 and the underlying layers, that is, the conductor layer 60, the intermediate layer 50, and the semiconductor layer 40. In this case, the data line and the lower layer of the data line remain in the data wiring portion A, and only the semiconductor layer should remain in the channel portion C, and the upper three layers 60, 50, 40 must be removed to expose the gate insulating film 30.

First, as shown in FIGS. 18A and 18B, the exposed conductor layer 60 of the other portion B is removed to expose the lower intermediate layer 50. In this process, both a dry etching method and a wet etching method may be used. In this case, the conductor layer 60 may be etched and the photoresist patterns 112 and 114 may be hardly etched. However, in the case of dry etching, it is difficult to find a condition in which only the conductor layer 60 is etched and the photoresist patterns 112 and 114 are not etched, so that the photoresist patterns 112 and 114 may also be etched together. In this case, the thickness of the first portion 114 is thicker than that of the wet etching so that the first portion 114 is removed in this process so that the lower conductive layer 60 is not exposed.

When the conductor layer 60 is any one of Mo or MoW alloy, Al or Al alloy, and Ta, either dry etching or wet etching can be used. However, since Cr is not easily removed by the dry etching method, it is preferable to use only wet etching if the conductor layer 60 is Cr. In the case of wet etching in which the conductor layer 60 is Cr, CeNHO ₃ may be used as an etchant. In the case of dry etching in which the conductor layer 60 is Mo or MoW, the mixed gas or CF of CF ₄ and HCl may be used as the etching gas. A mixed gas of ₄ and O ₂ can be used, and in the latter case, the etching ratio to the photoresist film is almost the same.

In this way, as shown in Figs. 18A and 18B, only the conductor layer of the channel portion C and the data wiring portion B, that is, the conductor pattern 67 for the source / drain and the conductor pattern 64 for the storage capacitor All of the conductor layer 60 of the remaining portion B is removed, revealing the underlying intermediate layer 50. The remaining conductor patterns 67 and 64 have the same shape as the data lines 62, 64, 65, 66 and 68 except that the source and drain electrodes 65 and 66 are connected without being separated. In addition, when dry etching is used, the photoresist patterns 112 and 114 are also etched to a certain thickness.

Subsequently, as shown in FIGS. 19A and 19B, the exposed intermediate layer 50 of the other portion B and the semiconductor layer 40 thereunder are simultaneously removed by the dry etching method together with the first portion 114 of the photosensitive film. do. At this time, etching is performed under the condition that the photoresist patterns 112 and 114, the intermediate layer 50, and the semiconductor layer 40 (the semiconductor layer and the intermediate layer have almost no etching selectivity) are simultaneously etched, and the gate insulating layer 30 is not etched. In particular, it is preferable to etch under conditions where the etching ratios of the photoresist patterns 112 and 114 and the semiconductor layer 40 are almost the same. For example, by using a mixed gas of SF ₆ and HCl or a mixed gas of SF ₆ and O ₂ , the two films can be etched to almost the same thickness. When the etching ratios of the photoresist patterns 112 and 114 and the semiconductor layer 40 are the same, the thickness of the first portion 114 should be equal to or smaller than the sum of the thicknesses of the semiconductor layer 40 and the intermediate layer 50.

In this way, as shown in FIGS. 19A and 19B, the first portion 114 of the channel portion C is removed to reveal the source / drain conductor pattern 67 and the intermediate layer 50 of the other portion B. And the semiconductor layer 40 is removed to expose the gate insulating layer 30 thereunder. On the other hand, since the second portion 112 of the data wiring portion A is also etched, the thickness becomes thin. In this step, the semiconductor patterns 42 and 48 are completed. Reference numerals 57 and 58 denote intermediate layer patterns under the source / drain conductor patterns 67 and intermediate layer patterns under the storage capacitor conductor patterns 64, respectively.

Subsequently, ashing removes photoresist residue remaining on the surface of the source / drain conductor pattern 67 of the channel portion C.

Next, as illustrated in FIGS. 20A and 20B, the source / drain conductor pattern 67 of the channel portion C and the source / drain interlayer pattern 57 below the substrate C are etched and removed. In this case, the etching may be performed only by dry etching with respect to both the source / drain conductor pattern 67 and the intermediate layer pattern 57. The etching may be performed by wet etching on the source / drain conductor pattern 67. 57 may be performed by dry etching. In the former case, it is preferable to perform etching under a condition in which the etching selectivity of the source / drain conductor pattern 67 and the interlayer pattern 57 is large, which is difficult to find the etching end point when the etching selectivity is not large. This is because it is not easy to adjust the thickness of the semiconductor pattern 42 remaining in Fig. 2). For example, those of etching the SF ₆ and O ₂ by using the mixed gas of the source / drain conductive pattern 67. In the latter case of alternating between wet etching and dry etching, the side surface of the conductive pattern 67 for wet etching of the source / drain is etched, but the intermediate layer pattern 57 which is dry etched is hardly etched, and thus is formed in a step shape. Examples of the etching gas used to etch the intermediate layer pattern 57 and the semiconductor pattern 42 include the aforementioned mixed gas of CF ₄ and HCl or mixed gas of CF ₄ and O ₂ , and CF ₄ and O _{Using 2} can leave the semiconductor pattern 42 in a uniform thickness. In this case, as shown in FIG. 20B, a portion of the semiconductor pattern 42 may be removed to reduce the thickness, and the second portion 112 of the photoresist pattern may also be etched to a certain thickness at this time. At this time, the etching should be performed under the condition that the gate insulating film 30 is not etched, and the photoresist film is not exposed so that the second portion 112 is etched so that the data lines 62, 64, 65, 66, and 68 underneath are not exposed. It is a matter of course that the pattern is thick.

In this way, the source electrode 65 and the drain electrode 66 are separated, thereby completing the data lines 62, 64, 65, 66, and 68 and the contact layer patterns 55, 56, and 58 under the data lines.

Finally, the second photoresist layer 112 remaining in the data wiring portion A is removed. However, the removal of the second portion 112 may be made after removing the conductor pattern 67 for the channel portion C source / drain and before removing the intermediate layer pattern 57 thereunder.

As mentioned earlier, wet and dry etching can be alternately used or only dry etching can be used. In the latter case, since only one type of etching is used, the process is relatively simple, but it is difficult to find a suitable etching condition. On the other hand, in the former case, the etching conditions are relatively easy to find, but the process is more cumbersome than the latter.

After the data wirings 62, 64, 65, 66, and 68 are formed in this manner, as shown in FIGS. 21A and 21C, silicon nitride is deposited by the CVD method to form the protective film 70. In this case, similarly to the formation of the gate insulating film 30, the protective film 70 is preferably laminated for a time period of 5 minutes or more in a temperature range of 300 ° C. or higher. Subsequently, the passivation layer 70 is etched together with the gate insulating layer 30 using a mask to expose the drain electrode 66, the gate pad 24, the data pad 68, and the conductive capacitor 64 for the storage capacitor, respectively. Contact holes 76, 74, 78, 72 are formed.

Finally, as shown in Figs. 12 to 14, IZO and amorphous ITO are deposited in the same manner as in the first embodiment and patterned with dry or aluminum etchant or chromium etchant using a mask to drain the electrode 66 and the storage capacitor. The pixel electrode 82 connected to the existing conductor pattern 64, the auxiliary gate pad 86 connected to the gate pad 24, and the auxiliary data pad 88 connected to the data pad 68 are formed. In this case, the etching solution for patterning the amorphous ITO and IZO of the pixel electrode 82, the auxiliary gate pad 86, and the auxiliary data pad 88 uses a chromium etchant or an aluminum etchant, which does not corrode the aluminum-based metal. Corrosion can be prevented from aluminum-based metals exposed in the contact structure. Here again, the gas used in the pre-heating process before laminating amorphous ITO and IZO has a metal on top of the metal films 24, 64, 66 and 68 exposing the contact holes 72, 74, 76 and 78. It is preferable to use nitrogen to prevent the formation of an oxide film.

In the second embodiment of the present invention, the data wirings 62, 64, 65, 66, and 68 and the contact layer patterns 55, 56, 58 and the semiconductor pattern 42 below the data wirings 62, 64, 65, 66, and 68, as well as the effects of the first embodiment. , 48) may be formed using one mask, and the source electrode 65 and the drain electrode 66 may be separated in this process to simplify the manufacturing process.

As described above, according to the present invention, when the transparent conductive film pattern is formed using amorphous ITO and IZO, uniform transmittance can be ensured and patterning can be performed under conditions that do not corrode wiring. In addition, the manufacturing process may be simplified to manufacture a thin film transistor substrate for a liquid crystal display, thereby simplifying the manufacturing process and reducing the manufacturing cost.

Claims (21)

A transparent conductive film for display devices, in which an amorphous ITO layer and an IZO layer are laminated. A method of manufacturing a transparent conductive film for a display device, comprising: laminating amorphous ITO and IZO and patterning together by wet etching using a chromium etchant or an aluminum etchant. delete In claim 2, And annealing the transparent conductive film for the display device. In claim 2, The amorphous ITO and IZO are laminated to a thickness in the range of 300-600 kPa and 800-1,200 kPa, respectively. Forming a gate line on the insulating substrate, the gate line including a gate line and a gate electrode connected to the gate line; Stacking a gate insulating film, Forming a semiconductor layer, Forming a data line including a data line crossing the gate line, a source electrode connected to the data line and a drain electrode adjacent to the gate electrode, and a drain electrode opposite to the source electrode; Laminating a protective film, Stacking amorphous ITO and IZO and patterning them together using wet etching using a chromium etchant or an aluminum etchant to form a pixel electrode of a transparent conductive layer connected to the drain electrode Method of manufacturing a thin film transistor substrate comprising a. In claim 6, Annealing the transparent conductive film further comprising a method of manufacturing a thin film transistor substrate for a liquid crystal display device. delete In claim 6, Wherein the amorphous ITO and IZO are laminated to a thickness in the range of 300-600 Hz and 800-1,200 Hz, respectively. In claim 6, The gate line further includes a gate pad connected to the gate line, and the data line further includes a data pad connected to the data line. And forming an auxiliary gate pad coupled to the gate pad and an auxiliary data pad coupled to the data pad in the pixel electrode forming step. In claim 10, And forming contact holes in the gate insulating layer and the protective layer to expose the drain electrode, the gate pad, and the data pad, respectively. In claim 6, And the data line and the semiconductor layer are formed together in a photolithography process using a photoresist pattern having a partially different thickness. In claim 12, The photoresist pattern may include a first part having a first thickness, a second part thicker than the first thickness, and a third part having no thickness and excluding the first and second parts. Manufacturing method. In claim 13, In the photolithography process, the photoresist pattern is formed using a photomask including a first region, a second region having a lower transmittance than the first region, and a third region having a higher transmittance than the first region. Method of manufacturing a substrate. The method of claim 14, And forming the first portion between the source electrode and the drain electrode and the second portion above the data line in the photolithography process. The method of claim 15, And a slit pattern smaller than the resolution of a translucent film or an exposure machine is formed in the photomask to differently control the transmittances of the first to third regions. The method of claim 16, And forming an ohmic contact layer between the semiconductor layer and the data line. The method of claim 17, And forming the data line, the contact layer, and the semiconductor layer using a single mask. A gate wiring formed on an insulating substrate and including a gate line and a gate electrode, A gate insulating film formed on the gate wiring, A data line formed over the gate insulating layer, insulated from and intersecting with the gate line to define a pixel, a source electrode connected to the data line and adjacent to the gate electrode, and opposite to the source electrode with respect to the gate electrode; A data wiring comprising a drain electrode positioned thereon, A pixel electrode formed in the pixel and composed of an amorphous ITO layer and an IZO layer Thin film transistor substrate for a liquid crystal display device comprising a. The method of claim 19, The gate line further includes a gate pad connected to the gate line, and the data line further includes a data pad connected to the data line. The thin film transistor substrate of claim 1, further comprising an auxiliary gate pad connected to the gate pad and an auxiliary data pad connected to the data pad. The method of claim 20, Further comprising a passivation layer formed on the data line, The pixel electrode, the auxiliary gate pad, and the auxiliary data pad are formed on the passivation layer.

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