KR100670050B1 - Thin film transistor panels for liquid crystal display and method manufacturing the same - Google Patents

Abstract

A gate wiring including a gate line, a gate pad, and a gate electrode, a common wiring including a common signal line and a common electrode, and a pixel wiring including a pixel electrode are formed on the substrate, and the gate insulating film, the semiconductor layer, the intermediate layer, and the conductor layer are continuous. After deposition, a positive photoresist film is applied thereon. The photosensitive film is irradiated with light through a mask and then developed to form a photosensitive film pattern. The first portion of the photoresist pattern positioned in the channel portion between the source electrode and the drain electrode is made smaller in thickness than the second portion located in the portion where the data line is to be formed, and all other portions of the photoresist are removed. This can be done by forming a pattern or slit smaller than the resolution in the mask or by placing a translucent film to control the amount of light irradiated onto the photosensitive film or to make a thin film through reflow. Next, the conductor layer exposed to the other portion is removed by a dry or wet etching method to expose the lower intermediate layer, and the exposed intermediate layer and the semiconductor layer below it are dry-etched together with the first portion of the photoresist film. Remove at the same time. After removing the photoresist residue remaining on the surface of the conductor layer through ashing, the source layer and the drain electrode are separated by etching and removing the conductor layer and the intermediate layer pattern under the channel portion. After removing the remaining photoresist second portion, a protective film having a drain electrode and a contact hole exposing the pixel wiring, the data line, and the data pad is formed, and an auxiliary including an auxiliary data line, an auxiliary data pad, and an auxiliary drain electrode on the protective film. A data wiring is formed.

Reflow, mask, channel, resolution, photoresist, common electrode, pixel electrode

Description

Thin film transistor substrate for liquid crystal display device and manufacturing method thereof {THIN FILM TRANSISTOR PANELS FOR LIQUID CRYSTAL DISPLAY AND METHOD MANUFACTURING THE SAME}

1 is a layout view of a thin film transistor substrate for a liquid crystal display according to a first exemplary embodiment of the present invention.

2 and 3 are cross-sectional views of the thin film transistor substrate shown in FIG. 1 taken along lines II-II 'and III-III';

4A is a layout view of a thin film transistor substrate in a first step of manufacturing according to the first embodiment of the present invention,

4B and 4C are cross-sectional views taken along the lines IVb-IVb 'and IVc-IVc' in FIG. 4A, respectively.

5A and 5B are cross-sectional views taken along the IVb-IVb 'line and the IVc-IVc' line in FIG. 4A, respectively, and are cross-sectional views of the next steps of FIGS. 4B and 4C.

6A is a layout view of a thin film transistor substrate in the next steps of FIGS. 5A and 5B;

6B and 6C are cross-sectional views taken along lines VIb-VIb 'and VIc-VIc' in FIG. 6A, respectively.

7A, 8A, 9A, and 7B, 8B, and 9B are cross-sectional views taken along lines VIb-VIb 'and VIc-VIc' in FIG. 6A, respectively, illustrating the following steps in the order of the process. ,

10A is a layout view of a thin film transistor substrate in the next steps of FIGS. 9A and 9B;

10B and 10C are cross-sectional views taken along lines Xb-Xb 'and Xc-Xc', respectively, in FIG. 10A;

11 is a layout view of a thin film transistor substrate for a liquid crystal display according to a second exemplary embodiment of the present invention.

12 and 13 are cross-sectional views of the thin film transistor substrate shown in FIG. 11 taken along lines XII-XII 'and XIII-XIII';

14A to 14C are diagrams illustrating a manufacturing method according to a second embodiment of the present invention, respectively, and FIGS. 5B and 5B are the following steps;

15A and 15B are cross-sectional views at the next stage of FIGS. 14B and 14C, respectively.

The present invention relates to a thin film transistor substrate for a liquid crystal display device and a manufacturing method thereof.

The liquid crystal display is one of the most widely used flat panel display devices. The liquid crystal display includes two substrates on which electrodes are formed and a liquid crystal layer interposed therebetween, and rearranges the liquid crystal molecules of the liquid crystal layer by applying a voltage to the electrode. By controlling the amount of light transmitted.

One of the liquid crystal display devices is designed to improve the viewing angle. The liquid crystal molecules are arranged in parallel with each other on one of the two substrates and are arranged in parallel with the planes of the two substrates by switching the voltage applied to the electrodes. There is a liquid crystal display device having a thin film transistor for rearranging the thin film transistor, and the thin film transistor is generally formed on a substrate on which two electrodes are formed.

The substrate on which the thin film transistor is formed is generally manufactured by a photolithography process using a mask. Currently, five or six masks are generally used, but in order to reduce production cost, it is preferable to reduce the number of masks.

An object of the present invention is to provide a new method that can reduce the number of masks when manufacturing a thin film transistor substrate for a liquid crystal display device.

In order to achieve the above object, in the present invention, a photoresist pattern having different thicknesses of at least two portions is used as an etching mask to form a data line and a semiconductor pattern below the same by a four-shot etching process using one mask.

In this case, the photoresist pattern is positioned on a portion corresponding to the semiconductor pattern not covered by the data wiring, and includes a first portion having a first thickness and a second portion having a thickness thicker than the first portion and positioned at a portion corresponding to the data wiring. Located in a portion other than the first and second portions, and may include a third portion having no thickness, and located in the channel portion between the source electrode and the drain electrode, and corresponding to the first portion having the first thickness and the data line. It may include a second portion located in the portion and having a thickness thicker than the first thickness, and a third portion located in a portion other than the first and second portions and having no thickness.

According to the present invention, first, a gate wiring including a gate line and a gate electrode connected to the insulating substrate, a common wiring including a common signal line and a common electrode connected thereto, and a pixel wiring including a pixel electrode arranged in parallel with the common electrode. To form. Then, a gate insulating film covering the gate wiring, the common wiring and the pixel wiring, and a resistive contact layer pattern formed thereon with a semiconductor pattern thereon, are formed separately from each other, the source electrode and the drain electrode made of the same layer, and the source electrode A data line including a data line connected to the first line is formed. A passivation layer pattern covering the data line and having a first contact hole exposing the drain electrode and the pixel line is formed, and an auxiliary electrode connecting the drain electrode and the pixel line is formed through the first contact hole. Here, the data line and the semiconductor pattern are formed through a photolithography process using a single photoresist pattern, and the photoresist pattern includes a portion corresponding to the channel portion between the source electrode and the drain electrode and has a first portion having a first thickness. A second portion having a thickness thicker than the first thickness and a third portion without thickness.

Here, the mask used in the photolithography process includes a first part where only part of the light can be transmitted, a second part where the light can be completely transmitted, and a third part where light cannot be completely transmitted, and the photoresist pattern is a positive photoresist film. The first, second and third portions of the mask are preferably aligned to correspond to the first, second and third portions of the photosensitive film pattern during the exposure process.

In this case, the first portion of the mask may include a translucent film or may include a pattern having a smaller size than the resolution of the light source used in the exposure step.

Alternatively, the first portion of the photoresist pattern may be formed through reflow.

On the other hand, the thickness of the first portion of the photosensitive film pattern is preferably 1/2 or less of the thickness of the second portion, in particular, the thickness of the second portion of the photosensitive film pattern is 1 μm to 2 μm, and the thickness of the first part is 2,000 to It is preferable that it is 5,000 mV, especially 3,000-4,000 mV.

According to the exemplary embodiment of the present invention, the data line, the contact layer pattern, and the semiconductor pattern may be formed using one mask. In this case, the gate insulating film, the semiconductor pattern, the contact layer pattern and the data wiring are formed through the following steps. First, a gate insulating film, a semiconductor layer, a contact layer, and a conductive layer are deposited, a photosensitive film is applied thereon, and then exposed and developed through a mask to form a photosensitive film pattern so that the second portion is located above the data line. Subsequently, the conductive layer under the third part and the contact layer and semiconductor layer below it, the thickness of the first part and the conductive layer and contact layer below, and the second part are etched to form the conductive layer, the contact layer and the semiconductor layer. After forming the data wiring, the contact layer pattern, and the semiconductor pattern, respectively, the photoresist pattern is removed. At this time, the data wiring, the contact layer pattern, and the semiconductor pattern can be formed through the following three steps. First, the conductive layer under the third part is wet or dry etched to expose the contact layer, and then the contact layer under the third part and the semiconductor layer under it are dry etched together with the first part under the third part. A semiconductor pattern made of a semiconductor layer is completed while exposing the gate insulating film and the conductive layer under the first portion. Finally, the conductive layer under the first portion and the contact layer underneath are removed by etching to complete the data wiring and the contact layer pattern.

Here, when the data line is formed of a material capable of dry etching, the semiconductor layer pattern, the data line, and the contact layer pattern may be completed in one etching step according to the thickness of the photoresist pattern of the first portion.

In this case, the semiconductor pattern may be formed so as to extend out of the data line, and in this case, the first portion of the photosensitive film pattern may be formed at a portion corresponding to the periphery of the data line.

The gate line may further include a gate pad connected to the gate line to receive a signal from the outside, and the data line may further include a data pad connected to the data line to receive a signal from the outside. Second and third contact holes exposing the pad and the data pad, in which case the auxiliary gate pad and the auxiliary data are connected to the gate pad and the data pad through the second and third contact holes and in the same layer as the auxiliary conductive layer. The method may further include forming a pad.

The passivation layer may further include forming an auxiliary data line having a fourth contact hole exposing the data line, connected to the data line through the fourth contact hole, and having the same layer as the auxiliary conductive layer.

In this case, the auxiliary conductive film or the drain electrode may take various structures to overlap the common wiring to form the storage capacitor.

Then, the liquid crystal display according to an exemplary embodiment of the present invention and a manufacturing method thereof will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily implement the present invention.

As described above, the present invention reduces the number of processes by forming a thin photosensitive film pattern between the two electrodes when separating the source electrode and the drain electrode made of the same layer.

First, the structure of the thin film transistor substrate for a liquid crystal display according to the first embodiment of the present invention will be described in detail with reference to FIGS. 1 to 3.

FIG. 1 is a layout view of a thin film transistor substrate for a liquid crystal display according to a first embodiment of the present invention, and FIGS. 2 and 3 are lines II-II 'and III-III' of the thin film transistor substrate shown in FIG. A cross-sectional view taken along the line.

First, a gate made of a metal or a conductor such as aluminum (Al) or aluminum alloy (Al alloy), molybdenum (Mo) or molybdenum-tungsten (MoW) alloy, chromium (Cr), tantalum (Ta) or the like on the insulating substrate 10. Wiring, common wiring and pixel wiring are formed. The gate wiring is connected to the scan signal line or the gate line 22 extending in the horizontal direction and the gate line 22 and the gate pad 24 and the gate which receive the scan signal from the outside and transmit the scan signal to the gate line 22. The gate electrode 23 of the thin film transistor which is a part of the line 22 is included. The common line is formed in parallel with the gate line 22, and the common signal line 26 and the vertical which receive a signal such as a common voltage from the outside. And a common electrode 28 formed in a direction and being a branch of the common signal line 26. In addition, the pixel wirings are connected in parallel with the common electrode 28 and connected to the lower end of the pixel electrode 27 and the pixel electrode 27 to which the image signal is transmitted, and are connected to the drain electrode 66 to be described later to connect the image signal. It includes a pixel electrode connection unit 29 that receives the.

The gate wirings 22, 23, 24, the common wirings 26, 28, and the pixel wirings 27, 29 may be formed in a single layer, but may also be formed in a double layer or a triple layer. In the case where more than two layers are formed, it is preferable that one layer is made of a material having a low resistance and the other layer is made of a material having good contact properties with other materials, especially ITO, which is used as a pad material. This is because the pad part forms the wiring material and the pad material together to reinforce the pad part electrically connected to the outside. When the pad material is formed of ITO, materials having good contact properties with ITO include chromium (Cr), molybdenum (Mo), titanium (Ti) and tantalum (Ta), and Cr / Al (or Al alloys). The bilayer of) or Al / Mo bilayer is mentioned as an example.

A gate insulating film 30 made of silicon nitride (SiN _x ) is formed on the gate wirings 22, 23, 24, the common wirings 26, 28, and the pixel wirings 27, 29 to form the gate wirings 22, 23, 24. ), The common wirings 26 and 28 and the pixel wirings 27 and 29.

A semiconductor pattern 42 including a channel portion c on which the thin film transistor channel is formed is formed on the gate insulating layer 30, and is formed of a semiconductor such as hydrogenated amorphous silicon. An ohmic contact layer pattern or intermediate layer patterns 55 and 56 formed of amorphous silicon doped with a high concentration of n-type impurities such as phosphorus (P) are formed thereon.

On the contact layer patterns 55 and 56, data wirings made of a conductive material such as Mo or MoW alloy, Cr, Al or Al alloy, and Ta are formed. The data line is a thin film transistor which is a branch of the data line 62 formed in the vertical direction, the data pad 64 connected to one end of the data line 62 to receive an image signal from the outside, and the data line 62. And a data line portion of the source electrode 65 of the source electrode 65. The data line portion is separated from the data line portions 62, 64, and 65, and the source electrode 65 with respect to the gate electrode 23 or the channel portion C of the thin film transistor. A drain electrode 66 of the thin film transistor positioned on the opposite side. Here, the drain electrode 66 extends to the upper portion of the pixel electrode connector 29.

The data lines 62, 64, 65, and 66 may be formed in a single layer like the gate lines 22, 23, and 24, but may also be formed in a double layer or a triple layer. Of course, when forming more than two layers, it is preferable that one layer is made of a material having a low resistance and the other layer is made of a material having good contact properties with other materials.

The contact layer patterns 55 and 56 lower the contact resistance of the semiconductor pattern 42 below and the data lines 62, 64, 65, and 66 above it, and the data lines 62, 64, and 65. , 66). That is, the data line part intermediate layer pattern 55 is the same as the data line parts 62, 64, and 65, and the drain electrode intermediate layer pattern 56 is the same as the drain electrode 66.

The semiconductor patterns 42 and 48 have the same shapes as the data lines 62, 64, 65 and 66 and the contact layer patterns 55 and 56 except for the channel portion C of the thin film transistor. Specifically, the semiconductor pattern 42 for thin film transistors is slightly different from the rest of the data wiring and contact layer pattern. That is, the data line parts 62, 64, 65, in particular, the source electrode 65 and the drain electrode 66 are separated from the channel portion C of the thin film transistor, and the contact layer pattern for the data line intermediate layer 55 and the drain electrode is separated. Although 56 is also separated, the semiconductor pattern 42 for thin film transistors is not disconnected here and is connected to generate a channel of the thin film transistor.

The passivation layer 70 is formed on the data lines 62, 64, 65, and 66 and the semiconductor pattern 42 not covered by the data line, and the passivation layer 70 is formed along with the gate insulating layer 30. And contact holes 73 and 76 exposing the data pads 64 and contact holes exposing the gate pad 24 and the drain electrode 66 and the pixel electrode connection portion 29 together with the gate insulating film 30. 74, 78). The passivation layer 70 may be made of an organic insulating material such as silicon nitride or acrylic.

An auxiliary data line electrically connected to the data line is formed on the passivation layer 70. The auxiliary data line overlaps the data line parts 62 and 65 and is parallel to the data line parts 62 and 65 and connected to the data line 62 through the contact hole 73 and the data pad 62 through the contact hole 76. An auxiliary data line formed of an auxiliary data pad 84 connected to the first and second electrodes 64, and connected to the drain electrode 66 and the pixel electrode connecting part 29 through the contact hole 78 to electrically connect the common electrodes. An auxiliary drain electrode 88 is included as an auxiliary conductive film partially overlapping with 28 to form a storage capacitor. Here, although the storage capacitor is formed by overlapping the auxiliary drain electrode 88 with the common electrode 28, the storage capacitor may be formed using only the drain electrode 66, and the common electrode 28 may be sufficiently secured to secure the storage capacitor. ) And the drain electrode 66 or the auxiliary drain electrode 88 may be formed in various modified structures. In this case, the auxiliary data lines 82, 84, and 88 may be made of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO) or an opaque conductive material. Meanwhile, the auxiliary data lines 82, 84, and 88 may be formed on the gate pad 24. Auxiliary gate pads 86 formed therein through contact holes 74 are formed, and the auxiliary gate pads 86 and the auxiliary data pads 84 adhere to the pads 24 and 64 with external circuit devices. Complementary and protective pads are not essential and their application is optional.

Next, a method of manufacturing the liquid crystal display substrate according to the first embodiment of the present invention will be described in detail with reference to FIGS. 4A to 10C and FIGS. 1 to 3.

First, as illustrated in FIGS. 4A to 4C, a conductive layer such as a metal is deposited to a thickness of 1,000 kPa to 3,000 kPa by a sputtering method, and first, dry or wet etch using a mask to form a gate on the substrate 10. A gate wiring including a line 22, a gate pad 24, and a gate electrode 23, a common wiring including a common signal line 26 and a common electrode 28, a pixel electrode 27, and a pixel electrode connection unit ( A pixel wiring including 29 is formed.

Next, as shown in FIGS. 5A and 5B, the gate insulating film 30, the semiconductor layer 40, and the intermediate layer 50 are respectively 1,500 kV to 5,000 kV, 500 kV to 2,000 kV, and 300 kV using chemical vapor deposition. Continuously deposited to a thickness of 600 to 600 kPa, and then depositing a conductor layer 60 such as a metal to a thickness of 1,500 kPa to 3,000 kPa by sputtering or the like, and then depositing a photoresist film 110 thereon at a thickness of 1 μm to 2 μm. Apply with

Thereafter, the photosensitive film 110 is irradiated with light through a second mask and then developed to form photosensitive film patterns 112 and 114 as illustrated in FIGS. 6B and 6C. In this case, among the photoresist patterns 112 and 114, the channel portion C of the thin film transistor, that is, the first portion 114 positioned between the source electrode 65 and the drain electrode 66, is the data wiring portion A, that is, the data. The thickness of the wirings 62, 64, 65, and 66 is smaller than that of the second portion 112 positioned at the portion where the wirings 62, 64, 65, and 66 are to be formed, and all of the photosensitive film of the other portion B is removed. At this time, the ratio of the thickness of the photoresist film 114 remaining in the channel portion C to the thickness of the photoresist film 112 remaining in the data wiring portion A should be different depending on the process conditions in an etching process which will be described later. Preferably, the thickness of the first portion 114 is 1/2 or less of the thickness of the second portion 112, and the thickness of the second portion is formed to be about 1.6 to 1.9 µm, and the thickness of the first portion 114 is. It is good to form about 3,000 ~ 4,000 Å in the range of 2,000 ~ 5,000 Å or less. Here, when the photosensitive film is positive, the transmittance of the data wiring portion A is 3% or less, the transmittance of the channel portion C is 20 to 60%, more preferably 30 to 40, and the transmittance of the other portion B is It is preferable to make a mask so that it may be 90% or more. on

As such, there may be various ways of varying the thickness of the photoresist film according to the position. Here, two methods are presented for the case of using the positive photoresist film. In this case, it is preferable that the thickness of the photoresist film is formed to be about 1.6 to 2 μm thicker than the usual thickness, in order to make it possible to control the film remaining after development.

The first of these is to form a pattern smaller than the resolution in the mask, for example, a slit or lattice pattern or to place a translucent film to control the amount of light irradiation. At this time, the line width or spacing of the slit pattern should be smaller than the resolution of the exposure machine used at the time of exposure so that only the transmittance can be adjusted. On the other hand, in the case of using a translucent film, the light transmittance may be controlled by adjusting the thickness of the film when fabricating the mask, and the light transmittance may be controlled by forming a plurality of films having different transmittances into a multilayer film. In this case, in order to adjust the irradiation amount of light, chromium (Cr), MgO, MoSi, a-Si, or the like may be used.

When the light is irradiated to the photoresist through a slit pattern or a mask having a translucent film that can control the light transmittance, the polymers of the photoresist are decomposed by the light. do. When the exposure ends when the polymers in the part completely exposed to light are completely decomposed, the photoresist molecules are not decomposed in this part because the amount of irradiation of the slit or translucent film is smaller than the part directly exposed to the light. . In this case, if the exposure time is prolonged, the polymers of all parts are completely decomposed, so it should not be so. Subsequently, when the photoresist film is developed, the photoresist film of the portion where the polymers are not decomposed is left at the thickness of the initial state, and the photoresist film having a medium thickness remains on the part irradiated with little light by the slit pattern or the translucent film, and completely decomposed by the light The photoresist is hardly left in the part. Using this method, the photosensitive film patterns 112 and 114 having partially different thicknesses can be formed.

The next method is to use reflow of the photoresist film. In this case, using a conventional mask divided into a part that can completely transmit light and a part that cannot completely transmit light, a conventional photoresist pattern is formed in which there is no photoresist film or remains at a certain thickness. Subsequently, the photoresist pattern is reflowed and flowed down to a portion where no photoresist remains, thereby forming a new photoresist pattern having an intermediate thickness.

Through this method, photoresist patterns 112 and 114 having different thicknesses are formed according to positions.

Subsequently, etching is performed on the photoresist patterns 112 and 114 and the lower layers thereof, that is, the conductor layer 60, the intermediate layer 50, and the semiconductor layer 40. In this case, the data line and the lower layer of the data line remain in the data wiring portion A, and only the semiconductor layer should remain in the channel portion C, and the upper three layers 60, 50, 40 must be removed to expose the gate insulating film 30.

First, as shown in FIGS. 7A and 7B, the exposed conductor layer 60 of the other portion B is removed to expose the lower intermediate layer 50. In this process, both a dry etching method and a wet etching method may be used. In this case, the conductor layer 60 may be etched and the photoresist patterns 112 and 114 may be hardly etched. However, in the case of dry etching, it is difficult to find a condition in which only the conductor layer 60 is etched and the photoresist patterns 112 and 114 are not etched, so that the photoresist patterns 112 and 114 may also be etched together. In this case, the thickness of the first portion 114 is thicker than that of the wet etching so that the first portion 114 is removed in this process so that the lower conductive layer 60 is not exposed.

When the conductor layer 60 is any one of Mo or MoW alloy, Al or Al alloy, and Ta, either dry etching or wet etching can be used. However, since Cr is not easily removed by the dry etching method, it is preferable to use only wet etching if the conductor layer 60 is Cr. In the case of wet etching in which the conductor layer 60 is Cr, CeNHO ₃ may be used as an etchant. In the case of dry etching in which the conductor layer 60 is Mo or MoW, the mixed gas or CF of CF ₄ and HCl may be used as the etching gas. A mixed gas of ₄ and O ₂ can be used, and in the latter case, the etching ratio to the photoresist film is almost the same.

In this way, as shown in FIGS. 7A and 7B, only the conductor layer of the channel portion C and the data wiring portion B, that is, the conductor pattern 67 for the source / drain remains, and the conductor layer of the other portion B ( 60 are all removed to reveal the underlying intermediate layer 50. The remaining conductor patterns 67 and 68 have the same shape as the data lines 62, 64, 65, 66, and 68 except that the source and drain electrodes 65 and 66 are connected without being separated. In addition, when dry etching is used, the photoresist patterns 112 and 114 are also etched to a certain thickness.

Subsequently, as shown in FIGS. 8A and 8B, the exposed intermediate layer 50 of the other portion B and the semiconductor layer 40 below it are simultaneously removed together with the first portion 114 of the photosensitive film by a dry etching method. do. At this time, etching is performed under the condition that the photoresist patterns 112 and 114, the intermediate layer 50, and the semiconductor layer 40 (the semiconductor layer and the intermediate layer have almost no etching selectivity) are simultaneously etched, and the gate insulating layer 30 is not etched. In particular, it is preferable to etch under conditions where the etching ratios of the photoresist patterns 112 and 114 and the semiconductor layer 40 are almost the same. For example, by using a mixed gas of SF ₆ and HCl or a mixed gas of SF ₆ and O ₂ , the two films can be etched to almost the same thickness. When the etching ratios of the photoresist patterns 112 and 114 and the semiconductor layer 40 are the same, the thickness of the first portion 114 should be equal to or smaller than the sum of the thicknesses of the semiconductor layer 40 and the intermediate layer 50.

In this way, as shown in FIGS. 8A and 8B, the first portion 114 of the channel portion C is removed to reveal the source / drain conductor pattern 67 and the intermediate layer 50 of the other portion B. And the semiconductor layer 40 is removed to expose the gate insulating layer 30 thereunder. On the other hand, since the second portion 112 of the data wiring portion A is also etched, the thickness becomes thin. In this step, the semiconductor pattern 42 is completed. Reference numeral 57 denotes an interlayer pattern under the source / drain conductor pattern 67, respectively.

Subsequently, ashing removes photoresist residue remaining on the surface of the source / drain conductor pattern 67 of the channel portion C. As the method of ashing, plasma gas or microwave may be used, and the composition mainly used includes oxygen.

Next, as shown in FIGS. 9A and 9B, the source / drain conductor pattern 67 of the channel portion C and the source / drain interlayer pattern 57 under the etching are removed by etching. In this case, the etching may be performed only by dry etching with respect to both the source / drain conductor pattern 67 and the intermediate layer pattern 57. The etching may be performed by wet etching on the source / drain conductor pattern 67. 57 may be performed by dry etching. In the former case, it is preferable to perform etching under a condition in which the etching selectivity of the source / drain conductor pattern 67 and the interlayer pattern 57 is large, which is difficult to find the etching end point when the etching selectivity is not large. This is because it is not easy to adjust the thickness of the semiconductor pattern 42 remaining in Fig. 2). For example, those of etching the SF ₆ and O ₂ by using the mixed gas of the source / drain conductive pattern 67. In the latter case of alternating between wet etching and dry etching, the side surface of the conductive pattern 67 for wet etching of the source / drain is etched, but the intermediate layer pattern 57 which is dry etched is hardly etched, and thus is formed in a step shape. Examples of the etching gas used to etch the intermediate layer pattern 57 and the semiconductor pattern 42 include the aforementioned mixed gas of CF ₄ and HCl or mixed gas of CF ₄ and O ₂ , and CF ₄ and O _{Using 2} can leave the semiconductor pattern 42 in a uniform thickness. In this case, as shown in FIG. 9A, a portion of the semiconductor pattern 42 may be removed to reduce the thickness, and the second portion 112 of the photoresist pattern may also be etched to a certain thickness at this time. At this time, the etching must be performed under the condition that the gate insulating layer 30 is not etched. Of course, thick is preferable.

In this case, the source electrode 65 and the drain electrode 66 are separated, thereby completing the data lines 62, 64, 65, and 66 and the contact layer patterns 55 and 56 thereunder.

Finally, the second photoresist layer 112 remaining in the data wiring portion A is removed. However, the removal of the second portion 112 may be made after removing the conductor pattern 67 for the channel portion C source / drain and before removing the intermediate layer pattern 57 thereunder.

In addition, when the data line is formed of a material capable of dry etching, the thickness of the photoresist pattern is controlled to form the contact layer pattern, the semiconductor layer pattern, and the data line in one etching process without going through several intermediate processes as described above. can do. That is, during the etching of the metal layer 60, the contact layer 50, and the semiconductor layer 40 in the portion B, the photoresist pattern 114 and the contact layer 50 under the portion are etched in the C portion, and the photoresist pattern in the A portion. A condition for etching only part of the 112 may be selected and formed in one step.

As mentioned earlier, wet and dry etching can be alternately used or only dry etching can be used. In the latter case, since only one type of etching is used, the process is relatively easy, but it is difficult to find a suitable etching condition. On the other hand, in the former case, the etching conditions are relatively easy to find, but the process is more cumbersome than the latter.

After forming the data lines 62, 64, 65, and 66 in this manner, as shown in FIGS. 10A to 10C, silicon nitride is deposited by a CVD method or by spin coating an organic insulating material to obtain a protective film having a thickness of 2,000 Å or more. 70). Subsequently, the passivation layer 70 is etched together with the gate insulating layer 30 by using a third mask to form the data line 62, the gate pad 24, the data pad 64, the drain electrode 66, and the pixel electrode connection unit 29. ) To form contact holes 73, 74, 76, 78, respectively.

Finally, as shown in FIGS. 1 to 3, the transparent conductive material or the opaque conductive material is deposited and etched using a fourth mask to assist the auxiliary data wires 82, 84, and 88 and the auxiliary gate pad 86. To form.

As described above, in the present exemplary embodiment, the data line 62, 64, 65, and 66, the contact layer patterns 55, 56, and the semiconductor pattern 42 under the same may be formed using one mask to simplify the manufacturing process. have. In addition, it is possible to prevent the disconnection of the wiring by forming a double data wiring.

In the embodiment of the present invention, the auxiliary data lines 82, 84, and 88 are formed after the data lines 62, 64, 65, and 66 are formed, but they may be formed in a reversed order.

In the second embodiment of the present invention, the semiconductor pattern 42 and the data lines 62, 64, 65, and 66 except for the channel portion C are formed in the same shape. 64, 65, 66) may be formed to come out. This will be described in detail with reference to the drawings.

FIG. 11 is a layout view of a TFT substrate for a liquid crystal display according to a second exemplary embodiment of the present invention, FIG. 12 is a cross-sectional view taken along the line XII-XII ′ in FIG. 11, and FIG. 13 is XIII-XIII in FIG. 11. '' A cross section cut along a line.

11 to 13, the structure of the thin film transistor substrate according to the second embodiment is similar to that of the first embodiment. However, the semiconductor pattern 42 is formed so as to extend out of the data lines 62, 64, 65, and 66.

Next, a method of manufacturing the liquid crystal display substrate according to the second exemplary embodiment of the present invention will be described in detail with reference to FIGS. 14A to 15B and FIGS. 14 to 16. 14A to 14C illustrate a manufacturing process of a thin film transistor substrate for a liquid crystal display according to a second exemplary embodiment of the present invention, and show the next steps of FIGS. 5A and 5B.

Most of the manufacturing method according to the second embodiment of the present invention is similar to the manufacturing method of the first embodiment.

Alternatively, as shown in FIGS. 14A and 14B, the photoresist layer 110 is coated and the photoresist patterns 112 and 114 are formed by a photolithography process using a second mask, and the photoresist pattern 114 having a thin thickness is formed by a thin film transistor. It is formed not only in the channel portion C but also in the periphery of the data wiring portion A.

15A and 15B, similarly to the first embodiment, the semiconductor pattern 42 is formed using the photoresist patterns 112 and 114, and the data line 62 is formed using the photoresist pattern 112. , 64, 65, 66 are formed inside the semiconductor pattern 42, and the intermediate layer 50 is etched using the data wires 62, 64, 65, 66, or the photoresist pattern 112 as a mask to form the intermediate layer pattern 55. , 56). In this case, a portion of the semiconductor pattern 42 may be etched.

Subsequent manufacturing processes are performed in the same manner as in the first embodiment to form the passivation layer 70, the auxiliary data lines 82, 84, 88, and the auxiliary gate pad 86 as shown in FIGS. 11 to 13.

As described above, according to the present invention, when the thin film transistor substrate for a liquid crystal display device is manufactured, the number of masks can be effectively reduced, and wire breakage can be prevented.

Claims (23)

Forming a pixel wiring including a gate wiring including a gate line and a gate electrode connected thereto, a common wiring including a common signal line and a common electrode connected thereto, and a pixel wiring including a pixel electrode on an insulating substrate; Forming a gate insulating film covering the gate wiring, the common wiring and the pixel wiring; Forming a semiconductor pattern on the gate insulating layer; Forming an ohmic contact layer pattern on the semiconductor pattern; Forming a data line formed on the contact layer and separated from each other and including a source electrode and a drain electrode made of the same layer, and a data line connected to the source electrode; Forming a passivation layer pattern covering the data line and having a first contact hole exposing the drain electrode and a portion of the pixel line; Forming an auxiliary electrode connecting the drain electrode and the pixel wiring through the first contact hole; Including; The data line and the semiconductor pattern are formed through a photolithography process using one photoresist pattern, and the photoresist pattern includes a portion corresponding to a channel portion between the source electrode and the drain electrode and has a first thickness. And a second portion having a thickness thicker than the first thickness and a third portion located at a portion other than the first and second portions and having no thickness. In claim 1, The mask used in the photolithography process includes a first portion through which only part of the light can be transmitted, a second portion through which light cannot be transmitted completely, and a third portion through which light can be completely transmitted, wherein the photoresist pattern is a positive photoresist layer, The first, second, and third portions of the mask may be aligned to correspond to the first, second, and third portions of the photoresist pattern during the exposure process. In claim 2, And a first portion of the mask comprises a translucent film. In claim 2, And a first portion of the mask comprises a pattern smaller in size than the resolution of the light source used in the exposing step. In claim 1, And a first portion of the photoresist pattern is formed through reflow. In claim 1, The thickness of the 1st part of the said photosensitive film pattern is a manufacturing method of the thin film transistor substrate for liquid crystal display devices which is half or less of the thickness of the said 2nd part. In claim 6, The thickness of the second portion of the photosensitive film pattern is a manufacturing method of a thin film transistor substrate for a liquid crystal display device. In claim 7, The thickness of the first portion of the photosensitive film pattern is a manufacturing method of a thin film transistor substrate for a liquid crystal display device range of 2,000 ~ 5,000 kHz. In claim 1, And forming the data line, the contact layer pattern, and the semiconductor pattern using a mask. In claim 9, The forming of the gate insulating film, the semiconductor pattern, the contact layer pattern, and the data wiring may include Depositing the gate insulating film, the semiconductor layer, the contact layer, and the conductive layer, Applying a photoresist film on the conductive layer, Exposing the photosensitive film through the mask; Developing the photoresist to form the photoresist pattern such that the second portion is located above the data line; Etching the conductive layer below the third portion and a contact layer and semiconductor layer below it, the conductive layer and contact layer below the first portion and below, and a partial thickness of the second portion to etch the conductive layer, the Forming the data line, the contact layer pattern, and the semiconductor pattern each consisting of a contact layer, the semiconductor layer, Removing the photoresist pattern Method of manufacturing a thin film transistor substrate comprising a. In claim 10, Forming the data line, the contact layer pattern, and the semiconductor pattern, Wet or dry etch the conductive layer under the third portion to expose the contact layer, Dry etching the contact layer under the third portion and the semiconductor layer thereunder with the first portion to expose the gate insulating film under the third portion and the conductive layer under the first portion and simultaneously Completing the semiconductor pattern made of a semiconductor layer, Completing the data line and the contact layer pattern by etching and removing the conductive layer under the first portion and the contact layer under it. Method of manufacturing a thin film transistor substrate comprising a. In claim 1, And the first portion further includes a portion corresponding to a peripheral portion of the data line. In claim 1, The gate line further includes a gate pad connected to the gate line to receive a signal from the outside, and the data line further includes a data pad connected to the data line to receive a signal from the outside, The passivation pattern and the gate insulating layer may have second and third contact holes exposing the gate pad and the data pad. Forming an auxiliary gate pad and an auxiliary data pad on the same layer as the auxiliary electrode and connected to the gate pad and the data pad through the second and third contact holes. Manufacturing method. In claim 1, The passivation pattern has a fourth contact hole exposing the data line, And forming an auxiliary data line connected to the data line through the fourth contact hole and having the same layer as the auxiliary electrode. Board, A gate line formed on the substrate, the gate line including a gate line through which a scan signal extending in a horizontal direction is transmitted, and a gate electrode of a thin film transistor that is part of the gate line; A common wiring formed on the substrate and including a common signal line extending in the same direction as the gate line and a common electrode which is a branch of the common signal line; A pixel wiring formed on the substrate and including pixel electrodes arranged in parallel with the common electrode; A gate insulating film covering the gate wiring, the common wiring and the pixel wiring; A semiconductor pattern formed on the gate insulating layer and formed of a semiconductor; The thin film transistor formed on the semiconductor pattern and extending in a vertical direction, a source electrode of the thin film transistor which is a branch of the data line, and separated from the source electrode and facing the source electrode with respect to the gate electrode. A data wiring including a drain electrode, A passivation layer pattern formed over the data line and having a first contact hole that exposes the drain electrode and the pixel line together with the gate insulating layer; An auxiliary conductive layer formed on the passivation layer pattern and connecting the drain electrode and the pixel wiring through the first contact hole; Thin film transistor substrate for a liquid crystal display device comprising a. The method of claim 15, The gate line further includes a gate pad connected to the gate line to receive a signal from the outside, and the data line further includes a data pad connected to the data line to receive a signal from the outside, The passivation layer pattern and the gate insulating layer have second and third contact holes exposing the gate pad and the data pad. And an auxiliary gate pad and an auxiliary data pad connected to the gate pad and the data pad through the second and third contact holes and formed of the same layer as the auxiliary conductive layer. The method of claim 15, The auxiliary conductive layer or the drain electrode overlaps the common wiring to form a storage capacitor. The method of claim 15, The passivation pattern has a fourth contact hole exposing the data line, And a second data line connected to the data line through the fourth contact hole and formed of the same layer as the auxiliary conductive layer. The method of claim 18, The auxiliary data line and the auxiliary conductive layer are formed of a transparent conductive material. The method of claim 15, And a resistive contact layer pattern formed between the semiconductor pattern and the data line and heavily doped with impurities. The method of claim 20, The thin film transistor substrate having the same contact layer pattern as the data line. The method of claim 15, The semiconductor pattern has the same shape as the data line except for the channel portion. The method of claim 15, And the semiconductor pattern is formed to extend out of the data line.

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